A high-uis avalanche tolerance power vdmosfet device and a manufacturing method thereof

Abstract

The application discloses a high UIS avalanche tolerance power VDMOSFET device and a preparation method thereof. The device comprises an N-type substrate region, an N-type drift region formed by one-time epitaxy above the N-type substrate region, an injection region in a trench on both sides of the N-type drift region, the injection region comprising a P-type low-concentration doped base region, a P-type high-concentration doped region and an N-type high-concentration source region, the N-type high-concentration source region being between the P-type low-concentration doped base region and the P-type high-concentration doped region, a functional region formed by multi-time epitaxy above the N-type drift region, the functional region comprising a current expansion layer and a P-type high-concentration shielding layer, a gate region on both sides of the functional region, the gate region being formed by high-temperature oxidation and comprising a gate oxide layer and a gate, and a source and a drain, both formed by device metallization. The current expansion layer and the P-type high-concentration shielding layer can improve the UIS avalanche tolerance of the MOSFET device without sacrificing the basic electrical characteristics of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, and particularly relates to a power VDMOSFET device with high UIS avalanche resistance and a preparation method thereof. BACKGROUND

[0002] The power semiconductor device has the advantages of large driving current, high breakdown voltage, fast speed, low power, large output power and the like, can realize power control and conversion in different ranges, and is widely applied to power management of satellites, spacecrafts and electric vehicles, and has great development potential in space and vehicle application fields. The silicon carbide power semiconductor device usually has the characteristics of small size and large energy density, but when there is a parasitic inductance in a circuit and the device is in reverse bias, and when the switching state of the circuit changes, the energy stored in the inductance is released through the power device, so that the device enters an avalanche state, a large number of electron-hole pairs are generated, the current flowing through the base region causes a parasitic transistor to be triggered, and the device eventually fails due to excessive current or overheating. The avalanche resistance of the existing MOSFET device is not large enough, resulting in low working reliability. SUMMARY

[0003] The present application provides a power VDMOSFET device with high UIS avalanche resistance and a preparation method thereof, to overcome the problem of low avalanche resistance of the existing semiconductor power device.

[0004] In order to achieve the above-mentioned purpose, the technical scheme of the present application is as follows:

[0005] A power VDMOSFET device with high UIS avalanche resistance, comprising:

[0006] An N-type substrate region;

[0007] An N-type drift region on the upper surface of the N-type substrate region;

[0008] An injection region in the trenches on both sides of the N-type drift region, comprising: a P-type light concentration doped base region, a P-type high concentration doped region and an N-type high concentration source region, the N-type high concentration source region being between the P-type light concentration doped base region and the P-type high concentration doped region;

[0009] A functional region in the middle of the N-type drift region, comprising: a current expansion layer and a P-type high concentration shielding layer, the current expansion layer being below the P-type high concentration shielding layer;

[0010] A gate region on both sides of the functional region, comprising: a gate oxide layer and a gate electrode, the gate oxide layer surrounding the four sides of the gate electrode;

[0011] a source electrode connected above the gate region and the functional region;

[0012] a drain electrode connected below the N-type substrate region.

[0013] Further, the current spreading layer in the functional region has a thickness of 0.6 μm, a width of 1.15 μm, and an ion doping concentration ranging from 8 x 10 16 cm -3 to 2 x 10 17 cm -3 ; the P-type high-concentration shielding layer has a thickness of 0.3 μm, a width of 1.15 μm, and an ion doping concentration peak value of 1 x 10 19 cm -3 .

[0014] Further, the injection region has a trench depth ranging from 0.3 μm to 0.6 μm; the P-type light-concentration doped base region has a width of 2.1 μm, a depth of 1.0 μm, and an ion doping concentration peak value ranging from 1 x 10 17 cm -3 to 5 x 10 18 cm -3 ; the P-type high-concentration doped region has a width of 1.2 μm, a depth of 0.8 μm, and an ion doping concentration peak value ranging from 1 x 10 20 cm -3 to 2 x 10 20 cm -3 .

[0015] Further, the N-type drift region has a total thickness of 10.6 μm and an ion doping concentration ranging from 6 x 10 15 cm -3 to 8 x 10 15 cm -3 .

[0016] Further, the gate oxide layer has a thickness of 0.05 μm.

[0017] Further, a preparation method of a high-UIS avalanche tolerance power VSMOSFET device is provided, comprising the following steps:

[0018] S1, preparing an N-type substrate region required by a high-UIS avalanche tolerance power VDMOSFET device;

[0019] S2, forming an N-type drift region on the upper surface of the N-type substrate region by a chemical vapor deposition epitaxy method;

[0020] S3, forming a current spreading layer on the upper surface of the N-type drift region by a chemical vapor deposition epitaxy method again;

[0021] S4, implanting a mask plate on the current spreading layer with a thickness of 30-200 nm, and forming a P-type high-concentration shielding layer by multiple ion implantation;

[0022] S5, forming a groove on the mask plate by a slotting technology and a plasma etching method, and the groove is on both sides of the top of the N-type drift region;

[0023] S6, sequentially forming a P-type light-concentration base region, an N-type high-concentration source region and a P-type high-concentration doped region on the groove by ion implantation;

[0024] S7, performing high-temperature dry oxygen oxidation on the obtained device, forming a gate oxide layer above the groove, depositing polysilicon and doping phosphorus, and then etching to form a gate;

[0025] S8, after the above-mentioned semiconductor device is subjected to metal contact opening, depositing high-melting-point metal nickel or metal titanium, and then annealing to form a source and a drain with an ohmic contact characteristic.

[0026] Beneficial effects: The application discloses a high-UIS avalanche tolerance power VDMOSFET device and a preparation method thereof, the current spreading layer can effectively reduce the on-resistance of the device and the temperature generated when the current flows through the JFET region; the P-type high-concentration shielding layer can reduce the electric field of the gate oxide layer and inhibit the injection of hot holes in the gate oxide layer when the device enters a single pulse and a repeated pulse non-clamping inductive stress; based on the above two technical means of the electric field modulation method and the electric field shielding effect, the UIS avalanche tolerance of the MOSFET device can be significantly improved without sacrificing the basic electrical characteristics of the device, so that the reliability and stability of the device during operation are improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0028] Figure 1 It is a schematic diagram of the cell structure of the prior art planar gate power MOSFET device;

[0029] Figure 2 It is a schematic diagram of the cell structure of the high-UIS avalanche tolerance VDMOSFET device of the present application;

[0030] Figure 3This is a schematic diagram of the structure corresponding to the end of steps S1 to S4 in the preparation method of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure corresponding to step S5 in the preparation method of the present invention;

[0032] Figure 5 This is a schematic diagram of the structure corresponding to the first half of step S6 in the preparation method of the present invention;

[0033] Figure 6 This is a schematic diagram of the structure corresponding to the second half of step S6 in the preparation method of the present invention;

[0034] Figure 7 This is a schematic diagram of the structure corresponding to step S7 in the preparation method of the present invention;

[0035] Figure 8 This is a schematic diagram of the structure corresponding to step S8 in the preparation method of the present invention;

[0036] Figure 9 This is a flowchart of the fabrication method of the VDMOSFET device of the present invention;

[0037] Figure 10 for Figure 1 The plot shows the lattice temperature of the UIS device under avalanche conditions as a function of time.

[0038] Figure 11 for Figure 2 The plot shows the lattice temperature of the UIS device under avalanche conditions as a function of time.

[0039] In the figure: 100, N-type substrate region; 101, N-type drift region; 102, P-type lightly doped base region; 103, P-type heavily doped region; 104, N-type heavily doped source region; 105, current spread layer; 106, P-type heavily doped shielding layer; 200, drain; 201, source; 300, gate oxide layer; 400, gate. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Example 1

[0042] This embodiment provides a power VDMOSFET device with high UIS avalanche tolerance, such asFigure 2 As shown, comprising:

[0043] N-type substrate region 100;

[0044] N-type drift region 101, on the upper surface of the N-type substrate region 100;

[0045] Injection region, in the trenches on both sides of the N-type drift region 101, comprising: P-type lightly doped base region 102, P-type high concentration doped region 103 and N-type high concentration source region 104 between the P-type lightly doped base region 102 and the P-type high concentration doped region 103;

[0046] Functional region, in the middle of the N-type drift region 101, comprising: current spreading layer 105 and P-type high concentration shielding layer 106, the current spreading layer 105 is below the P-type high concentration shielding layer 106;

[0047] Gate region, on both sides of the functional region, comprising: gate oxide layer 300 and gate 400, the gate oxide layer 300 surrounds the four sides of the gate 400;

[0048] Source 201, connected above the gate region and functional region;

[0049] Drain 200, connected below the N-type substrate region 100.

[0050] Specifically, the injection region and the trench where it is located have two groups respectively, which are arranged on the left and right sides of the device, and the injection region includes P-type lightly doped base region 102, P-type high concentration doped region 103 and N-type high concentration source region 104, wherein the N-type high concentration source region 104 is located at the top of the injection region and between the P-type lightly doped base region 102 and the P-type high concentration doped region 103; The size of the P-type lightly doped base region 102 is divided into two parts, that is, the inside and outside heights are different, wherein the inside height of the P-type lightly doped base region 102 is larger, equal to the height of the P-type high concentration doped region 103, and greater than the height of the N-type high concentration source region 104, while the outside height of the P-type lightly doped base region 102 is smaller, and the sum of the height of the P-type lightly doped base region 102 and the height of the N-type high concentration source region 104 is equal to the height of the P-type high concentration doped region 103.

[0051] Specifically, the functional region is provided with a current spreading layer 105 (CSL) under the P-type high-concentration shielding layer 106, and the sum of the heights of the two is equal to the height of the gate region; the gate region is also provided with two groups, which are above the two groups of injection regions, and the two groups of gate regions are connected by the functional region, and the upper part is connected with the source 201, and the sum of the widths of the gate region and the two groups of injection regions is equal to the total width of the device, and the gate oxide layer 300 in the gate region surrounds the periphery of the gate 400.

[0052] In the embodiment, the cell structure of the application is compared with the conventional cell structure by simulation verification, as shown in Figure 1 Fig. 1, which is a schematic diagram of the cell structure of a prior art planar gate power MOSFET device, a 1200V planar gate power MOSFET device is selected, the cell width is 9μm, the drift region thickness is 10μm, the ion doping concentration of the drift region is 6×10 15 cm -3 , and the thickness of the gate oxide layer is 0.05μm; as shown in Figure 2 Fig. 2, which is a schematic diagram of the reinforced cell structure of the high UIS avalanche resistance power VDMOSFET device of the application, the cell width is 9μm, the thickness of the N-type drift region 101 is 10.6μm, the ion doping concentration of the N-type drift region 101 is 6×10 15 cm -3 , and the thickness of the gate oxide layer 300 is 0.05μm.

[0053] It should be noted that the non-clamp inductive switch refers to when there is a parasitic inductance in the circuit, the device will release the energy stored in the inductance to the device in a very short time when the device is in a switching state, so as to force the device to enter the avalanche state. Based on the above principle, the cell devices of the two structures are simulated and tested.

[0054] As shown in Figure 10 Fig. 3, which is a curve diagram of the device lattice temperature changing with time under the UIS avalanche condition of the conventional cell structure. When the inductance of 2mH is connected in series between the two ends of the device, the bias voltage between the inductances is 100V, and the gate of the device is in the high level, which is in the charging stage of the inductance, the charging time is set to 660μs, when the device is in the closing moment, the device is forced to enter the avalanche state, and the avalanche voltage of the device reaches 1500V, at this time, the highest temperature of the device also exceeds 960K, which will cause serious degradation of the metal aluminum structure and even the final failure of the device.

[0055] As shown in Figure 11As shown in the figure, the device lattice temperature of the high UIS avalanche tolerance cell structure of the application changes with time under the UIS avalanche condition. The inductance size in series with the device drain 200 is also 2 mH, the bias voltage of the inductance is also 100 V, the time of the high level of the gate is increased to 730 microseconds, the maximum avalanche voltage of the rugged cell structure is reduced to 1400 V, and the maximum lattice temperature thereof is about 1000 K, that is, the charging time of the inductance is increased by 70 microseconds and the temperature is only increased by 40 K. In addition, the current spreading layer 105 and the P-type high concentration shielding layer 106 are introduced above the JFET region of the rugged cell structure. The current spreading layer 105 can suppress the increase of resistance caused by the top P-type high concentration shielding layer 106, further reduce the resistance of the JFET region, so that the same current flowing through the JFET region can generate less heat; when the device is in an avalanche state, the electrons generated by collision ionization are quickly extracted by the drain 200, and a part of the holes with higher energy will be injected into the gate oxide layer 300 under the action of the negative gate bias. The introduction of the P-type high concentration shielding layer 106 above the JFET can form a hole discharge path, effectively inhibiting the injection of "hot holes" in the gate oxide layer 300, better protecting the gate oxide layer 300, and improving the UIS avalanche tolerance of the device while inhibiting the premature breakdown of the gate oxide layer 300, so that the gate reliability of the rugged cell structure of the application is much higher than that of the ordinary cell structure. Moreover, the introduction of the P-type high concentration shielding layer 106 makes the internal electric field distribution of the device more uniform when the device enters an avalanche state. When a large number of free electron-hole pairs are generated in the device, the P-type high concentration shielding layer 106 can also effectively absorb the hole current and inhibit the false opening of the parasitic transistor, further improving the avalanche tolerance of the device.

[0056] Embodiment 2

[0057] The embodiment provides a preparation method of a high UIS avalanche tolerance power VDMOSFET device, as shown in the figure, comprising the following steps: Figure 9

[0058] S1, preparing an N-type substrate region 100 required by the high UIS avalanche tolerance power VDMOSFET device, the ion doping concentration of which is 5×10 18 cm -3 ;

[0059] S2, forming an N-type drift region 101 on the upper surface of the N-type substrate region 100 by one-time chemical vapor deposition epitaxy, the doping concentration of which is 6×10 15 cm -3 , which can ensure that the breakdown voltage of the device plane junction is not less than 1500 V;

[0060] ​S3, forming a current spreading layer 105 on the upper surface of the N-type drift region 101 formed above by chemical vapor deposition epitaxy, with a doping concentration of 1×10 17 cm -3 , which can reduce the on-resistance of the device and in turn reduce the heat generated when current flows through the JFET region;

[0061] S4, injecting a mask on the current spreading layer 105 with a thickness of 30-200 nm, and forming a P-type high-concentration shielding layer 106 connected to the source 201 by multiple ion implantation, the presence of the mask can effectively suppress the channeling effect caused by ion implantation, and better control the implantation depth;

[0062] S5, forming the trench with good anisotropy by plasma etching under the blocking of the mask using slotting technology, the trench is on both sides of the top of the N-type drift region 101;

[0063] S6, sequentially forming a P-type light-concentration doped base region 102, an N-type high-concentration source region 104, and a P-type high-concentration doped region 103 on the trench by ion implantation;

[0064] S7, performing high-temperature dry oxygen oxidation on the device obtained above to form a high-quality gate oxide layer 300, then depositing polysilicon and doping phosphorus to form a gate 400 after etching;

[0065] S8, depositing high-melting-point metal nickel or metal titanium on the semiconductor device obtained above after metal contact opening, and then annealing to form a source 201 and a drain 200 with good ohmic contact characteristics.

[0066] Specifically, as shown in the cell structure Figure 3 corresponding to the above steps S1-S4: first make an N-type substrate region 100, then form an N-type drift region 101 on the upper surface of the N-type substrate region 100 by one-time epitaxy, then form a current spreading layer 105 (CSL) on the upper surface of the N-type drift region 101 by one-time epitaxy, and then form a P-type high-concentration shielding layer 106 on the upper surface of the current spreading layer 105 by multiple ion implantation; wherein the total thickness of the N-type drift region 101 is 10.6 μm, and the ion doping concentration ranges from 6×10 15 cm -3 to 8×10 15 cm -3 , which can make the breakdown voltage of the device planar node always higher than 1500V;

[0067] Specifically, the thickness of the current spreading layer 105 is 0.6 μm, the width is 1.15 μm, and the ion doping concentration ranges from 8×10 16 cm-3 Up to 2×10 17 cm -3 , Select 1×10 17 cm -3 The optimal ion doping concentration can effectively reduce the on-resistance and on-loss of the device, reduce the heat generated when current flows through the JFET region, and has no adverse effect on the breakdown of the device, thus significantly improving the reliability of the device.

[0068] Specifically, the P-type high-concentration shielding layer 106 has a thickness of 0.3 μm and a width of 2.3 μm. This size protects the gate oxide layer 300 when absorbing hot carriers without increasing the on-resistance of the device due to the formation of an excessively large depletion region. The ion doping concentration of the P-type high-concentration shielding layer 106 is 1 × 10⁻⁶. 19 cm -3 This concentration can form an ohmic contact electrode connecting the source electrode and also shield the electric field of the gate oxide layer 300, thereby improving the reliability of the gate oxide layer 300, and will not affect the breakdown voltage of the device due to an excessively large depletion region.

[0069] like Figure 4 The cellular structure shown corresponds to step S5 above, that is, using conventional grooving techniques, in the obtained... Figure 3 Two trenches are etched on both sides of the top of the epitaxial wafer of the structure shown. The depth of the trenches ranges from 0.3μm to 0.6μm. The device achieves the best performance when the trench depth is 0.6μm, that is, the charge in the drift region can be exhausted without affecting the breakdown voltage, and the conduction characteristics of the device will not be significantly affected at this thickness.

[0070] like Figure 5 and Figure 6 The cell structure shown corresponds to step S6 above, that is, in the obtained above... Figure 4 In the trench of the structure shown, the implantation region is formed by multiple ion implantations. The formation sequence is as follows: first, a P-type lightly doped base region 102 is formed by implantation from the top of the trench; then, an N-type high-concentration source region 104 is formed by implantation from the top of the trench; and finally, a P-type high-concentration doped region 103 is formed by implantation from the outside of the trench inward.

[0071] Specifically, the width of the P-type lightly doped base region 102 is 2.1 μm, the junction depth of the doped base region is 1.0 μm, and the peak ion doping concentration ranges from 1 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3The doping concentration in this range not only keeps the threshold voltage of the device within a reasonable range, but also gives the device a high avalanche tolerance. Furthermore, the high doping concentration of the P-type lightly doped base region 102 can suppress device punch-through and reduce the parasitic resistance of the P-type lightly doped base region 102, thereby increasing the threshold voltage for parasitic BJT triggering.

[0072] Specifically, the P-type high-concentration doped region 103 has a width of 1.2 μm, an effective depth of 0.8 μm, and a peak ion doping concentration range of 1 × 10⁻⁶. 20 cm -3 Up to 2×10 20 cm -3 High doping concentration is beneficial to the formation of ohmic contacts with low contact resistance, and at the same time, it avoids the depletion of the lightly doped P-type base region 102 to a certain extent, thereby improving the breakdown voltage of the device.

[0073] like Figure 7 The cell structure shown corresponds to step S7 above, that is, in the obtained above... Figure 6 Above the trench of the structure shown, a gate region is formed by a high-temperature oxidation device. The gate region includes a gate 400 and a gate oxide layer 300. The gate oxide layer 300 is made of silicon dioxide and surrounds the gate 400. The thickness of the gate oxide layer 300 and the sidewall oxide layer of the device is 0.05 μm. The gate oxide layer 300 can be further improved by forming an oxide layer with high interface quality through dry oxidation at 1300 degrees Celsius.

[0074] like Figure 8 The cell structure shown corresponds to step S8 above, that is, in the obtained above... Figure 7 The device shown has a source 201 formed at the top of the device by metallization to connect the trench and the functional region, and a drain 200 formed at the bottom of the device to connect the N-type substrate region 100.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high UIS avalanche tolerance power VDMOSFET device characterized in that, Comprise: N-type substrate region (100); N-type drift region (101), the N-type drift region (101) is on the upper surface of the N-type substrate region (100); Injection region, the injection region is in the groove on both sides above the N-type drift region (101), comprising: P-type light concentration doped base region (102), P-type high concentration doped region (103) and N-type high concentration source region (104), the N-type high concentration source region (104) is between the P-type light concentration doped base region (102) and the P-type high concentration doped region (103); Functional region, the functional region is in the middle above the N-type drift region (101), comprising: current spreading layer (105) and P-type high concentration shielding layer (106), the current spreading layer (105) is below the P-type high concentration shielding layer (106); The sum of the height of both is equal to the height of the gate region; Gate region is also provided with two groups, above the two groups of injection region respectively, the two groups of gate regions are connected through the functional region, and the source (201) is connected above; Gate region, the gate region is on both sides of the functional region, comprising: gate oxide layer (300) and gate (400), the gate oxide layer (300) surrounds the four sides of the gate (400); a source electrode (201) connected above the gate region and the functional region; a drain electrode (200) connected below the N-type substrate region (100); the current spreading layer (105) in the functional region has a thickness of 0.6 um, a width of 1.15 um, and an ion doping concentration ranging from 8x10 16 cm -3 to 2x10 17 cm -3 ; The thickness of the P-type high concentration shielding layer (106) is 0.3 um, the width is 1.15 um, the peak value of ion doping concentration is 1x10 19 cmm -3 .

2. The high UIS avalanche tolerance power VDMOSFET device of claim 1, wherein, The depth of the groove where the injection region is located ranges from 0.3um to 0.6um; The width of the P-type light concentration doped base region (102) is 2.1 μm, the depth is 1.0 μm, the peak value of ion doping concentration ranges from 1x10 17 cm -3 to 5x10 18 cm -3 ; the width of the P-type high concentration doped region (103) is 1.2 μm, the depth is 0.8 μm, the peak value of ion doping concentration ranges from 1x10 20 cm -3 to 2x10 20 cm -3 .

3. The high UIS avalanche tolerance power VDMOSFET device of claim 1, wherein, The total thickness of the N-type drift region (101) is 10.6 μm, and the ion doping concentration ranges from 6 x 1014cm-3to 8 x 1014cm-3. 15 cm -3 -3. 15 cm -3 -3.

4. The high UIS avalanche tolerance power VDMOSFET device of claim 1, wherein, The thickness of the gate oxide layer (300) is 0.05μm.

5. The method of claim 1 to 4, wherein the method is characterized by, Comprise the following steps: S1, prepare the N-type substrate region (100) required for the power VDMOSFET device with high UIS avalanche resistance; S2, form the N-type drift region (101) on the upper surface of the N-type substrate region (100) by once chemical vapor deposition epitaxy; S3, form the current spreading layer (105) on the upper surface of the N-type drift region (101) again by chemical vapor deposition epitaxy; S4, inject mask plate on the current spreading layer (105) above 30nm to 200nm thickness, form P-type high concentration shielding layer (106) by multiple ion implantation; S5, form the groove on both sides of the top of the N-type drift region (101) by using plasma etching method under the block of the mask plate by using slotting technology; S6, form P-type light concentration doped base region (102), N-type high concentration source region (104) and P-type high concentration doped region (103) in sequence on the groove by ion implantation; S7, the obtained device is subjected to high temperature dry oxygen oxidation, and the gate oxide layer (300) is formed above the groove, and then the gate (400) is formed after depositing polysilicon and doping phosphorus etching; S8, after the above obtained semiconductor device is subjected to metal contact opening, deposit high melting point metal nickel or metal titanium, and then anneal to form the source (201) and the drain (200) with ohmic contact characteristics.

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