Rram bottom electrode structure and method of forming the same

Abstract

The application provides a RRAM lower electrode structure and a forming method thereof, and the method comprises the following steps: taking a planarized first metal / dielectric layer as a substrate, and exposing the surface of the first metal / dielectric layer to the first metal in whole or in part; infiltrating the first metal / dielectric layer with silane at a preset infiltration temperature to form a first metal silicide layer on the surface of the first metal; forming a continuous and planar dielectric stop layer on the first metal silicide layer; forming a RRAM cell lower electrode on the surface of the dielectric stop layer; and forming a RRAM cell on the RRAM cell lower electrode after metal surface planarization treatment. By using the application, the adhesion of the first metal and the silicon-based dielectric layer interface can be effectively improved, so that the electromigration and stress migration characteristics of the first metal are further improved, the reliability and yield of the device are improved, the process flow is simplified, the process cycle is shortened, and the process cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and more particularly to a RRAM bottom electrode structure and a forming method thereof. BACKGROUND

[0002] Resistive Random Access Memory (RRAM) is one of the strong competitors to replace the Floating Gate (FG) memory due to its high programming / erasing speed, high device density, scalability, low power consumption, radiation resistance, data retention after power-off, and compatibility with CMOS (Complementary Metal-Oxide Semiconductor) process, etc. As a memory using a non-charge storage mechanism, RRAM has great development space in high-end applications at 32 nm process node and below.

[0003] At present, the RRAM memory cell is embedded between the back-end metals, i.e., a pattern for a lower metal (Mx) wire / metal hole / metal contact is formed on a dielectric layer and planarized (CMP, Chemical Mechanical Polishing), then a dielectric layer is covered, a bottom electrode (BE) of the RRAM memory cell, a resistive layer, and an upper electrode are sequentially formed by a damascene process, a pattern for an upper metal (Mx+1) wire / metal hole / metal contact is formed and planarized, and finally, the back-end multi-layer metal interconnection is realized.

[0004] In the existing RRAM bottom electrode metal forming process, the adhesion and the cohesion between the dielectric film layer and the metal material are often poor, which leads to the problems of forming a cavity, a crack, and even peeling of the film layer. On the one hand, it may cause product scrap, machine pollution, and delay of the running cycle; on the other hand, the poor adhesion and cohesion between the dielectric film layer and the metal material easily lead to the problems of electro-migration (EM) and stress-migration (SM) of the metal Cu, and the reliability and stability of the device are not good.

[0005] To solve the above problems, Figure 1 and Figure 2 respectively show two existing RRAM bottom electrode metal forming processes, in which Figure 1 and Figure 2 1, 12, and 14 are grids, 2 and 4 are lower metals, 5 is an etching stop layer, 6 is a dielectric layer, and 16 is a cap layer.

[0006] As shown in Figure 1 , in a prior art RRAM bottom electrode structure, a lower metal 2 is first formed on a dielectric layer 6, and then a silane soaking is performed on the planarized surface with partial metal and dielectric exposed in a heated and non-plasma environment before depositing an etch stop layer (ESL) 5, so that the Cu silicide is formed on the Cu surface by the thermal diffusion of SiH4 molecules, so as to form a good adhesion between the subsequently grown silicon-based thin film material and the Cu surface. However, the silane soaking only diffuses in a thin layer (e.g. <2nm) of Cu surface, and not only the thickness uniformity is difficult to control, but also the thin layer of Cu silicide is prone to pinholes due to various reasons such as surface defect states, back-end process thermal budget control, etc., thereby resulting in limited effects of improving the adhesion of metal / dielectric layer interface and preventing Cu diffusion; if the silane soaking time is long enough or the silane diffuses deeply into the Cu, the process cycle is too long, and the Cu silicide has a higher resistance than Cu, and the formation of the silicide consumes part of the Cu material, which is a more and more prominent problem with the evolution of technology and CD shrinkage.

[0007] In Figure 2 , in the RRAM bottom electrode structure, a cobalt (Co) cap layer 16 which is not prone to electromigration or stress migration is grown on the exposed Cu surface by selective growth on the planarized surface with partial metal and dielectric exposed, so as to prevent the upward migration of metal Cu. Compared with the structure shown in Figure 1 , the average time to failure (MTTF) of the interconnection structure shown in Figure 2 is significantly increased, the stress-induced void defects are significantly reduced, and the parasitic capacitance is also reduced. However, on the one hand, in order to reduce the parasitic capacitance between metals; on the other hand, due to the characteristics of the selective growth process, the cap layer is often formed only on the surface of the metal Cu, which leads to a weak point between the metal cap and the diffusion barrier layer of the metal sidewall, and Cu atoms still diffuse out from there, resulting in problems in the reliability and stability of the device. SUMMARY

[0008] In view of the above problems, the present application aims to provide a novel RRAM lower electrode structure and a forming method thereof, wherein before a surface of a metal layer is infiltrated with silane SiH4, the metal surface is treated with a high-reducing gas, and then a dielectric material layer required for forming a lower electrode of an RRAM cell is deposited, so as to effectively improve the adhesion of Cu and a silicon-based dielectric layer interface.

[0009] According to an aspect of the present application, there is provided a forming method of an RRAM lower electrode structure, comprising: taking a planarized first metal / dielectric layer as a substrate, and exposing a surface of the first metal / dielectric layer to the first metal in whole or in part;

[0010] infiltrating the first metal / dielectric layer with silane at a preset infiltration temperature, so as to form a first metal silicide layer on the surface of the first metal;

[0011] forming a continuous and planar dielectric stop layer on the first metal silicide layer;

[0012] forming a lower electrode of an RRAM cell on the surface of the dielectric stop layer;

[0013] after performing a metal surface planarization treatment on the lower electrode of the RRAM cell, forming an RRAM cell on the lower electrode.

[0014] Optionally, before infiltrating the first metal / dielectric layer with silane, the method further comprises: removing impurities on the surface of the first metal / dielectric layer with a reducing gas; and the reducing gas is one or a combination of H2, HF, NH3, and H2S.

[0015] Optionally, while infiltrating the surface of the first metal with silane at the preset infiltration temperature, the method further comprises: infiltrating the first metal / dielectric layer with silane at the preset infiltration temperature, so as to form silane adsorption and silicon islands on the surface of the dielectric layer.

[0016] Optionally, the preset temperature is 50-500°C.

[0017] Optionally, the method of forming the dielectric stop layer comprises: forming a continuous and planar silicon-based dielectric film on the first metal silicide layer as the dielectric stop layer by introducing a precursor for forming the dielectric stop layer; and the precursor is introduced in a growth / filling manner.

[0018] Optionally, after forming the dielectric stop layer, the method further comprises: performing a surface planarization treatment on the dielectric stop layer by CMP.

[0019] Optionally, the method for forming the RRAM cell lower electrode on the surface of the dielectric stop layer comprises the following steps: forming the RRAM cell lower electrode on the surface of the dielectric stop layer by using the steps of mask layer deposition, photolithography, etching and metal material filling.

[0020] Optionally, the metal material is one or a combination of any of W, TiN, Co, Ni, Ru, Ti and Al.

[0021] Optionally, before and after the metal material is filled, an annealing treatment in H2 atmosphere at 50-500℃ is performed to remove the natural oxide on the exposed Cu surface and repair the defect states on the sidewall surface of the dielectric stop layer which is etched.

[0022] According to another aspect of the present application, there is also provided a RRAM lower electrode structure formed by the above-mentioned method for forming the RRAM lower electrode structure.

[0023] By using the above-mentioned method for forming the RRAM lower electrode structure and the RRAM lower electrode structure according to the present application, the adhesion between the first metal and the silicon-based dielectric layer interface can be effectively improved by treating the metal surface with a high-reducing gas before the metal layer surface is infiltrated with silane and then depositing the dielectric material layer required for forming the RRAM cell lower electrode, so that the electromigration and stress migration properties of the first metal are further improved, the reliability of the device is effectively improved, the yield is improved, the process flow is simplified, the process cycle is shortened and the process cost is reduced.

[0024] To the accomplishment of the foregoing and related ends, one or more aspects of the application comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the application. These aspects are indicative, however, of but a few of the various ways in which the principles of the application can be employed. Other aspects and advantages of the application will be apparent from the following detailed description and the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0025] Other objects and results of the application will become more fully apparent from the following detailed description, taken in conjunction with the accompanying drawings, upon examination of the described principles of the application. In the drawings:

[0026] Figure 1 An existing RRAM lower electrode metal forming process is shown;

[0027] Figure 2 Another existing RRAM lower electrode metal forming process is shown;

[0028] Figure 3A flow chart of a method of forming a RRAM lower electrode structure according to an embodiment of the present application is shown.

[0029] Figure 4 A schematic diagram of a RRAM lower electrode structure according to an embodiment of the present application is shown.

[0030] The same reference numbers in all the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0031] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It can be evident, however, that such embodiment(s) can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

[0032] To overcome the above-mentioned problems in the existing RRAM lower electrode metal forming process, improve the interface adhesion of the first metal / dielectric layer, and improve the reliability and stability of the device on the basis of shortening the process cycle, the present application proposes a new RRAM lower electrode structure and a method of forming the same. Before the surface of the metal layer is infiltrated with silane (SiH4), the surface of the metal layer is treated with a highly reducing gas, and then a dielectric material layer required for forming the lower electrode of the RRAM cell is deposited.

[0033] In the following, specific embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0034] Figure 3 A flow chart of a method of forming a RRAM lower electrode structure according to an embodiment of the present application is shown.

[0035] As shown in Figure 3 the method of forming the RRAM electrode structure provided in the present embodiment comprises the following steps:

[0036] S310: using the planarized first metal / dielectric layer as a substrate, so that the surface of the first metal / dielectric layer is fully or partially exposed to the first metal.

[0037] To embed the RRAM cell (resistive random access memory storage unit) between the back-end metals, a pattern for the lower layer metal wire / metal hole / metal contact is first formed on the dielectric layer and planarized, and then the planarized first metal / dielectric layer is used as a substrate, so that the surface of the metal layer is fully or partially exposed to the first metal (for example, Cu, Co, Ti, Ni, etc., which can react with silane).

[0038] After the first metal is exposed on the surface of the metal layer, the first metal / dielectric layer surface can be cleaned by removing impurities, especially natural oxide layer, with a reducing gas (e.g. one or a combination of H2, HF, NH3, H2S, etc.) to facilitate the attachment of silicide in the later infiltration process.

[0039] S320: Infiltrate the first metal / dielectric layer with silane at a pre-set infiltration temperature to form a first metal silicide layer on the surface of the first metal.

[0040] Specifically, as an example, the first metal / dielectric layer can be infiltrated with silane (SiH4) at an atmosphere of 50-500°C to form a first metal silicide layer (e.g. copper silicide) on the surface of the first metal, and silane adhesion and silicon islands on the surface of the dielectric layer.

[0041] S330: Form a continuous and planar dielectric stop layer on the first metal silicide layer.

[0042] Specifically, as an example, a continuous and planar silicon-based dielectric film can be formed on the first metal silicide layer as the dielectric stop layer by introducing a precursor containing Si (e.g. SiH4, TEOS, etc.) to form a silicon-based dielectric stop layer. The precursor can be introduced in a growth / filling manner, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal growth, etc.

[0043] To facilitate the later formation of the lower electrode, the dielectric stop layer can be further planarized by CMP after the dielectric stop layer is formed.

[0044] S340: Form a RRAM Cell lower electrode on the surface of the dielectric stop layer.

[0045] Specifically, the RRAM Cell bottom electrode (BE) can be formed on the surface of the silicon-based dielectric film as the dielectric stop layer by lithography, etching, filling and other steps. More specifically, the RRAM Cell bottom electrode can be formed on the surface of the dielectric stop layer by the steps of deposition through a mask layer, lithography, etching, and filling of a metal material, wherein the metal for filling of the metal material can be one or a combination of any of W, TiN, Co, Ni, Ru, Ti, and Al.

[0046] In addition, before and after filling of the metal material, the formed bottom electrode structure can also be subjected to an annealing treatment in a H2 atmosphere at 50-500°C to remove the natural oxide on the exposed surface of the first metal and repair the defect states on the sidewall surface of the etched dielectric stop layer.

[0047] S350: After the metal surface planarization treatment of the RRAM Cell bottom electrode, a RRAM Cell is formed thereon.

[0048] The RRAM bottom electrode structure formed by the above process flow can effectively improve the adhesion of the first metal to the interface of the silicon-based dielectric layer, thereby further improving the electromigration and stress migration properties of the first metal, effectively improving the reliability of the device, improving the yield, while simplifying the process flow, shortening the process cycle, and reducing the process cost.

[0049] The process flow of the method for forming the RRAM bottom electrode structure of the present application will be described in detail below in combination with specific examples.

[0050] Example 1 of the process flow:

[0051] Step 1: Taking the planarized first metal / dielectric layer as a substrate, the first metal Cu is exposed on the surface of the metal layer in whole or in part, and the impurities on the surface of the first metal / dielectric layer, especially the natural oxide layer, are removed by reducing gas H2;

[0052] Step 2: In an atmosphere at 100°C±5°C, the surface of the metal / dielectric layer is infiltrated with silane to form a thin layer of Cu silicide, silane adsorption and silicon islands;

[0053] Step 3: A continuous and flat dielectric stop layer is formed on the thin layer of Cu silicide by physical vapor deposition of a precursor, which can be a dielectric stop layer formed of SiN, SiC, SiON, SiCN, SiOCN, etc.

[0054] Step 4: The bottom electrode of the RRAM Cell is formed on the surface of the dielectric stop layer by the steps of deposition through a mask layer, lithography, etching, and filling of a metal material;

[0055] Step 5: Planarization of the formed RRAM Cell bottom electrode metal surface, then form RRAM Cell on it.

[0056] Flowchart of Example 2:

[0057] Step 1: Use the planarized first metal / dielectric layer as the base, the metal layer surface is fully or partially exposed to the first metal (such as Cu, Co, Ti, Ni, etc. which can react with silane), remove the impurities on the surface of the first metal / dielectric layer with reducing gas HF, especially the native oxide layer;

[0058] Step 2: In an atmosphere of 200°C±5°C, use silane to infiltrate the surface of the first metal layer to form a thin layer of Cu Silicide;

[0059] Step 3: Use atomic layer deposition to pass in the precursor to form a continuous and flat dielectric stop layer on the Cu Silicide thin layer, which can be a dielectric stop layer formed by SiN, SiC, SiON, SiCN, SiOCN, etc. materials;

[0060] Step 4: Form the bottom electrode of the RRAM Cell on the surface of the dielectric stop layer through Mask Layer deposition, photolithography, etching, metal material filling, etc. Before and after filling BE Metal, H2 atmosphere annealing (Anneal) can be performed at 50°C-500°C, which can remove the native oxide on the exposed Cu surface and repair the defect states on the sidewall surface of the etched Stop Layer;

[0061] Step 5: Planarization of the formed RRAM Cell bottom electrode metal surface, then form RRAM Cell on it.

[0062] Flowchart of Example 3:

[0063] Step 1: Use the planarized first metal / dielectric layer as the base, the metal layer surface is fully or partially exposed to the first metal (such as Cu, Co, Ti, Ni, etc. which can react with silane), remove the impurities on the surface of the first metal / dielectric layer with reducing gas NH3, especially the native oxide layer;

[0064] Step 2: In an atmosphere of 300°C±10°C, use silane to infiltrate the surface of the first metal layer to form a thin layer of Cu Silicide;

[0065] Step 3: pass the precursor in a thermal growth manner to form a continuous and flat dielectric stop layer on the Cu Silicide thin layer, which can be a dielectric stop layer formed by SiN, SiC, SiON, SiCN, SiOCN, etc.

[0066] Step 4: form the lower electrode of the RRAM cell on the surface of the dielectric stop layer through Mask Layer deposition, photolithography, etching, metal material filling, etc. Before and after filling the BE Metal, an H2 atmosphere annealing treatment (Anneal) at 50-500 DEG C can be performed to remove the natural oxide on the exposed Cu surface and repair the defect states on the sidewall surface of the Stop Layer.

[0067] Step 5: perform a planarization treatment on the metal surface of the formed lower electrode of the RRAM cell, and then form the RRAM cell thereon.

[0068] Embodiment 4 of the flow:

[0069] Step 1: take the planarized first metal / dielectric layer as a bottom, and expose the first metal (for example, Cu, Co, Ti, Ni, etc. which can react with silane) on the surface of the metal layer in whole or in part, to remove impurities on the surface of the first metal / dielectric layer, especially the natural oxide layer, by using a reducing gas H2S;

[0070] Step 2: soak the surface of the first metal layer with silane at an atmosphere of 400 DEG C ± 10 DEG C to form a Cu Silicide thin layer;

[0071] Step 3: pass the precursor in an atomic layer deposition manner to form a continuous and flat dielectric stop layer on the Cu Silicide thin layer, which can be a dielectric stop layer formed by SiN material;

[0072] Step 4: form the lower electrode of the RRAM cell on the surface of the dielectric stop layer through Mask Layer deposition, photolithography, etching, metal material filling, etc. Before and after filling the BE Metal, an H2 atmosphere annealing treatment (Anneal) at 50-500 DEG C can be performed to remove the natural oxide on the exposed Cu surface and repair the defect states on the sidewall surface of the Stop Layer.

[0073] Step 5: perform a planarization treatment on the metal surface of the formed lower electrode of the RRAM cell, and then form the RRAM cell thereon.

[0074] In addition, the application also provides a RRAM lower electrode structure formed by using the above process flow. Figure 4A structural diagram of a RRAM bottom electrode structure according to an embodiment of the present application is shown.

[0075] As shown in Figure 4 The RRAM bottom electrode structure provided by the present embodiment includes a base layer (Base) as the lowermost layer, a first metal / dielectric layer (IMD1) formed on the base layer, a dielectric stop layer (Stop Layer) formed on the first metal / dielectric layer, a RRAM Cell bottom electrode (BE) formed on the dielectric stop layer, a RRAM Cell formed on the RRAM Cell bottom electrode, and a second dielectric layer (IMD2) finally filled and formed.

[0076] The RRAM bottom electrode structure and the forming method thereof according to the present application are described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various modifications can be made to the RRAM bottom electrode structure and the forming method thereof according to the present application described above without departing from the content of the present application. Therefore, the protection scope of the present application should be determined by the content of the appended claims.

Claims

1. A method for forming a RRAM bottom electrode structure, comprising: using a planarized first metal / dielectric layer as a substrate, and exposing a surface of the first metal / dielectric layer entirely or partially to the first metal; removing impurities on the surface of the first metal / dielectric layer by a reducing gas; immersing the first metal / dielectric layer in silane at a preset immersion temperature to form a first metal silicide layer on the surface of the first metal and to form silane adsorption and silicon islands on the surface of the dielectric layer; forming a continuous and planar dielectric stop layer on the first metal silicide layer; forming a RRAM Cell bottom electrode on the surface of the dielectric stop layer by steps of deposition, photolithography, etching and filling of a metal material through a mask layer; and forming a RRAM Cell on the RRAM Cell bottom electrode after a metal surface planarization treatment. 2.The method for forming a RRAM bottom electrode structure according to claim 1, wherein the reducing gas is one or a combination of H 2, HF, NH 3 and H 2S.

3. The method of forming a RRAM bottom electrode structure of claim 2, wherein, the preset immersion temperature is 50-500 ℃.

4. The method of forming a RRAM bottom electrode structure as claimed in claim 1, wherein, the method for forming the dielectric stop layer comprises forming a continuous and planar silicon-based dielectric film as the dielectric stop layer on the first metal silicide layer by introducing a precursor for forming the dielectric stop layer, and the precursor is introduced in a growth / filling manner.

5. The method of forming a RRAM bottom electrode structure as claimed in claim 1, wherein, after forming the dielectric stop layer, the method further comprises performing a surface planarization treatment on the dielectric stop layer by CMP. 6.The method for forming a RRAM bottom electrode structure according to claim 1, wherein the metal material is one or a combination of W, TiN, Co, Ni, Ru, Ti and Al.

7. The method of forming a RRAM bottom electrode structure as claimed in claim 3, wherein, before and after filling the metal material, an annealing treatment in a H 2 atmosphere at 50-500 ℃ is performed to remove natural oxides on the exposed surface of the first metal and to repair defect states on the sidewall surface of the etched dielectric stop layer. 8.A RRAM bottom electrode structure formed by the method for forming a RRAM bottom electrode structure according to any one of claims 1-7.

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