Switching converter, controller and control method thereof

Abstract

The application discloses a switching converter, a controller and a control method thereof. The controller comprises a hysteresis value generating circuit, a switch control circuit and a frequency locking circuit. The hysteresis value generating circuit generates an upper limit value and a lower limit value of hysteresis according to an output voltage of the switching converter. The switch control circuit generates a switch control signal according to a current sampling signal representing a current flowing through a main switch tube in the switching converter, the upper limit value and the lower limit value of hysteresis to control the turn-on and turn-off of the main switch tube. The frequency locking circuit adjusts the upper limit value or the lower limit value of hysteresis according to the switch control signal and a clock signal. When the input voltage changes greatly, the output voltage can be stabilized, the switching frequency can be basically constant, and the electromagnetic interference can be reduced.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more specifically, to a switching converter, its controller, and control method. Background Technology

[0002] Fixed-frequency peak current control is a commonly used control method for switching converters. Under fixed-frequency peak current control, the feedback signal representing the switching converter output signal and the reference voltage are fed into an error amplifier to generate a compensation signal. The main transistor is turned on when the clock signal arrives and turned off when the current sampling signal representing the current flowing through it increases to the compensation signal. Due to the internal delay of the control circuit, there is a minimum on-time; the main transistor can only be turned off after its on-time reaches the minimum on-time.

[0003] As the input voltage of the switching converter increases, the on-time of the main transistor decreases. Due to the existence of a minimum on-time, the on-time of the main transistor cannot be reduced further after reaching this minimum. At this point, the output voltage rises, resulting in a larger ripple in the output voltage. Summary of the Invention

[0004] Therefore, the purpose of this invention is to solve the above-mentioned technical problems of the prior art and to propose a switching converter, its controller and control method.

[0005] According to an embodiment of the present invention, a controller for a switching converter is provided. The switching converter includes a main switching transistor. The controller includes: a hysteresis value generation circuit that generates an upper hysteresis limit and a lower hysteresis limit based on the output voltage of the switching converter; a switching control circuit that provides a switching control signal to control the main switching transistor, wherein in a first mode, the switching control circuit controls the turn-on time of the main switching transistor by comparing a current sampling signal representing the current flowing through the main switching transistor with the lower hysteresis limit and controls the turn-off time of the main switching transistor by comparing the current sampling signal with the upper hysteresis limit; and in a second mode, the switching control circuit controls the turn-on time of the main switching transistor according to a clock signal and controls the turn-off time of the main switching transistor according to the current sampling signal; and a frequency locking circuit that adjusts the upper hysteresis limit or the lower hysteresis limit based on the switching control signal and the clock signal.

[0006] According to an embodiment of the present invention, a controller for a switching converter is provided. The switching converter includes a main switching transistor. The controller includes: a hysteresis value generation circuit that generates an upper hysteresis limit and a lower hysteresis limit based on the output voltage of the switching converter; a switching control circuit coupled to the hysteresis value generation circuit that generates a switching control signal based on a current sampling signal representing the current flowing through the main switching transistor, the upper hysteresis limit, and the lower hysteresis limit to control the on and off states of the main switching transistor, wherein the current sampling signal is compared with the upper hysteresis limit to control the off-time of the main switching transistor, and the current sampling signal is compared with the lower hysteresis limit to control the on-time of the main switching transistor; and a frequency locking circuit that adjusts the upper hysteresis limit or the lower hysteresis limit based on the switching control signal and a clock signal.

[0007] According to an embodiment of the present invention, a switching converter is also proposed, including the controller described above.

[0008] According to an embodiment of the present invention, a control method for a switching converter is also proposed. The switching converter includes a main switching transistor. The control method includes: generating an upper hysteresis limit and a lower hysteresis limit based on the output voltage of the switching converter; when the switching converter is in a first mode, generating a switching control signal based on a current sampling signal representing the current flowing through the main switching transistor, the upper hysteresis limit, and the lower hysteresis limit to control the on and off of the main switching transistor, wherein the current sampling signal is compared with the upper hysteresis limit to control the off time of the main switching transistor, and the current sampling signal is compared with the lower hysteresis limit to control the on time of the main switching transistor; and adjusting the upper hysteresis limit or the lower hysteresis limit based on the switching control signal and a clock signal.

[0009] According to embodiments of the present invention, when the input voltage varies greatly, it is possible to ensure the stability of the output voltage and achieve a basically constant switching frequency, thereby reducing electromagnetic interference. Attached Figure Description

[0010] To better understand this invention, it will be described in detail with reference to the following figures:

[0011] Figure 1 This is a block diagram of a switching converter 100 according to an embodiment of the present invention;

[0012] Figure 2 This is a circuit diagram of the switch control circuit 12 according to an embodiment of the present invention;

[0013] Figure 3 This is a circuit diagram of a switch control circuit 12 according to another embodiment of the present invention;

[0014] Figure 4 This is a circuit diagram of the hysteresis value generation circuit 13 according to an embodiment of the present invention;

[0015] Figure 5 This is a circuit diagram of the hysteresis value generation circuit 13 according to another embodiment of the present invention;

[0016] Figure 6 This is a circuit diagram of a switching converter 100 according to an embodiment of the present invention;

[0017] Figure 7 This is a flowchart of a control method 700 for a switching converter according to an embodiment of the present invention.

[0018] In the accompanying drawings, the same or corresponding reference numerals are used to denote the same or corresponding elements. Detailed Implementation

[0019] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0020] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “coupled to” or “connected to” another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly coupled to” or “directly connected to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Figure 1 This is a block diagram of a switching converter 100 according to an embodiment of the present invention. Figure 1In the illustrated embodiment, the switching converter 100 includes a switching circuit 11, a controller 20, a current sampling circuit 15, and a feedback circuit 16. The switching circuit 11 includes a main switch transistor, receives the input voltage Vin, and converts the input voltage Vin into an output voltage Vo. The switching circuit 11 can employ any suitable topology, such as a buck converter, boost converter, buck-boost converter, flyback converter, etc. The feedback circuit 16 is coupled to the switching circuit, samples the output voltage Vo of the switching circuit, and generates a voltage feedback signal FB representing the output voltage. The current sampling circuit 15 samples the current flowing through the main switch transistor and generates a current sampling signal Vcs representing the current flowing through the main switch transistor.

[0022] The controller 20 includes a switch control circuit 12, a hysteresis value generation circuit 13, and a frequency locking circuit 14. The hysteresis value generation circuit 13 generates an upper hysteresis limit value Vthh and a lower hysteresis limit value Vthl based on the output voltage Vo. The switch control circuit 12 provides a switch control signal PWM to control the main switch transistor. In one embodiment, the switch control circuit 12 is coupled to the hysteresis value generation circuit 13 and generates the switch control signal PWM based on the current sampling signal Vcs, the upper hysteresis limit value Vthh, and the lower hysteresis limit value Vthl to control the turn-on and turn-off of the main switch transistor. The current sampling signal Vcs is compared with the upper hysteresis limit value Vthh to control the turn-off time of the main switch transistor, and the current sampling signal Vcs is compared with the lower hysteresis limit value Vthl to control the turn-on time of the main switch transistor. In another embodiment, when the switching converter 100 is in a first mode, the switching control circuit 12 controls the turn-on time of the main switch by comparing the current sampling signal Vcs with the hysteresis lower limit Vthl, and controls the turn-off time of the main switch by comparing the current sampling signal Vcs with the hysteresis upper limit Vthh. When the switching converter 100 is in a second mode, the switching control circuit 12 controls the turn-on time of the main switch according to the clock signal CLK, and controls the turn-off time of the main switch according to the current sampling signal Vcs. The first mode includes cases where the input voltage changes, such as, but not limited to, the startup process of the switching converter 100. The second mode includes cases where the input voltage remains constant, such as, but not limited to, after the switching converter 100 has finished starting. The switching converter according to this embodiment can smoothly switch between the first and second modes without sudden changes or jitter in the switching frequency or output voltage. The frequency locking circuit 14 adjusts the hysteresis upper limit Vthh or the hysteresis lower limit Vthl according to the switching control signal PWM and the clock signal CLK, such that the frequency of the switching control signal PWM is equal to the frequency of the clock signal CLK. In one embodiment, the frequency locking circuit 14 generates a hysteresis adjustment signal Fadj based on the difference between the frequency of the switching control signal PWM and the frequency of the clock signal CLK to adjust the upper limit of the hysteresis Vthh or the lower limit of the hysteresis Vthl.

[0023] According to the embodiments of the present invention, the switching converter can effectively prevent the main transistor from reaching its minimum conduction time when the input voltage changes significantly, thus ensuring the stability of the output voltage Vo, and can also achieve a basically constant switching frequency, thereby reducing electromagnetic interference.

[0024] Figure 2 This is a circuit diagram of the switch control circuit 12 according to an embodiment of the present invention. Figure 2 In the illustrated embodiment, the switch control circuit 12 includes a selection circuit 121 and a comparison circuit 122. The selection circuit 121 receives a hysteresis upper limit value Vthh, a hysteresis lower limit value Vthl, and a selection signal Sel. The selection circuit 121 selects either the output hysteresis upper limit value Vthh or the hysteresis lower limit value Vthl as the current reference signal Iref based on the selection signal Sel. In one embodiment, the selection signal Sel is generated based on the switch control signal PWM. The comparison circuit 122 generates the switch control signal PWM by comparing the current sampling signal Vcs and the current reference signal Iref. In one embodiment, when the switch control signal PWM controls the main switch to remain off, the selection signal Sel selects the hysteresis lower limit value Vthl as the current reference signal Iref, and the comparison circuit 122 generates the switch control signal PWM based on the comparison result of the current sampling signal Vcs and the hysteresis lower limit value Vthl to control the turn-on time of the main switch. In one embodiment, when the PWM control signal keeps the main switch on, the selection signal Sel selects the hysteresis upper limit value Vthh as the current reference signal Iref. The comparator circuit 122 generates the PWM control signal based on the comparison result between the current sampling signal Vcs and the hysteresis upper limit value Vthh to control the turn-off time of the main switch. Figure 2 In the illustrated embodiment, the comparator circuit 122 includes a first input terminal for receiving a current sampling signal Vcs, a second input terminal for receiving a current reference signal Iref, and an output terminal for providing a switch control signal PWM. In one embodiment, the selection signal Sel is the inverted signal of the switch control signal PWM. For example, the switch control signal PWM is received by an inverter 123 and inverted to generate the selection signal Sel.

[0025] Figure 3 This is a circuit diagram of a switch control circuit 12 according to another embodiment of the present invention. Figure 3In the illustrated embodiment, the output of the comparator circuit 122 provides a control signal Ct1, and the switch control circuit 12 further includes a trigger circuit 123 and a selection circuit 124. The trigger circuit 123 includes a set terminal S, a reset terminal R, and an output terminal Q. Its set terminal S receives a clock signal CLK, its reset terminal is coupled to the comparator circuit 122 to receive the first control signal Ct1, and its output terminal generates a control signal Ct2. The selection circuit 124 is coupled to the comparator circuit 122 and the trigger circuit 123, and generates a switch control signal PWM based on the control signals Ct1 and Ct2. In one embodiment, the selection circuit 124 receives a mode indication signal SSOK. In one embodiment, when the mode indication signal SSOK is in a first state, for example, a low level, it indicates that the switch converter 100 is in a first mode; when the mode indication signal SSOK is in a second state, for example, a high level, it indicates that the switch converter 100 is in a second mode. In one embodiment, when the mode indicator signal SSOK is in a first state, the selection circuit 124 selects the control signal Ct1 as the switch control signal PWM; when the mode indicator signal SSOK is in a second state, the selection circuit 124 selects the control signal Ct2 as the switch control signal PWM. In one embodiment, the switch control circuit 12 further includes a logic circuit 125. The logic circuit 125 includes, for example, a NOR gate. The first input of the logic circuit 125 receives the mode indicator signal SSOK, the second input of the logic circuit 125 receives the inverted signal of the switch control signal PWM, and the output of the logic circuit 125 provides a selection signal Sel based on the inverted signal of the switch control signal PWM and the mode indicator signal SSOK. In one embodiment, when the switching converter 100 is in a second mode, the selection circuit Sel selects the hysteresis lower limit value Vthl as the current reference signal Iref, and the comparison circuit 122 generates the control signal Ct1 by comparing the current sampling signal Vcs with the hysteresis lower limit value Vthl to control the turn-off time of the main switch. In another embodiment, when the switching converter 100 is in the second mode, the selection circuit Sel selects the upper hysteresis limit Vthh as the current reference signal Iref, and the comparator circuit 122 generates a control signal Ct1 based on the comparison between the current sampling signal Vcs and the upper hysteresis limit Vthh to control the turn-off time of the main switch. In one embodiment, when the switching converter 100 is in the first mode and the main switch remains off under the control of the switching control signal PWM, the selection circuit Sel selects the lower hysteresis limit Vthl as the current reference signal Iref, and the comparator circuit 122 controls the turn-on time of the main switch based on the comparison result between the current sampling signal Vcs and the lower hysteresis limit Vthl.In another embodiment, when the switching converter 100 is in the first mode and the main switch is kept on under the control of the switching control signal PWM, the selection circuit Sel selects the hysteresis upper limit value Vthh as the current reference signal Iref, and the comparison circuit 122 controls the turn-off time of the main switch according to the comparison result of the current sampling signal Vcs and the hysteresis upper limit value Vthh.

[0026] Figure 4 This is a circuit diagram of a hysteresis value generation circuit 13 according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the hysteresis value generation circuit 13 includes an error circuit 131, a controllable current source 132, and a resistor 133. Figure 4 In the illustrated embodiment, the error circuit 131 includes an error amplifier. The error circuit 131 includes a first input terminal, a second input terminal, and an output terminal. Its first input terminal receives a voltage feedback signal FB, and its second input terminal receives a voltage reference signal Vref. The error circuit 131 generates an error signal EAO at its output terminal based on the difference between the voltage feedback signal FB and the voltage reference signal Vref. Figure 4 In the illustrated embodiment, the error signal EAO serves as the lower hysteresis limit Vthl. The controllable current source 132, under the control of the hysteresis adjustment signal Fadj, adjusts its output current based on the difference between the frequency of the switching control signal PWM and the frequency of the clock signal CLK. Resistor 133 includes a first terminal and a second terminal. The first terminal of resistor 133 is coupled to the output terminal of the error circuit 131, and the second terminal of resistor 133 is coupled to the controllable current source 132. The output current of the controllable current source 132 flows through resistor 133, and resistor 133 provides the upper hysteresis limit Vthh at its second terminal.

[0027] Figure 5 This is a circuit diagram of a hysteresis value generation circuit 13 according to another embodiment of the present invention. Figure 5 In the illustrated embodiment, the hysteresis value generation circuit 13 includes an error circuit 131, a controllable current source 135, and a resistor 134. Figure 5 In the illustrated embodiment, the error signal EAO serves as the upper hysteresis limit Vthh. The controllable current source 135, under the control of the hysteresis adjustment signal Fadj, adjusts its output current based on the difference between the frequency of the switching control signal PWM and the frequency of the clock signal CLK. Resistor 134 includes a first terminal and a second terminal; the first terminal of resistor 134 is coupled to the output of the error circuit 131, and the second terminal of resistor 134 is coupled to the controllable current source 135. The output current of the controllable current source 135 flows through resistor 134, and resistor 134 provides the lower hysteresis limit Vthl at its second terminal.

[0028] Figure 6This is a circuit diagram of a switching converter 100 according to an embodiment of the present invention. Figure 6 In the illustrated embodiment, the switching circuit 11 in the switching converter 100 is a synchronous buck circuit, including an input capacitor Cin, switching transistors S1 and S2, an inductor L, and an output capacitor Cout, connected as follows: Figure 6 As shown. The main switching transistor of the switching converter 100 includes, for example, switching transistor S1 or switching transistor S2. The feedback circuit 16 includes a resistor divider composed of resistors R3 and R4. The current sampling circuit 15 samples the current flowing through switching transistor S1 to obtain a current sampling signal Vcs. Those skilled in the art will understand that the current sampling circuit 15 can also sample the current flowing through switching transistor S2 to obtain a current sampling signal Vcs. The switching control signal PWM controls switching transistors S1 and S2 through the drive circuit 61.

[0029] Figure 7 The flowchart of a control method 700 for a switching converter according to an embodiment of the present invention includes steps S11 to S14.

[0030] In step S11, the upper limit and lower limit of the hysteresis loop are generated based on the output voltage of the switching converter.

[0031] In step S12, when the switching converter is in the first mode, a switching control signal is generated based on the current sampling signal representing the current flowing through the main switch, the upper limit of the hysteresis loop, and the lower limit of the hysteresis loop to control the turn-on and turn-off of the main switch. The current sampling signal is compared with the upper limit of the hysteresis loop to control the turn-off time of the main switch, and the current sampling signal is compared with the lower limit of the hysteresis loop to control the turn-on time of the main switch.

[0032] In step S13, when the switching converter is in the second mode, a switching control signal is generated based on the clock signal and the current sampling signal. The clock signal controls the turn-on time of the main switch, and the current sampling signal is compared with the upper or lower hysteresis limit to control the turn-off time of the main switch.

[0033] In step S14, the upper and lower limits of the hysteresis loop are adjusted according to the switch control signal and the clock signal, so that the frequency of the switch control signal is equal to the frequency of the clock signal.

[0034] It should be noted that the execution order of the steps in the flowchart above is not limited to... Figure 7 As shown, two consecutive function blocks can be executed simultaneously or in reverse order.

[0035] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A controller for a switching converter, the switching converter including a main switching transistor, the controller comprising: The hysteresis value generation circuit generates the upper and lower hysteresis limits based on the output voltage of the switching converter. A switching control circuit provides a switching control signal to control a main switching transistor, wherein in a first mode, the switching control circuit controls the turn-on time of the main switching transistor by comparing a current sampling signal representing the current flowing through the main switching transistor with a hysteresis lower limit and controls the turn-off time of the main switching transistor by comparing the current sampling signal with a hysteresis upper limit; and in a second mode, the switching control circuit controls the turn-on time of the main switching transistor according to a clock signal and controls the turn-off time of the main switching transistor according to the current sampling signal. as well as The frequency locking circuit adjusts the upper or lower limit of the hysteresis loop based on the switch control signal and the clock signal.

2. The controller as claimed in claim 1, wherein the frequency locking circuit adjusts the upper or lower hysteresis limit based on the difference between the frequency of the switch control signal and the frequency of the clock signal.

3. The controller of claim 1, wherein the hysteresis value generation circuit further comprises: The error circuit generates an error signal at its output as the upper limit of the hysteresis loop based on the difference between the voltage feedback signal and the voltage reference signal, which represent the output voltage. A controllable current source that adjusts its output current based on the difference between the frequency of the switch control signal and the frequency of the clock signal; as well as A resistor has a first terminal and a second terminal. The first terminal of the resistor is coupled to the output of an error circuit, and the second terminal of the resistor is coupled to a controllable current source. The resistor provides a hysteresis lower limit at its second terminal.

4. The controller of claim 1, wherein the hysteresis value generation circuit further comprises: The error circuit generates an error signal at its output as the lower limit of the hysteresis loop based on the difference between the voltage feedback signal and the voltage reference signal, which represent the output voltage. A controllable current source that adjusts its output current based on the difference between the frequency of the switch control signal and the frequency of the clock signal; as well as A resistor has a first terminal and a second terminal. The first terminal of the resistor is coupled to the output of an error circuit, and the second terminal of the resistor is coupled to a controllable current source. The resistor provides a hysteresis upper limit value at its second terminal.

5. The controller of claim 1, wherein the switch control circuit further comprises: The comparator circuit generates a switch control signal based on the current sampling signal, the upper limit of the hysteresis loop, and the lower limit of the hysteresis loop. The comparator circuit controls the turn-off time of the main switch based on the comparison result of the current sampling signal and the upper limit of the hysteresis loop, and controls the turn-on time of the main switch based on the comparison result of the current sampling signal and the lower limit of the hysteresis loop.

6. The controller of claim 1, wherein the switch control circuit further comprises: The comparator circuit generates a first control signal based on the current sampling signal, the upper limit of the hysteresis loop, and the lower limit of the hysteresis loop. The trigger circuit includes a set terminal, a reset terminal, and an output terminal. Its set terminal receives the clock signal, its reset terminal receives a first control signal, and its output terminal generates a second control signal. as well as The selection circuit generates a switching control signal based on the first control signal and the second control signal. in When the switching converter is in the first mode, the selection circuit selects the first control signal as the switching control signal, and when the switching converter is in the second mode, the selection circuit selects the second control signal as the switching control signal.

7. The controller of claim 6, wherein when the switching converter is in the first mode and the main switch is kept on under the control of the switching control signal, the comparator circuit generates the switching control signal based on the comparison result of the current sampling signal and the hysteresis upper limit value to control the turn-off time of the main switch.

8. The controller of claim 6, wherein when the switching converter is in the first mode and the main switch is kept off under the control of the switching control signal, the comparator circuit generates the switching control signal based on the comparison result of the current sampling signal and the hysteresis lower limit value to control the turn-on time of the main switch.

9. A controller for a switching converter, the switching converter including a main switching transistor, the controller comprising: The hysteresis value generation circuit generates the upper and lower hysteresis limits based on the output voltage of the switching converter. A switching control circuit, coupled to a hysteresis value generation circuit, generates a switching control signal based on a current sampling signal representing the current flowing through the main switch, an upper hysteresis value, and a lower hysteresis value to control the on and off states of the main switch. The current sampling signal is compared with the upper hysteresis value to control the off-time of the main switch, and the current sampling signal is compared with the lower hysteresis value to control the on-time of the main switch. The frequency locking circuit adjusts the upper or lower limit of the hysteresis loop based on the switch control signal and a clock signal.

10. The controller of claim 9, wherein the frequency locking circuit adjusts the upper or lower hysteresis limit based on the difference between the frequency of the switch control signal and the frequency of the clock signal.

11. The controller of claim 9, wherein the hysteresis value generation circuit further comprises: The error circuit generates an error signal at its output as the upper limit of the hysteresis loop based on the difference between the voltage feedback signal and the voltage reference signal, which represent the output voltage. A controllable current source that adjusts its output current based on the difference between the frequency of the switch control signal and the frequency of the clock signal; as well as A resistor has a first terminal and a second terminal. The first terminal of the resistor is coupled to the output of an error circuit, and the second terminal of the resistor is coupled to a controllable current source. The resistor provides a hysteresis lower limit at its second terminal.

12. The controller of claim 9, wherein the hysteresis value generation circuit further comprises: The error circuit generates an error signal at its output as the lower limit of the hysteresis loop based on the difference between the voltage feedback signal and the voltage reference signal, which represent the output voltage. A controllable current source that adjusts its output current based on the difference between the frequency of the switch control signal and the frequency of the clock signal; as well as A resistor has a first terminal and a second terminal. The first terminal of the resistor is coupled to the output of an error circuit, and the second terminal of the resistor is coupled to a controllable current source. The resistor provides a hysteresis upper limit value at its second terminal.

13. A switching converter, comprising: A switching circuit, including a main transistor, converts the input voltage into an output voltage; The feedback circuit is coupled to the switching circuit, samples the output voltage of the switching circuit, and generates a voltage feedback signal representing the output voltage. The current sampling circuit samples the current flowing through the main transistor and generates a current sampling signal representing the current flowing through the main transistor. as well as The controller as described in any one of claims 1 to 12.

14. A control method for a switching converter, the switching converter including a main switching transistor, the control method comprising: Based on the output voltage of the switching converter, generate the upper and lower limits of the hysteresis loop; When the switching converter is in the first mode, a switching control signal is generated based on a current sampling signal representing the current flowing through the main switch, an upper hysteresis limit, and a lower hysteresis limit to control the on and off of the main switch. The current sampling signal is compared with the upper hysteresis limit to control the off-time of the main switch, and the current sampling signal is compared with the lower hysteresis limit to control the on-time of the main switch. Adjust the upper or lower limit of the hysteresis loop based on the switch control signal and a clock signal.

15. The control method of claim 14, further comprising: When the switching converter is in the second mode, a switching control signal is generated based on the clock signal and the current sampling signal. The clock signal controls the turn-on time of the main switching transistor, and the current sampling signal controls the turn-off time of the main switching transistor.

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