Control logic circuit for a dc-dc converter and dc-dc converter

Abstract

Embodiments of the present disclosure provide a control logic circuit for a DC-DC converter, which comprises a trigger control circuit, a first trigger circuit, and a second trigger circuit. The trigger control circuit is configured to generate a trigger control signal according to a PWM signal of the DC-DC converter, a valley value current limiting indication signal of the DC-DC converter, and a clock signal, and provide the trigger control signal to the first trigger circuit and the second trigger circuit. The trigger control signal is at an inactive level when the clock signal is at an active level. The first trigger circuit is configured to generate a freewheeling tube turn-on trigger signal according to the trigger control signal and the clock signal, and output the freewheeling tube turn-on trigger signal from an output end of the first trigger circuit. The second trigger circuit is configured to generate a power tube turn-on trigger signal according to the trigger control signal and the clock signal, and output the power tube turn-on trigger signal from an output end of the second trigger circuit. The power tube turn-on trigger signal and the freewheeling tube turn-on trigger signal are complementary signals.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to control logic circuits for DC-DC converters and DC-DC converters. Background Technology

[0002] With the rapid development of the integrated circuit industry and the expanding analog integrated circuit market, DC-DC (direct-to-direct-current) converters have also received widespread attention and rapid development. As a high-efficiency switching power supply technology, DC-DC converters have advantages such as fast dynamic response, simple control, and direct control of output current. In a DC-DC converter, the power transistor and freewheeling transistor alternately conduct to control the charging and discharging of the inductor, thereby achieving a stable output. A current detection circuit can be incorporated into the DC-DC converter. When the inductor current flowing through it is too high, charging of the inductor can be stopped by controlling the power transistor and freewheeling transistor. Charging of the inductor is allowed to resume when the inductor current drops to its lowest current-limiting value. Summary of the Invention

[0003] The embodiments described herein provide a control logic circuit for a DC-DC converter and a DC-DC converter.

[0004] According to a first aspect of this disclosure, a control logic circuit for a DC-DC converter is provided. The control logic circuit includes a trigger control circuit, a first trigger circuit, and a second trigger circuit. The trigger control circuit is configured to generate a trigger control signal based on the PWM signal of the DC-DC converter, a valley current limiting indication signal of the DC-DC converter, and a clock signal from a clock signal terminal, and provide the trigger control signal to the first and second trigger circuits via a first node. The trigger control signal is at an inactive level when the clock signal is at an active level. The first trigger circuit is configured to generate a freewheeling diode conduction trigger signal based on the trigger control signal and the clock signal, and output the freewheeling diode conduction trigger signal from its output terminal. The second trigger circuit is configured to generate a power transistor conduction trigger signal based on the trigger control signal and the clock signal, and output the power transistor conduction trigger signal from its output terminal. The power transistor conduction trigger signal and the freewheeling diode conduction trigger signal are inverse signals.

[0005] In some embodiments of this disclosure, the control logic circuit further includes a clock leading edge delay circuit. The clock leading edge delay circuit is configured to delay the falling edge of the clock signal to generate a clock leading edge delay signal, and output the clock leading edge delay signal from its output terminal to a first trigger circuit and a second trigger circuit. The period of the clock leading edge delay signal is equal to the period of the clock signal.

[0006] In some embodiments of this disclosure, the trigger control circuit includes a NAND gate and a first inverter. A first input of the NAND gate is provided with a PWM signal. A second input of the NAND gate is coupled to the output of the first inverter. A third input of the NAND gate is coupled to a clock signal. The output of the NAND gate is coupled to a first node. A valley current limiting indication signal is provided at the input of the first inverter.

[0007] In some embodiments of this disclosure, the first triggering circuit includes a first RS flip-flop. The set terminal of the first RS flip-flop is coupled to a clock signal terminal. The reset terminal of the first RS flip-flop is coupled to a first node. The output terminal of the first RS flip-flop serves as the output terminal of the first triggering circuit. The effective level for triggering the first RS flip-flop is a low level.

[0008] In some embodiments of this disclosure, the first triggering circuit includes a first RS flip-flop. The set terminal of the first RS flip-flop is coupled to the output of a clock leading-edge delay circuit. The reset terminal of the first RS flip-flop is coupled to a first node. The output of the first RS flip-flop serves as the output of the first triggering circuit. The effective level for triggering the first RS flip-flop is a low level.

[0009] In some embodiments of this disclosure, the second trigger circuit includes a second RS flip-flop. The set terminal of the second RS flip-flop is coupled to the first node. The reset terminal of the second RS flip-flop is coupled to a clock signal terminal. The output terminal of the second RS flip-flop serves as the output terminal of the second trigger circuit. The effective level for triggering the second RS flip-flop is a low level.

[0010] In some embodiments of this disclosure, the second trigger circuit includes a second RS flip-flop. The set terminal of the second RS flip-flop is coupled to the first node. The reset terminal of the second RS flip-flop is coupled to the output of the clock leading edge delay circuit. The output of the second RS flip-flop serves as the output of the second trigger circuit. The effective level for triggering the second RS flip-flop is a low level.

[0011] According to a second aspect of this disclosure, a control logic circuit for a DC-DC converter is provided. The control logic circuit includes: a NAND gate, a first inverter, a first RS flip-flop, and a second RS flip-flop. The first input of the NAND gate is provided with a PWM signal for the DC-DC converter. The second input of the NAND gate is coupled to the output of the first inverter. The third input of the NAND gate is coupled to a clock signal. The output of the NAND gate is coupled to the reset terminal of the first RS flip-flop and the set terminal of the second RS flip-flop. The input of the first inverter is provided with a valley current limiting indication signal for the DC-DC converter. The set terminal of the first RS flip-flop is coupled to the clock signal. A freewheeling diode turn-on trigger signal is output from the output of the first RS flip-flop. The effective level for triggering the first RS flip-flop is low. The reset terminal of the second RS flip-flop is coupled to the clock signal. A power transistor turn-on trigger signal is output from the output of the second RS flip-flop. The effective level for triggering the second RS flip-flop is low.

[0012] In some embodiments of this disclosure, the control logic circuit further includes a clock leading edge delay circuit. The input terminal of the clock leading edge delay circuit is coupled to a clock signal terminal. The output terminal of the clock leading edge delay circuit is coupled to the set terminal of a first RS flip-flop and the reset terminal of a second RS flip-flop. The clock leading edge delay circuit is configured to delay the falling edge of the clock signal to generate a clock leading edge delay signal, and to output the clock leading edge delay signal from its output terminal. The period of the clock leading edge delay signal is equal to the period of the clock signal.

[0013] According to a third aspect of this disclosure, a DC-DC converter is provided, comprising: control logic circuitry as described in the first or second aspect of this disclosure.

[0014] In some embodiments of this disclosure, the DC-DC converter is a boost converter. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0016] Figure 1 An exemplary circuit diagram of a DC-DC converter;

[0017] Figure 2 It is used for Figure 1 The timing diagram of some signals of the DC-DC converter shown is shown.

[0018] Figure 3 This is an exemplary circuit diagram of a DC-DC converter according to embodiments of the present disclosure;

[0019] Figure 4 It is used for Figure 3 The timing diagram of some signals of the DC-DC converter shown is shown.

[0020] Figure 5 This is another exemplary circuit diagram of a DC-DC converter according to embodiments of the present disclosure; and

[0021] Figure 6 It is used for Figure 5 The timing diagram shows some signals of the DC-DC converter.

[0022] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1An exemplary circuit diagram of a DC-DC converter 100 is shown. This DC-DC converter 100 is a fixed-frequency valley current-mode boost converter. The DC-DC converter 100 includes: an error amplifier EA, a PWM comparator CP1, a capacitor Cc, a resistor Rc, a resistor Rs, a transistor MN2, a current source I, a NAND gate NAND, a first inverter NG, a second inverter NG2, a first RS flip-flop LH1, a second RS flip-flop LH2, a freewheeling diode minimum on-time control circuit 110, a power transistor minimum on-time control circuit 120, a freewheeling diode MH, a power transistor ML, an inductor L, and an output capacitor Cout. Figure 1 The load resistance Rload is also shown.

[0027] exist Figure 1In the example, the error amplifier EA generates an error signal eaout based on the output voltage Vout of the DC-DC converter 100 and the reference voltage VREF. The error signal eaout is provided to the inverting input of the PWM comparator CP1. The non-inverting input of the PWM comparator CP1 is coupled to the current source I and the resistor Rs via node sum. The current value of the current source I is Idc-Isns, where Idc represents the constant current value and Isns represents the inductance current flowing through the inductor L. When the freewheeling diode turn-on control signal HG is low, the transistor MN2 is turned on, and the voltage at node sum is pulled low to ground, so the PWM signal output by the PWM comparator CP1 is low. Thus, the output signal MAIN_TRIP of the NAND gate is high. When the clock signal CLK flips to an active level (low level), the freewheeling diode turn-on trigger signal HT output by the first RS flip-flop LH1 becomes high, and the power transistor turn-on trigger signal LT output by the second RS flip-flop LH2 becomes low. The high-level freewheeling diode turn-on trigger signal HT causes the freewheeling diode turn-on control signal HG output by the freewheeling diode minimum conduction time control circuit 110 to become high, thereby turning on the freewheeling diode MH. The freewheeling diode turn-on control signal HG is maintained at an effective level (high level) for at least the minimum conduction time controlled by the freewheeling diode minimum conduction time control circuit 110. The low-level power transistor turn-on trigger signal LT causes the power transistor turn-on control signal LG output by the power transistor minimum conduction time control circuit 120 to become low, thereby turning off the power transistor ML. Therefore, the inductor L discharges, and the inductor current flowing through the inductor L gradually decreases. At this time, because the freewheeling diode turn-on control signal HG is high, transistor MN2 is cut off, and the current provided by current source I flows through resistor Rs, thereby forming a voltage at node sum. The voltage at node sum becomes (Idc - Isns) × Rs, where Rs represents the resistance value of resistor Rs. When the voltage at node sum is greater than the voltage value of the error signal eaout, the PWM signal output by PWM comparator CP1 is at a high level.

[0028] exist Figure 1In the example, LIM represents the valley current limiting indicator signal. When the inductor current IL decreases and is equal to or lower than the valley current limiting value VY_LIM, the valley current limiting indicator signal LIM is low. Otherwise, the valley current limiting indicator signal LIM is high. When the valley current limiting indicator signal LIM is low, the output signal MAIN_TRIP of the NAND gate toggles low. The effective levels triggering the first RS flip-flop LH1 and the second RS flip-flop LH2 are both low. When the clock signal CLKB is high, the freewheeling transistor turn-on trigger signal HT toggles low, and the power transistor turn-on trigger signal LT toggles high. In this situation, the power transistor ML is turned on and the freewheeling transistor MH is turned off, the inductor L charges, and the inductor current flowing through inductor L gradually increases.

[0029] However, Figure 1 The DC-DC converter 100 shown is susceptible to a logic race hazard. This hazard occurs when the output signal MAIN_TRIP of the NAND gate flips low while the clock signal CLKB is also low (see [link]). Figure 2 At time t1, the set and reset terminals of the first RS flip-flop LH1 and the second RS flip-flop LH2 will be simultaneously at a low level. Due to the internal design of the first RS flip-flop LH1 and the second RS flip-flop LH2, the reset capability of the reset terminal will be stronger than the set capability of the set terminal. Therefore, the first RS flip-flop LH1 and the second RS flip-flop LH2 will simultaneously output a low level, thereby turning off the freewheeling transistor MH and the power transistor ML at the same time. The freewheeling transistor turn-on control signal HG, which is at a low level, controls the transistor MN2 to turn on. Therefore, the PWM signal becomes low, thereby causing MAIN_TRIP to flip to a high level. The body diode of the freewheeling transistor MH will continue to freewheel until the clock signal CLKB flips to a low level again at time t4, which will turn on the freewheeling transistor MH. After the minimum conduction time of the freewheeling transistor, the high level of the MAIN_TRIP signal at time t5 will turn on the power transistor ML, thereby causing the inductor current IL to start to rise. The logic race between the clock signal CLKB and the MAIN_TRIP signal causes the inductor current IL to drop significantly from time t1 to time t5. This will severely reduce the load capacity of the DC-DC converter 100.

[0030] Embodiments of this disclosure present a DC-DC converter. Figure 3 An exemplary circuit diagram of a DC-DC converter 300 according to an embodiment of the present disclosure is shown. The DC-DC converter 300 may include: an error amplifier circuit 350, a duty cycle modulation circuit 340, a control logic circuit 330, a freewheeling diode minimum on-time control circuit 310, a power transistor minimum on-time control circuit 320, a freewheeling diode MH, a power transistor ML, an inductor L, and an output capacitor Cout. Figure 3The load resistance Rload is also shown.

[0031] Error amplifier circuit 350 may include error amplifier EA, resistor Rc, and capacitor Cc. Error amplifier EA generates error signal eaout based on the output voltage Vout of DC-DC converter 100 and reference voltage VREF. Error signal eaout is provided to the input of duty cycle modulation circuit 340.

[0032] The duty cycle modulation circuit 340 may include a PWM comparator CP1, a resistor Rs, a transistor MN2, a current source I, and a second inverter NG2. The inverting input of the PWM comparator CP1 is coupled to the input of the duty cycle modulation circuit 340. The non-inverting input of the PWM comparator CP1 is coupled to the current source I and the resistor Rs via node sum. The current value of the current source I is Idc - Isns, where Idc represents a constant current value and Isns represents the inductance current flowing through the inductor L. A PWM signal is output from the output of the PWM comparator CP1. The control terminal of the transistor MN2 is coupled to the output of the second inverter NG2. The first terminal of the transistor MN2 is coupled to the second terminal of the resistor Rs and ground. The second terminal of the transistor MN2 is coupled to the first terminal of the resistor Rs and node sum. The input of the second inverter NG2 is provided with a freewheeling diode on-control signal HG.

[0033] The first input terminal of the control logic circuit 330 can be coupled to the output terminal of the duty cycle modulation circuit 340. The second input terminal of the control logic circuit 330 can be provided with the valley current limiting indication signal LIM of the DC-DC converter 300 (to avoid unnecessary details obscuring the subject matter of this disclosure, in...). Figure 3 (The circuit for generating the valley current limiting indication signal LIM is not shown in the example). The third input of the control logic circuit 330 can be coupled to the clock signal terminal CLKB. The first output of the control logic circuit 330 can be coupled to the input of the freewheeling diode minimum on-time control circuit 310. The second output of the control logic circuit 330 can be coupled to the input of the power transistor minimum on-time control circuit 320. The control logic circuit 330 may include: a trigger control circuit 331, a first trigger circuit 332, and a second trigger circuit 333.

[0034] The first input terminal of the trigger control circuit 331 can be coupled to the output terminal of the duty cycle modulation circuit 340. The second input terminal of the trigger control circuit 331 can be provided with the valley current limiting indication signal LIM of the DC-DC converter 300. The third input terminal of the trigger control circuit 331 can be coupled to the clock signal terminal CLKB. The output terminal of the trigger control circuit 331 can be coupled to the first input terminal of the first trigger circuit 332 and the second input terminal of the second trigger circuit 333 via the first node N1. The trigger control circuit 331 can be configured to generate a trigger control signal MAIN_TRIP based on the PWM signal of the DC-DC converter 300, the valley current limiting indication signal LIM of the DC-DC converter 300, and the clock signal CLKB from the clock signal terminal CLKB, and provide the trigger control signal MAIN_TRIP to the first trigger circuit 332 and the second trigger circuit 333 via the first node N1. The trigger control signal MAIN_TRIP is at an invalid level (high level) when the clock signal CLKB is at an active level (low level).

[0035] In some embodiments of this disclosure, the trigger control circuit 331 may include a NAND gate and a first inverter NG1. A first input terminal of the NAND gate is provided with a PWM signal. A second input terminal of the NAND gate is coupled to the output terminal of the first inverter NG1. A third input terminal of the NAND gate is coupled to a clock signal terminal CLKB. The output terminal of the NAND gate is coupled to a first node N1. A valley current limiting indication signal LIM is provided at the input terminal of the first inverter NG1.

[0036] The first input terminal of the first trigger circuit 332 can be coupled to the output terminal of the trigger control circuit 331 via the first node N1. The second input terminal of the first trigger circuit 332 can be coupled to the clock signal terminal CLKB. The output terminal of the first trigger circuit 332 can serve as the first output terminal of the control logic circuit 330. The first trigger circuit 332 can be configured to generate a freewheeling diode conduction trigger signal HT based on the trigger control signal MAIN_TRIP and the clock signal CLKB, and output the freewheeling diode conduction trigger signal HT from the output terminal of the first trigger circuit 332.

[0037] In some embodiments of this disclosure, the first trigger circuit 332 may include a first RS flip-flop LH1. The set terminal S of the first RS flip-flop LH1 is coupled to a clock signal terminal CLKB. The reset terminal R of the first RS flip-flop LH1 is coupled to a first node N1. The output terminal Q of the first RS flip-flop LH1 serves as the output terminal of the first trigger circuit 332. The effective level for triggering the first RS flip-flop LH1 is a low level. When the set terminal S of the first RS flip-flop LH1 receives a low-level signal and the reset terminal R of the first RS flip-flop LH1 receives a high-level signal, the first RS flip-flop LH1 outputs a high-level signal. When the set terminal S of the first RS flip-flop LH1 receives a high-level signal and the reset terminal R of the first RS flip-flop LH1 receives a low-level signal, the first RS flip-flop LH1 outputs a low-level signal. When the set terminal S of the first RS flip-flop LH1 receives a low-level signal and the reset terminal R of the first RS flip-flop LH1 receives a low-level signal, the first RS flip-flop LH1 outputs a low-level signal. When the set terminal S of the first RS flip-flop LH1 receives a high-level signal and the reset terminal R of the first RS flip-flop LH1 receives a high-level signal, the output of the first RS flip-flop LH1 remains unchanged from the previous state.

[0038] The first input terminal of the second trigger circuit 333 can be coupled to the clock signal terminal CLKB. The second input terminal of the second trigger circuit 333 can be coupled to the output terminal of the trigger control circuit 331 via the first node N1. The output terminal of the second trigger circuit 333 can serve as the second output terminal of the control logic circuit 330. The second trigger circuit 333 can be configured to generate a power transistor turn-on trigger signal LT based on the trigger control signal MAIN_TRIP and the clock signal CLKB, and output the power transistor turn-on trigger signal LT from the output terminal of the second trigger circuit 333. The power transistor turn-on trigger signal LT and the freewheeling diode turn-on trigger signal HT are inverted signals.

[0039] In some embodiments of this disclosure, the second trigger circuit 333 may include a second RS flip-flop LH2. The set terminal S of the second RS flip-flop LH2 is coupled to the first node N1. The reset terminal R of the second RS flip-flop LH2 is coupled to the clock signal terminal CLKB. The output terminal Q of the second RS flip-flop LH2 serves as the output terminal of the second trigger circuit 333. The effective level for triggering the second RS flip-flop LH2 is a low level. When the set terminal S of the second RS flip-flop LH2 receives a low-level signal and the reset terminal R of the second RS flip-flop LH2 receives a high-level signal, the second RS flip-flop LH2 outputs a high-level signal. When the set terminal S of the second RS flip-flop LH2 receives a high-level signal and the reset terminal R of the second RS flip-flop LH2 receives a low-level signal, the second RS flip-flop LH2 outputs a low-level signal. When the set terminal S of the second RS flip-flop LH2 receives a low-level signal and the reset terminal R of the second RS flip-flop LH2 receives a low-level signal, the second RS flip-flop LH2 outputs a low-level signal. When the set terminal S of the second RS flip-flop LH2 receives a high-level signal and the reset terminal R of the second RS flip-flop LH2 receives a high-level signal, the output of the second RS flip-flop LH2 remains unchanged from the previous state.

[0040] The input of the freewheeling diode minimum conduction time control circuit 310 can be coupled to the first output of the control logic circuit 330. The freewheeling diode minimum conduction time control circuit 310 is configured to continuously output a high-level freewheeling diode conduction control signal HG during the minimum conduction time of the freewheeling diode after receiving a high-level freewheeling diode conduction trigger signal HT.

[0041] The input of the power transistor minimum on-time control circuit 320 can be coupled to the second output of the control logic circuit 330. The power transistor minimum on-time control circuit 320 is configured to continuously output a high-level power transistor on-time control signal LG during the minimum on-time of the power transistor after receiving a high-level power transistor on-trigger signal LT.

[0042] The control terminal of the freewheeling diode MH can be coupled to the output terminal of the freewheeling diode minimum conduction time control circuit 310. The first terminal of the freewheeling diode MH can be coupled to the first terminal of the inductor L and the second terminal of the power transistor ML. The second terminal of the freewheeling diode MH can be coupled to the output terminal of the DC-DC converter 300.

[0043] The control terminal of power transistor ML can be coupled to the output of the power transistor minimum on-time control circuit 320. The first terminal of power transistor ML can be grounded.

[0044] The second terminal of inductor L can be coupled to the input voltage terminal Vin. The first terminal of output capacitor Cout can be coupled to the output terminal Vout. The second terminal of output capacitor Cout can be grounded.

[0045] exist Figure 3 In the example, the freewheeling transistor MH, the power transistor ML, and the transistor MN2 are all N-type transistors. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0046] Figure 4 Showing the use of Figure 3 The diagram shows the timing of some signals of the DC-DC converter. At time t1, the inductor current IL drops to the valley current limit value VY_LIM, so the valley current limit indicator signal LIM flips low. The PWM signal is high. At this time, the clock signal CLKB is low. Since the clock signal CLKB also controls the output signal MAIN_TRIP of the NAND gate, the output signal MAIN_TRIP of the NAND gate remains high. The low clock signal CLKB causes the freewheeling transistor turn-on trigger signal HT output from the first RS flip-flop LH1 to remain high and the power transistor turn-on trigger signal LT output from the second RS flip-flop LH2 to remain low. In this case, the freewheeling transistor MH remains on and the power transistor ML remains off.

[0047] When the clock signal CLKB flips to high level after time t1 (time t2), the output signal MAIN_TRIP of the NAND gate flips to low level. Therefore, the freewheeling transistor turn-on trigger signal HT output from the first RS flip-flop LH1 flips to low level, and the power transistor turn-on trigger signal LT output from the second RS flip-flop LH2 flips to high level. In this situation, the power transistor ML is turned on and the freewheeling transistor MH is turned off, the inductor L charges, and the inductor current flowing through inductor L gradually increases.

[0048] Figure 3 The DC-DC converter 300 shown avoids the risk of logic race hazards between the clock signal CLKB and the MAIN_TRIP signal, and the inductor current IL can exhibit regular ripple.

[0049] Figure 5 Another exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure is shown. Considering the potential delay between the output and input of a NAND gate, therefore, in Figure 5In the example, the control logic circuit 330 may further include a clock leading edge delay circuit 334. The clock leading edge delay circuit 334 may be coupled between the clock signal terminal CLKB and the set terminal S of the first RS flip-flop LH1 and the reset terminal R of the second RS flip-flop LH2. The clock leading edge delay circuit 334 may be configured to delay the falling edge of the clock signal CLKB to generate a clock leading edge delay signal CLKB_PRE, and output the clock leading edge delay signal CLKB_PRE from the output terminal of the clock leading edge delay circuit 334 to the first trigger circuit LH1 and the second trigger circuit LH2. The period of the clock leading edge delay signal CLKB_PRE is... Figure 5 The clock signals CLKB in the clock signals have the same period.

[0050] In some embodiments of this disclosure, the pulse width and phase of the clock leading edge delay signal CLKB_PRE are both... Figure 3 The clock signal CLKB is the same.

[0051] In some embodiments of this disclosure, the falling edge of the clock leading edge delay signal CLKB_PRE is relative to Figure 5 The falling edge delay time of the clock signal CLKB is a first preset time. The rising edge of the clock leading edge delay signal CLKB_PRE is relative to... Figure 5 The rising edge of the clock signal CLKB is advanced, and this advance time is also the first preset time.

[0052] exist Figure 5 In the example, the first trigger circuit 332 may include a first RS flip-flop LH1. The set terminal S of the first RS flip-flop LH1 is coupled to the output of the clock leading edge delay circuit 334. The reset terminal R of the first RS flip-flop LH1 is coupled to the first node N1. The output of the first RS flip-flop LH1 serves as the output of the first trigger circuit 332. The effective level for triggering the first RS flip-flop LH1 is a low level.

[0053] The second trigger circuit 333 may include a second RS flip-flop LH2. The set terminal S of the second RS flip-flop LH2 is coupled to the first node N1. The reset terminal R of the second RS flip-flop LH2 is coupled to the output of the clock leading edge delay circuit 334. The output of the second RS flip-flop LH2 serves as the output of the second trigger circuit 333. The effective level for triggering the second RS flip-flop LH2 is a low level.

[0054] Figure 6 Showing the use of Figure 5The diagram shows the timing of some signals of the DC-DC converter. At time t1, the inductor current IL drops to the valley current limit value VY_LIM, so the valley current limit indicator signal LIM flips low. The PWM signal is high. At this time, the clock signal CLKB is low. Since the clock signal CLKB also controls the output signal MAIN_TRIP of the NAND gate, the output signal MAIN_TRIP of the NAND gate remains high. The low-level clock leading edge delay signal CLKB_PRE keeps the freewheeling transistor turn-on trigger signal HT output from the first RS flip-flop LH1 high and the power transistor turn-on trigger signal LT output from the second RS flip-flop LH2 low. In this case, the freewheeling transistor MH remains on and the power transistor ML remains off.

[0055] Since the clock signal CLKB toggles to low before the clock leading edge delay signal CLKB_PRE, even if the NAND gate output is delayed, there will be no situation where a high level of the clock signal CLKB causes the output signal MAIN_TRIP to toggle to low while the clock leading edge delay signal CLKB_PRE is also low.

[0056] At time t3, the clock signal CLKB flips to a high level, and the output signal MAIN_TRIP of the NAND gate flips to a low level. At this time, the clock leading edge delay signal CLKB_PRE has already flipped to a high level before the clock signal CLKB. Therefore, even if the NAND gate has an output delay, its output signal MAIN_TRIP and the clock leading edge delay signal CLKB_PRE will not be at a low level simultaneously. At this time, the freewheeling transistor turn-on trigger signal HT output from the first RS flip-flop LH1 flips to a low level, and the power transistor turn-on trigger signal LT output from the second RS flip-flop LH2 flips to a high level. Under these conditions, the power transistor ML is turned on and the freewheeling transistor MH is turned off, the inductor L charges, and the inductor current flowing through inductor L gradually increases.

[0057] Figure 5 The DC-DC converter 300 shown can also avoid the risk of logic race conditions even when there is an output delay in the NAND gate. Therefore, the inductor current IL can exhibit regular ripple.

[0058] In summary, the control logic circuit for a DC-DC converter according to embodiments of this disclosure can avoid the risk of logic race conditions, ensuring that the power transistor and freewheeling transistor of the DC-DC converter do not turn off simultaneously. The DC-DC converter according to embodiments of this disclosure can output inductor current with regular ripple, thus improving load-carrying capacity.

[0059] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0060] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0061] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A control logic circuit for a DC-DC converter, comprising: The trigger control circuit, the first trigger circuit, and the second trigger circuit, The trigger control circuit is configured to generate a trigger control signal according to a PWM signal of the DC-DC converter, a valley current limit indication signal of the DC-DC converter, and a clock signal from a clock signal terminal, and provide the trigger control signal to the first trigger circuit and the second trigger circuit via a first node, wherein the trigger control signal is at an inactive level when the clock signal is at an active level, the valley current limit indication signal is at a low level when the inductor current drops and is equal to or lower than a valley current limit value, and the valley current limit indication signal is at a high level in other cases. The first trigger circuit is configured to generate a freewheeling tube conduction trigger signal according to the trigger control signal and the clock signal, and output the freewheeling tube conduction trigger signal from an output terminal of the first trigger circuit. The second trigger circuit is configured to generate a power tube conduction trigger signal according to the trigger control signal and the clock signal, and output the power tube conduction trigger signal from an output terminal of the second trigger circuit, wherein the power tube conduction trigger signal and the freewheeling tube conduction trigger signal are complementary signals. The trigger control circuit includes a NAND gate and a first inverter, The first input terminal of the NAND gate is provided with the PWM signal, the second input terminal of the NAND gate is coupled to the output terminal of the first inverter, the third input terminal of the NAND gate is coupled to the clock signal terminal, and the output terminal of the NAND gate is coupled to the first node. The input terminal of the first inverter is provided with the valley current limit indication signal.

2. The control logic circuit of claim 1, further comprising: The clock front edge delay circuit, The clock front edge delay circuit is configured to delay a falling edge of the clock signal to generate a clock front edge delay signal, and output the clock front edge delay signal from an output terminal of the clock front edge delay circuit to the first trigger circuit and the second trigger circuit. The period of the clock front edge delay signal is equal to the period of the clock signal.

3. The control logic circuit of claim 1, wherein, The first trigger circuit includes a first RS flip-flop, The set terminal of the first RS flip-flop is coupled to the clock signal terminal, the reset terminal of the first RS flip-flop is coupled to the first node, and the output terminal of the first RS flip-flop serves as the output terminal of the first trigger circuit. The active level for triggering the first RS flip-flop is a low level.

4. The control logic circuit of claim 2, wherein, The first trigger circuit includes a first RS flip-flop, The set terminal of the first RS flip-flop is coupled to the output terminal of the clock front edge delay circuit, the reset terminal of the first RS flip-flop is coupled to the first node, and the output terminal of the first RS flip-flop serves as the output terminal of the first trigger circuit. The active level for triggering the first RS flip-flop is a low level.

5. The control logic circuit of claim 1, wherein, The second trigger circuit includes a second RS flip-flop, The set end of the second RS flip-flop is coupled to the first node, and the reset end of the second RS flip-flop is coupled to the clock signal end. The active level for triggering the second RS flip-flop is a low level.

6. The control logic circuit of claim 2, wherein, The second trigger circuit comprises a second RS flip-flop, The set end of the second RS flip-flop is coupled to the first node, and the reset end of the second RS flip-flop is coupled to the output end of the clock front edge delay circuit. The active level for triggering the second RS flip-flop is a low level.

7. A control logic circuit for a DC-DC converter, comprising: The NAND gate, the first inverter, the first RS flip-flop, and the second RS flip-flop, The first input end of the NAND gate is provided with a PWM signal of the DC-DC converter, the second input end of the NAND gate is coupled to the output end of the first inverter, the third input end of the NAND gate is coupled to a clock signal end, and the output end of the NAND gate is coupled to the reset end of the first RS flip-flop and the set end of the second RS flip-flop. The input end of the first inverter is provided with a valley current limiting indication signal of the DC-DC converter, wherein the valley current limiting indication signal is at a low level when the inductor current drops and is equal to or lower than a valley current limiting value, and the valley current limiting indication signal is at a high level in other cases. The set end of the first RS flip-flop is coupled to the clock signal end, a freewheeling tube turn-on trigger signal is output from the output end of the first RS flip-flop, and the active level for triggering the first RS flip-flop is a low level. The reset end of the second RS flip-flop is coupled to the clock signal end, a power tube turn-on trigger signal is output from the output end of the second RS flip-flop, and the active level for triggering the second RS flip-flop is a low level.

8. The control logic circuit of claim 7, further comprising: The clock front edge delay circuit, The input end of the clock front edge delay circuit is coupled to the clock signal end, the output end of the clock front edge delay circuit is coupled to the set end of the first RS flip-flop and the reset end of the second RS flip-flop, and the clock front edge delay circuit is configured to delay the falling edge of the clock signal to generate a clock front edge delay signal and output the clock front edge delay signal from the output end of the clock front edge delay circuit. The period of the clock front edge delay signal is equal to the period of the clock signal.

9. A DC-DC converter comprising: The control logic circuit according to any one of claims 1 to 8.

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