Fixed on-time control circuit for DC-DC converter, and DC-DC converter

Abstract

Embodiments of the present disclosure provide a fixed on-time control circuit for a DC-DC converter, which includes: a freewheeling diode out-of-current-limiting detection circuit, a timing start control circuit, a fixed-time timing circuit, and a conduction control signal generation circuit. The freewheeling diode out-of-current-limiting detection circuit generates a first pulse signal according to the valley current-limiting indication signal of the DC-DC converter and the power transistor conduction control signal of the DC-DC converter. The timing start control circuit generates a timing control signal according to the first pulse signal, the valley current-limiting indication signal, and the timing arrival pulse signal output by the fixed-time timing circuit. The fixed-time timing circuit starts timing when the timing control signal indicates the start of timing, determines the timing duration according to the bandgap reference voltage from the bandgap reference voltage terminal, and provides a timing arrival pulse signal when the timing duration is reached. The conduction control signal generation circuit generates a conduction control signal according to the timing arrival pulse signal, the first pulse signal, and the clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and more particularly, to a fixed on-time control circuit for a DC-DC converter and a DC-DC converter. Background Art

[0002] With the rapid development of the integrated circuit industry and the growing expansion of the analog integrated circuit market, DC-DC (direct current to direct current) converters have received extensive attention and rapid development. As a highly efficient switching power supply technology, DC-DC converters have the advantages of fast dynamic response, simple control, and direct control of output current. In a DC-DC converter, a power transistor and a freewheeling diode conduct alternately to control the charging and discharging of an inductor in the DC-DC converter, thereby achieving a stable output of the DC-DC converter. A current detection circuit may be provided in the DC-DC converter. When the inductor current flowing through the inductor is too large, the charging of the inductor can be stopped by controlling the power transistor and the freewheeling diode. Charging of the inductor is allowed again when the inductor current drops to the valley current limit value. In this way, the function of overcurrent protection can be achieved. Summary of the Invention

[0003] Embodiments described herein provide a fixed on-time control circuit for a DC-DC converter and a DC-DC converter.

[0004] According to a first aspect of the present disclosure, there is provided a fixed on-time control circuit for a DC-DC converter. The fixed on-time control circuit includes: a freewheeling diode dropout current limit detection circuit, a timing start control circuit, a fixed-time timing circuit, and a conduction control signal generation circuit. Among them, the freewheeling diode dropout current limit detection circuit is configured to: generate a first pulse signal according to the valley current limit indication signal of the DC-DC converter and the power transistor conduction control signal of the DC-DC converter, and provide the first pulse signal to the timing start control circuit and the conduction control signal generation circuit via a first node. The timing start control circuit is configured to: generate a timing control signal according to the first pulse signal, the valley current limit indication signal, and the timing arrival pulse signal output by the fixed-time timing circuit, and provide the timing control signal to the fixed-time timing circuit via a second node. The fixed-time timing circuit is configured to: start timing when the timing control signal indicates timing start, determine the timing duration according to the bandgap reference voltage from the bandgap reference voltage terminal, and provide a timing arrival pulse signal to the timing start control circuit and the conduction control signal generation circuit via a third node when the timing duration is reached. The conduction control signal generation circuit is configured to: generate a conduction control signal according to the timing arrival pulse signal, the first pulse signal, and the clock signal from the clock signal terminal.

[0005] In some embodiments of the present disclosure, the clock signal has a fixed frequency.

[0006] In some embodiments of the present disclosure, the freewheeling diode exit current limiting detection circuit includes: a first monostable flip-flop and a NAND gate. Wherein, the input terminal of the first monostable flip-flop is provided with a valley current limiting indication signal. The output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate. The second input terminal of the NAND gate is provided with a power transistor conduction control signal. The output terminal of the NAND gate is coupled to the first node. The first monostable flip-flop is triggered at the rising edge of the valley current limiting indication signal from the first level to the second level to generate a second pulse signal.

[0007] In some embodiments of the present disclosure, the pulse width of the second pulse signal is equal to the period of the clock signal.

[0008] In some embodiments of the present disclosure, the timing start control circuit includes: a first OR gate. Wherein, the first input terminal of the first OR gate is coupled to the third node. The second input terminal of the first OR gate is coupled to the first node. The third input terminal of the first OR gate is provided with a valley current limiting indication signal. The output terminal of the first OR gate is coupled to the second node.

[0009] In some embodiments of the present disclosure, the fixed-time timing circuit includes: a constant current source, a capacitor, a first transistor, a voltage comparator, and a second monostable flip-flop. Wherein, the constant current source is configured to provide a constant current to the first end of the capacitor. The first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor. The second end of the capacitor is coupled to the first pole of the first transistor and the second voltage terminal. The control pole of the first transistor is coupled to the second node. The second input terminal of the voltage comparator is coupled to the bandgap reference voltage terminal. The output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop. The output terminal of the second monostable flip-flop is coupled to the third node. The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate a timing arrival pulse signal.

[0010] In some embodiments of the present disclosure, the pulse width of the timing arrival pulse signal is determined according to the discharge speed of the capacitor.

[0011] In some embodiments of the present disclosure, the conduction control signal generation circuit includes: an AND gate and a second OR gate. Wherein, the first input terminal of the AND gate is coupled to the first node. The second input terminal of the AND gate is coupled to the clock signal terminal. The output terminal of the AND gate is coupled to the first input terminal of the second OR gate. The second input terminal of the second OR gate is coupled to the third node.

[0012] According to a second aspect of the present disclosure, a fixed-on-time control circuit for a DC-DC converter is provided. The fixed-on-time control circuit includes: a first monostable flip-flop, a NAND gate, a first OR gate, a constant current source, a capacitor, a first transistor, a voltage comparator, a second monostable flip-flop, an AND gate, and a second OR gate. Among them, the input terminal of the first monostable flip-flop is provided with a valley current limit indication signal of the DC-DC converter. The output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate. The first monostable flip-flop is triggered at the rising edge of the valley current limit indication signal from the first level to the second level to generate a second pulse signal. The second input terminal of the NAND gate is provided with a power transistor conduction control signal of the DC-DC converter. The output terminal of the NAND gate is coupled to the second input terminal of the first OR gate. The first input terminal of the first OR gate is coupled to the output terminal of the second monostable flip-flop. The third input terminal of the first OR gate is provided with a valley current limit indication signal. The output terminal of the first OR gate is coupled to the control electrode of the first transistor. The constant current source is configured to provide a constant current to the first end of the capacitor. The first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor. The second end of the capacitor is coupled to the first pole of the first transistor and the second voltage terminal. The second input terminal of the voltage comparator is coupled to a bandgap reference voltage terminal. The output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop. The output terminal of the second monostable flip-flop is coupled to the second input terminal of the second OR gate. The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate a timing arrival pulse signal. The first input terminal of the AND gate is coupled to the output terminal of the NAND gate. The second input terminal of the AND gate is coupled to a clock signal terminal. The output terminal of the AND gate is coupled to the first input terminal of the second OR gate.

[0013] According to a third aspect of the present disclosure, a DC-DC converter is provided, including: the fixed-on-time control circuit according to the first aspect or the second aspect of the present disclosure.

[0014] In some embodiments of the present disclosure, the DC-DC converter is a boost converter. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0016] Figure 1 is an exemplary circuit diagram of a DC-DC converter;

[0017] Figure 2 is for Figure 1 the timing diagrams of some signals of the DC-DC converter shown;

[0018] Figure 3 is an exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0019] Figure 4 is a schematic block diagram of a fixed on-time control circuit according to an embodiment of the present disclosure;

[0020] Figure 5 is an exemplary circuit diagram of a fixed on-time control circuit according to an embodiment of the present disclosure; and

[0021] Figure 6 is for Figure 3 a timing diagram of some signals of the DC-DC converter shown.

[0022] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. Detailed Description of the Embodiments

[0023] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure pertains. Further, it will be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless expressly defined herein otherwise. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of a transistor are symmetric, and the conduction current directions between the source and drain (emitter and collector) of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled intermediate terminal of the transistor is referred to as the control electrode, and the remaining two ends of the transistor are respectively referred to as the first electrode and the second electrode. The transistors used in the embodiments of the present disclosure are mainly switching transistors. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Figure 1 An exemplary circuit diagram of a DC-DC converter 100 is shown. The DC-DC converter 100 is a fixed-frequency valley current mode boost converter. The DC-DC converter 100 includes: an error amplifier EA, a PWM comparator CP1, a capacitor Cc, a resistor Rc, a resistor Rs, a transistor MN2, a current source I, an AND gate AND2, an inverter NG, a first RS flip-flop LH1, a second RS flip-flop LH2, a freewheeling diode MH, a power transistor ML, an inductor L, an output capacitor Cout, and a minimum on-time control circuit. Figure 1 A load resistor Rload is also shown.

[0027] In Figure 1 example, the error amplifier EA generates an error signal eaout based on the output voltage Vout and the reference voltage VREF of the DC-DC converter 100. The error signal eaout is provided to the inverting input terminal of the PWM comparator CP1. The non-inverting input terminal of the PWM comparator CP1 is coupled to the current source I and the resistor Rs via a node sum. The current value of the current source I is Idc - Isns, where Idc represents a constant current value and Isns represents the value of the inductor current flowing through the inductor L. When the power transistor conduction control signal LG is at a high level, the transistor MN2 conducts, and the voltage at the node sum is pulled down to ground. Therefore, the PWM signal output by the PWM comparator CP1 is at a low level. Thus, the output signal MAIN_TRIP of the AND gate AND2 is at a low level. After passing through the minimum on-time, when the clock signal CLK flips to a high level, both the freewheeling diode conduction control signal HG output by the first RS flip-flop LH1 and the power transistor conduction control signal LG output by the second RS flip-flop LH2 become low levels, thereby turning on the freewheeling diode MH and turning off the power transistor ML. The inductor L discharges, and the inductor current flowing through the inductor L gradually decreases. At this time, since the power transistor conduction control signal LG is at a low level, the transistor MN2 is cut off, and the current provided by the current source I flows through the resistor Rs, thereby forming a voltage at the node sum. The voltage at the node sum becomes (Idc - Isns) × Rs, where Rs represents the resistance value of the resistor Rs. When the voltage at the node sum is greater than the voltage value of the error signal eaout, the PWM signal output by the PWM comparator CP1 is at a high level.

[0028] In Figure 1In the example, LIM represents the valley current limit indication signal. When the inductor current decreases and is equal to or lower than the valley current limit, the valley current limit indication signal LIM is at a low level. Otherwise, the valley current limit indication signal LIM is at a high level. When the valley current limit indication signal LIM is at a low level, the waveform of the output signal MAIN_TRIP of AND gate AND2 follows the waveform of the PWM signal.

[0029] When the output signal MAIN_TRIP of the AND gate AND2 is at a high level, the freewheeling tube conduction control signal HG output by the first RS flip-flop LH1 and the power tube conduction control signal LG output by the second RS flip-flop LH2 both become high levels, thereby turning on the power tube ML and turning off the freewheeling tube MH. The inductor L is charged, and the inductor current flowing through the inductor L gradually increases.

[0030] When the current of the freewheeling transistor MH is higher than the valley current limit (the valley current limit indication signal LIM is at a high level), even if the clock signal CLK flips to a high level, the on / off state of the freewheeling transistor MH and the power transistor ML cannot be changed. The freewheeling transistor MH is not turned off and the power transistor ML is turned on until the current of the freewheeling transistor MH drops below the valley current limit.

[0031] exist Figure 1 In the example, the clock signal CLK is provided to the minimum on-time control circuit. The minimum on-time control circuit can control the power transistor ML to be turned off by the high-level clock signal CLK only after the minimum on-time has elapsed.

[0032] Figure 2 Shown for Figure 1 The timing diagram of some signals of the DC-DC converter 100 shown in FIG. Figure 2 To describe Figure 1 The operating process of the DC-DC converter 100 shown in FIG. At time t1, the clock signal CLK flips to a high level, turning on the freewheeling transistor MH and turning off the power transistor ML, causing the inductor current IL to decrease. At time t2, the inductor current IL drops to the valley current limit value VY_LIM, causing the valley current limit indication signal LIM to go low. At this time, the PWM signal is at a high level, so the output signal MAIN_TRIP of the AND gate AND2 is at a high level, turning on the power transistor ML and turning off the freewheeling transistor MH. As a result, the inductor L is charged, and the inductor current IL flowing through the inductor L gradually increases.

[0033] Starting from time t2, after the minimum on-time ton, if the clock signal CLK happens to turn to a high level at this time (i.e., time t3), the power tube ML is immediately turned off. Figure 2 As shown, the waveform of the inductor current IL will show a periodic large and small wave phenomenon.

[0034] By increasing the minimum on-time of the boost converter, the above-mentioned large and small wave problems can be alleviated, but this will affect the minimum duty cycle of the boost converter, so it is not a good solution.

[0035] Embodiments of the present disclosure propose a DC-DC converter. Figure 3 An exemplary circuit diagram of a DC-DC converter 300 according to an embodiment of the present disclosure is shown. Relative to Figure 1 the shown DC-DC converter 100, Figure 3 the shown DC-DC converter 300 replaces the minimum on-time control circuit in Figure 1 with a fixed on-time control circuit 310. The fixed on-time control circuit 310 is configured to: start timing when the inductor current drops to the valley current limit value VY_LIM, and turn off the power transistor ML and turn on the freewheeling transistor MH when the timing reaches the fixed on-time. In this way, the waveform of the inductor current can be regular and there will be no large and small wave phenomena due to the clock signal CLK turning high.

[0036] Figure 4 A schematic block diagram of a fixed on-time control circuit 410 according to an embodiment of the present disclosure is shown. The fixed on-time control circuit 410 may include: a freewheeling transistor out-of-current-limit detection circuit 411, a timing start control circuit 412, a fixed-time timing circuit 413, and a conduction control signal generation circuit 414.

[0037] The output terminal of the freewheeling transistor out-of-current-limit detection circuit 411 may be coupled to the first input terminal of the timing start control circuit 412 and the first input terminal of the conduction control signal generation circuit 414 via a first node N1. The freewheeling transistor out-of-current-limit detection circuit 411 may also be provided with a valley current limit indication signal LIM of the DC-DC converter 300 and a power transistor conduction control signal LG of the DC-DC converter 300. The freewheeling transistor out-of-current-limit detection circuit 411 may be configured to: generate a first pulse signal LIM_SHOTB according to the valley current limit indication signal LIM and the power transistor conduction control signal LG, and provide the first pulse signal LIM_SHOTB to the timing start control circuit 412 and the conduction control signal generation circuit 414 via the first node N1.

[0038] The first input terminal of the timing start control circuit 412 can be coupled to the output terminal of the freewheeling diode exit current limiting detection circuit 411 and the first input terminal of the conduction control signal generation circuit 414 via the first node N1. The second input terminal of the timing start control circuit 412 can be coupled to the output terminal of the fixed-time timing circuit 413 and the second input terminal of the conduction control signal generation circuit 414 via the third node N3. The output terminal of the timing start control circuit 412 can be coupled to the input terminal of the fixed-time timing circuit 413 via the second node N2. The timing start control circuit 412 can be provided with the valley current limiting indication signal LIM of the DC-DC converter 300. The timing start control circuit 412 can be configured to: generate a timing control signal according to the first pulse signal LIM_SHOTB, the valley current limiting indication signal LIM, and the timing arrival pulse signal Ton_SHOT output by the fixed-time timing circuit 413, and provide the timing control signal to the fixed-time timing circuit 413 via the second node N2.

[0039] The input terminal of the fixed-time timing circuit 413 can be coupled to the output terminal of the timing start control circuit 412 via the second node N2. The output terminal of the fixed-time timing circuit 413 can be coupled to the second input terminal of the timing start control circuit 412 and the second input terminal of the conduction control signal generation circuit 414 via the third node N3. The input terminal of the fixed-time timing circuit 413 can also be coupled to the bandgap reference voltage terminal VBG. The fixed-time timing circuit 413 can be configured to: start timing when the timing control signal indicates the start of timing, determine the timing duration according to the bandgap reference voltage VBG from the bandgap reference voltage terminal VBG, and provide the timing arrival pulse signal Ton_SHOT to the timing start control circuit 412 and the conduction control signal generation circuit 414 via the third node N3 when the timing duration is reached. In some embodiments of the present disclosure, the start of timing is indicated when the timing control signal flips from a high level to a low level.

[0040] The first input terminal of the conduction control signal generation circuit 414 can be coupled to the output terminal of the freewheeling diode exit current limiting detection circuit 411 via the first node N1. The second input terminal of the conduction control signal generation circuit 414 can be coupled to the output terminal of the fixed-time timing circuit 413 and the second input terminal of the timing start control circuit 412 via the third node N3. The conduction control signal generation circuit 414 can also be coupled to the clock signal terminal CLK. The conduction control signal generation circuit 414 can be configured to: generate a conduction control signal CTL according to the timing arrival pulse signal Ton_SHOT, the first pulse signal LIM_SHOTB, and the clock signal CLK from the clock signal terminal CLK. The conduction control signal CTL can be output from the output terminal of the conduction control signal generation circuit 414.

[0041] In some embodiments of the present disclosure, the clock signal CLK has a fixed frequency. The pulse width of the first pulse signal LIM_SHOTB is equal to the period of the clock signal CLK.

[0042] Figure 6 Shows the timing diagram of some signals for Figure 3 the DC-DC converter 300 shown below in conjunction with Figure 3 , Figure 4 and Figure 6 to describe the working principle of the fixed on-time control circuit 410. At time t2, the inductor current drops to the valley current limit value VY_LIM, and the valley current limit indication signal LIM becomes low. The output signal MAIN_TRIP of the AND gate AND2 becomes high, so that the power transistor conduction control signal LG becomes high. Therefore, the power transistor ML conducts, and the inductor current IL starts to rise. Since the power transistor conduction control signal LG becomes high, the transistor MN2 conducts, and the voltage of the node sum is pulled down to ground. At this time, the PWM signal becomes low. Therefore, the output signal MAIN_TRIP of the AND gate AND2 becomes low.

[0043] The freewheeling diode dropout current detection circuit 411 generates the first pulse signal LIM_SHOTB based on the valley current limit indication signal LIM and the power transistor conduction control signal LG. The first pulse signal LIM_SHOTB may have a low-level pulse to indicate that the freewheeling diode MH exits the current limit state. The timing start control circuit 412 generates a low-level timing control signal based on the first pulse signal LIM_SHOTB with a low-level pulse, the valley current limit indication signal LIM in the low level, and the timing arrival pulse signal Ton_SHOT in the low level. The timing control signal triggers the fixed-time timing circuit 413 to start timing. The first pulse signal LIM_SHOTB with a low-level pulse can control the conduction control signal generation circuit 414 not to be controlled by the clock signal CLK, so as to output a low-level conduction control signal CTL. Since both the output signal MAIN_TRIP of the AND gate AND2 and the conduction control signal CTL are in the low level, the freewheeling diode MH and the power transistor ML both maintain their previous states, and the inductor current IL continues to rise.

[0044] At time t4, the timing duration ton_new is reached. The fixed-time timing circuit 413 outputs a timing arrival pulse signal Ton_SHOT with a high-level pulse. The timing arrival pulse signal Ton_SHOT with a high-level pulse can cause the timing control signal output by the timing start control circuit 412 to flip to a high level, thereby controlling the reset of the fixed-time timing circuit 413 and causing the conduction control signal CTL generated by the conduction control signal generation circuit 414 to flip to a high level. The conduction control signal CTL at a high level can cause the power transistor conduction control signal LG to become a low level, thereby turning off the power transistor ML and turning on the freewheeling diode MH.

[0045] The timing duration ton_new can be set to the normal conduction time of the DC-DC converter 300, that is, ton_new = (1 - Vin / Vout) × Tsw. Wherein, Vin represents the voltage value of the input voltage of the DC-DC converter 300, Vout represents the voltage value of the output voltage of the DC-DC converter 300, and Tsw represents the period of the PWM signal.

[0046] In this way, the fixed conduction time control circuit 410 can control the inductor current of the DC-DC converter 300 to be regular and prevent the phenomenon of large and small waves.

[0047] Figure 5 An exemplary circuit diagram of a fixed conduction time control circuit according to an embodiment of the present disclosure is shown. The freewheeling diode exit current limiting detection circuit 511 may include: a first monostable flip-flop 5111 and a NAND gate NAND1. Wherein, the input terminal of the first monostable flip-flop 5111 is provided with a valley current limiting indication signal LIM. The output terminal of the first monostable flip-flop 5111 is coupled to the first input terminal of the NAND gate NAND1. The second input terminal of the NAND gate NAND1 is provided with the power transistor conduction control signal LG. The output terminal of the NAND gate NAND1 is coupled to the first node N1. The first monostable flip-flop 5111 is triggered at the falling edge of the valley current limiting indication signal LIM from the first level to the second level to generate a second pulse signal LIM_FD. In some embodiments of the present disclosure, the second pulse signal LIM_FD has a high-level pulse. The pulse width of the second pulse signal LIM_FD is equal to the period of the clock signal CLK. The first level is a high level, the second level is a low level, and the falling edge from the first level to the second level is a falling edge. The first monostable flip-flop 5111 is a falling-edge triggered monostable flip-flop.

[0048] The timing start control circuit 512 may include: a first OR gate OR1. Among them, the first input terminal of the first OR gate OR1 is coupled to the third node N3. The second input terminal of the first OR gate OR1 is coupled to the first node N1. The third input terminal of the first OR gate OR1 is provided with a valley current limiting indication signal LIM. The output terminal of the first OR gate OR1 is coupled to the second node N2.

[0049] The fixed-time timing circuit 513 may include: a constant current source Ion, a capacitor Con, a first transistor M1, a voltage comparator COMP, and a second monostable flip-flop 5131. Among them, the constant current source Ion may be coupled to the first voltage terminal V1 and the first end of the capacitor Con. The constant current source Ion is configured to provide a constant current to the first end of the capacitor Con. The first end of the capacitor Con is coupled to the first input terminal of the voltage comparator COMP and the second pole of the first transistor M1. The second end of the capacitor Con is coupled to the first pole of the first transistor M1 and the second voltage terminal V2. The control pole of the first transistor M1 is coupled to the second node N2. The second input terminal of the voltage comparator COMP is coupled to the bandgap reference voltage terminal VBG. The output terminal of the voltage comparator COMP is coupled to the input terminal of the second monostable flip-flop 5131. The output terminal of the second monostable flip-flop 5131 is coupled to the third node N3. The second monostable flip-flop 5131 is triggered at the rising edge of the output signal Ton_END of the voltage comparator COMP from the second level to the first level to generate a timing arrival pulse signal Ton_SHOT.

[0050] In some embodiments of the present disclosure, the timing arrival pulse signal Ton_SHOT has a high-level pulse. The pulse width of the timing arrival pulse signal Ton_SHOT is determined according to the discharge speed of the capacitor Con. It should be ensured that the conduction time of the first transistor M1 is sufficient to completely release the charge of the capacitor Con. The first level is the high level, the second level is the low level, and the rising edge from the second level to the first level is the rising edge. The second monostable flip-flop 5131 is a rising-edge-triggered monostable flip-flop.

[0051] The conduction control signal generation circuit 514 may include: an AND gate AND1 and a second OR gate OR2. Among them, the first input terminal of the AND gate AND1 is coupled to the first node N1. The second input terminal of the AND gate AND1 is coupled to the clock signal CLK terminal. The output terminal of the AND gate AND1 is coupled to the first input terminal of the second OR gate OR2. The second input terminal of the second OR gate OR2 is coupled to the third node N3. The output terminal of the second OR gate OR2 is coupled to the reset terminal R of the first RS flip-flop LH1 and the second RS flip-flop LH2.

[0052] In Figure 5In the example, a high voltage is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the voltage comparator COMP is the non-inverting input terminal, and the second input terminal is the inverting input terminal. The first transistor M1 is an N-type transistor. Those skilled in the art should understand that variations made to the Figure 5 circuit shown should also fall within the scope of protection of the present disclosure. In this variation, the above-mentioned transistors and voltage terminals may also have settings different from those in the Figure 5 example shown.

[0053] Next, in conjunction with Figure 3 , Figure 5 and Figure 6 , the working principle of the fixed conduction time control circuit 510 will be described. At time t2, the inductor current drops to the valley current limit value VY_LIM, and the valley current limit indication signal LIM becomes low level. The output signal MAIN_TRIP of the AND gate AND2 becomes high level, so that the power transistor conduction control signal LG becomes high level. Therefore, the power transistor ML conducts, and the inductor current IL starts to rise. Since the power transistor conduction control signal LG becomes high level, the transistor MN2 conducts, and the voltage of the node sum is pulled down to ground. At this time, the PWM signal becomes low level. Therefore, the output signal MAIN_TRIP of the AND gate AND2 becomes low level.

[0054] The falling edge of the valley current limit indication signal LIM triggers the first monostable flip-flop 5111 to generate a second pulse signal LIM_FD with a high-level pulse. At this time, the power transistor conduction control signal LG is at a high level. Therefore, the NAND gate NAND1 generates a first pulse signal LIM_SHOTB with a low-level pulse. When all three inputs of the first OR gate OR1 are low level, the first OR gate OR1 outputs a timing control signal at a low level. The timing control signal causes the first transistor M1 to turn off, and the current source Ion starts to charge the capacitor Con. A ramp signal RAMP is generated at the first end of the capacitor Con. At the same time, the first pulse signal LIM_SHOTB with a low-level pulse can cause the AND gate AND1 to keep its output low level within the pulse width of the first pulse signal LIM_SHOTB. In this way, during this period, the conduction control signal generation circuit 514 is not controlled by the clock signal CLK and can output a low-level conduction control signal CTL. Since both the output signal MAIN_TRIP of the AND gate AND2 and the conduction control signal CTL are at a low level, the freewheeling diode MH and the power transistor ML both maintain their previous states, and the inductor current IL continues to rise.

[0055] At time t4, the timing duration ton_new is reached. The voltage value of the ramp signal RAMP rises to the bandgap reference voltage VBG, and the output signal Ton_END of the voltage comparator COMP flips to a high level. The rising edge of the output signal Ton_END triggers the second monostable flip-flop 5131 to output a timing arrival pulse signal Ton_SHOT with a high-level pulse. The timing arrival pulse signal Ton_SHOT with a high-level pulse enables the first OR gate OR1 to output a high-level timing control signal to turn on the first transistor M1, and enables the conduction control signal CTL output by the second OR gate OR2 to flip to a high level. After the first transistor M1 is turned on, the capacitor Con starts to discharge, and the ramp signal RAMP drops below the bandgap reference voltage VBG. Therefore, the output signal Ton_END of the voltage comparator COMP flips to a low level. Since the timing arrival pulse signal Ton_SHOT output by the second monostable flip-flop 5131 will remain at a high level for a period of time, it can control the first transistor M1 to remain on for a period of time, so that the capacitor Con can be fully discharged. The conduction control signal CTL at a high level can make the power transistor conduction control signal LG become low level, thereby turning off the power transistor ML and turning on the freewheeling diode MH.

[0056] The timing duration ton_new can be set as the normal conduction time of the DC-DC converter 300, that is, ton_new = (1 - Vin / Vout) × Tsw. Wherein, Vin represents the voltage value of the input voltage of the DC-DC converter 300, Vout represents the voltage value of the output voltage of the DC-DC converter 300, and Tsw represents the period of the PWM signal.

[0057] According to the internal structure of the fixed-time timing circuit 513, it can be obtained that:

[0058]

[0059] Wherein, Con represents the capacitance value of the capacitor Con, VBG represents the voltage value of the bandgap reference voltage VBG, and Ion represents the constant current value output by the constant current source Ion. Therefore, by setting Con, VBG, and Ion, it can be made that

[0060]

[0061] In this way, the fixed conduction time control circuit 510 can control the inductor current of the DC-DC converter 300 to be regular and will not have the phenomenon of large and small waves.

[0062] In summary, the fixed on-time control circuit for a DC-DC converter according to an embodiment of the present disclosure can generate an on-control signal, and the on-control signal can force the power transistor of the DC-DC converter to turn off the power transistor and turn on the freewheeling diode only after turning on for a fixed on-time. Due to the adoption of the fixed on-time control circuit according to an embodiment of the present disclosure, the waveform of the inductor current of the DC-DC converter according to an embodiment of the present disclosure is regular and there will be no phenomenon of large and small waves.

[0063] Unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural is generally included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited herein. Where the term "example" is used in this specification, particularly when it is placed after a list of terms, the "example" is merely illustrative and explanatory and should not be considered exclusive or extensive.

[0064] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that the various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are for illustrative purposes only and are not intended to limit the scope of the present application.

[0065] The above has described in detail several embodiments of the present disclosure. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A fixed-on-time control circuit for a DC-DC converter, comprising: The freewheeling diode exit current limiting detection circuit, the timing start control circuit, the fixed-time timing circuit, and the conduction control signal generation circuit, wherein, the freewheeling diode exit current limiting detection circuit is configured to: generate a first pulse signal according to the valley current limiting indication signal of the DC-DC converter and the power transistor conduction control signal of the DC-DC converter, and provide the first pulse signal to the timing start control circuit and the conduction control signal generation circuit via a first node; the timing start control circuit is configured to: generate a timing control signal according to the first pulse signal, the valley current limiting indication signal, and the timing arrival pulse signal output by the fixed-time timing circuit, and provide the timing control signal to the fixed-time timing circuit via a second node; the fixed-time timing circuit is configured to: start timing when the timing control signal indicates the start of timing, determine the timing duration according to the bandgap reference voltage from the bandgap reference voltage terminal, and provide the timing arrival pulse signal to the timing start control circuit and the conduction control signal generation circuit via a third node when the timing duration is reached; the conduction control signal generation circuit is configured to: generate a conduction control signal according to the timing arrival pulse signal, the first pulse signal, and the clock signal from the clock signal terminal.

2. The fixed conduction time control circuit according to claim 1, wherein, The clock signal has a fixed frequency.

3. The fixed conduction time control circuit according to claim 2, wherein The freewheeling diode exit current limiting detection circuit includes: a first monostable flip-flop and a NAND gate, wherein, the input terminal of the first monostable flip-flop is provided with the valley current limiting indication signal, and the output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate; the second input terminal of the NAND gate is provided with the power transistor conduction control signal, and the output terminal of the NAND gate is coupled to the first node; The first monostable flip-flop is triggered at the rising edge of the valley current limiting indication signal from the first level to the second level to generate a second pulse signal.

4. The fixed conduction time control circuit according to claim 3, wherein, The pulse width of the second pulse signal is equal to the period of the clock signal.

5. The fixed conduction time control circuit according to any one of claims 1 to 4, wherein, The timing start control circuit includes: a first OR gate, wherein, the first input terminal of the first OR gate is coupled to the third node, the second input terminal of the first OR gate is coupled to the first node, the third input terminal of the first OR gate is provided with the valley current limiting indication signal, and the output terminal of the first OR gate is coupled to the second node.

6. The fixed conduction time control circuit according to any one of claims 1 to 4, wherein The fixed-time timing circuit includes: a constant current source, a capacitor, a first transistor, a voltage comparator, and a second monostable flip-flop, wherein, the constant current source is configured to provide a constant current to the first end of the capacitor; the first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor, and the second end of the capacitor is coupled to the first pole of the first transistor and the second voltage terminal; the control pole of the first transistor is coupled to the second node; the second input terminal of the voltage comparator is coupled to the bandgap reference voltage terminal, and the output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop; The output terminal of the second monostable flip-flop is coupled to the third node; The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate the timing arrival pulse signal.

7. The fixed conduction time control circuit according to claim 6, wherein, The pulse width of the timing arrival pulse signal is determined according to the discharge speed of the capacitor.

8. The fixed conduction time control circuit according to any one of claims 1 to 4, wherein, The conduction control signal generation circuit includes: an AND gate and a second OR gate, wherein, the first input terminal of the AND gate is coupled to the first node, the second input terminal of the AND gate is coupled to the clock signal terminal, and the output terminal of the AND gate is coupled to the first input terminal of the second OR gate; The second input terminal of the second OR gate is coupled to the third node.

9. A fixed on-time control circuit for a DC-DC converter, comprising: A first monostable flip-flop, a NAND gate, a first OR gate, a constant current source, a capacitor, a first transistor, a voltage comparator, a second monostable flip-flop, an AND gate, and a second OR gate, wherein, the input terminal of the first monostable flip-flop is provided with the valley current limit indication signal of the DC-DC converter, the output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate, and the first monostable flip-flop is triggered at the rising edge of the valley current limit indication signal from the first level to the second level to generate a second pulse signal; The second input terminal of the NAND gate is provided with the power transistor conduction control signal of the DC-DC converter, and the output terminal of the NAND gate is coupled to the second input terminal of the first OR gate; The first input terminal of the first OR gate is coupled to the output terminal of the second monostable flip-flop, the third input terminal of the first OR gate is provided with the valley current limit indication signal, and the output terminal of the first OR gate is coupled to the control pole of the first transistor; The constant current source is configured to provide a constant current to the first end of the capacitor; The first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor, and the second end of the capacitor is coupled to the first pole of the first transistor and the second voltage terminal; The second input terminal of the voltage comparator is coupled to the bandgap reference voltage terminal, and the output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop; The output terminal of the second monostable flip-flop is coupled to the second input terminal of the second OR gate; The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate a timing arrival pulse signal; The first input terminal of the AND gate is coupled to the output terminal of the NAND gate, the second input terminal of the AND gate is coupled to the clock signal terminal, and the output terminal of the AND gate is coupled to the first input terminal of the second OR gate.

10. A DC-DC converter, comprising: The fixed conduction time control circuit according to any one of claims 1 to 9.

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