Off-time control circuit

Abstract

This disclosure provides a turn-off time control circuit, comprising: an adaptive turn-off time frequency-fixed circuit, a turn-off time optimization circuit, an OR gate, and an RS flip-flop. The turn-off time control circuit can determine the pulse width modulation signal of the power switch transistor based on a first turn-off time corresponding to the existing adaptive turn-off time frequency-fixed circuit during a stable period, and can also determine the pulse width modulation signal of the power switch transistor based on a second turn-off time less than the first turn-off time corresponding to a delay unit during an unstable period (within a preset number of periods before heavy load shedding). This solves the problem in multi-phase power supply applications where the existing adaptive turn-off time frequency-fixed mode, when shedding heavy load, results in limited output voltage regulation capability, significant output undershoot, and affects output voltage stability.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a turn-off time control circuit. Background Technology

[0002] In the design of control circuits for multiphase power supplies, existing technologies employ an adaptive turn-off time fixed-frequency mode, calculating the turn-on time of the transistor to achieve frequency fixation. However, multiphase power supplies are often used in applications with high load currents, thus experiencing a wide range of light-load to heavy-load transitions. During heavy-load transitions, in the adaptive turn-off time fixed-frequency mode, a longer turn-off time means a longer output voltage discharge time, limiting output voltage regulation capabilities, resulting in greater output undershoot and affecting output voltage stability. Summary of the Invention

[0003] The embodiments described herein provide a turn-off time control circuit to address the problem that, in multiphase power supply applications, the existing adaptive turn-off time fixed-frequency mode causes limited output voltage regulation capability, large output undershoot, and affects output voltage stability when switching to heavy loads.

[0004] This disclosure provides a shutdown time control circuit comprising: an adaptive shutdown time frequency-fixed circuit, a shutdown time optimization circuit, an OR gate, and an RS flip-flop; wherein, the adaptive shutdown time frequency-fixed circuit is configured to control the shutdown time of the power switch in the multiphase power supply according to a first operating frequency via the flip-flop of a comparator during a stable period, the shutdown time corresponding to the stable period being the first shutdown time; the shutdown time optimization circuit is configured to control the shutdown time of the power switch in the multiphase power supply via a delay unit during an unstable period, the unstable period being a preset number of periods corresponding to load switching, the shutdown time corresponding to the unstable period being the second shutdown time, the second shutdown time being less than the first shutdown time; the OR gate is configured to select either a first output signal of the adaptive shutdown time frequency-fixed circuit or a second output signal of the shutdown time optimization circuit; the RS flip-flop is configured to control the shutdown time according to the first output signal or the second output signal selected by the OR gate, and output a pulse width modulation signal of the power switch.

[0005] Optionally, the turn-off time optimization circuit includes: a delay unit, a turn-off optimization cycle number control circuit, a first D flip-flop, a counter, a first NOT gate, a second NOT gate, and an AND gate; wherein, the delay unit is configured to set the turn-off time corresponding to the unstable cycle according to the second turn-off time, the pulse width modulation signal of the power switch is fed back to the first input terminal of the delay unit after passing through the first NOT gate, the second input terminal of the delay unit is connected to the output terminal of the AND gate, and the output terminal of the delay unit is connected to one input terminal of the OR gate; the turn-off optimization cycle number control circuit is configured to cooperate with the counter to control the preset number corresponding to the unstable cycle. The input terminal of the shutdown optimization cycle count control circuit is connected to the output terminal of the counter, and the output terminal of the shutdown optimization cycle count control circuit is connected to the reset terminal of the first D flip-flop; the output terminal of the first D flip-flop is connected to one input terminal of the AND gate, and the load switching signal is connected to the first D flip-flop after passing through the second NOT gate; the counter is configured to count the number of pulses of the pulse width modulation signal of the power switch, and cooperate with the shutdown optimization cycle count control circuit to control the preset number corresponding to the unstable cycle, the reset terminal of the counter is connected to the output terminal of the AND gate; the other input terminal of the AND gate is connected to the soft start completion indication signal.

[0006] Optionally, the shutdown optimization cycle number control circuit includes: a decoding circuit and a multiplexer; wherein, the input of the decoding circuit is connected to the output of the counter, and the output of the decoding circuit is connected to the multiplexer; the multiplexer receives external digital data through an external digital input terminal, the number of bits of the external digital input terminal being determined according to the number of D flip-flops in the counter.

[0007] Optionally, the first D flip-flop further includes two input terminals and two output terminals, wherein the first input terminal is connected to the second output terminal, the second input terminal is connected to the output terminal of the second NOT gate, and the first output terminal is connected to one input terminal of the AND gate.

[0008] Optionally, the counter includes n D flip-flops: each of the n D flip-flops includes a reset terminal, two input terminals, and two output terminals; the first input terminal of each D flip-flop is connected to its own second output terminal; n is an integer greater than or equal to 1; the second input terminal of the first D flip-flop is connected to the pulse width modulation signal of the power switch; the second input terminals of the other D flip-flops are connected to the node between the first input terminal and the second output terminal of the previous D flip-flop; the reset terminals of all n D flip-flops are connected together as the reset terminal of the counter; the first and second output terminals of all n D flip-flops are used as the output terminals of the counter.

[0009] Optionally, the adaptive turn-off time frequency-determining circuit includes a first current source and a second current source that convert the input voltage of the multiphase power supply into current, a third current source that converts the output voltage of the multiphase power supply into current, a resistor, a capacitor, a switch, and a comparator: wherein the second current source and the third current source are connected in series between the operating voltage input terminal and the ground terminal of the adaptive turn-off time frequency-determining circuit; the first current source and the capacitor are connected in series between the operating voltage input terminal and the ground terminal; one end of the resistor is connected to the node between the second current source and the third current source, and the other end of the resistor is connected to the ground terminal; the switch is connected in parallel across the capacitor; the positive input terminal of the comparator is connected to the node between the first current source and the capacitor, the negative input terminal of the comparator is connected to the node between the second current source and the third current source, and the output terminal of the comparator is connected to the other input terminal of the OR gate.

[0010] Optionally, the RS flip-flop includes two input terminals and an output terminal, wherein the first input terminal is connected to the output terminal of the OR gate, the second input terminal receives the peak sampling signal of the inductor current of the control circuit of the multiphase power supply, and the output terminal outputs the pulse width modulation signal of the power switch.

[0011] Optionally, the counter includes four D flip-flops, and the external digital input of the multiplexer has two bits.

[0012] Optionally, the turn-off time control circuit is a multi-phase turn-off time control circuit, and the pulse width modulation signal of the power switch is the pulse width modulation signal of the power switch corresponding to a certain phase.

[0013] Optionally, the first operating frequency is a preset phase operating frequency corresponding to the multi-phase power supply.

[0014] The shutdown time control circuit of this disclosure includes: an adaptive shutdown time frequency-fixed circuit, a shutdown time optimization circuit, an OR gate, and an RS flip-flop; wherein, the adaptive shutdown time frequency-fixed circuit is configured to control the shutdown time of the power switch in the multiphase power supply according to a first operating frequency through the switching of a comparator during a stable period, and the shutdown time corresponding to the stable period is the first shutdown time; the shutdown time optimization circuit is configured to control the shutdown time of the power switch in the multiphase power supply through a delay unit during an unstable period, the unstable period being a preset number of periods corresponding to load switching, and the shutdown time corresponding to the unstable period is the second shutdown time, the second shutdown time being less than the first shutdown time; the OR gate is configured to select a first output signal of the adaptive shutdown time frequency-fixed circuit or a second output signal of the shutdown time optimization circuit; the RS flip-flop is configured to control the shutdown time according to the first output signal or the second output signal selected by the OR gate, and output a pulse width modulation signal of the power switch. The turn-off time control circuit of this embodiment can determine the pulse width modulation signal of the power switch transistor according to the first turn-off time corresponding to the existing adaptive turn-off time fixed-frequency circuit during the stable period, and can also determine the pulse width modulation signal of the power switch transistor according to the second turn-off time corresponding to the delay unit during the unstable period. The unstable period is a preset number of periods before load switching, and the second turn-off time is shorter than the first turn-off time. Therefore, a smaller turn-off time can be achieved when switching to a heavy load, thereby reducing the output voltage discharge time, improving voltage regulation capability, optimizing output undershoot, and improving output voltage stability. Furthermore, during the stable period, the adaptive turn-off time fixed-frequency mode can be restored, so that the operating frequency of all phases returns to the normal set frequency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0016] Figure 1 This is an exemplary circuit diagram of an existing shutdown time control mode;

[0017] Figure 2 yes Figure 1 The timing diagram corresponding to the circuit;

[0018] Figure 3 This is a schematic diagram of the structure of a turn-off time control circuit according to an embodiment of the present disclosure;

[0019] Figure 4 This is a schematic diagram of the structure of a shutdown time optimization circuit according to an embodiment of the present disclosure;

[0020] Figure 5 This is an exemplary circuit diagram of a shutdown time control circuit according to an embodiment of the present disclosure;

[0021] Figure 6 This is an exemplary circuit diagram of another shutdown time control circuit according to an embodiment of the present disclosure.

[0022] Figure 7 yes Figure 6 Timing diagram of the timing signals of the key nodes of the circuit corresponding to the turn-off time control circuit.

[0023] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0026] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0027] Figure 1 An exemplary circuit diagram 100 shows an existing adaptive turn-off time fixed-frequency mode in the control circuit of a multiphase power supply. Figure 2 for Figure 1 The timing diagram corresponding to the circuit shows that PWM is the pulse width modulation signal of a specific upper transistor. Figure 1 Circuit diagram and Figure 3 In the timing diagram, when an adaptive turn-off time scheme is adopted, the length of the turn-off time (turn-off time of the upper transistor) is based on the input voltage V of the multiphase power supply. in and output voltage Vout Calculated when V in and V out Once fixed, assuming its duty cycle is D, its reference voltage REF can be expressed as:

[0028] REF = (gm2V) in -gm3DV in )R

[0029] Among them, gm2V in This represents the current value corresponding to the current source gm2*Vin in the diagram. This current source is generated by the input voltage V. in A current source that converts current into electric current, gm3DV in For gm3*V in the figure in The current value corresponding to the current source of *D is generated by the output voltage V. out =DV in The current source is converted into electric current, and R is the resistance value of resistor R in the figure.

[0030] By V in The determined charging current gm1V in When capacitor C is charged, the voltage across capacitor C can be expressed as:

[0031]

[0032] Among them, V in gm1 is gm1*V in the diagram. in The current value corresponding to the current source, which is generated by the input voltage V. in A current source converted into electric current, T off The upper transistor is turned off, which is also the lower transistor is turned on. C is the capacitance value corresponding to capacitor C in the figure.

[0033] Figure 1 In this process, each time the lower transistor is turned on (at which time LG low on is in the off state), the current charges the capacitor. When the capacitor voltage Slope exceeds the reference voltage REF, the comparator COMP flips, thus turning off the lower transistor and turning on the upper transistor. This completes the turn-off time calculation, which can be expressed as:

[0034] T off =(1-D)RC*K

[0035] Where K is a positive coefficient greater than or equal to 1, and K is 1 when gm1 = gm2 = gm3.

[0036] As can be seen from the above formula, when R and C are fixed, i.e., when the operating frequency is fixed, i.e., in the adaptive off-time fixed-frequency mode, when D is small, T offThe output voltage adjustment time will be relatively long, which is not conducive to the output voltage adjustment effect and speed when the multi-phase power supply is switched to heavy load. The output undershoot is relatively large, which affects the output voltage stability.

[0037] To address the limitations in output voltage regulation, significant undershoot, and poor output voltage stability caused by existing adaptive turn-off time fixed-frequency modes during heavy load shedding in multiphase power supply applications, this disclosure proposes a novel turn-off time control circuit. This circuit can determine the pulse width modulation (PWM) signal of the power switch based on the first turn-off time corresponding to the existing adaptive turn-off time fixed-frequency mode during the stable period, and also determine the PWM signal based on the second turn-off time corresponding to the delay unit during the unstable period. The unstable period is a preset number of cycles before load switching, and the second turn-off time is shorter than the first turn-off time. Therefore, a shorter turn-off time can be achieved during heavy load shedding, thereby reducing output voltage discharge time, improving voltage regulation, optimizing output undershoot, and enhancing output voltage stability. Furthermore, during the stable period, the adaptive turn-off time fixed-frequency mode can be restored, allowing the operating frequencies of all phases to return to the normal set frequencies. The turn-off time control circuit of this disclosure will be described in detail below.

[0038] like Figure 3The diagram shown is a schematic representation of a turn-off time control circuit 200 according to an embodiment of this disclosure. The turn-off time control circuit 200 includes: an adaptive turn-off time frequency-fixing circuit 21, a turn-off time optimization circuit 22, an RS flip-flop 23, and an OR gate 24. The adaptive turn-off time frequency-fixing circuit 21 is connected to one input of the OR gate 24 and is configured to control the turn-off time of the power switch in the multi-phase power supply according to a first operating frequency via comparator switching within a stable period. The turn-off time corresponding to the stable period is the first turn-off time, and the first operating frequency is the preset phase operating frequency (the normal operating frequency of the phase set by the system) corresponding to the multi-phase power supply. The turn-off time optimization circuit 22 receives the pulse width modulation (PWM) signal from the power switch and its output is connected to the OR gate 24. At the other input of gate 24, the turn-off time optimization circuit 22 is configured to control the turn-off time of the power switch in the multiphase power supply through a delay unit during an unstable period. The unstable period is the number of pre-set periods corresponding to load switching (mainly when switching from heavy load). The turn-off time corresponding to the unstable period is the second turn-off time, wherein the second turn-off time is less than the first turn-off time. The output of the OR gate 24 is connected to the RS flip-flop 23 and is configured to select either the first output signal of the adaptive turn-off time frequency-fixed circuit 21 or the second output signal of the turn-off time optimization circuit 22. The RS flip-flop 23 is configured to control the turn-off time according to the first or second output signal selected by the OR gate 24 and output the pulse width modulation signal PWM of the power switch. As can be seen in this embodiment, the pulse width modulation (PWM) signal of the power switch is determined according to the first turn-off time corresponding to the adaptive turn-off time frequency-fixed circuit 21 during the stable period, and according to the second turn-off time corresponding to the delay unit 221 during the unstable period. The unstable period is a preset number of periods before load switching, and the second turn-off time is shorter than the first turn-off time. Therefore, a smaller turn-off time can be achieved when switching to a heavy load, thereby reducing the output voltage discharge time, improving voltage regulation capability, optimizing output undershoot, and improving output voltage stability. Furthermore, during the stable period, the adaptive turn-off time frequency-fixed mode can be restored, allowing the operating frequency of all phases to return to the normal set frequency.

[0039] Furthermore, such as Figure 4The diagram shown is a schematic representation of a turn-off time optimization circuit 22 according to an embodiment of this disclosure. The turn-off time optimization circuit 22 includes: a delay unit 221, a turn-off optimization cycle number control circuit 222, a first D flip-flop 223, a counter 224, a first NOT gate 225, a second NOT gate 226, and an AND gate 227. The delay unit 221 is configured to set the turn-off time corresponding to the unstable cycle according to the second turn-off time; that is, the delay set in the delay unit 221 is the second turn-off time. The pulse width modulation signal (PWM) of the power switch is fed back to the first input terminal IN of the delay unit 221 after passing through the first NOT gate 225. The second input terminal EN of the delay unit 221 is connected to the output terminal of the AND gate 227, and the output terminal of the delay unit 221 is connected to one input terminal of the OR gate 24. The delay unit 221 outputs a Delay_out signal. The turn-off optimization cycle number control circuit 222 is configured to cooperate with the counter 224 to control the turn-off time corresponding to the unstable cycle. The input of the preset quantity and the shutdown optimization cycle count control circuit 222 are connected to the output of the counter 224 to receive the output signal Q1 of the counter 224. The output of the shutdown optimization cycle count control circuit 222 is connected to the reset terminal of the first D flip-flop 223. The output of the first D flip-flop 223 is connected to one input of the AND gate 227. The load switching indication signal EAO_LOW is connected to the first D flip-flop 223 after passing through the second NOT gate 226. The counter 224 is configured to count the number of pulses of the pulse width modulation signal PWM of the power switch transistor and cooperate with the shutdown optimization cycle count control circuit 222 to control the preset quantity corresponding to the unstable cycle. The reset terminal of the counter 224 is connected to the output of the AND gate 227. The other input of the AND gate 227 is connected to the soft start completion indication signal Ssend, and the output of the AND gate 227 outputs the TURBO signal.

[0040] The working principle of the shutdown time optimization circuit 22 is as follows: when the power supply switches to heavy load, the load switching indicator signal EAO_LOW turns low, and then the first D flip-flop 223 outputs an enable signal. When the soft start completion indicator signal Ssend turns high, the enable signal enables the counter 224 and simultaneously inputs to the delay unit 221 to enable the delay unit 221. The rising edge of the pulse width modulation signal PWM of the power switch (upper transistor) turns high again after the delay of the delay unit 221. That is, the upper transistor turns off for the second shutdown time and then turns on again. The second shutdown time is less than the first shutdown time. Therefore, during this period, the comparator COMP in the adaptive shutdown time fixed frequency circuit 21 has not yet reached the flip time, thus shortening the shutdown time when switching to heavy load. In addition, after the counter 224 is enabled, the counter 224 starts to calculate the number of PWM pulses. Then, by inputting the output Q1 of the counter 224 to the shutdown optimization cycle number control circuit 222, the number of shutdown times or cycles to be optimized can be determined by external digital settings, that is, the number of cycles corresponding to the unstable cycle (corresponding to the aforementioned preset number of values).

[0041] Furthermore, such as Figure 5 The diagram shown is an exemplary circuit diagram of a shutdown time control circuit 200 according to an embodiment of this disclosure. The shutdown optimization cycle number control circuit 222 includes a decoding circuit (Decode) and a multiplexer (MUX). The input of the decoding circuit (Decode) is connected to the output of a counter 224, and the output of the decoding circuit (Decode) is connected to the multiplexer (MUX). The multiplexer (MUX) receives external digital data through external digital input terminals (BIT0~BITM), and the number of bits of the external digital input terminals is determined according to the number of D flip-flops in the counter 224. The decoding circuit (Decode) and the multiplexer (MUX), in conjunction with the counter 224, control the number of shutdown times or cycles to be optimized. Specifically, the output of the multiplexer (MUX) is connected to the reset terminal (Reset) of the first D flip-flop 223.

[0042] The first D flip-flop 223 also includes two input terminals and two output terminals, wherein the first input terminal D and the second output terminal D are connected. The second input terminal CLK is connected to the output terminal of the second NOT gate 226, and the first output terminal Q is connected to one input terminal of the AND gate 227.

[0043] Counter 224 comprises n D flip-flops: each of the n D flip-flops includes a reset terminal (Reset), two input terminals, and two output terminals. The first input terminal (D) of each D flip-flop is connected to its own second output terminal. The connection is as follows: n is an integer greater than or equal to 1; the second input terminal CLK of the first D flip-flop in the n D flip-flops is connected to the pulse width modulation signal PWM of the power switch, and the second input terminal CLK of the other D flip-flops is connected to the first input terminal D and the second output terminal of the previous D flip-flop. The middle node; the reset terminals (Reset) of all n D flip-flops are connected together as the reset terminal of counter 224; the first output terminal (Q) and the second output terminal of all n D flip-flops. All of these are used as output terminals of counter 224 and connected to the input terminals of the decoding circuit Decode. That is, the output signal Q1 of counter 224 includes the first output terminal Q and the second output terminal Q of all n D flip-flops. The output signal.

[0044] The adaptive turn-off time fixed-frequency circuit 21 includes a first current source gm1*Vin and a second current source gm2*Vin, which convert the input voltage Vin of the multiphase power supply into current, and the output voltage V of the multiphase power supply. outThe circuit consists of a third current source (gm3*Vin*D), a resistor (R), a capacitor (C), a switch (LG low on), and a comparator (COMP). The second current source (gm2*Vin) and the third current source (gm3*Vin*D) are connected in series between the operating voltage input and ground of the adaptive turn-off time fixed-frequency circuit 21. The first current source (gm1*Vin) and the capacitor (C) are connected in series between the operating voltage input and ground. One end of the resistor (R) is connected to the node between the second and third current sources (gm2*Vin and gm3*Vin*D), and the other end is connected to ground. The switch (LG low on) is connected in parallel across the capacitor (C). The positive input of the comparator (COMP) is connected to the node between the first current source (gm1*Vin) and the capacitor (C), and the negative input is connected to the node between the second and third current sources (gm2*Vin and gm3*Vin*D). The output of the comparator (COMP) is connected to the other input of the OR gate 24. The switch (LG low on) is off when the lower transistor is on.

[0045] RS flip-flop 23 includes two input terminals and an output terminal. The first input terminal S is connected to the output terminal of OR gate 24, the second input terminal R receives the peak sampling signal Ipeak of the inductor current of the multiphase power supply control circuit, and the output terminal Q outputs the pulse width modulation signal PWM of the power switch transistor.

[0046] Furthermore, embodiments of this disclosure also provide a turn-off time control circuit 200, such as... Figure 6 As shown, the second turn-off delay is set to 300ns, which is less than the first turn-off time. In practical applications, the value of the second turn-off time is adaptively adjusted according to specific application requirements. The counter 224 contains four D flip-flops, and the external digital input of the multiplexer MUX has two bits, making the multiplexer a 4-to-1 selector. Combined with... Figure 6The circuit principle of the off-time control circuit 200 disclosed herein is explained as follows: When the power supply switches to heavy load, the load switching indication signal EAO_LOW turns low, and then the Q terminal of the first D flip-flop 223 outputs an enable signal. When the soft start completion indication signal Ssend turns high, the enable signal enables the counter 224 composed of D flip-flops 1 to 4. At the same time, it is input to the enable terminal EN terminal of the delay unit 221 to enable the delay unit 221. The rising edge of the pulse width modulation signal PWM of the power switch (upper transistor) turns high again after the delay of the delay unit 221. That is, the upper transistor turns off for the second off time and then turns on again. The second off time is less than the first off time. Therefore, during this period, the comparator COMP in the adaptive off-time fixed frequency circuit 21 has not yet reached the flip time. In addition, after counter 224 is enabled, it begins to calculate the number of PWM pulses. Then, by inputting the output of counter 224 to the shutdown optimization cycle number control circuit 222, the number of shutdown times or cycles to be optimized can be determined by an external digital setting, i.e., the number of cycles corresponding to the unstable cycle (corresponding to the aforementioned preset value). Specifically, when the external digital is set to 00, the shutdown time of the upper transistor in the previous cycle is selected as 300ns when the power supply switches to heavy load; when the external digital is set to 01, the shutdown time of the upper transistor in the first two cycles is selected as 300ns when the power supply switches to heavy load; when the external digital is set to 10, the shutdown time of the upper transistor in the first four cycles is selected as 300ns when the power supply switches to heavy load; and when the external digital is set to 11, the shutdown time of the upper transistor in the first eight cycles is selected as 300ns. When the selected optimized turn-off time period (non-stable period) ends, the output of the data selector resets the first D flip-flop 223, the output of AND gate 227 is 0, the delay unit 221 is disabled, the 300ns turn-off time cannot be achieved, the first turn-off time is restored, that is, the turn-off time is determined by the adaptive turn-off time frequency-fixed circuit 21, and all phases are restored to the normally set operating frequency (the first operating frequency corresponding to the first turn-off time).

[0047] To further illustrate the effects of the turn-off time control circuit 200 in the embodiments of this disclosure Figure 7 This shows what happens when the external number is set to 00. Figure 6 The timing diagram of the key nodes in the turn-off time control circuit 200 is shown below. From top to bottom, the timing diagrams are for the EAO_LOW signal, Ipeak signal, PWM signal (the first corresponding PWM signal), TURBO signal, and the inductor current signals iL1 to iL6 corresponding to the first to sixth phases. Figure 7As can be seen, during the time the TURBO signal remains high, the turn-off time of the first phase is shortened to 300ns. The comparator, which originally determined to turn on the upper transistor, has not yet reached its toggle time and turns on after a 300ns delay. In addition, the other phases will also turn on their upper transistors earlier in sequence, shortening their turn-off times, thereby increasing the adjustment frequency of all phases.

[0048] In summary, the turn-off time control circuit of this embodiment can determine the pulse width modulation signal of the power switch transistor according to the first turn-off time corresponding to the existing adaptive turn-off time fixed-frequency circuit during the stable period, and can also determine the pulse width modulation signal of the power switch transistor according to the second turn-off time corresponding to the delay unit during the unstable period. The unstable period is a preset number of periods before load switching, and the second turn-off time is shorter than the first turn-off time. Therefore, a smaller turn-off time can be achieved when switching to a heavy load, thereby reducing the output voltage discharge time, improving voltage regulation capability, optimizing output undershoot, and improving output voltage stability. Furthermore, during the stable period, the adaptive turn-off time fixed-frequency mode can be restored, so that the operating frequency of all phases returns to the normal set frequency.

[0049] The descriptions of the same or corresponding module units in the various embodiments of this disclosure can be referenced in turn.

[0050] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0051] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

[0052] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0053] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0054] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A turn-off time control circuit, characterized in that, The shutdown time control circuit includes: an adaptive shutdown time frequency-fixed circuit, a shutdown time optimization circuit, an OR gate, and an RS flip-flop; The adaptive turn-off time frequency-fixed circuit is configured to control the turn-off time of the power switch in the multiphase power supply according to the first operating frequency through the flipping of the comparator within a stable period. The turn-off time corresponding to the stable period is the first turn-off time. The shutdown time optimization circuit is configured to control the shutdown time of the power switch in the multiphase power supply through a delay unit during an unstable period. The unstable period is a preset number of periods corresponding to the load switching. The shutdown time corresponding to the unstable period is the second shutdown time, which is less than the first shutdown time. The OR gate is configured to select either the first output signal of the adaptive off-time frequency-fixed circuit or the second output signal of the off-time optimization circuit. The RS flip-flop is configured to control the turn-off time based on a first output signal or a second output signal selected by the OR gate, and output a pulse width modulation signal of the power switch.

2. The turn-off time control circuit according to claim 1, characterized in that, The shutdown time optimization circuit includes: a delay unit, a shutdown optimization cycle number control circuit, a first D flip-flop, a counter, a first NOT gate, a second NOT gate, and an AND gate; The delay unit is configured to set the turn-off time corresponding to the unstable period according to the second turn-off time. The pulse width modulation signal of the power switch is fed back to the first input terminal of the delay unit after passing through the first NOT gate. The second input terminal of the delay unit is connected to the output terminal of the AND gate, and the output terminal of the delay unit is connected to one input terminal of the OR gate. The shutdown optimization cycle number control circuit is configured to cooperate with the counter to control a preset number of unstable cycles. The input terminal of the shutdown optimization cycle number control circuit is connected to the output terminal of the counter, and the output terminal of the shutdown optimization cycle number control circuit is connected to the reset terminal of the first D flip-flop. The output of the first D flip-flop is connected to one input of the AND gate, and the load switching signal is connected to the first D flip-flop after passing through the second NOT gate; The counter is configured to count the number of pulses of the pulse width modulation signal of the power switch, and cooperate with the shutdown optimization cycle number control circuit to control the preset number corresponding to the unstable cycle. The reset terminal of the counter is connected to the output terminal of the AND gate. The other input of the AND gate is connected to a soft-start completion indication signal.

3. The turn-off time control circuit according to claim 2, characterized in that, The shutdown optimization cycle number control circuit includes: a decoding circuit and a multiplexer. The input of the decoding circuit is connected to the output of the counter, and the output of the decoding circuit is connected to the multiplexer. The multiplexer receives external digital data through an external digital input terminal, the number of bits of which is determined according to the number of D flip-flops in the counter.

4. The turn-off time control circuit according to claim 3, characterized in that, The first D flip-flop further includes two input terminals and two output terminals, wherein the first input terminal is connected to the second output terminal, the second input terminal is connected to the output terminal of the second NOT gate, and the first output terminal is connected to one input terminal of the AND gate.

5. The turn-off time control circuit according to claim 4, characterized in that, The counter comprises n D flip-flops: Each of the n D flip-flops includes a reset terminal, two input terminals, and two output terminals. The first input terminal of each D flip-flop is connected to its own second output terminal, and n is an integer greater than or equal to 1. The second input terminal of the first D flip-flop among the n D flip-flops is connected to the pulse width modulation signal of the power switch, and the second input terminals of the other D flip-flops are connected to the node between the first input terminal and the second output terminal of the previous D flip-flop. The reset terminals of all n D flip-flops are connected together as the reset terminal of the counter; The first and second outputs of all n D flip-flops serve as the outputs of the counter.

6. The turn-off time control circuit according to claim 2, characterized in that, The adaptive turn-off time fixed-frequency circuit includes a first current source and a second current source that convert the input voltage of the multiphase power supply into current, a third current source that converts the output voltage of the multiphase power supply into current, resistors, capacitors, switches, and comparators. The second current source and the third current source are connected in series and then connected between the working voltage input terminal and the ground terminal of the adaptive turn-off time fixed frequency circuit. The first current source is connected in series with the capacitor and then connected between the working voltage input terminal and the ground terminal; One end of the resistor is connected to the node between the second current source and the third current source, and the other end of the resistor is connected to the ground terminal. The switch is connected in parallel across the capacitor. The positive input terminal of the comparator is connected to the node between the first current source and the capacitor, the negative input terminal of the comparator is connected to the node between the second current source and the third current source, and the output terminal of the comparator is connected to the other input terminal of the OR gate.

7. The turn-off time control circuit according to claim 6, characterized in that, The RS flip-flop includes two input terminals and an output terminal. The first input terminal is connected to the output terminal of the OR gate, the second input terminal receives the peak sampling signal of the inductor current of the control circuit of the multiphase power supply, and the output terminal outputs the pulse width modulation signal of the power switch.

8. The turn-off time control circuit according to claim 5, characterized in that, The counter includes four D flip-flops, and the external digital input of the multiplexer has two bits.

9. The turn-off time control circuit according to claim 1, characterized in that, The turn-off time control circuit is a multi-phase turn-off time control circuit, and the pulse width modulation signal of the power switch is the pulse width modulation signal of the power switch corresponding to a certain phase.

10. The turn-off time control circuit according to claim 9, characterized in that, The first operating frequency is the preset phase operating frequency corresponding to the multiphase power supply.

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