An electromagnetic radiation suppression circuit, circuit board and method for clock signals

Abstract

The present invention discloses a clock signal electromagnetic radiation suppression circuit, a circuit board and a method, relating to the technical field of electromagnetic compatibility. The circuit includes: a clock judgment module and a clock shutdown module. Corresponding to a printed circuit board that does not connect a clock signal to a baseboard management controller. Since the circuit cannot detect the sampling signal of the clock signal, the circuit sends a control signal through the clock shutdown module to set the internal register of the physical layer chip, turn off the clock signal, and suppress the electromagnetic radiation radiated into space by the clock signal through the unconnected wires on the circuit board. Through a clock signal electromagnetic radiation suppression circuit disclosed in an embodiment of the present invention, it is possible to automatically judge whether a corresponding clock signal is used by the baseboard management controller by detecting the clock signal on one side of the baseboard management controller, reduce the electromagnetic radiation efficiency caused by the clock signal, while ensuring the reduction of electromagnetic radiation, reduce the workload of engineering technicians and save labor costs.

Description

Technical Field

[0001] The present invention relates to the technical field of electromagnetic compatibility, and particularly relates to a clock signal electromagnetic radiation suppression circuit, a circuit board and a method. Background Art

[0002] With the development of information technology devices towards high speed, high sensitivity, high integration and high stability, the requirements for electromagnetic compatibility are becoming increasingly stringent, and electromagnetic compatibility issues must be considered in the early stage of device design. For the interconnection devices of high-speed digital systems, the electromagnetic radiation problem of clock signals is relatively serious. As the communication rate becomes higher and higher, the frequency of the clock signal also becomes higher and higher. When the clock frequency increases, it means that the rising edge and falling edge of the clock signal become steeper, and the rising edge time and falling edge time become shorter. Corresponding to the frequency domain components, the frequency will become higher and higher. The higher the frequency, the shorter the corresponding wavelength, and the shorter the size of the available antenna or equivalent antenna. Electromagnetic waves are more likely to radiate into space, causing serious electromagnetic interference problems.

[0003] As a server, which is an information technology device, it is usually used in cooperation with a switch. The baseboard management controller (BMC) in the server is interconnected with the physical layer chip of the switch through a dedicated network port to implement the RGMII (Reduced Gigabit Media Independent Interface) protocol transmission. Usually, the clock I / O pin of the physical layer chip of the switch outputs a clock signal externally for use by the MAC (Media Access Control) module in the baseboard management controller; another common situation is that the clock I / O pin of the physical layer chip of the switch is not connected to the MAC module of the baseboard management controller, and correspondingly, no connection is made between the clock signal and the baseboard management controller. However, during PCB design, whether or not the clock signal is connected to the baseboard management controller, a measurement point for the clock signal needs to be reserved on the PCB for the oscilloscope probe to capture the signal. When the clock signal is not connected to the baseboard management controller, the clock signal trace on the server PCB presents a "broken head line" form, which causes the trace of the "broken head line" part on the PCB to be equivalent to an antenna, radiating electromagnetic waves externally. The electromagnetic waves are further coupled to the network port cable through space coupling, and the network port cable radiates the electromagnetic radiation noise inside the chassis into space, resulting in excessive electromagnetic radiation. Figure 1 Shows the electromagnetic radiation index caused by the "broken head line" of the 125 MHz clock in the existing design. From Figure 1It can be seen that the test results of the quadruple frequency (500 MHz) of 125 MHz have exceeded the standard limit, resulting in the non-compliance of the server's electromagnetic radiation index. For the connection of the above two clock signals, if engineers manually judge and set the chip to turn off the unconnected clock, it will bring a huge workload and consume a large amount of labor costs. Therefore, there is an urgent need for a clock signal electromagnetic radiation suppression circuit and method to directly judge whether the clock signal sent by the physical layer chip of the switch is connected to the baseboard management controller through the circuit, and automatically set the on or off of the relevant clock signal according to the actual situation of whether the clock signal is connected to the baseboard management controller. Summary of the Invention

[0004] In order to solve the problem in the prior art that due to the compatibility design of the printed circuit board, the electromagnetic radiation of the clock signal not connected to the baseboard management controller exceeds the standard, the embodiments of the present invention provide a clock signal electromagnetic radiation suppression circuit, circuit board and method, which can automatically turn off the clock signal not connected to the baseboard management controller instead of manual operation, so as to reduce the electromagnetic radiation level and make the electromagnetic radiation of the product meet the corresponding standard.

[0005] In order to solve the above one or more technical problems, the technical solutions adopted by the present invention are as follows:

[0006] In the first aspect, a clock signal electromagnetic radiation suppression circuit is provided. The circuit is used to connect the physical layer chip and the baseboard management controller, and suppress the electromagnetic radiation generated by the clock signal sent by the physical layer chip but not connected to the baseboard management controller. The circuit includes: a clock judgment module and a clock shutdown module;

[0007] Among them, the clock judgment module includes: an operational amplifier sub-module, a filtering sub-module, a switching sub-module, a sampling sub-module, and a logic judgment sub-module;

[0008] The operational amplifier sub-module includes: an operational amplifier first port, an operational amplifier second port, an operational amplifier third port, an operational amplifier fourth port, and an operational amplifier fifth port. The filtering sub-module includes: a filtering first port, a filtering second port, and a filtering third port. The switching sub-module includes: a switching first port, a switching second port, and a switching third port. The sampling sub-module includes: a sampling first port and a sampling second port. The logic judgment sub-module includes: a judgment first port, a judgment second port, and a judgment third port;

[0009] The operational amplifier first port is electrically connected to the first pin of the baseboard management controller. The operational amplifier fourth port is connected to the power supply voltage. The operational amplifier fifth port is grounded. The operational amplifier third port is electrically connected to the switching first port;

[0010] The first filtering port is electrically connected to the first pin of the physical layer chip, the second filtering port is grounded, the third filtering port is electrically connected to the second port of the switch, and the third filtering port is also electrically connected to the first judgment port;

[0011] The first sampling port is electrically connected to the second pin of the baseboard management controller, and the second sampling port is electrically connected to the second judgment port;

[0012] The third judgment port is electrically connected to the third pin of the baseboard management controller;

[0013] The clock shutdown module includes the fourth pin of the baseboard management controller and the second pin of the physical layer chip which are connected to each other.

[0014] Further, when the clock signal is connected to the baseboard management controller, the third port of the switch is electrically connected to the first sampling port.

[0015] Further, the operational amplifier sub-module includes an operational amplifier;

[0016] The positive input terminal of the operational amplifier serves as the first op-amp port, the negative input terminal of the operational amplifier serves as the second op-amp port, the output terminal of the operational amplifier serves as the third op-amp port, the positive power supply terminal of the operational amplifier serves as the fourth op-amp port, and the negative power supply terminal of the operational amplifier serves as the fifth op-amp port.

[0017] Further, the filtering sub-module includes a first resistor R1 and a capacitor C;

[0018] One end of the first resistor R1 serves as the second filtering port, the other end of the first resistor R1 serves as the first filtering port and is electrically connected to one end of the capacitor C, and the other end of the capacitor C serves as the third filtering port and is grounded.

[0019] Further, the switch sub-module includes a metal-oxide-semiconductor transistor;

[0020] The gate g of the metal-oxide-semiconductor transistor serves as the first switch port, the drain d of the metal-oxide-semiconductor transistor serves as the second switch port, and the source s of the metal-oxide-semiconductor transistor serves as the third switch port.

[0021] Further, the metal-oxide-semiconductor transistor is an N-type doped metal-oxide-semiconductor transistor.

[0022] Further, the sampling sub-module includes a second resistor R2;

[0023] One end of the second resistor R2 serves as the first sampling port, and the other end of the second resistor R2 serves as the second sampling port.

[0024] Further, the logic judgment sub-module includes an AND gate;

[0025] The first input terminal of the AND gate serves as the first judgment port, the second input terminal of the AND gate serves as the second judgment port, and the output terminal of the AND gate serves as the third judgment port.

[0026] In a second aspect, a circuit board for suppressing electromagnetic radiation of a clock signal is provided. The circuit board at least includes a circuit for suppressing electromagnetic radiation of a clock signal described in the first aspect above;

[0027] Among them, the operational amplifier sub-module, the filter sub-module, and the switch sub-module are arranged within a first range at a first preset distance from the edge of the physical layer chip;

[0028] The sampling sub-module and the logic judgment sub-module are arranged within a second range at a second preset distance from the edge of the baseboard management controller.

[0029] In a third aspect, a method for suppressing electromagnetic radiation of a clock signal is provided, which is applied to a circuit for suppressing electromagnetic radiation of a clock signal described in the first aspect above. The method includes:

[0030] Obtain a clock signal from the first pin of the physical layer chip and filter the clock signal;

[0031] Sample the filtered clock signal to obtain a sampling signal, and send the sampling signal and the filtered clock signal to the second judgment port and the first judgment port respectively;

[0032] Obtain the effective value of the signal at the third judgment port and determine whether the effective value of the signal is less than a preset threshold;

[0033] If so, the baseboard management controller sends a clock shutdown instruction to the physical layer chip.

[0034] Furthermore, before the above method, it also includes:

[0035] Power on the baseboard management controller and the physical layer chip to make the baseboard management controller and the physical layer chip operate normally.

[0036] The beneficial effects brought by the technical solutions provided in the embodiments of the present invention are:

[0037] 1. Through a circuit for suppressing electromagnetic radiation of a clock signal disclosed in the embodiments of the present invention, it is possible to automatically determine whether a corresponding clock signal is used by the baseboard management controller by detecting the clock signal on the side of the baseboard management controller;

[0038] 2. When the sampling sub-module monitors that the baseboard management controller does not receive the clock signal sent by the physical layer chip, the corresponding clock link is automatically cut off, reducing the electromagnetic radiation efficiency caused by the clock signal;

[0039] 3. If the sampling sub-module monitors that the baseboard management controller receives the clock signal sent by the physical layer chip, the current operating state of the circuit is maintained without intervention.

[0040] 4. Through a clock signal electromagnetic radiation suppression circuit disclosed in an embodiment of the present invention, it automatically determines whether the baseboard management controller uses the clock signal sent by the physical layer chip. While ensuring electromagnetic radiation suppression, it reduces the workload of engineering and technical personnel and saves labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a schematic diagram of the test result of 125MHz clock electromagnetic radiation;

[0043] Figure 2 It is a schematic diagram of a clock signal electromagnetic radiation suppression circuit module provided by an embodiment of the present invention;

[0044] Figure 3 It is a schematic diagram of a clock signal electromagnetic radiation suppression circuit module when the clock signal is not connected to the baseboard management controller provided by an embodiment of the present invention;

[0045] Figure 4 It is a schematic diagram of a clock signal electromagnetic radiation suppression circuit module when the clock signal is connected to the baseboard management controller provided by an embodiment of the present invention;

[0046] Figure 5 It is a schematic diagram of a clock signal electromagnetic radiation suppression circuit when the clock signal is not connected to the baseboard management controller provided by an embodiment of the present invention;

[0047] Figure 6 It is a schematic diagram of a clock signal electromagnetic radiation suppression circuit when the clock signal is connected to the baseboard management controller provided by an embodiment of the present invention;

[0048] Figure 7 It is a schematic diagram of the setting range of the circuit module provided by an embodiment of the present invention on the circuit board;

[0049] Figure 8 It is a schematic diagram of the test result obtained by performing electromagnetic radiation testing on a server that does not connect the baseboard management controller to the 125MHz clock signal using a clock signal electromagnetic radiation suppression circuit board provided by an embodiment of the present invention;

[0050] Figure 9 It is a schematic diagram of a method for suppressing electromagnetic radiation of a clock signal provided by an embodiment of the present invention. Detailed implementation manners

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0052] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second", and similar terms used in this disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms "a", "an", or "the" and the like do not denote a limitation of quantity, but mean that there is at least one. The numbers in the accompanying drawings of the specification only represent the distinction between various functional components or modules, and do not represent the logical relationship between the components or modules. The term "including" or "comprising" and the like mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The term "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0053] For the component symbols involved in the specification of this application, in a circuit diagram, they represent the types of components and distinguish each component, for example: R1, R2, C, etc.; in the corresponding formula, they represent the magnitudes of the corresponding physical quantities of the components, which are distinguished by italics, for example: the resistance value corresponding to the resistor R1 is R1.

[0054] Next, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structures and functions, and repeated descriptions thereof will be omitted.

[0055] In the prior art, due to the compatibility design of the printed circuit board, the electromagnetic radiation of the clock signal that is not connected to the baseboard management controller exceeds the standard. Embodiments of the present invention provide a clock signal electromagnetic radiation suppression circuit, a circuit board, and a method, which can automatically turn off the clock signal that is not connected to the baseboard management controller instead of manual operation, so as to reduce the electromagnetic radiation level and make the electromagnetic radiation of the product meet the corresponding standard.

[0056] In one embodiment, a clock signal electromagnetic radiation suppression circuit is used to connect a physical layer chip and a baseboard management controller, and suppress the electromagnetic radiation generated by the clock signal emitted by the physical layer chip but not connected to the baseboard management controller. The clock signal electromagnetic radiation suppression circuit includes: a clock judgment module 1 and a clock shutdown module 2, as Figure 2 shown.

[0057] Among them, the clock judgment module 1 includes: an operational amplifier sub-module 11, a filtering sub-module 12, a switching sub-module 13, a sampling sub-module 14, and a logic judgment sub-module 15, as Figure 3 shown.

[0058] The operational amplifier sub-module 11 includes: an operational amplifier first port 111, an operational amplifier second port 112, an operational amplifier third port 113, an operational amplifier fourth port 114, and an operational amplifier fifth port 115. The filtering sub-module 12 includes: a filtering first port 121, a filtering second port 122, and a filtering third port 123. The switching sub-module 13 includes: a switching first port 131, a switching second port 132, and a switching third port 133. The sampling sub-module 14 includes: a sampling first port 141 and a sampling second port 142. The logic judgment sub-module 15 includes: a judgment first port 151, a judgment second port 152, and a judgment third port 153.

[0059] The operational amplifier first port 111 is electrically connected to the first pin of the baseboard management controller. The operational amplifier fourth port 114 is connected to the power supply voltage. The operational amplifier fifth port 115 is grounded. The operational amplifier third port 113 is electrically connected to the switching first port 131. Among them, the first pin of the baseboard management controller is used to indicate whether the baseboard management controller is normally powered on. When the baseboard management controller is normally powered on, the first pin of the baseboard management controller outputs a high level.

[0060] In a preferred embodiment, the operational amplifier second port 112 is grounded. In this connection mode, the operational amplifier sub-module 11 has a high driving ability, and the voltage output by the operational amplifier third port 113 is sufficient to drive the switching sub-module 13 to conduct or turn off.

[0061] In another embodiment, the second port 112 of the operational amplifier is electrically connected to the third port 113 of the operational amplifier. In this connection mode, the operational amplification sub-module 11 acts as a voltage follower, and in the case where the threshold voltage of the device selected by the switch sub-module 13 is less than the output voltage of the first pin of the baseboard management controller, the switch sub-module 13 can be driven in this connection mode.

[0062] The first port 121 of the filter is electrically connected to the first pin of the physical layer chip, the second port 122 of the filter is grounded, the third port 123 of the filter is electrically connected to the second port 132 of the switch, and the third port 123 of the filter is also electrically connected to the first port 151 of the determination. Among them, the first pin of the physical layer chip outputs a clock signal. The filter sub-module 12 is used to filter the electromagnetic radiation frequency in a targeted manner.

[0063] The first port 141 of the sampling is also electrically connected to the second pin of the baseboard management controller, the second port 142 of the sampling is electrically connected to the second port 152 of the determination, and the second pin of the baseboard management controller is used to receive the clock signal. If the clock signal is not connected to the second pin of the baseboard management controller by wiring, as Figure 3 shown, the sampling signal cannot be detected at the second port 142 of the sampling, and the effective value of the signal output from the third port 153 of the determination will be less than the preset threshold, and the third pin of the baseboard management controller receives a low level.

[0064] When the clock signal is connected to the baseboard management controller, the first port 141 of the sampling is electrically connected to the second pin of the baseboard management controller, and the second port 142 of the sampling is electrically connected to the second port 152 of the determination.

[0065] The third port 153 of the determination is electrically connected to the third pin of the baseboard management controller.

[0066] The level state received by the third pin of the baseboard management controller indicates whether the baseboard management controller is connected to the clock signal. The third pin of the baseboard management controller receives a high level, indicating that the baseboard management controller is connected to the clock signal; the third pin of the baseboard management controller receives a low level, indicating that the baseboard management controller is not connected to the clock signal.

[0067] The clock shutdown module 2 includes the fourth pin of the baseboard management controller and the second pin of the physical layer chip which are interconnected. When the baseboard management controller is powered on and after a preset time, if the level of the third pin of the baseboard management controller is low, it is determined that the signal is not connected to the baseboard management controller. At this time, the first pin of the baseboard management controller outputs a low level, so that the output of the third port 113 of the operational amplifier cannot drive the switch sub-module 13, and the switch sub-module 13 is turned off, cutting off the clock signal transmission path. At the same time, the fourth pin of the baseboard management controller outputs a control signal to the second pin of the physical layer chip to set the internal register of the physical layer chip, closing the path for the clock signal of the physical layer chip to be output from the first pin of the physical layer chip, and the first pin of the physical layer chip no longer outputs the clock signal. The specific form of the above control signal can be defined by the user himself / herself, and this application does not limit it.

[0068] When the clock signal is connected to the baseboard management controller, the third port 133 of the switch is electrically connected to the first sampling port 141, as Figure 4 shown. If the second pin of the baseboard management controller receives the clock signal, a sampling signal will be output at the second sampling port 142, and the waveform of the sampling signal is the same as that of the clock signal. It is judged that the effective value of the signal output at the third port 153 will be greater than the preset threshold, and the third pin of the baseboard management controller receives a high level. The switch sub-module 13 remains in the open state, and the clock signal passes through the open switch sub-module 13 and continues to be input to the baseboard management controller.

[0069] Specifically, the operational amplification sub-module 11 is an operational amplifier 110;

[0070] The positive input terminal of the operational amplifier 110 serves as the first port 111 of the operational amplifier, the negative input terminal of the operational amplifier 110 serves as the second port 112 of the operational amplifier, the output terminal of the operational amplifier 110 serves as the third port 113 of the operational amplifier, the positive power supply terminal of the operational amplifier 110 serves as the fourth port 114 of the operational amplifier, and the negative power supply terminal of the operational amplifier 110 serves as the fifth port 115 of the operational amplifier.

[0071] Specifically, the filtering sub-module 12 includes a first resistor R1 and a capacitor C;

[0072] One end of the first resistor R1 serves as the second port 122 of the filter, the other end of the first resistor R1 serves as the first port 121 of the filter and is electrically connected to one end of the capacitor C, and the other end of the capacitor C serves as the third port 123 of the filter and is grounded.

[0073] The cut-off frequency f res of this filtering sub-module 12 = 1 / 2πR1C. By adjusting the specific values of the first resistor R1 or the capacitor C, the cut-off frequency of the filtering sub-module 12 can be adjusted to filter the noise carried by the clock signal of the corresponding frequency.

[0074] Specifically, the switch sub-module 13 includes a metal-oxide-semiconductor transistor 130;

[0075] The gate g of the metal-oxide-semiconductor transistor 130 serves as the first switch port 131, the drain d of the metal-oxide-semiconductor transistor 130 serves as the second switch port 132, and the source s of the metal-oxide-semiconductor transistor 130 serves as the third switch port 133.

[0076] Further, the metal-oxide-semiconductor transistor 130 is an N-type doped metal-oxide-semiconductor transistor.

[0077] When the first switch port 131 receives a high level, the switch sub-module 13 is turned on, and the filtered clock signal is transmitted to the circuit at the back end of the switch sub-module 13.

[0078] When the first switch port 131 receives a low level, the switch sub-module 13 is turned off, and the filtered clock signal cannot be transmitted backward through the switch sub-module 13.

[0079] Specifically, the sampling sub-module 14 includes a second resistor R2;

[0080] One end of the second resistor R2 serves as the first sampling port 141, and the other end of the second resistor R2 serves as the second sampling port 142.

[0081] Specifically, the logic judgment sub-module 15 includes an AND gate 150;

[0082] The first input terminal of the AND gate 150 serves as the first judgment port 151, the second input terminal of the AND gate 150 serves as the second judgment port 152, and the output terminal of the AND gate 150 serves as the third judgment port 153.

[0083] The effective value of the output voltage can be obtained by measuring the third judgment port 153, and the corresponding high and low levels are distinguished based on this effective value.

[0084] Corresponding to the case where the clock signal is not connected to the baseboard management controller, a specific form of the clock signal electromagnetic radiation suppression circuit is as Figure 5 shown.

[0085] Corresponding to the case where the clock signal is connected to the baseboard management controller, a specific form of the clock signal electromagnetic radiation suppression circuit is as Figure 6 shown.

[0086] In another embodiment, a clock signal electromagnetic radiation suppression circuit board, the circuit board at least includes a clock signal electromagnetic radiation suppression circuit described in the above first aspect;

[0087] Among them, the operational amplifier sub-module 11, the filter sub-module 12, and the switch sub-module 13 are arranged within a first range at a first preset distance from the edge of the physical layer chip;

[0088] The sampling sub-module 14 and the logic judgment sub-module 15 are arranged within a second range at a second preset distance from the edge of the baseboard management controller.

[0089] The above-mentioned first range is a figure enclosed by parallel lines at a distance of 120 mil from the edge of the baseboard management controller, minus the area of the baseboard management controller part;

[0090] The above-mentioned second range is a figure enclosed by parallel lines at a distance of 120 mil from the edge of the baseboard management controller, minus the area of the baseboard management controller part. A schematic diagram of the corresponding module distribution is as Figure 7 shown, Figure 7 which is only used to schematically show that the corresponding modules are arranged within the first range and the second range. For the specific positions of the modules, the present application does not make any limitations.

[0091] Preferably, the circuit board is a printed circuit board.

[0092] In one of the embodiments, for the case where the 125 MHz clock signal is not connected to the baseboard management controller, an electromagnetic radiation test is performed on the above-mentioned clock signal electromagnetic radiation suppression circuit board, and the results are as Figure 8 shown. The electromagnetic radiation results are within the standard.

[0093] In another embodiment, as Figure 9 shown, a method for suppressing electromagnetic radiation of a clock signal includes:

[0094] Step S1: Obtain a clock signal from the first pin of the physical layer chip and filter the clock signal;

[0095] Step S2: Sample the filtered clock signal to obtain a sampling signal, and send the sampling signal and the filtered clock signal to the judgment second port and the judgment first port respectively;

[0096] If there is a connection between the clock signal and the baseboard management controller on the printed circuit board, the sampling waveform of the clock signal can be obtained;

[0097] If there is no connection between the clock signal and the baseboard management controller on the printed circuit board, the sampling waveform of the clock signal cannot be obtained.

[0098] Step S3: Obtain the effective value of the signal at the judgment third port and judge whether the effective value of the signal is less than a preset threshold;

[0099] If so, then step S4: Send a clock shutdown instruction from the baseboard management controller to the physical layer chip;

[0100] Otherwise, step S4': Keep sending the clock signal.

[0101] Preferably, before a method for suppressing electromagnetic radiation of a clock signal, it further includes:

[0102] Step S0: Power on the baseboard management controller and the physical layer chip to make the baseboard management controller and the physical layer chip operate normally.

[0103] All of the above optional technical solutions can be combined arbitrarily to form alternative embodiments of the present invention, which will not be elaborated one by one here.

[0104] Embodiment 1

[0105] The following Figure 2 , 3, 5 are specifically used to elaborate a clock signal electromagnetic radiation suppression circuit. This circuit is used to connect the physical layer chip and the baseboard management controller to suppress the electromagnetic radiation generated by the clock signal emitted by the physical layer chip but not connected to the baseboard management controller. The above clock signal electromagnetic radiation suppression circuit includes: a clock judgment module 1 and a clock shutdown module 2, as Figure 2 shown.

[0106] Among them, the clock judgment module 1 includes: an operational amplifier sub-module 11, a filtering sub-module 12, a switching sub-module 13, a sampling sub-module 14, and a logic judgment sub-module 15, as Figure 3 shown.

[0107] The operational amplifier sub-module 11 includes: an operational amplifier first port 111, an operational amplifier second port 112, an operational amplifier third port 113, an operational amplifier fourth port 114, and an operational amplifier fifth port 115. The filtering sub-module 12 includes: a filtering first port 121, a filtering second port 122, and a filtering third port 123. The switching sub-module 13 includes: a switching first port 131, a switching second port 132, and a switching third port 133. The sampling sub-module 14 includes: a sampling first port 141 and a sampling second port 142. The logic judgment sub-module 15 includes: a judgment first port 151, a judgment second port 152, and a judgment third port 153.

[0108] In this embodiment, the model of the baseboard management controller is AST2600, the frequency of the clock signal is 125 MHz, and the clock signal is not connected to the baseboard management controller.

[0109] The first port 111 of the operational amplifier is electrically connected to the first pin of the baseboard management controller. The fourth port 114 of the operational amplifier is connected to the power supply voltage. The fifth port 115 of the operational amplifier is grounded. The third port 113 of the operational amplifier is electrically connected to the first port 131 of the switch. Among them, the first pin of the baseboard management controller is used to indicate whether the baseboard management controller is powered on normally. When the baseboard management controller is powered on normally, the first pin of the baseboard management controller outputs a high level.

[0110] The second port 112 of the operational amplifier is grounded. The voltage output from the third port 113 of the operational amplifier is sufficient to drive the switch sub-module 13 to conduct or turn off.

[0111] The first port 121 of the filter is electrically connected to the first pin of the physical layer chip. The second port 122 of the filter is grounded. The third port 123 of the filter is electrically connected to the second port 132 of the switch. The third port 123 of the filter is also electrically connected to the first port 151 of the judgment. Among them, the first pin of the physical layer chip outputs a clock signal. The filter sub-module 12 is used to filter the electromagnetic radiation frequency in a targeted manner.

[0112] The first port 141 of the sampling is also electrically connected to the second pin of the baseboard management controller. The second port 142 of the sampling is electrically connected to the second port 152 of the judgment. The second pin of the baseboard management controller is used to receive the clock signal. If the clock signal is not connected to the second pin of the baseboard management controller through the wiring, as Figure 3 shown, the sampling signal cannot be detected at the second port 142 of the sampling. The effective value of the signal output from the third port 153 of the judgment will be less than the preset threshold, and the third pin of the baseboard management controller receives a low level.

[0113] The third port 153 of the judgment is electrically connected to the third pin of the baseboard management controller.

[0114] The level state received by the third pin of the baseboard management controller indicates whether the baseboard management controller is connected to the clock signal. When the third pin of the baseboard management controller receives a high level, it means that the baseboard management controller is connected to the clock signal. When the third pin of the baseboard management controller receives a low level, it means that the baseboard management controller is not connected to the clock signal.

[0115] The first port 141 of the sampling is electrically connected to the second pin of the baseboard management controller. The second port 142 of the sampling is electrically connected to the second port 152 of the judgment.

[0116] The third port 153 of the judgment is electrically connected to the third pin of the baseboard management controller.

[0117] The level state received by the third pin of the baseboard management controller indicates whether the baseboard management controller is connected to the clock signal. When the third pin of the baseboard management controller receives a low level, it means that the baseboard management controller is not connected to the clock signal.

[0118] The clock shutdown module 2 includes the fourth pin of the baseboard management controller and the second pin of the physical layer chip which are interconnected. After the baseboard management controller is powered on and passes a preset time, if the level of the third pin of the baseboard management controller is low, it is determined that the signal is not connected to the baseboard management controller. At this time, the first pin of the baseboard management controller outputs a low level, so that the output of the third port 113 of the operational amplifier cannot drive the switch sub-module 13, and the switch sub-module 13 is turned off, cutting off the clock signal transmission path. At the same time, the fourth pin of the baseboard management controller outputs a control signal to the second pin of the physical layer chip to set the internal register of the physical layer chip, closing the path for the clock signal of the physical layer chip to be output from the first pin of the physical layer chip, and the first pin of the physical layer chip no longer outputs the clock signal. The specific form of the above control signal can be defined by the user himself, and this application does not limit it.

[0119] Specifically, the operational amplifier sub-module 11 is an operational amplifier 110;

[0120] The positive input terminal of the operational amplifier 110 serves as the first port 111 of the operational amplifier, the negative input terminal of the operational amplifier 110 serves as the second port 112 of the operational amplifier, the output terminal of the operational amplifier 110 serves as the third port 113 of the operational amplifier, the positive power supply terminal of the operational amplifier 110 serves as the fourth port 114 of the operational amplifier, and the negative power supply terminal of the operational amplifier 110 serves as the fifth port 115 of the operational amplifier.

[0121] Specifically, the filter sub-module 12 includes a first resistor R1 and a capacitor C;

[0122] One end of the first resistor R1 serves as the second port 122 of the filter, the other end of the first resistor R1 serves as the first port 121 of the filter, and is electrically connected to one end of the capacitor C. The other end of the capacitor C serves as the third port 123 of the filter and is grounded.

[0123] The cut-off frequency f of the filter sub-module 12 res = 1 / 2πR1C. By adjusting the specific values of the first resistor R1 or the capacitor C, the cut-off frequency of the filter sub-module 12 can be adjusted to filter the noise carried by the clock signal of the corresponding frequency.

[0124] Specifically, the switch sub-module 13 includes a metal-oxide-semiconductor transistor 130;

[0125] The gate g of the metal-oxide-semiconductor transistor 130 serves as the first port 131 of the switch, the drain d of the metal-oxide-semiconductor transistor 130 serves as the second port 132 of the switch, and the source s of the metal-oxide-semiconductor transistor 130 serves as the third port 133 of the switch.

[0126] Further, the metal-oxide-semiconductor transistor 130 is an N-type doped metal-oxide-semiconductor transistor.

[0127] When the first port 131 of the switch receives a high level, the switch sub-module 13 is turned on, and the filtered clock signal is transmitted to the circuit at the back end of the switch sub-module 13;

[0128] When the first port 131 of the switch receives a low level, the switch sub-module 13 is turned off, and the filtered clock signal cannot be transmitted backward through the switch sub-module 13.

[0129] Specifically, the sampling sub-module 14 includes a second resistor R2;

[0130] One end of the second resistor R2 serves as the first sampling port 141, and the other end of the second resistor R2 serves as the second sampling port 142.

[0131] Specifically, the logic judgment sub-module 15 includes an AND gate 150;

[0132] The first input terminal of the AND gate 150 serves as the first judgment port 151, the second input terminal of the AND gate 150 serves as the second judgment port 152, and the output terminal of the AND gate 150 serves as the third judgment port 153.

[0133] For the case where the clock signal is not connected to the baseboard management controller, a specific form of a clock signal electromagnetic radiation suppression circuit is as Figure 5 shown. Measuring the third port 153 can obtain the effective value of its output voltage. At this time, the effective value of the voltage is lower than the preset threshold and is determined to be a low level.

[0134] Embodiment 2

[0135] Next, in combination with Figure 2 , 4, 6, a clock signal electromagnetic radiation suppression circuit is specifically described. This circuit is used to connect the physical layer chip and the baseboard management controller to suppress the electromagnetic radiation generated by the clock signal emitted by the physical layer chip but not connected to the baseboard management controller. The above clock signal electromagnetic radiation suppression circuit includes: a clock judgment module 1, a clock shutdown module 2, as Figure 2 shown.

[0136] Among them, the clock judgment module 1 includes: an operational amplifier sub-module 11, a filtering sub-module 12, a switch sub-module 13, a sampling sub-module 14, a logic judgment sub-module 15, as Figure 4 shown.

[0137] The operational amplifier sub-module 11 includes: an operational amplifier first port 111, an operational amplifier second port 112, an operational amplifier third port 113, an operational amplifier fourth port 114, and an operational amplifier fifth port 115. The filtering sub-module 12 includes: a filtering first port 121, a filtering second port 122, and a filtering third port 123. The switching sub-module 13 includes: a switching first port 131, a switching second port 132, and a switching third port 133. The sampling sub-module 14 includes: a sampling first port 141 and a sampling second port 142. The logic judgment sub-module 15 includes: a judgment first port 151, a judgment second port 152, and a judgment third port 153.

[0138] In this embodiment, the baseboard management controller model is AST2600, the clock signal frequency is 125 MHz, and the clock signal is connected to the baseboard management controller.

[0139] The operational amplifier first port 111 is electrically connected to the first pin of the baseboard management controller. The operational amplifier fourth port 114 is connected to the power supply voltage. The operational amplifier fifth port 115 is grounded. The operational amplifier third port 113 is electrically connected to the switching first port 131. Among them, the first pin of the baseboard management controller is used to indicate whether the baseboard management controller is powered on normally. When the baseboard management controller is powered on normally, the first pin of the baseboard management controller outputs a high level.

[0140] The operational amplifier second port 112 is grounded, and the voltage output from the operational amplifier third port 113 is sufficient to drive the switching sub-module 13 to conduct or turn off.

[0141] The filtering first port 121 is electrically connected to the first pin of the physical layer chip. The filtering second port 122 is grounded. The filtering third port 123 is electrically connected to the switching second port 132, and the filtering third port 123 is also electrically connected to the judgment first port 151. Among them, the first pin of the physical layer chip outputs a clock signal. The filtering sub-module 12 is used to filter the electromagnetic radiation frequency in a targeted manner.

[0142] The switching third port 133 is electrically connected to the sampling first port 141. The sampling first port 141 is also electrically connected to the second pin of the baseboard management controller. The sampling second port 142 is electrically connected to the judgment second port 152. The second pin of the baseboard management controller is used to receive the clock signal. If the second pin of the baseboard management controller receives the clock signal, a sampling signal will be output at the sampling second port 142. The waveform of the sampling signal is the same as the waveform of the clock signal, and the effective value of the signal output at the judgment third port 153 will be greater than the preset threshold, and the third pin of the baseboard management controller receives a high level.

[0143] In this embodiment, the clock signal is connected to the baseboard management controller. The sampling first port 141 is electrically connected to the second pin of the baseboard management controller, and the sampling second port 142 is electrically connected to the judgment second port 152.

[0144] The judgment third port 153 is electrically connected to the third pin of the baseboard management controller.

[0145] The level state received by the third pin of the baseboard management controller indicates whether the baseboard management controller is connected to the clock signal. When the third pin of the baseboard management controller receives a high level, it means that the baseboard management controller is connected to the clock signal.

[0146] When the clock signal is connected to the baseboard management controller, the switch third port 133 is electrically connected to the sampling first port 141, as Figure 4 shown. If the second pin of the baseboard management controller receives the clock signal, a sampling signal will be output at the sampling second port 142. The waveform of the sampling signal is consistent with the waveform of the clock signal. The effective value of the signal output at the judgment third port 153 will be greater than the preset threshold, and the third pin of the baseboard management controller receives a high level. The switch sub-module 13 remains in the open state, and the clock signal passes through the open switch sub-module 13 and continues to be input to the baseboard management controller.

[0147] The clock off module 2 includes the fourth pin of the baseboard management controller and the second pin of the physical layer chip that are connected to each other.

[0148] Specifically, the operational amplification sub-module 11 is an operational amplifier 110;

[0149] The positive input terminal of the operational amplifier 110 serves as the operational amplifier first port 111, the negative input terminal of the operational amplifier 110 serves as the operational amplifier second port 112, the output terminal of the operational amplifier 110 serves as the operational amplifier third port 113, the positive power supply terminal of the operational amplifier 110 serves as the operational amplifier fourth port 114, and the negative power supply terminal of the operational amplifier 110 serves as the operational amplifier fifth port 115.

[0150] Specifically, the filtering sub-module 12 includes a first resistor R1 and a capacitor C;

[0151] One end of the first resistor R1 serves as the filtering second port 122, the other end of the first resistor R1 serves as the filtering first port 121 and is electrically connected to one end of the capacitor C. The other end of the capacitor C serves as the filtering third port 123 and is grounded.

[0152] The cut-off frequency f of this filtering sub-module 12 res = 1 / 2πR1C. By adjusting the specific values of the first resistor R1 or the capacitor C, the cut-off frequency of the filtering sub-module 12 can be adjusted to filter the noise carried by the clock signal of the corresponding frequency.

[0153] Specifically, the switch sub-module 13 includes a metal-oxide-semiconductor transistor 130;

[0154] The gate g of the metal-oxide-semiconductor transistor 130 serves as the first switch port 131, the drain d of the metal-oxide-semiconductor transistor 130 serves as the second switch port 132, and the source s of the metal-oxide-semiconductor transistor 130 serves as the third switch port 133.

[0155] Furthermore, the metal-oxide-semiconductor transistor 130 is an N-type doped metal-oxide-semiconductor transistor.

[0156] When a high level is received at the first switch port 131, the switch sub-module 13 is turned on, and the filtered clock signal is transmitted to the circuit at the back end of the switch sub-module 13.

[0157] Specifically, the sampling sub-module 14 includes a second resistor R2;

[0158] One end of the second resistor R2 serves as the first sampling port 141, and the other end of the second resistor R2 serves as the second sampling port 142.

[0159] Specifically, the logic judgment sub-module 15 includes an AND gate 150;

[0160] The first input terminal of the AND gate 150 serves as the first judgment port 151, the second input terminal of the AND gate 150 serves as the second judgment port 152, and the output terminal of the AND gate 150 serves as the third judgment port 153.

[0161] The effective value of the output voltage can be obtained by measuring the third judgment port 153, and the corresponding high and low levels are distinguished based on this effective value.

[0162] Corresponding to the above situation where the clock signal is connected to the baseboard management controller, a specific form of the clock signal electromagnetic radiation suppression circuit is as Figure 6 shown.

[0163] Embodiment III

[0164] Next, in combination with Figure 7 , a clock signal electromagnetic radiation suppression circuit board will be specifically described. The circuit board at least includes a clock signal electromagnetic radiation suppression circuit described in the first aspect above. This circuit board is a printed circuit board.

[0165] Among them, the operational amplifier sub-module 11, the filtering sub-module 12, and the switch sub-module 13 are arranged within a first range at a first preset distance from the edge of the physical layer chip.

[0166] The first range is a figure enclosed by parallel lines 120 mil away from the edge of the baseboard management controller, minus the area of the baseboard management controller part; the second range is a figure enclosed by parallel lines 120 mil away from the edge of the baseboard management controller, minus the area of the baseboard management controller part, as Figure 7 shown.

[0167] Figure 7 It is illustrated that the corresponding modules are arranged within the first range and the second range, without limiting the specific positions where the modules are arranged.

[0168] The sampling sub-module 14 and the logic judgment sub-module 15 are arranged within the second range at a second preset distance from the edge of the baseboard management controller.

[0169] Embodiment 4

[0170] Next, in combination with Figure 8 , an electromagnetic radiation suppression method for clock signals is described, including:

[0171] Step S1: Obtain a clock signal from the first pin of the physical layer chip and filter the clock signal.

[0172] Step S2: Sample the filtered clock signal to obtain a sampling signal, and send the sampling signal and the filtered clock signal to the judgment second port and the judgment first port respectively.

[0173] Step S3: Obtain the effective value of the signal at the judgment third port and judge whether the effective value of the signal is less than a preset threshold.

[0174] If so, then step S4: Send a clock shutdown instruction from the baseboard management controller to the physical layer chip.

[0175] If not, then step S4': Keep sending the clock signal.

[0176] In one of the preferred implementation manners, before an electromagnetic radiation suppression method for clock signals, it further includes:

[0177] Step S0: Power on the baseboard management controller and the physical layer chip to make the baseboard management controller and the physical layer chip operate normally.

[0178] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program loaded on a computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a memory, or installed from a ROM. When the computer program is executed by an external processor, the above functions defined in the method of the embodiment of the present application are executed.

[0179] It should be noted that the computer-readable medium of the embodiment of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the embodiment of the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device. In the embodiment of the present application, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which computer-readable program codes are carried. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program codes contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0180] The above computer-readable medium may be included in the above server; or it may exist independently without being assembled into the server. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the server, the server is caused to: obtain the frame rate of an application on the terminal in response to detecting that the peripheral mode of the terminal is not activated; determine whether the user is obtaining the screen information of the terminal when the frame rate meets the screen-off condition; and control the screen to enter an immediate dimming mode in response to a determination result that the user is not obtaining the screen information of the terminal.

[0181] Computer program code for performing the operations of the embodiments of the present application may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0182] Each embodiment in this specification is described in a progressive manner. For parts that are the same or similar among the embodiments, reference may be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for a system or system embodiment, since it is basically similar to a method embodiment, the description is relatively simple. For related parts, reference may be made to the partial description of the method embodiment. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.

[0183] The above has introduced the technical solution provided by this application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

[0184] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A clock signal electromagnetic radiation suppression circuit, which is used to connect a physical layer chip and a baseboard management controller, and suppresses the electromagnetic radiation generated by the clock signal emitted by the physical layer chip but not connected to the baseboard management controller. It is characterized in that The circuit includes: a clock judgment module and a clock shutdown module; Among them, the clock judgment module includes: an operational amplifier sub-module, a filtering sub-module, a switching sub-module, a sampling sub-module, and a logic judgment sub-module; The operational amplifier sub-module includes: an operational amplifier first port, an operational amplifier second port, an operational amplifier third port, an operational amplifier fourth port, and an operational amplifier fifth port. The filtering sub-module includes: a filtering first port, a filtering second port, and a filtering third port. The switching sub-module includes: a switch first port, a switch second port, and a switch third port. The sampling sub-module includes: a sampling first port and a sampling second port. The logic judgment sub-module includes: a judgment first port, a judgment second port, and a judgment third port; When the clock signal is connected to the baseboard management controller, the switch third port is electrically connected to the sampling first port; The operational amplifier first port is electrically connected to the first pin of the baseboard management controller. The operational amplifier fourth port is connected to the power supply voltage. The operational amplifier fifth port is grounded. The operational amplifier third port is electrically connected to the switch first port; The filtering first port is electrically connected to the first pin of the physical layer chip. The filtering third port is grounded. The filtering second port is electrically connected to the switch second port. The filtering second port is also electrically connected to the judgment first port; The sampling first port is electrically connected to the second pin of the baseboard management controller. The sampling second port is electrically connected to the judgment second port; The judgment third port is electrically connected to the third pin of the baseboard management controller; The clock shutdown module includes the fourth pin of the baseboard management controller and the second pin of the physical layer chip which are connected to each other.

2. The electromagnetic radiation suppression circuit for clock signals according to claim 1, wherein The operational amplifier sub-module includes an operational amplifier; The positive input terminal of the operational amplifier serves as the operational amplifier first port. The negative input terminal of the operational amplifier serves as the operational amplifier second port. The output terminal of the operational amplifier serves as the operational amplifier third port. The positive power supply terminal of the operational amplifier serves as the operational amplifier fourth port. The negative power supply terminal of the operational amplifier serves as the operational amplifier fifth port.

3. The electromagnetic radiation suppression circuit for clock signals according to claim 1, wherein The filtering sub-module includes: a first resistor R1 and a capacitor C; One end of the first resistor R1 serves as the filtering second port. The other end of the first resistor R1 serves as the filtering first port and is electrically connected to one end of the capacitor C. The other end of the capacitor C serves as the filtering third port and is grounded.

4. The electromagnetic radiation suppression circuit for clock signals according to claim 1, characterized in that The switching sub-module includes a metal-oxide-semiconductor transistor; The gate g of the metal-oxide-semiconductor transistor serves as the switch first port. The drain d of the metal-oxide-semiconductor transistor serves as the switch second port. The source s of the metal-oxide-semiconductor transistor serves as the switch third port.

5. The electromagnetic radiation suppression circuit for clock signals according to claim 1, wherein The sampling sub-module includes a second resistor R2; One end of the second resistor R2 serves as the sampling first port. The other end of the second resistor R2 serves as the sampling second port.

6. The electromagnetic radiation suppression circuit for clock signals according to claim 1, characterized in that, The logic judgment sub-module includes an AND gate; The first input terminal of the AND gate serves as the first judgment port, the second input terminal of the AND gate serves as the second judgment port, and the output terminal of the AND gate serves as the third judgment port.

7. A clock signal electromagnetic radiation suppression circuit board, characterized in that The circuit board at least includes a clock signal electromagnetic radiation suppression circuit according to any one of claims 1-6. Among them, the operational amplifier sub-module, the filter sub-module, and the switch sub-module are arranged within a first range at a first preset distance from the edge of the physical layer chip. The sampling sub-module and the logic judgment sub-module are arranged within a second range at a second preset distance from the edge of the baseboard management controller.

8. A method for suppressing electromagnetic radiation of a clock signal, applied to a clock signal electromagnetic radiation suppression circuit according to any one of claims 1-6, characterized in that, The method includes: Obtaining a clock signal from the first pin of the physical layer chip and filtering the clock signal. Sampling the filtered clock signal to obtain a sampling signal, and respectively sending the sampling signal and the filtered clock signal to the second judgment port and the first judgment port. Obtaining the effective value of the signal at the third judgment port and judging whether the effective value of the signal is less than a preset threshold. If so, the baseboard management controller sends a clock shutdown instruction to the physical layer chip.

9. A method for suppressing electromagnetic radiation of a clock signal according to claim 8, characterized in that, Before the method, it also includes: Powering on the baseboard management controller and the physical layer chip to enable the normal operation of the baseboard management controller and the physical layer chip.

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