Ultrasonic flow meter and ultrasonic flow metering method

Abstract

An ultrasonic flow meter comprises a first transducer (11) and a second transducer (12), a first impedance circuit (41) and a second impedance circuit (42) comprising a variable impedance, a first terminal (13) and a second terminal (14) coupled to the first transducer (11) and the second transducer (12) via the first impedance circuit (41) and the second impedance circuit (42), a signal generator (16) and a signal evaluation circuit (20). The signal generator (16) and the signal evaluation circuit (20) are coupled to the first terminal (13) and the second terminal (14). The signal evaluation circuit (20) comprises a time-to-digital converter (22) and a first comparator (23) coupling a signal input (21) to the time-to-digital converter (22). A control circuit (32) sets an impedance value of the variable impedance depending on a first up-time signal (SD1UP) and a first down-time signal (SD1DO) generated by the time-to-digital converter (22) in an up mode (A) and a down mode (B).

Description

[0001] This disclosure relates to an ultrasonic flow meter and a method for ultrasonic flow measurement.

[0002] This patent application claims priority to European patent application EP 20164632.0, the disclosure of which is incorporated herein by reference.

[0003] For example, ultrasonic flow meters can be used to measure various parameters, such as the velocity, flow rate, or flow rate of a medium, like a fluid or gas. Typically, an ultrasonic flow meter includes a time-to-digital converter that measures the time of flight (ToF) of the ultrasonic signal between two points where the ultrasonic source and the ultrasonic detector are located. The measurement relies on comparing the ToF of the ultrasonic signal introduced into the medium in the upstream and / or downstream directions of the flow. The transducer of an ultrasonic flow meter can function as both an ultrasonic source and an ultrasonic detector. Ultrasonic flow meters typically include a first transducer and a second transducer, which may exhibit small mismatches in their characteristics.

[0004] The aim is to provide an ultrasonic flow meter and a method for ultrasonic flow measurement that reduces the impact of differences in transducer characteristics.

[0005] These objectives are achieved through the subject matter of the independent claims. Further developments and exemplary embodiments are described in the dependent claims.

[0006] Unless otherwise stated, the above definitions also apply to the following descriptions.

[0007] In an exemplary embodiment, the ultrasonic flow meter includes: a first transducer and a second transducer; a first impedance circuit and a second impedance circuit including variable impedance; a first terminal coupled to the first transducer via the first impedance circuit; a second terminal coupled to the second transducer via the second impedance circuit; a signal generator having a signal output terminal; and a signal evaluation circuit having a signal input terminal. The signal output terminal and the signal input terminal are coupled to the first terminal and the second terminal. The signal evaluation circuit includes a time-to-digital converter and a first comparator that couples the signal input terminal to the first input terminal of the time-to-digital converter.

[0008] Furthermore, the ultrasonic flow meter includes a control circuit coupled to a signal generator, a signal evaluation circuit, and a variable impedance. The control circuit is configured to set the ultrasonic flow meter to an uplink mode and a downlink mode, and to set the impedance value of the variable impedance as a function of a first uplink time signal generated by a time-to-digital converter in the uplink mode and a first downlink time signal generated by a time-to-digital converter in the downlink mode.

[0009] Advantageously, the impedance value of the variable impedance can be selected to increase the matching between the first and second transducers. Advantageously, the variable impedance improves the symmetry of the received signal between the uplink and downlink modes. The received signal is received at the signal input terminal. Therefore, the received signal of the ultrasonic flowmeter is optimized.

[0010] In an exemplary embodiment of the ultrasonic flow meter, the variable impedance is configured to obtain an impedance value from a first number L impedance values. This impedance value is determined during the calibration phase and used in the measurement phase following the calibration phase.

[0011] In an exemplary embodiment of the ultrasonic flow meter, the control circuit optimizes the impedance value of the variable impedance such that the first upward time signal and the first downward time signal are similar to each other during the measurement phase and differ primarily in the time difference DIFTOF. The time difference DIFTOF corresponds to the value of the flow velocity or flow rate to be determined during the measurement phase.

[0012] In an exemplary embodiment of the ultrasonic flow meter, the time difference is zero or approximately zero at zero flow. The ultrasonic flow meter achieves zero time difference at zero flow.

[0013] In an exemplary embodiment of the ultrasonic flowmeter, in uplink mode, a first comparator generates a first comparator signal with a second number K pulses, and a time-to-digital converter (TDC) generates a first uplink time signal having a value TOF_k_C1_l_UP corresponding to the second number K pulses of the first comparator signal. The index k ranges from 1 to K. The index l indicates an impedance value among a first number L impedance values ​​and can have a value from 1 to L.

[0014] In an exemplary embodiment of the ultrasonic flow meter, in downlink mode, a first comparator generates a first comparator signal with a second number of pulses K, and a time-to-digital converter generates a first downlink time signal having a value TOF_k_C1_l_DOWN corresponding to the second number of K pulses of the first comparator signal.

[0015] In an exemplary embodiment of the ultrasonic flow meter, the control circuit determines the l-th impedance value among a first number L possible impedance values, at which the following sum f(l) is minimized:

[0016]

[0017] Wherein, TOF_k_C1_l_UP is the value of the first uplink time signal generated at the k-th pulse of the first comparator signal, which is the l-th impedance value among the first number L impedance values ​​using variable impedance in uplink mode, and TOF_k_C1_l_UP_DOWN is the value of the first downlink time signal generated at the k-th pulse of the first comparator signal, which is the l-th impedance value among the first number L impedance values ​​using variable impedance in downlink mode. Advantageously, the best fit of the received signal in both uplink and downlink modes is achieved at the minimum value of the sum f(l), and the impedance that produces said minimum value is the optimal impedance.

[0018] In an exemplary embodiment of the ultrasonic flow meter, the signal generator generates a square wave or pulse signal having a third number N pulses.

[0019] In an exemplary embodiment of the ultrasonic flow meter, the signal evaluation circuit includes at least a second comparator that couples a signal input to at least a second input of a time-to-digital converter.

[0020] In an exemplary embodiment of the ultrasonic flowmeter, the signal evaluation circuit includes a fourth number of M comparators. The control circuit determines the l-th impedance value among a first number L of possible impedance values, at which the following sum f(l) is minimized:

[0021]

[0022] Wherein, TOF_k_Cm_l_UP is the value of the first uplink time signal generated at the kth pulse of the second number of K pulses of the m comparator signal, where the l-th impedance value out of the first number of L impedance values ​​used in uplink mode is used. TOF_k_Cm_l_DOWN is the value of the first downlink time signal generated at the kth pulse of the second number of K pulses of the m comparator signal, where the l-th impedance value out of the first number of L impedance values ​​used in downlink mode is used. Index k ranges from 1 to K. Index m ranges from 1 to M (therefore Cm ranges from C1 to CM). Index l can have values ​​from 1 to L. The fourth number of M comparators couples the signal input to the fourth number of M inputs of the time-to-digital converter or the fourth number of M time-to-digital converter. One of the first number of L impedance values ​​is the optimal value for low mismatch.

[0023] In an exemplary embodiment of the ultrasonic flow meter, one of the first impedance circuit and the second impedance circuit includes a variable impedance having an impedance value set by a control circuit, and the other of the first impedance circuit and the second impedance circuit does not have an impedance with a variable impedance value. For example, the first impedance circuit includes a variable impedance having an impedance value set by a control circuit, and the second impedance circuit has an impedance having a constant impedance value. Optionally, the second impedance circuit includes a variable impedance having an impedance value set by a control circuit, and the first impedance circuit has an impedance having a constant impedance value. A constant impedance value means that the impedance does not change over time and / or is not set by a control signal. The variable impedance has a first number L different impedance values.

[0024] In an alternative exemplary embodiment of the ultrasonic flow meter, the first impedance circuit includes a variable impedance having an impedance value set by a control circuit. The second impedance circuit includes other variable impedances having other impedance values ​​set by the control circuit. Different values ​​of the first impedance circuit and different values ​​of the second impedance circuit can be combined. Therefore, the variable impedance and the other variable impedances together have a first number L different impedance values.

[0025] In an exemplary embodiment of the ultrasonic flow meter, the first impedance circuit includes a first capacitor having a first electrode connected to a first terminal of a first transducer and a second electrode connected to a second terminal of the first transducer. The second impedance circuit includes a second capacitor having a first electrode connected to a first terminal of a second transducer and a second electrode connected to a second terminal of the second transducer. The first capacitor and / or the second capacitor can be implemented as variable impedance. The impedance values ​​of the first capacitor and / or the second capacitor can be set by a control circuit. For example, if the first capacitor can obtain l_1 different capacitance values ​​and the second capacitor can obtain l_2 different capacitance values, the first quantity L is equal to l_1·l_2.

[0026] The first transducer can be an up-flow transducer and the second transducer can be a down-flow transducer.

[0027] In an exemplary embodiment, the ultrasonic flow meter includes a switching circuit. The signal output terminal and the signal input terminal of the signal generator are coupled to a first terminal and a second terminal via the switching circuit.

[0028] In an exemplary embodiment, a method for ultrasonic flow metering includes: operating an ultrasonic flow meter in an uplink mode and a downlink mode by coupling a signal output terminal of a signal generator and a signal input terminal of a signal evaluation circuit to a first terminal and a second terminal, and by setting an impedance value of a variable impedance via a control circuit based on a first uplink time signal generated by a time-to-digital converter in an uplink mode and a first downlink time signal generated by a time-to-digital converter in a downlink mode. The first impedance circuit and the second impedance circuit include variable impedances. The first terminal is coupled to a first transducer via the first impedance circuit, and the second terminal is coupled to a second transducer via the second impedance circuit. The signal evaluation circuit includes a time-to-digital converter and a first comparator that couples the signal input terminal to a first input terminal of the time-to-digital converter.

[0029] The method for ultrasonic flow measurement can be implemented, for example, by an ultrasonic flow meter according to one of the exemplary embodiments defined above. It can also be implemented by the method using only the features and exemplary embodiments described in conjunction with the ultrasonic flow meter, and vice versa.

[0030] In an exemplary embodiment of the method, during the calibration phase, the control circuit determines the impedance value of the variable impedance based on a first uplink time signal generated by a time-to-digital converter in uplink mode and a first downlink time signal generated by a time-to-digital converter in downlink mode. More specifically, during the calibration phase, a series of first uplink and first downlink time signals with different impedance values ​​of the variable impedance are executed to determine the optimal impedance value. In the measurement phase following the calibration phase, the control circuit sets the optimal impedance value and determines the time difference by performing measurements in both uplink and downlink modes.

[0031] In an exemplary embodiment of the method, in uplink mode, the switching circuit couples the signal output to the first terminal and the signal input to the second terminal. In downlink mode, the switching circuit couples the signal output to the second terminal and the signal input to the first terminal. The switching circuit is optional, as it is not necessarily required.

[0032] In exemplary embodiments, ultrasonic flow meters can be applied to, for example, gas meters and water meters. Advantageously, ultrasonic flow meters improve signal symmetry, thereby reducing zero-flow offset and simplifying production calibration. Ultrasonic flow meters are implemented without frequency domain signal processing. The ultrasonic flow meter automatically performs received signal optimization.

[0033] In an exemplary embodiment, the ultrasonic flow meter is based on a comparison of up-flight time-of-flight (TOF) and down-flight (ToF) measurements. For such an ultrasonic flow meter, the use of symmetrical signal transmission is advantageous, far exceeding feasible transducer pairings. This is because a difference of as low as 10% between the up-flight and down-flight ToF signals can be of interest for optimal zero-flow-offset behavior. The ultrasonic flow meter improves symmetrical behavior by directly comparing multiple dedicated ToF values ​​within the ToF signals to optimize received signals with the same receive burst shape.

[0034] In an exemplary embodiment, the ultrasonic flow meter optimizes the utilization of the natural reciprocity of the flow meter conduit at zero flow. The ultrasonic flow meter optimizes signal transmission by adjusting, for example, resistors and / or capacitors in the signal path. Ultrasonic flow meters using Time-to-F (ToF) measurements optimize the shape of the received signal in the time domain. A ToF system typically includes a time-to-digital converter (TDC) that measures specific points in the received signal curve, typically the point where the received voltage curve intersects with a reference or comparator level or voltage.

[0035] In an exemplary embodiment of the ultrasonic flow meter, several reference levels or voltages are applied and corresponding points from the upstream and downstream measurements are compared. Despite a general time offset, known as the actual time difference of ToF (DIFTOF), the difference between corresponding points of the upstream and downstream measurements should be reduced to zero to achieve a symmetrical signal shape. The remaining common time difference, DIFTOF, is the actual meter signal, which should disappear at zero flow. However, this method operates at any flow rate by allowing this time difference of ToF and optimizing only the deviation of the time difference between corresponding measurement points. A method to approximate the disappearance of the difference and thus approach a symmetrical signal shape is to tune the variable impedance of the signal transmission path. This impedance uses parallel and series impedances, such as capacitors and resistors. The ultrasonic flow meter automatically optimizes its parameter settings.

[0036] In an exemplary embodiment, the ultrasonic flow meter performs impedance tuning at its front end. The ultrasonic flow meter utilizes an analog signal path tuning method. This is done based on a purely time-domain approach, which is highly energy-efficient. Advantageously, zero flow offset performance is achieved, and the ultrasonic flow meter operates with very low current. This simplifies calibration and reduces zero flow offset with very low current consumption, which is beneficial to the user.

[0037] In an exemplary embodiment, the ultrasonic flow meter improves the symmetry of the received signal, wherein the tuning method is in the time domain and based on Time-of-Flight (ToF) measurements. The tuning objective is to optimize the calculated time-domain signal to obtain optimal received signal shape symmetry. The ToF values ​​are generated at 1…M different reference voltage levels. Signal balancing is achieved through front-end impedance tuning. The time-domain method is well-suited for time-to-digital controllers. The ultrasonic flow meter is configured to vary the transmitting and receiving impedances to achieve identical time-domain characteristics for both the upstream and downstream received signals.

[0038] The following description of the exemplary embodiments with accompanying drawings further illustrates and explains aspects of the ultrasonic flow meter and the method for ultrasonic flow measurement. Devices and circuit components having the same structure and effect are shown with equivalent reference numerals. Because devices or circuit components correspond to each other in terms of their function in different figures, their descriptions will not be repeated for each of the following figures.

[0039] Figure 1A and Figure 1B An exemplary embodiment of an ultrasonic flow meter and its signal is shown;

[0040] Figure 2A and Figure 2B Another exemplary embodiment of the ultrasonic flow meter and its signal is shown;

[0041] Figure 3A and Figure 3B Another exemplary embodiment of the ultrasonic flow meter and its signal is shown; and

[0042] Figures 4A to 4D Other exemplary embodiments of the ultrasonic flow meter and its signal are shown.

[0043] Figure 1AAn exemplary embodiment of an ultrasonic flow meter 10 (hereinafter referred to as the meter) including a first transducer 11 and a second transducer 12 is shown. The first transducer 11 and the second transducer 12 are implemented as ultrasonic transducers, such as piezoelectric transducers or capacitive transducers. Ultrasonic transducers convert alternating current or alternating voltage into ultrasonic waves, and vice versa. When a voltage is applied, a piezoelectric transducer, such as a piezoelectric crystal, changes its size and shape; the alternating voltage causes it to oscillate and generate ultrasonic waves. Capacitive transducers utilize an electrostatic field between two electrodes, such as a conductive diaphragm and a backplate. Furthermore, the meter 10 includes a first terminal 13 and a second terminal 14. The first terminal 13 is coupled to the first transducer 11, and the second terminal 14 is coupled to the second transducer 12. The first transducer 11 and the second transducer 12 are also coupled to a reference potential terminal 15. Thus, the first terminal 13 is coupled to the first terminal of the first transducer 11. The second terminal of the first transducer 11 is connected to the reference potential terminal 15. Accordingly, the second terminal 14 is coupled to the first terminal of the second transducer 12. The second terminal of the second transducer 12 is connected to the reference potential terminal 15.

[0044] In addition, the instrument 10 includes a signal generator 16 having a signal output terminal 17. The signal output terminal 17 is coupled to a first terminal 13 and a second terminal 14. The signal generator 16 has another terminal connected to a reference potential terminal 15. Furthermore, the signal generator 16 has a control input terminal 18.

[0045] Instrument 10 includes a signal evaluation circuit 20 with a signal input terminal 21. The signal input terminal 21 is coupled to a first terminal 13 and a second terminal 14. The signal evaluation circuit 20 includes a time-to-digital converter 22 (referred to as a converter or TDC) and a first comparator 23. The first input terminal 24 of the first comparator 23 is coupled to the signal input terminal 21. The output terminal 25 of the first comparator 23 is coupled to the first input terminal 26 of the converter 22. A first reference voltage source 27 of the evaluation circuit 20 couples the second input terminal 28 of the first comparator 23 to a reference potential terminal 15. Furthermore, the evaluation circuit 20 includes a pre-charge switch 30 that couples a reference voltage terminal 31 to the signal input terminal 21.

[0046] In addition, instrument 10 includes control circuitry 32. Control circuitry 32 can be coupled to control input terminal 18 of signal generator 16 via a connection line (not shown). Control circuitry 32 can also be coupled to start input terminal 33 of converter 22. Control circuitry 32 may include a microprocessor or microcontroller.

[0047] Optionally, the instrument 10 includes a switching circuit 35 that couples a signal output terminal 17 to a first terminal 13 and a second terminal 14, and also couples a signal input terminal 21 to the first terminal 13 and the second terminal 14. Therefore, the signal output terminal 17 is alternatively coupled to either the first terminal 13 or the second terminal 14, and the signal input terminal 21 is alternatively connected to either the first terminal 13 or the second terminal 14, i.e., connected to the terminal of the two terminals 13, 14 that is not connected to the signal output terminal 17 at that time.

[0048] The switching circuit 35 includes a first changeover switch 36, which has an input terminal connected to signal output terminal 17 and two output terminals connected to first terminal 13 and second terminal 14. Furthermore, the switching circuit 35 includes a second changeover switch 37, which has an output terminal connected to signal input terminal 21 and two input terminals connected to first terminal 13 and second terminal 14. In uplink mode A, the first changeover switch 36 connects signal output terminal 17 to first terminal 13, and the second changeover switch 37 connects second terminal 14 to signal input terminal 21. In downlink mode B, the first changeover switch 36 connects signal output terminal 17 to second terminal 14, and the second changeover switch 37 connects first terminal 13 to signal input terminal 21.

[0049] Signal generator 16 generates an output signal SOUT at signal output terminal 17. A receive signal SIN can be tapped at signal input terminal 21. A reference potential GND is tapped at reference potential terminal 15. Control circuit 32 provides generator control signal SGEN to control input terminal 18 of signal generator 16. Through control circuit 32, a first control signal SCI is provided to the control terminal of first changeover switch 36, and a second control signal SC2 is provided to the control terminal of second changeover switch 37. According to the first control signal SC1, the output signal SOUT is provided to either first terminal 13 or second terminal 14 via first changeover switch 36. According to the second control signal SC2, the voltage tapped at first terminal 13 or second terminal 14 is provided to signal input terminal 21 via second changeover switch 37, and thus to the first input terminal 24 of first comparator 23.

[0050] The first input terminal 24 of the first comparator 23 is implemented as a non-inverting input terminal, and the second input terminal 28 of the first comparator 23 is implemented as an inverting input terminal. The first comparator signal SCOM1 is provided by the first comparator 23 at the output terminal 25 of the first comparator 23 and is applied to the first input terminal 26 of the converter 22.

[0051] The first reference voltage VR1 is generated by the first reference voltage generator 27 and applied to the second input terminal 28 of the first comparator 23. The start reference voltage VREF is applied to the reference terminal 31. If the pre-charge switch 30 is set to the on state by the control circuit 32, the start reference voltage VREF is provided to the first input terminal 24 of the first comparator 23. For example, this state can be achieved before the instrument 10 starts operating.

[0052] Instrument 10 may also lack switch circuit 35.

[0053] Figure 1B It shows Figure 1A An exemplary signal of instrument 10 is described in the figure. The signal is shown as a function of time t. Figure 1B The top three lines show the signals under uplink mode A, which can be an uplink measurement mode. The bottom three lines show the signals under downlink mode B, which can be a downlink measurement mode. For example... Figure 1A As indicated by arrow F, the medium can flow in the direction from the first transducer 11 to the second transducer 12. In uplink mode A, the first transducer 11 receives the output signal SOUT and the second transducer 12 generates the receive signal SIN. In downlink mode B, the first transducer 11 generates the receive signal SIN and the second transducer 12 receives the output signal SOUT. Figure 1B The first and fourth rows show the output signal SOUT, the second and fifth rows show the received signal SIN, and the third and sixth rows show the first comparator signal SCOM1.

[0054] Control circuit 32 can set instrument 10 to uplink mode A in a first stage, and then set instrument 10 to downlink mode B in a second stage. The second stage follows the first stage. Alternatively, control circuit 32 can set instrument 10 to downlink mode B in the first stage, and then set instrument 10 to uplink mode A in the second stage.

[0055] The first comparator signal SCOM1 and the output signal SOUT are implemented as pulse signals. The first comparator signal SCOM1 consists of a second number of K pulses. The output signal SOUT consists of a third number of N pulses. Figure 1BThe third quantity N shown is four. However, the third quantity N can be one, two, three, or greater than four. For example, the third quantity N of the pulses can be outside the range of 1≤N≤100 or 10≤N≤40. Each pulse of the output signal SOUT can have a 50% duty cycle. A series of pulses of the output signal SOUT can be called a "fire". The start of a series of pulses of the output signal SOUT can be triggered by the generator control signal SGEN. The start of operation of converter 22 is triggered by the start signal STA provided from the control circuit 32 to the start input terminal 33. When the series of pulses of the output signal SOUT begins, converter 22 also starts, Figure 1B The time point t0 is used as the indicator. Therefore, the start-up time of converter 22, t0, can be equal to the rising edge of the first pulse of the output signal SOUT.

[0056] The received signal SIN can also be referred to as the "received wave". Due to the transmission of ultrasound in the medium, there is a delay between the start of the output signal SOUT at t0 and the start of the available value of the received signal SIN. Some disturbances may exist in the received signal SIN before the pulse generated by the first transducer 11 is detected by the second transducer 12. Due to the damping provided by the fluid and due to the characteristics of the first transducer 11 and the second transducer 12, the received signal SIN does not have the form of a sharp pulse, but instead has a wave similar to a sine wave, which has an increasing amplitude at the beginning of a series of waves and a decreasing amplitude at the end of a series of waves.

[0057] The first comparator 23 uses the received signal SIN and the first reference voltage VR1 as inputs to generate a pulse-form first comparator signal SCOM1. The first comparator signal SCOM1 can be referred to as a "Time-of-Flight (ToF) hit". Typically, the second number K of the pulses of the first comparator signal SCOM1 is higher than the third number N of the pulses of the output signal SOUT. In uplink mode A, the rising edge of the first pulse of the first comparator signal SCOM1 has a first delay TOFA relative to the rising edge of the first pulse of the output signal SOUT. In uplink mode A, the first delay TOFA can be referred to as the "Time-of-Flight value" (or simply the ToF value).

[0058] In downlink mode B, the output signal SOUT can have the same number of pulses as the output signal SOUT in uplink mode A. Before the pulse generated by the second transducer 12 reaches the first transducer 11, the received signal SIN first shows some interference waves and can be detected in the received signal SIN. The output signal SOUT can be named "fire". The rising edge of the first pulse of the first comparator signal SCOM1 has a second delay TOFB relative to the rising edge of the first pulse of the output signal SOUT. In downlink mode B, the second delay TOFB can be called the "time of flight value". In the case of flow along this direction or arrow F, the second delay TOFB is greater than the first delay TOFA. Therefore, the time difference DIFTOF can be calculated according to the following formula:

[0059] DIFTOF = TOFB - TOFA

[0060] The time difference DIFTOF increases with increasing flow rate or velocity value (e.g., linearly dependent on said value). The time difference DIFTOF can also be called time deviation or time offset. Ideally, the time difference DIFTOF can be directly proportional to the flow rate or velocity value. Furthermore, ideally, the time difference DIFTOF can be zero or approximately zero at zero flow rate.

[0061] Instrument 10 is based on Time-of-Flight (ToF) measurement and uses TDC 22 to measure the zero-crossing of the received signal SIN. In an exemplary embodiment of instrument 10, averaging the measured zero-crossings (“hit”) allows for the calculation of the difference between the measured uplink and downlink, known as the Time Difference to Time (DIFTOF). This DIFTOF is a good measurement of the flow rate value to be determined. Multiple positive slopes of the first comparator signal SCOM1 can be defined and averaged for the calculation of the DIFTOF.

[0062] Figure 2A Another exemplary embodiment of the instrument 10 is shown, which is Figure 1AA further development of the exemplary embodiment shown. Instrument 10 further includes a first impedance circuit 41 and a second impedance circuit 42. The first impedance circuit 41 is coupled between a first terminal 13 and a first transducer 11. The second impedance circuit 42 is coupled between a second terminal 14 and a second transducer 12. Thus, one terminal of the first impedance circuit 41 is connected to the first terminal 13, and the other terminal of the first impedance circuit 41 is connected to the first terminal of the first transducer 11. Correspondingly, one terminal of the second impedance circuit 42 is connected to the second terminal 14, and the other terminal of the second impedance circuit 42 is connected to the first terminal of the second transducer 12. The other terminals of the first impedance circuit 41 and the second impedance circuit 42 can be connected to a reference potential terminal 15. The first impedance circuit 41 can be implemented as a variable impedance. The second impedance circuit 42 can also be implemented as a variable impedance.

[0063] Therefore, the first impedance control signal SI1 can be applied to the control terminal of the first impedance circuit 41. Similarly, the second impedance control signal SI2 can be provided to the control terminal of the second impedance circuit 42. Advantageously, the effects of mismatch between the first transducer 11 and the second transducer 12 can be reduced by the first impedance circuit 41 and / or the second impedance circuit 42. The first impedance control signal SI1 and / or the second impedance control signal SI2 are generated by the control circuit 32.

[0064] Figure 2B It shows that it can be used Figure 1A or Figure 2A An exemplary embodiment of the signal tapped at instrument 10. The first reference voltage source 27 can generate a first reference voltage VR1 with two different values, namely VR or VR+ΔV. In the first receiving phase R1, the first reference voltage VR1 has the value VR+ΔV, and in the second receiving phase R2, the first reference voltage VR1 has the value VR. The value VR can be equal to zero (or equal to the reference potential GND). The value ΔV is a voltage difference other than zero and can take a small positive value.

[0065] After the output signal SOUT begins, the first reference voltage source 27 provides the value VR+ΔV to the first reference voltage VR1. At the time tR when the first comparator signal SCOM1 receives the rising edge of the second pulse, the first receiving phase R1 ends and the second receiving phase R2 begins. In the first receiving phase R1, by using the first reference voltage VR1 = VR+ΔV, the influence of interference in the received signal SIN on the first comparator signal SCOM1 is reduced. Since the value of the received signal SIN is higher in the second receiving phase R2 due to the transmission of the pulse generated by the signal generator 16, the influence of interference remains low and the first reference voltage VR1 can be equal to the reference potential GND.

[0066] exist Figure 2B The diagram shows a typical received signal SIN and a typical first comparator signal SCOM1 in an ultrasonic stream. The complete measurement sequence is characterized by two such measurements, for both uplink and downlink measurements. The instrument 10 with TDC 22 features an optimization function that makes the time-domain hit patterns of the uplink and downlink receptions similar to each other (leaving only the mentioned time difference DIFTOF). The first comparator level VR1 is increased above zero to suppress noise signals, especially at the beginning.

[0067] Alternatively, the transition point tR between the first receiving stage R1 and the second receiving stage R2 can be set at the end of the first pulse of the first comparator signal SCOM1 or at another time point.

[0068] Figure 3A Another exemplary embodiment of the instrument 10 is shown, which is Figure 1A and Figure 2A A further development of the exemplary embodiment shown. The first impedance circuit 41 includes a first capacitor 45. The second impedance circuit 42 includes a second capacitor 46. The first capacitor 45 couples a first terminal 13 to a reference potential terminal 15. Similarly, the second capacitor 46 couples a second terminal 14 to the reference potential terminal 15. Therefore, the first capacitor 45 is connected in parallel to the first transducer 11. Similarly, the second capacitor 46 is connected in parallel to the second transducer 12.

[0069] The first capacitor 45 and / or the second capacitor 46 may have controllable variable capacitance. A first impedance control signal SI1 may be provided to the control terminal of the first capacitor 45. A second impedance control signal SI2 may be provided to the control terminal of the second capacitor 46. The resonant frequencies of the first transducer 11 and the second transducer 12 can be adjusted via the first capacitor 45 and the second capacitor 46. The first capacitor 45 and the second capacitor 46 are implemented as variable impedance. The capacitance values ​​of the first capacitor 45 and / or the second capacitor 46 are set by the control circuit 32.

[0070] Figure 3B As shown Figure 3A An exemplary embodiment of the signal of the instrument 10 shown. The first reference voltage VR1 can be referred to as the "zero-crossing level". Figure 3BThe diagram shows a received signal SIN, another received signal SIN', a first comparator signal SCOM1, and another comparator signal SCOM1'. The other comparator signal SCOM1' is generated by the first comparator 23 based on the other received signal SIN1'. Both different received signals SIN and SIN' are generated, for example, in uplink mode A. The difference between the two received signals SIN and SIN' is caused by the change in capacitance values ​​of the first capacitor 45 and / or the second capacitor 46 between the two measurements. The received signal SIN includes more pulses than the other received signal SIN'. This may be due to the fact that, in the case of generating the received signal SIN, the first impedance circuit 41 and the second impedance circuit 42 achieve a better match between the first transducer 11 and the second transducer 12 compared to generating the other received signal SIN'. The first impedance circuit 41 and the second impedance circuit 42 can achieve simple but effective resonant frequency tuning.

[0071] Figure 4A Another exemplary embodiment of the instrument 10 is shown, which is a further development of the exemplary embodiment described above. A signal generator 16 is coupled to a first transducer 11 via a first terminal 13 and a first impedance circuit 41. Additionally, a second transducer 12 is coupled to a signal input terminal 21 via a second impedance circuit 42 and a second terminal 14. The instrument 10 has no switching circuit. The signal generator 16 is implemented as an AC voltage generator. The output signal SOUT has a sine wave form. The first transducer 11 can be referred to as a "flameout transducer" and the second transducer 12 can be referred to as an "ignition transducer".

[0072] The signal evaluation circuit 20 includes comparators 23, 51, and 52 of a fourth quantity M. Figure 4A In the exemplary embodiment shown, the fourth quantity M of the comparator is three. Alternatively, the fourth quantity M of the comparator may also be as follows: Figure 1A , Figure 2A and Figure 3A One, two, or more than three are shown. The signal evaluation circuit 20 further includes a fourth number M of reference voltage sources 27, 53, and 54. Each of the fourth number M comparators 23, 51, and 52 is connected at its first input to the signal input 21. Each of the fourth number M comparators 23, 51, and 52 is connected at its second input to one of the fourth number M reference voltage sources 27, 53, and 54. The outputs of the fourth number M comparators 23, 51, and 52 are connected to the fourth number M inputs 26, 55, and 56 of the converter 22. Therefore, the second comparator 51 is connected at its output to the second input 55 of the converter 22. The third comparator 52 is connected at its output to the third input 56 of the converter 22.

[0073] The fourth number of reference voltage sources M, 27, 53, and 54, provide reference voltages VR1, VR2, and VR3 with different values. The first reference voltage VR1 can have, for example, as shown in the figure. Figure 2B The values ​​shown. The second reference voltage VR2, tapped at the second reference voltage source 53, is different from the reference potential GND. The third reference voltage VR3 is different from the reference potential GND and may have the same sign as the second reference voltage VR2, or it may have the opposite sign. When the fourth quantity M is three or greater than three, the reference voltages VR1 to VR3 of the fourth quantity M may have opposite signs.

[0074] Comparators 23, 51, and 52 of a fourth quantity M generate comparator signals SCOM1 to SCOM3 of a fourth quantity M. Advantageously, the positive and negative half-waves trigger pulses in different comparator signals SCOM1 to SCOM3. Converter 22 generates a first time signal SD1 at each pulse of the first comparator signal SCOM1, for example, at each rising or falling edge of the pulse of the first comparator signal SCOM1. The value of the first time signal SD1 represents the time between the start signal STA and the pulse of the first comparator signal SCOM1. Additionally, converter 22 generates a second time signal SD2, which includes the value generated after receiving the pulse of the second comparator signal SCOM2. Furthermore, converter 22 generates a third time signal SD3, which includes the value generated after receiving the pulse of the third comparator signal SCOM3. The first time signal SD1, the second time signal SD2, and the third time signal SD3 are provided to control circuit 32. The time signals SD1 to SD3 are digital signals.

[0075] like Figure 4A As indicated by the dots shown, the signal evaluation circuit 20 may include additional comparators and additional reference voltage generators. The proposed method can work with any number of comparators and can benefit from, for example, a large number of comparators; three comparators are shown for illustration only. A single TDC 22 can be used to detect hits at different levels or reference voltages VR1 to VR3.

[0076] The signal generator 16 can also be implemented as follows: Figure 1A , Figure 2A and Figure 3A The pulse generator shown.

[0077] Figure 4BAn alternative exemplary embodiment of instrument 10 is shown, which is a further development of the exemplary embodiment described above. Signal evaluation circuit 20 includes a fourth number M time-to-digital converters 22, 60, 61. A fourth number M comparators 23, 51, 52 are connected at their output sides to the fourth number M time-to-digital converters 22, 60, 61. For example, signal evaluation circuit 20 includes a second time-to-digital converter 60 and a third time-to-digital converter 61. The second time-to-digital converter 60 is connected at its input side to the output of the second comparator 51. Similarly, the third time-to-digital converter 60 is connected at its input side to the output of the third comparator 52. Each of the fourth number M time-to-digital converters 22, 60, 61 has a start input 33 and receives the same start signal STA.

[0078] The first impedance circuit 41 includes a first capacitor 45 coupling a first terminal of the first transducer 11 to a reference potential terminal 15. Furthermore, the first impedance circuit 41 includes a first resistor 62 coupling a first terminal of the first transducer 11 to a first terminal 13. Correspondingly, the second impedance circuit 42 includes a second capacitor 46 coupling a first terminal of the second transducer 12 to the reference potential terminal 15. Furthermore, the first impedance circuit 41 includes a second resistor 63 coupling a first terminal of the second transducer 12 to a second terminal 14.

[0079] Additionally, the first impedance circuit 41 includes a third resistor 64 that couples the first terminal of the first transducer 11 to the reference potential terminal 15. The second impedance circuit 42 includes a fourth resistor 65 that couples the first terminal of the second transducer 12 to the reference potential terminal 15.

[0080] Furthermore, the first impedance circuit 41 includes a third capacitor 66 that couples the first terminal of the first transducer 11 to the first terminal 13. The second impedance circuit 42 includes a fourth capacitor 67 that couples the first terminal of the second transducer 12 to the second terminal 14.

[0081] The first to fourth capacitors 45, 46, 66, and 67 can be controlled by the impedance control signal generated by the control circuit 32. The first to fourth resistors 62 to 65 can be controlled by the impedance control signal generated by the control circuit 32.

[0082] Therefore, the variable impedance of the first impedance circuit 41 is achieved by at least one element from the group consisting of a first capacitor 45 and a third capacitor 66, and a first resistor 62 and a third resistor 64. The variable impedance of the second impedance circuit 42 is achieved by at least one element from another group consisting of a second capacitor 45 and a fourth capacitor 67, and a second resistor 63 and a fourth resistor 65.

[0083] The first impedance circuit 41 and the second impedance circuit 42 allow tuning of twice the eight variables. Figure 4B Possible implementations with adjustable capacitors 45, 46, 66, and 67 and adjustable resistors 62 to 65 on both the transmitting and receiving sides are shown. The optimization variables are eight adjustable elements, which may have different values ​​in the uplink case (as shown) and in the downlink case (then the transducer and tuning elements are swapped). The optimization objective is to achieve nearly identical receive burst shapes in both the uplink and downlink cases.

[0084] Figure 4B This is just one possible implementation; the number, type, and connection of the tuning elements can vary arbitrarily. The TDC used and the fourth number M of the comparator are also not fixed; this method can operate with only one TDC and only one comparator. Instrument 10 uses a method to determine the optimal impedance by optimizing the similarity of the received burst shape, despite the residual time difference DIFTOF. This time difference DIFTOF is the actual measurement result.

[0085] Therefore, during the measurement phase, the control circuit 32 can set a first value of the variable impedance in uplink mode A and a second value of the variable impedance in downlink mode B. Alternatively, during the measurement phase, the control circuit 32 can set the same variable impedance value in both uplink mode A and downlink mode B.

[0086] It is also possible for only some circuit elements of the first impedance circuit 41 and the second impedance circuit 42 to be controllable; other circuit elements remain unchanged.

[0087] Figure 4C It shows the result of Figure 4A or Figure 4B An exemplary embodiment of the signal generated by the instrument 10 shown. The second reference voltage VR2 has a positive value relative to the reference potential GND, and the third reference voltage VR3 has a negative value relative to the reference potential GND. Figure 4C The diagram shows comparator signals SCOM1 to SCOM3 for receiving the signal SIN and a fourth quantity M. In an exemplary embodiment of instrument 10, the fourth quantity M is three. The number of waves in the received signal SIN is greater than the third pulse number N of the output signal SOUT. The first transducer 11, together with the first impedance circuit 41, the second transducer 12, together with the second impedance circuit 42, and the medium between the two transducers 11 and 12 form an oscillation system. Figure 4C As can be seen, the first comparator signal SCOM1 has a larger number of pulses compared to the second comparator signal SCOM2 and the third comparator signal SCOM3. This is due to the low analog values ​​of the received signal SIN at the first and last pulses of the received signal SIN.

[0088] Evaluate the positive and negative slopes of the three comparator signals SCOM1 through SCOM3. It is advantageous to eliminate noise from the evaluation, for example, by increasing the level of the first comparator 23 above the zero-crossing level. Other measures are also possible, such as using a delay for windowing or initiating the evaluation after one of the other comparators 51 or 52 receives a step signal.

[0089] Figure 4D It shows Figure 4C A detailed view of the signal shown. Figure 4D The diagram shows the first to third comparator signals SCOM1 to SCOM3, as well as the received signal SIN in uplink mode A and the received signal SIN* in downlink mode B. Therefore, the dashed lines represent a sketch of the received signal SIN* in the opposite measurement direction, characterized by the time difference DIFTOF. The time difference DIFTOF only obtains smaller values. Figure 4D An exemplary embodiment is illustrated in which the edges of the three comparator signals SCOM1 to SCOM3 can be explicitly named.

[0090] The time-to-digital converter 22 determines the values ​​of the first to third time signals SD1, SD2, and SD3 at each rising and falling edge of each pulse of the first to third comparator signals SCOM1, SCOM2, and SCOM3. The first comparator signal SCOM1 has a second number of pulses, K. A variable k is used, ranging from k=0 to k=K. In uplink mode A, the first time signal SD1 is the first uplink time signal SD1UP. The value of the first time signal SD1UP at the rising edge of the reference pulse is marked with P. The falling edge of the pulse is also converted to the value of the first time signal SD1UP and marked with M. Figure 4D Variables or names are written at the corresponding falling or rising edge of the pulse, such as TOF_1_C1_1_UP_P and TOF_1_C1_1_UP_M for the first time signal SD1UP. In downlink mode B, the first time signal SD1 is the first downlink time signal SD1DO.

[0091] Converter 22 at each rising edge of the first comparator signal SCOM1 (at Figure 4D In the process, the value of the first pulse is named TOF_1_C1_1_UP_P, the value of the second pulse is named TOF_2_C1_1_UP_P, etc.) or at the falling edge of each pulse of the first comparator signal SCOM1 (at Figure 4D In this process, the value of the first pulse is named TOF_1_C1_1_UP_M, the value of the second pulse is named TOF_2_C1_1_UP_M, etc., generating the first time signal SD1UP. Correspondingly, in Figure 4DIn this process, the value of the second time signal SD2UP at the rising edge of each pulse of the second comparator signal SCOM2 is named TOF_1_C2_1_UP_P for the first pulse, TOF_2_C2_1_UP_P for the second pulse, and so on; and the value of the second time signal SD2UP at the falling edge of each pulse of the second comparator signal SCOM2 is named TOF_1_C2_1_UP_M for the first pulse, TOF_2_C2_1_UP_M for the second pulse, and so on. The value of the third time signal SD3UP is named accordingly. These values ​​are indicated for uplink mode A.

[0092] exist Figure 4D In the first time signal SD1DO, the two values ​​TOF_1_C1_1_DOWN_P and TOF_1_C1_1_DOWN_M are indicated for use in downlink mode B. Figure 4D All the values ​​shown are determined using the first impedance value out of the first number L impedance values ​​of the variable impedance, therefore l = 1.

[0093] like Figure 4D The ToF measurement shown can be performed, for example, via six TDC channels (e.g., via the six inputs of a TDC22). Looking at the offset dashed line signal, the received signal SIN* is characterized by a global temporal offset from the corresponding ToF measurement result of the time difference DIFTOF. However, in real-world systems, the signal shapes of the uplink and downlink measurements do not perfectly match the desired picosecond level. Therefore, the difference between corresponding points of the uplink received signal SIN and the downlink received signal SIN* is not equal to the time difference DIFTOF, but rather a deviation from the time difference DIFTOF due to a lack of signal shape symmetry. In other words, in an example of arbitrarily selected point pairs,

[0094] (TOF_2_C1_1_UP-TOF_2_C1_1_DOWN-DIFTOF) 2 >0

[0095] Wherein, TOF_2_C1_1_UP is the value of the first time signal SD1UP for the second pulse (k=2) using the first comparator 23 (C1) in uplink mode A (UP), and TOF_2_C1_1_DOWN is the value of the first time signal SD1DO for the second pulse (k=2) using the first comparator 23 (C1) in downlink mode A (DOWN). For both values, the first impedance value of the variable impedance (I=1) is used. Ideally, the term on the left will be zero.

[0096] However, there are different methods available to increase signal symmetry, such as adding (adjustable) parallel capacitors 45 and 46 to the receiving transducers 11 and 12 in the receiving case (e.g.) Figure 3A and Figure 4B As shown), or by adjusting the resistor to change the transmission impedance and / or reception impedance (e.g. Figure 4B (As shown). This list is not exhaustive; typically, instrument 10 achieves a more symmetrical signal shape by applying tuning parameters (parallel and / or series impedances, frequency) to the signal path. Instrument 10 automatically adjusts the applied parameters. Appropriate parameter tuning is achieved through any optimization algorithm, with the goal of minimizing the sum f(l) of all differences corresponding to the ToF value.

[0097] If instrument 10 includes exactly one comparator, then the following formula can be used during the calibration phase:

[0098]

[0099] Wherein, TOF_k_C1_1_UP is the value of the first uplink time signal SD1UP for the k-th pulse of the first comparator signal SCOM1 (measured in uplink mode A), TOF_k_C1_1_DOWN is the value of the first downlink time signal SD1DO for the k-th pulse of the first comparator signal SCOM1 (measured in downlink mode A), and k is the index of a pulse in a pulse sequence of number K, ranging from 1 to K. Furthermore, 1 is the index of the first impedance value among a first number L impedance values ​​of the variable impedance.

[0100] During the calibration phase, the sum f(1) is determined for each of the first number L possible impedance values ​​or several values ​​of the variable impedance provided by the first impedance circuit 41 and the second impedance circuit 42. The optimal value of the first impedance circuit 41 and the second impedance circuit 42 is the value that the sum f(1) obtains in the calibration phase and will be used in the measurement phase after the calibration phase.

[0101] When instrument 10 includes a comparator of the fourth quantity M, the following formula can be used during the calibration phase:

[0102]

[0103] Wherein, TOF_k_Cm_l_UP is the value of the m-th uplink time signal SDmUP for the k-th pulse of the m-th comparator signal SCOMm (measured in uplink mode A), and TOF_k_Cm_l_DOWN is the value of the m-th downlink time signal SDmDO for the k-th pulse of the m-th comparator signal SCOMm (measured in downlink mode B). k is the index of a pulse in a pulse sequence of number K, ranging from 1 to K, and m is the index of a comparator in a fourth number M comparators, indicating the corresponding time signals SDmUP and SDmDO, ranging from 1 to M (therefore, the identifiers range from C1 to CM). The value of index l is 1 to L.

[0104] The parameters for the optimization process are the values ​​of the tunable hardware components mentioned above and the global time difference (DIFTOF). At the optimal point, the optimized DIFTOF is the desired measurement value, while the tuned impedance compensates for the system's asymmetry and thus approximates a symmetrical received signal shape. The optimized DIFTOF value is characterized by a lower offset than the corresponding measurement in an unoptimized system due to improved signal symmetry. This method is not limited to the case where DIFTOF = 0; it can be used under any flow conditions.

[0105] Therefore, the first impedance circuit 41 and the second impedance circuit 42 can obtain a first number of L possible impedance values. During the calibration phase, the control circuit 32 determines the optimal impedance value among the time difference DIFTOF and the first number of L possible impedance values, at which the sum f(l) is minimized. During the calibration phase, the control circuit 32 stores information about the first impedance control signal SI1 and the second impedance control signal SI2 (which may be bus signals) used subsequently in the measurement phase.

[0106] The values ​​of the first time signals SD1UP and SD1DO at the rising edge indicated by _P or at the falling edge indicated by _M, or both, can be used in the above formula. The values ​​of the second, third, or other time signals SD2Up, SD2DO, SD3UP, and SD3DO can be used in the same manner.

[0107] Advantageously, optimization can be performed entirely in the time domain, without the need for an analog-to-digital converter or a fast Fourier transform. This signal balancing method is efficiently accomplished based on TDC measurements in the time domain.

[0108] As shown in Figures 1 to 1 Figure 4DThe embodiments shown represent exemplary embodiments of the improved ultrasonic flow meter (hereinafter referred to as the meter); therefore, they do not constitute a complete list of all embodiments according to the improved meter. For example, actual ultrasonic flow meter configurations may differ from the exemplary embodiments shown in terms of circuitry, construction, shape, size, and quantity.

[0109] Figure Labels

[0110] 10. Ultrasonic Flow Meter

[0111] 11 First transducer

[0112] 12 Second transducer

[0113] 13 First terminal

[0114] 14 Second terminal

[0115] 15 Reference Potential Terminal

[0116] 16 Signal Generator

[0117] 17. Signal Output Terminal

[0118] 18 Control Input Terminals

[0119] 20 Signal Evaluation Circuit

[0120] 21 Signal Input Terminal

[0121] 22 Time to Digital Converter

[0122] 23 First Comparator

[0123] 24 First Input Terminal

[0124] 25 Output terminal

[0125] 26 First Input Terminal

[0126] 27 First Reference Voltage Source

[0127] 28 Second Input Terminal

[0128] 30 Pre-charge switch

[0129] 31 Reference voltage terminal

[0130] 32 Control Circuit

[0131] 33 Start Input Terminal

[0132] 35 Switching Circuit

[0133] 36 First changeover switch

[0134] 35 Switching Circuit

[0135] 36 First changeover switch

[0136] 37 Second changeover switch

[0137] 41 First Impedance Circuit

[0138] 42 Second Impedance Circuit

[0139] 45 First Capacitor

[0140] 46 Second capacitor

[0141] Comparators 51 and 52

[0142] 53, 54 Reference voltage sources

[0143] Input terminals 55 and 56

[0144] 60, 61 Time to Digital Converter

[0145] 62 to 65 resistors

[0146] Capacitors 66 and 67

[0147] A Uplink Mode

[0148] B Downlink Mode

[0149] DIFTOF time difference

[0150] F arrow

[0151] GND reference potential

[0152] R1, R2 receiving phase

[0153] SC1 and SC2 control signals

[0154] SCOM1 First Comparator Signal

[0155] SCOM2 Second Comparator Signal

[0156] SCOM3 Third Comparator Signal

[0157] SD1DO First Downlink Time Signal

[0158] SD1UP First Uplink Time Signal

[0159] SGEN generator control signal

[0160] SIN, SIN' received signals

[0161] SIN* Received Signal

[0162] SI1, SI2 impedance control signals

[0163] SOUT output signal

[0164] STA start signal

[0165] t time

[0166] TOFA First Delay

[0167] TOFB Second Delay

[0168] tR, t0 time points

[0169] VR reference voltage value

[0170] VR1, VR2, VR3 reference voltage

[0171] VRE Start Reference Voltage

[0172] ΔV differential voltage

Claims

1. An ultrasonic flow meter, comprising: First transducer (11) and second transducer (12). It includes a first impedance circuit (41) with variable impedance and a second impedance circuit (42). It is coupled to the first terminal (13) of the first transducer (11) via the first impedance circuit (41). It is coupled to the second terminal (14) of the second transducer (12) via the second impedance circuit (42). A signal generator (16) having a signal output terminal (17) and a signal evaluation circuit (20) having a signal input terminal (21), wherein the signal output terminal (17) and the signal input terminal (21) are coupled to a first terminal (13) and a second terminal (14), wherein the signal evaluation circuit (20) includes a time-to-digital converter (22) and a first comparator (23), the first comparator (23) coupling the signal input terminal (21) to a first input terminal (26) of the time-to-digital converter (22), and A control circuit (32), coupled to the signal generator (16), the signal evaluation circuit (20), and the variable impedance, is configured to set the ultrasonic flow meter (10) in an uplink mode (A) and a downlink mode (B), and to set the impedance value of the variable impedance based on the first uplink time signal (SD1UP) generated by the time-to-digital converter (22) in the uplink mode (A) and the first downlink time signal (SD1DO) generated by the time-to-digital converter (22) in the downlink mode (B).

2. The ultrasonic flow meter according to claim 1, in, The variable impedance is configured to obtain an impedance value from a first number of L impedance values.

3. The ultrasonic flow meter according to claim 1, wherein, The control circuit (32) is configured to optimize the impedance value of the variable impedance such that the first uplink time signal (SD1UP) and the first downlink time signal (SD1DO) are similar to each other and differ primarily in time difference (DIFTOF).

4. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, In the uplink mode (A), the first comparator (23) is configured to generate a first comparator signal (SCOM1) having a second number of K pulses, and the time-to-digital converter (22) is configured to generate a first uplink time signal (SD1UP), the first uplink time signal (SD1UP) having a value TOF_k_C1_l_UP corresponding to the second number of K pulses of the first comparator signal (SCOM1), and In the downlink mode (B), the first comparator (23) is configured to generate a first comparator signal (SCOM1) having a second number of K pulses, and the time-to-digital converter (22) is configured to generate a first downlink time signal (SD1DO), the first downlink time signal (SD1DO) having a second number of K values ​​TOF_k_C1_l_DOWN corresponding to the second number of K pulses of the first comparator signal (SCOM1).

5. The ultrasonic flow meter according to claim 4, in, The control circuit (32) is configured to determine the time difference (DIFTOF) and the l-th impedance value among a first number of L possible impedance values, at which the following sum f(l) is minimized: ， Wherein, TOF_k_C1_l_UP is the value of the first uplink time signal (SD1UP) generated at the kth pulse of the second number of K pulses of the first comparator signal (SCOM1) under the uplink mode (A), using the lth impedance value out of the first number of L impedance values ​​of the variable impedance. Wherein, TOF_k_C1_l_DOWN is the value of the first downlink time signal (SD1DO) generated at the kth pulse of the second number of K pulses of the first comparator signal (SCOM1) under the downlink mode (B), using the lth impedance value among the first number of L impedance values ​​of the variable impedance.

6. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, The signal generator (16) is configured to generate a square wave signal (SOUT) with a third number of N pulses.

7. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, The signal evaluation circuit (20) includes at least a second comparator that couples the signal input (21) to at least a second input of the time-to-digital converter (22).

8. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, The signal evaluation circuit (20) includes a fourth number of M comparators. The control circuit (32) is configured to determine the time difference (DIFTOF) and the l-th impedance value among a first number of L possible impedance values, at which the following sum f(l) is minimized: ， Wherein, TOF_k_Cm_l_UP is the value of the first uplink time signal (SD1UP) generated at the kth pulse of the second number of K pulses of the m-th comparator signals (SCOM1-SCOM3) using the l-th impedance value out of the first number of L impedance values ​​of the variable impedance in the uplink mode (A), and Wherein, TOF_k_Cm_l_DOWN is the value of the first downlink time signal (SD1DO) generated at the kth pulse of the second number of K pulses of the m comparator signals (SCOM1-SCOM3) using the lth impedance value among the first number of L impedance values ​​of the variable impedance in the downlink mode (B).

9. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, One of the first impedance circuit (41) and the second impedance circuit (42) has a variable impedance with an impedance value set by the control circuit (32), and the other of the first impedance circuit (41) and the second impedance circuit (42) does not have an impedance with a variable impedance value, or The first impedance circuit (41) includes a variable impedance having an impedance value set by the control circuit (32), and the second impedance circuit (42) includes another variable impedance having another impedance value set by the control circuit (32).

10. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, The first impedance circuit (41) includes a first capacitor (45), the first capacitor (45) having a first electrode connected to a first terminal of the first transducer (11) and a second electrode connected to a second terminal of the first transducer (11), and The second impedance circuit (42) includes a second capacitor (46) having a first electrode connected to a first terminal of the second transducer (12) and a second electrode connected to a second terminal of the second transducer (12).

11. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, The first transducer (11) is an uplink transducer, and the second transducer (12) is a downlink transducer.

12. The ultrasonic flow meter according to any one of claims 1 to 3, wherein, The ultrasonic flow meter (10) includes a switching circuit (35), and The signal output terminal (17) and the signal input terminal (21) are coupled to the first terminal (13) and the second terminal (14) through the switching circuit (35).

13. A method for ultrasonic flow measurement, comprising: - The ultrasonic flow meter (10) is operated in uplink mode (A) and downlink mode (B) by coupling the signal output terminal (17) of the signal generator (16) and the signal input terminal (21) of the signal evaluation circuit (20) to the first terminal (13) and the second terminal (14). - The control circuit (32) sets the impedance value of the variable impedance based on the first uplink time signal (SD1UP) generated by the time-to-digital converter (22) in uplink mode (A) and the first downlink time signal (SD1DO) generated by the time-to-digital converter (22) in downlink mode (B). The first impedance circuit (41) and the second impedance circuit (42) include variable impedances. The first terminal (13) is coupled to the first transducer (11) via the first impedance circuit (41), and the second terminal (14) is coupled to the second transducer (12) via the second impedance circuit (42). The signal evaluation circuit (20) includes the time-to-digital converter (22) and a first comparator (23), wherein the first comparator (23) couples the signal input terminal (21) to the first input terminal (26) of the time-to-digital converter (22).

14. The method according to claim 13, in, In the uplink mode (A), the switching circuit (35) couples the signal output terminal (17) of the signal generator (16) to the first terminal (13) and the signal input terminal (21) of the signal evaluation circuit (20) to the second terminal (14), and In the downlink mode (B), the switching circuit (35) couples the signal output terminal (17) of the signal generator (16) to the second terminal (14) and the signal input terminal (21) of the signal evaluation circuit (20) to the first terminal (13).

Images