On-site Monitoring of On-chip Thermal, Power Distribution Networks, and Grid Reliability

Abstract

Various embodiments may include methods and systems for monitoring characteristics of a system-on-chip. Various embodiments may include: inputting test data into a first scan chain segment from a test data input connection, the first scan chain segment including a first set of logic gates located within a first region of the SoC. Various embodiments may include: providing a clock signal to the first set of logic gates from a first clock gate associated with the first region of the SoC. Various embodiments may include: measuring the characteristic at a second region of the SoC using a first sensor in response to providing the clock signal to the first set of logic gates. Embodiments may also include: processing or analyzing the measured characteristic to determine a test result.

Description

[0001] Claiming priority under 35 U.S.C. § 119

[0002] This application claims priority to U.S. Patent Application No. 16 / 826,729, filed on March 23, 2020, entitled "IN-FIELD MONITORING OF ON-CHIP THERMAL, POWER DISTRIBUTION NETWORK, AND POWER GRID RELIABILITY", which is hereby incorporated by reference in its entirety. BACKGROUND OF THE INVENTION

[0003] System-on-chip (SoC) designs and devices have become increasingly complex, enabling smaller physical footprints and continuously decreasing conductor path sizes for transmitting data at higher rates than previous SoCs. Operating at higher speeds with greater physical design constraints can increase power requirements, which can increase the temperature that the SoC experiences during operation. Higher temperatures during testing, startup, and normal operation can increase the risk of initialization and runtime errors within the SoC. These and other errors (such as those introduced in a malicious attack) may occur at a higher rate when the circuitry within the SoC ages or when the power grid fails or malfunctions. SUMMARY OF THE INVENTION

[0004] Various aspects include methods and circuitry for monitoring in-field characteristics of a system-on-chip (SoC). Various aspects can include: inputting test data into a first scan chain segment from a test data input connection, the first scan chain segment including a first set of logic gates located within a first region of the SoC; providing a clock signal to the first set of logic gates from a first clock gate associated with the first region of the SoC; and in response to providing the clock signal to the first set of logic gates, measuring a characteristic at a second region of the SoC using a first sensor.

[0005] Some aspects may include: configuring a first clock gate via a clock gate controller to provide a clock signal to a first set of logic gates; and in response to configuring the first clock gate to provide the clock signal to the first set of logic gates, configuring a second clock gate associated with a second region of the SoC via the clock gate controller to gate the clock signal from entering a second set of logic gates, wherein the second scan chain segment includes the second set of logic gates located within the second region of the SoC. Various aspects may also include: inputting test data into the second scan chain segment from a test data input connection; configuring the second clock gate via the clock gate controller to provide the clock signal to the second set of logic gates; and in response to configuring the second scan to provide the clock signal to the second set of logic gates, configuring the first clock gate via the clock gate controller to gate the clock signal from entering the first set of logic gates. Various aspects may also include: providing the clock signal from the second clock gate to the second set of logic gates; and in response to providing the clock signal to the second set of logic gates, measuring a characteristic at a first region of the SoC using a second sensor.

[0006] In some aspects, the on-site characteristics may include thermal characteristics, voltage drop, and power grid characteristics. In some aspects, the clock gate controller may be provided with a high-speed clock or a turbo shift clock.

[0007] Some aspects may also include: generating test data from a pattern generator, wherein inputting the test data into the first set of logic gates and the second set of logic gates may also include serially shifting the test data into the first set of logic gates and the second set of logic gates.

[0008] In some aspects, the first region and the second region may be arranged in a grid configuration logic, which has a plurality of scan chain segments corresponding to multiple regions of the SoC.

[0009] In some aspects, the first sensor and the second sensor may be temperature sensors, and the characteristic may be the temperature of the corresponding region. In some aspects, the first sensor and the second sensor may be voltage sensors, and the characteristic may be the voltage in the corresponding region.

[0010] Some aspects may include: comparing the measured values of the characteristics of the first sensor and the second sensor with thresholds corresponding to the respective regions; in response to the measured characteristic exceeding the threshold, identifying an error in the SoC, wherein the error is an indication of an aging power delivery network, an on-chip or off-chip power attack, or a hard error; and in response to identifying the error, implementing a remedial action.

[0011] Some aspects may include: generating test data input to the first scan chain section and the second scan chain section by a pattern generator coupled to a test data input connection. In some aspects, the logic gates in the first set of logic gates may be serially connected, the logic gates in the second set of logic gates may be serially connected, and inputting the test data into the first scan chain section and the second scan chain section may further include serially shifting the test data through the first set of logic gates and the second set of logic gates.

[0012] In some aspects, the first region and the second region may be logically arranged in a grid configuration, where multiple scan chain sections correspond to multiple regions of the SoC.

[0013] Other aspects include a non-transitory processor-readable storage medium storing processor-executable software instructions configured to cause a processor to perform the operations of any of the methods outlined above. Other aspects include a system-on-chip (SoC) having components for performing the functions of any of the methods outlined above.

[0014] Other aspects include a system-on-chip configured to implement any of the methods outlined above. The SoC may include: a first scan chain section, which may include a first set of logic gates located in a first region of the SoC; and a first clock gate configurable to provide a clock signal to the first set of logic gates. In some aspects, the first clock gate may be associated with the first region. The SoC may further include: a test data input connection configured to input test data into the first scan chain section; and a first sensor configured to measure a characteristic at a second region of the SoC.

[0015] Some aspects of the SoC may further include: a second scan chain section, which may include a second set of logic gates located in a second region of the SoC; and a second clock gate configurable to provide a clock signal to the second set of logic gates. In some aspects, the second clock gate may be associated with the second region. The SoC may further include: a second sensor configured to measure a characteristic at the first region of the SoC; and a clock gate controller configured to control the first clock gate to provide a clock signal to the first set of logic gates while controlling the second clock gate to gate the clock signal from entering the second set of logic gates, and to control the second clock gate to provide a clock signal to the second set of logic gates while controlling the first clock gate to gate the clock signal from entering the first set of logic gates. In some aspects, the test data input connection may be configured to input test data into the second scan chain section, the first sensor may be configured to measure a characteristic at the second region in response to the clock signal provided to the first set of logic gates, and the second sensor may be configured to measure a characteristic at the first region in response to the clock signal provided to the second set of logic gates.

[0016] In some aspects, the SoC can also be configured to: compare the characteristic measurements of the first sensor and the second sensor with thresholds corresponding to the respective regions; identify an error in the SoC in response to the measured characteristic exceeding the threshold; and implement a remedial action in response to identifying the error. In some aspects, the error can be an indication of an aging power delivery network, an on-chip or off-chip power attack, or a hard error.

[0017] Some aspects of the SoC can also include a pattern generator, coupled to the test data input connection and configured to generate test data input to the first scan chain section and the second scan chain section.

[0018] In some aspects, the logic gates in the first set of logic gates can be serially connected, and the logic gates in the second set of logic gates can be serially connected. In some aspects, the test data can be input into the first scan chain section and the second scan chain section by serially shifting the test data through the first set of logic gates and the second set of logic gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings incorporated herein and constituting a part of this specification illustrate exemplary embodiments and, together with the general description given above and the detailed description given below, serve to explain the features of the various embodiments.

[0020] Figure 1 Illustrates a system including a computing device suitable for implementing various embodiments.

[0021] Figure 2A Illustrates an example of a conventional scan chain layer 200 before scan stitching.

[0022] Figure 2B Illustrates an example of a conventional scan chain layer 200 after scan stitching.

[0023] Figure 2C Illustrates an example of a portion of a conventional scan chain layer 200 including integrated clock gating.

[0024] Figure 3 Illustrates an overview of a scan chain layer during the design process suitable for implementing various embodiments.

[0025] Figure 4 Illustrates an overview of a scan chain layer incorporating clock gating for implementing various embodiments.

[0026] Figure 5 Illustrates an overview of two example scan chain grid portions of a scan chain layer for implementing various embodiments.

[0027] Figure 6A block diagram of a scan chain grid section with a flip-flop for implementing various embodiments is illustrated.

[0028] Figure 7 A block diagram of multiple scan chain grid sections between a decompressor and a compressor for implementing various embodiments is illustrated.

[0029] Figure 8 A process flow diagram is a process flow diagram of an exemplary method for monitoring on-chip system in-situ characteristics according to various embodiments.

[0030] Figure 9 A process flow diagram is a process flow diagram of an exemplary method for monitoring on-chip system in-situ characteristics including a second scan chain section according to various embodiments.

[0031] Figure 10 A component block diagram is a component block diagram of an exemplary wireless communication device suitable for use with various embodiments.

[0032] Figure 11 A component block diagram is a component block diagram of an exemplary computing device suitable for use with various embodiments.

[0033] Figure 12 A component block diagram is a component block diagram of an exemplary server suitable for use with various embodiments. Detailed Description

[0034] Aspects will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. References to specific examples and embodiments are for illustrative purposes only and are not intended to limit the scope of the aspects or the claims.

[0035] The term "system-on-chip" (SoC) is used herein to refer to a set of interconnected electronic circuits, typically but not exclusively including processing devices, memory, and communication interfaces. Processing devices can include various different types of processors 14 and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), subsystem processors for specific components of a computing device, such as an image processor for a camera subsystem or a display processor for a display, auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. Processing devices can also be implemented as other hardware and hardware combinations, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and time references. The integrated circuit can be configured such that the components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0036] As used herein, the term "computing device" refers to any one or all of a vehicle management system, a display subsystem, a driver assistance system, a vehicle controller, a vehicle system controller, a vehicle communication system, an infotainment system, a vehicle display system or subsystem, a vehicle data controller or router, a cellular phone, a smart phone, a personal or mobile multimedia player, a personal digital assistant (PDA), a laptop computer, a personal computer, a tablet computer, a smartbook, a palmtop computer, a wireless e-mail receiver, a multimedia Internet-enabled cellular phone, a vehicle controller, and similar electronic devices, including a programmable processor and memory and circuitry configured to perform the operations described herein.

[0037] For ease of reference, the term "scan chain" is used to refer to a technique for design for test (DFT) technology. Scan chain testing includes techniques that allow a SoC or any other computing device with a processor to selectively activate or use all of the flip-flops in the scan chain layer of a design as shift registers during a scan test. The scan chain layer can be a physical layer within the SoC that is inserted into the stack-up of the design layout. The flip-flops within the scan chain layer of the SoC are connected to combinational logic that is used to perform the various functions of the SoC. Scan chain testing can be used to test the functional hierarchy (e.g., CPU, GPU, etc.) of a computing device or SoC. A scan chain can include a serial grouping of multiple flip-flops within a circuit design, where each flip-flop contains at least two logic gates. In some embodiments, scan chain testing can include shifting data patterns into the SoC, where the flip-flops within the scan chain capture functional data generated by the test pattern, and the input pattern and the results of the flip-flop data capture are shifted out of the flip-flops. By connecting storage elements (e.g., flip-flops with two or more logic gates) to a long shift register or scan chain and by enhancing the logic of these elements to support a scan shift mode that allows serial loading and unloading of scan chain content, this internal scan improves the controllability and observability of the SoC logic.

[0038] As used herein, the term "scan stitching" refers to the process of logically and / or physically (e.g., electrically) connecting flip-flops to create a scan chain. Scan stitching can be implemented during the design process of an SoC or other computing device to map or "link" various flip-flops within a chip design together. Conventional scan stitching can include serially connecting flip-flops to create a scan chain using a netlist. In some embodiments, as opposed to using a netlist to create a scan chain, scan stitching can be physical-aware scan stitching, which sorts flip-flops based on their physical location within a chip design. Physical-aware scan stitching can include sorting flip-flops in such a way as to minimize the total physical length of the resulting scan chain to reduce DFT test time. Thermal grid-aware scan stitching refers to the process of grouping and connecting flip-flops based on the logical grid configuration of an SoC to create scan chain segments or sections.

[0039] As used herein, the term "scan chain section" refers to one flip-flop or a series of flip-flops used to perform scan chain testing. In some embodiments, a scan chain section can be a reconfigured or redesigned section or part within a scan chain layer. For example, a scan chain can be reconfigured into multiple independent scan chain sections during the design phase of a computing device. For example, a prefabricated scan chain can be organized via physical-aware scan stitching and then separated into scan chain sections (i.e., separate groups of flip-flops) that can be individually activated and tested, each section having test data inputs and outputs.

[0040] As used herein, the term "flip-flop" refers to a circuit that has two stable states and can be used to store state information. A flip-flop can include at least two logic gates to perform the storage function. A group of at least two flip-flops in a series configuration can be used as a shift register to serially shift state information bit by bit through the flip-flops. In some embodiments, a flip-flop can be referred to as a latch.

[0041] As used herein, the term "spatially" can refer to the physical layout and stack-up or the physical orientation and / or location of system components or regions within a computing device. For example, a group of flip-flops can be said to be spatially associated with a grid portion of an SoC, where the SoC is logically divided into respective parts with respect to the physical layout and / or stack-up of the SoC. A group of flip-flops can be spatially associated with a grid portion such that the group of flip-flops can be physically located within the logical boundaries of the grid portion. As another example, a group of flip-flops or a group of logic gates can be spatially associated with a scan chain section, and thus the scan chain section can be spatially associated with a corresponding grid portion that is spatially associated with the group of flip-flops.

[0042] As used herein, the term "mesh portion" refers to a physical portion of the SoC in three-dimensional space. For example, a mesh portion can be the volume in which the SoC is fabricated, where the mesh portion is different from other mesh portions arranged in a top-down view of the SoC fabrication. A mesh portion can include one or more SoC stacks or layers or a portion of one or more stacks or layers within the SoC. In some embodiments, a mesh portion can be referred to as a region of the SoC. In some embodiments, a portion of the SoC can not be a mesh portion, but can be a physical portion of the SoC having a volume and / or shape defined differently from the mesh configuration. For example, a portion of the SoC can be rectangular in size, or can be any other shape and volume determined during the design phase of the SoC. Thus, the SoC can be logically divided into any number of portions or regions, each having any kind of volume, such that a single SoC can be logically divided into at least two portions.

[0043] Various embodiments include methods, system-on-chip (SoC) designs, processing devices, and memories that are configured to implement methods for monitoring in-situ characteristics of an SoC. Various embodiments can be configured to monitor in-situ characteristics by implementing a scan chain to sequentially input test data into a group of logic gates corresponding to a physical region of the SoC and by measuring on-chip thermal, IR drop, and power grid reliability in response to the scan chain inputting the test data.

[0044] Continuous and in-situ monitoring of on-chip thermal characteristics, IR drop, and power grid reliability are important safety and security requirements in certain types of systems, processors, and SoCs. These in-situ characteristics can be particularly critical in systems where human safety is a priority, such as motor vehicle systems. A failure or unexpected degradation of an SoC that controls safety features or other features for normal operation (e.g., through excessive IR drop, power grid degradation, electromigration, etc.) can occur with too little or no warning of an impending failure or error.

[0045] Existing sensors (such as temperature and voltage sensors) located throughout the physical profile of the SoC can provide readings of temperature and voltage values under a given workload. However, the execution of a typical workload performing common operations may not execute in the SoC sufficient remote and discretized logic to activate online monitoring of all regions of the SoC. For example, the workload can include a functional data pattern that activates combinational logic corresponding to the GPU, which can create power demands within a region of the SoC including the GPU over a period of time. As another example, the workload can include a functional data pattern that activates combinational logic corresponding to the CPU, which can create power demands within different regions of the same SoC over a period of time. When either workload functional mode is implemented, the remainder of the SoC may be inactive or may not fully utilize the scope of combinational logic of a particular SoC function. Thus, conventional workloads may not provide power consumption that is stringent enough (i.e., sufficient temperature conditions) to discover or highlight potential problems within the SoC that may be caused by thermal and electrical conditions. Therefore, measuring temperature and voltage values under conventional workloads may not help isolate and specifically identify the exact cause of an SoC error or fault (e.g., an aging power delivery network, an increased IR drop value, an on-chip or off-chip power attack, a hard error, etc.).

[0046] Compared to the functional workload during normal operation, conventional scan chain testing attempts to provide a more stringent test of the SoC. Conventional scan chains typically activate all flip-flops within a scan chain layer simultaneously, resulting in all associated combinational logic being activated simultaneously in response. Thus, measuring thermal and electrical characteristics during scan chain activation can provide some insight into potential overall problems within the SoC (e.g., thermal "hot spots", power constraints). However, because conventional scan chains are activated in an all-or-nothing manner, conventional scan chains may not allow identification of the specific source of any observed problems or out-of-limit conditions. For example, activating a conventional scan chain may be able to detect a thermal hot spot; however, the specific circuitry within the SoC that causes the thermal problem may not be identifiable based on conventional scan chain activation.

[0047] Various embodiments address safety and security considerations through continuous and in-situ monitoring of on-chip thermal, power distribution networks, and grid reliability. Various embodiments can identify errors or faults associated with aging of the power grid on the SoC, which over time may lead to in-field functional failures due to poor voltage delivery. Various embodiments can identify trojans or hard attacks, which may result in high power leakage paths or burnouts when specific logic gates are activated. Various embodiments can further characterize the thermal path from an individual gate to the rest of the SoC to confirm expected operation and the absence of off-chip effects (e.g., redistribution layers).

[0048] Various embodiments include an SoC design that is particularly suitable for safety and security critical applications. For example, various embodiments may include circuitry, mechanisms, and methods for activating selected and specific portions of the SoC design during in-field operation. Various embodiments may include circuitry and mechanisms to detect any changes in the SoC power delivery network (or power grid), such as those caused by aging or attack, by capturing the electrical response within the SoC caused by activating a specific design segment within the SoC. As another example, some embodiments may include circuitry and mechanisms to detect changes in the thermal path (i.e., on-chip and off-chip) by capturing the thermal response after activating a specific design segment within the SoC. As a further example, some embodiments may include circuitry and mechanisms to detect any Trojans or hard faults in the design during in-field operation.

[0049] Various embodiments include separating a scan chain design into multiple segments and clock gating each individual segment. Separating the scan chain design into multiple segments can allow for the creation and testing of highly localized power-intensive regions on the SoC. By powering and / or activating each scan chain segment individually, sequentially, or in any other configuration, various embodiments are able to measure the thermal and electrical responses present in other unpowered and / or unactivated segments within the SoC. This allows for in-field testing to isolate potential problems (e.g., aging power delivery network, increased IR drop values, on-chip or off-chip power attacks, hard errors, etc.) based on the responses measured throughout the SoC, which are generated by each individually activated scan chain segment.

[0050] In some embodiments, the scan chain can be partitioned into individually logically located grid segments corresponding to the physical profile of the SoC. For example, during the physical design phase of the SoC, the physical profile of the SoC can be decomposed into a grid with different grid portions. Each grid portion can be logically overlaid on top of the SoC physical profile such that each logical grid portion can be associated with circuitry within the corresponding physical region of the SoC. Thus, the flip-flops of the scan chain layer can be similarly separated based on the grid configuration, where each portion of the grid can be associated with multiple flip-flops. The flip-flops within each grid can be linked or stitched together to create a single scan chain segment or section, where each section can be individually activated to generate and measure the thermal and electrical responses at every other segment of the grid-based scan chain. Thus, thermal grid-aware scan stitching can stitch the flip-flops together in order to determine the thermal characteristics in a grid or grid-like configuration.

[0051] Grid-based scan chain segmentation can be clocked to individually activate each scan chain segment in order to measure the corresponding response at each other grid section. For example, the scan chain layer can be designed to include clock gates before and after each section of the grid (i.e., to isolate each scan chain segment). This allows gating off the clock propagation to downstream and upstream logic (i.e., other flip-flops and their associated combinational logic in other sections of the grid). Thus, various embodiments can provide a clock signal to a single set of flip-flops associated with a grid section while gating the clock signal from entering other flip-flops associated with other grid sections.

[0052] After design and tape-out, each clock gate associated with each grid section can be serially selected and activated by software to sequentially activate each chain of the corresponding flip-flops. For example, clocking one grid section (i.e., the flip-flops physically associated with that logical grid section) may produce a measurable response in temperature and voltage sensors in other grid sections whose clocks are gated off. Each section of the grid can be sequentially activated by a clock gate controller to allow the SoC to determine the response at each grid section that is clock-gated off. The temperature and voltage measurements can be used for system characterization to identify potential problems caused by the clocked flip-flops associated with the activated grid section. In some embodiments, the thermal and electrical characteristics of the activated grid section can be measured individually or together with other grid sections whose clocks are gated off. Thus, the scan chain grid configuration can enable measuring the thermal and electrical responses across any combination of clocked or clock-gated-off grid sections in response to activating any single grid section or any combination of grid sections. For example, one grid section can be activated, and the thermal and electrical responses can be measured simultaneously across the activated grid section, another single grid section, multiple different grid sections, or all grid sections.

[0053] In some embodiments, the clock signaling used to activate each individual grid section or scan chain segment can be a high-speed clock signal (e.g., a turbo shift clock, a 3.2 GHz clock). Shifting data inputs into each set of flip-flops at a high frequency may cause the SoC to draw power at levels higher than normal operation (sometimes referred to herein as "high power") to implement the combinational logic associated with each clocked flip-flop. By increasing the power requirements for shifting data into flip-flops at high speed, the thermal and electrical responses generated at other sections of the SoC may be more easily measurable, and thus any associated errors or attacks may be more easily identifiable. Accordingly, various embodiments enable individual grid sections to be briefly activated while obtaining characteristic measurements (e.g., temperature, voltage, current, etc.) in other grid sections, and repeating the process quickly for many or all individual grid sections such that the measured characteristics are on average consistent with normal operation (where many grids are activated), while enabling variations in the measurements to be associated with a particular one or a few grid sections. This ability enables the potential performance of lifetime-limiting problems occurring during normal operation to be detected, while enabling the source of such problems to be localized to one or a few grid sections.

[0054] Figure 1 Illustrated is a system including a computing device 10 suitable for use with various embodiments. The computing device 10 may include a SoC 12 having a processor 14, a memory 16, a communication interface 18, a storage memory interface 20, and a sensor 28. The computing device 10 may also include a communication component 22 (such as a wired or wireless modem), a storage memory 24, and an antenna 26 for establishing a wireless communication link. The processor 14 may include any of a variety of processing devices, such as multiple processor cores.

[0055] The SoC 12 may include one or more processors 14. The computing device 10 may include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. The computing device 10 may also include a processor 14 not associated with the SoC 12. An individual processor 14 may be a multi-core processor. The processors 14 may be respectively configured for specific purposes that may be the same as or different from other processors 14 of the computing device 10. One or more of the processors 14 and processor cores of the same or different configurations may be grouped together. A group of processors 14 or processor cores may be referred to as a multi-processor cluster.

[0056] The memory 16 of the SoC 12 can be volatile or non-volatile memory, configured to store data and processor-executable code for access by the processor 14. The computing device 10 and / or the SoC 12 can include one or more memories 16, configured for various purposes. One or more memories 16 can include volatile memory, such as random access memory (RAM) or main memory or cache memory. These memories 16 can be configured to temporarily hold a limited amount of data received from a data sensor or subsystem, data and / or processor-executable code instructions requested from non-volatile memory, loaded into the memory 16 from non-volatile memory based on various factors for anticipated future access, and / or intermediate processing data and / or processor-executable code instructions generated by the processor 14 and temporarily stored for future quick access without being stored in non-volatile memory.

[0057] The memory 16 can be configured to at least temporarily store data and processor-executable code that is loaded into the memory 16 from another memory device (such as another memory 16 or the storage memory 24) for access by one or more processors 14. The data or processor-executable code loaded into the memory 16 can be loaded in response to the execution of a function by the processor 14. Loading the data or processor-executable code into the memory 16 in response to the execution of a function may be caused by an unsuccessful memory access request or a "miss" to the memory 16 because the requested data or processor-executable code is not located in the memory 16. In response to a miss, a memory access request can be made to another memory 16 or the storage memory 24 to load the requested data or processor-executable code from the other memory 16 or the storage memory 24 into the memory 16. Loading the data or processor-executable code into the memory 16 in response to the execution of a function can be generated by a memory access request to another memory 16 or the storage memory 24, and the data or processor-executable code can be loaded into the memory 16 for later access.

[0058] The storage memory interface 20 and the storage memory 24 can work together to allow the computing device 10 to store data and processor-executable code on a non-volatile storage medium. The storage memory 24 can be configured very similarly to an embodiment of the memory 16, where the storage memory 24 can store data or processor-executable code for access by one or more processors 14. The non-volatile storage memory 24 can retain information after the power of the computing device 10 has been turned off. When the power is reconnected and the computing device 10 restarts, the information stored on the storage memory 24 can be available to the computing device 10. The storage memory interface 20 can control access to the storage memory 24 and allow the processor 14 to read data from and write data to the storage memory 24.

[0059] The sensor 28 can be communicatively coupled to the processor 14, the memory 16, the communication interface 18, and the storage memory 20 via a bus or other communication link. The sensor 28 can include a thermal sensor and / or a voltage sensor physically located within the SoC 12. The sensor 28 can measure the thermal and electrical characteristics (e.g., temperature and voltage values) of the entire SoC 12 during test and normal operation procedures, as described in the embodiments. The temperature values and voltage values measured by the sensor 28 can be communicated to the processor 14 for processing, stored in the memory 16, and / or communicated from the SoC 12 via the communication interface 18 to other components in the computing device 10.

[0060] Some or all of the components of the computing device 10 and / or the SoC 12 can be differently arranged and / or combined while still serving the functions of the various embodiments. The computing device 10 is not limited to one of each of the components, and multiple instances of each component can be included in various configurations of the computing device 10. For example, the communication interface 18 can be used to communicate the measured field characteristics to the communication component 22. The communication component 22 can relay the measured field characteristics to an external additional computing device for diagnosing any errors based on the field characteristics. Similarly, the memory 16, the storage memory interface 20, and the storage memory 24 can store and communicate the measured field characteristics and other associated data according to the various embodiments.

[0061] Figure 2A An example of a conventional scan chain layer 200 before scan stitching is illustrated. The scan chain layer 200 can be an integrated circuit layer within the SoC 206 having various flip-flops 202 and integrated clock gating (ICG) components 204. The ICG component 204 can be used to clock gate the flip-flops 202 after connecting the flip-flops via scan stitching. The SoC 206 layout has multiple flip-flops 202 and multiple ICG components 204.

[0062] Figure 2B An example of a conventional scan chain layer 200 after scan stitching is illustrated. A typical implementation of a scan chain includes serially coupling multiple flip-flops (or scan registers) to form one or more scan chains within the SoC. During the design phase of the SoC, the scan chain layer can be implemented to implement DFT to locate potential problems within the SoC. The purpose of implementing a scan chain within the SoC is to simplify testing by providing a way to set and observe each flip-flop in the SoC.

[0063] As Figure 2BAs illustrated, multiple flip-flops 202 in the SoC 206 are connected together to form a single scan chain. During the design phase of a conventional SoC 206, normal or logical scan stitching is performed based on a generated netlist such that the stitching or linking of the flip-flops within the scan chain layer 200 for testing purposes is serially ordered according to the netlist. The result of the conventional stitching of the scan chain layer 200 is illustrated by a scan chain 210 that sequentially connects each of the flip-flops 202 without regard to the physical location within the outline of the SoC 206. The scan chain 210 is illustrated as a dotted line for representation purposes only and represents only the logical connections between the flip-flops 202, and not the physical / electrical connections as shown in the circuit schematic. For example, as shown in FIG. Figure 2B The scan chain 210 shown in the illustrated conventional scan chain layer 200 may start with a flip-flop 208. The flip-flop 208 may be electrically connected to a flip-flop 214, as logically shown by line 210. Scan chain stitching may continue to connect the remaining flip-flops 202 until each flip-flop within the scan chain layer 200 has been included in a scan chain 210.

[0064] In conventional scan chain designs, "scan_in" and "scan_out" signals, among others, define the inputs and outputs of the scan chain, where the scan_in signal can be a predefined test pattern or a randomly generated test pattern. The scan_in signal can be input to the first flip-flop within the scan chain, and the last flip-flop in the scan chain can output a scan_out signal that includes information about the response of the combinational logic to the scan_in signal (i.e., the state of each flip-flop in the scan chain). For example, the scan_in signal can be input to flip-flop 208 and serially shifted through the remaining flip-flops 202 until it reaches the last flip-flop of scan chain 210, and then outputs the scan_out signal. For SoCs that implement more than one scan chain in one or more scan chain layers, multiple scan_in and scan_out signals can be used.

[0065] Conventional scan chain designs include a scan enable pin or a test enable pin within the scan chain layer 200. In preparation for testing, enabling the test enable pin causes all flip-flops 202 to be connected into a single long shift register (i.e., scan chain 210). A clock enable pin or signal can then be sent to each of the ICGs ( Figure 2B ), to provide clocks to all serially connected flip-flops 202 to initiate shifting in and propagating scan_in test data. The frequency of the clock can control the rate at which the test pattern propagates throughout the scan chain and the speed at which the scan_out signal is read out from the last flip-flop 202.

[0066] likeFigure 2B As illustrated in the example of, a conventional scan stitching configuration can test an entire series of flip - flops 202 at once. However, due to the latency caused by the distance between each of the flip - flops 202, this takes a significant amount of time, such that the electrical signal representing the test data must physically travel between each of the flip - flops 202 along the scan chain 210. Physical - awareness scan stitching addresses this problem by spatially sorting the flip - flops. Physical - awareness scan stitching can organize the scan - layer connections between the flip - flops by connecting each flip - flop to the next closest flip - flop within the scan chain that has not yet been sorted, or by stitching the scan chain with the shortest total length in some similar way. By implementing physical - awareness scan stitching, the test time for performing a single scan is significantly reduced because the electrical signal representing the test data does not have to travel as long a distance as in normal non - physical - awareness scan stitching.

[0067] However, conventional scan stitching and conventional physical - awareness scan stitching cannot isolate or precisely indicate specific problems (e.g., power or thermal issues) with respect to various physical parts or regions of the SoC's layout and / or stack - up. In both non - physical - awareness and physical - awareness scan - chain implementations, the ICGs are used to reduce power during scan - chain data capture but are switched simultaneously. Since the test - enable pin activates all the ICGs at once, all the flip - flops 202 are activated simultaneously, and the test data runs through the scan chain to determine the scan_out data. This prevents the SoC 206 from determining whether any specific area or region of interest within the physical profile of the entire SoC 206 is the result of any other area / circuitry of the SoC 206 or any specific grouping of the flip - flops 202.

[0068] The inability to activate combinational logic in a region - based manner to determine the impact of the activated circuitry across various other regions of the SoC is illustrated in Figure 2C the figure. Figure 2CAn example of an expanded view of a portion of a conventional scan chain layer 200 including integrated clock gating is illustrated. In a conventional scan chain configuration, ICGs can be scattered throughout the physical profile of the SoC to simultaneously activate all the flip-flops within the scan chain. For example, the ICG component 212 can be designated, during the design phase, based on the netlist, to provide clock gating to the flip-flops 208, 214, 216, 218, 202, 220, and 222 within the scan chain 210. Additional groupings of flip-flops along the scan chain 210 can be designated to be clocked by additional ICG components 204. A clock gating controller can be used to switch the ICG component 212 and other ICG components 204 to simultaneously activate all the flip-flops in the scan chain 210. In addition to the all-or-nothing activation of the scan chain 210 as previously described with respect to switching the ICG component 204, the random or extended physical placement of the flip-flops corresponding to each ICG component 204 prevents the identification of potential issues within a specific region of the SoC that may occur due to the activation of a specific portion of the functional circuitry. For example, referring to Figure 2B and 2C , the extended physical placement of the flip-flops 202, 208, and 214 along the scan chain 210 does not allow for the isolation DFT of a specific region of the SoC.

[0069] Figure 3 An overview of a scan chain layer 300 during a design process suitable for implementing various embodiments is illustrated. The scan chain layer 300 can be implemented within the SoC 322, where the scan chain layer 300 includes a plurality of flip-flops 302. A logic grid 304 can be overlaid on the physical profile of the SoC 322, and the scan chain 320 can be reassembled based on the grid 304 for thermal characterization purposes. The scan chain 320 is illustrated as a dashed line for illustrative purposes only and represents only the logical connections and not the actual circuit connections between the flip-flops 202.

[0070] During the design process, the flip-flops 302 can be sorted within the scan chain layer 300 to form the scan chain 320. The scan chain 320 can be stitched using physical-aware scan stitching or some other scan stitching method that prioritizes an efficient scan chain layout to reduce the latency exhibited in conventional non-physical-aware and conventional physical-aware scan stitching and testing. The flip-flops 302 can be sorted manually, algorithmically, or by other automated means (e.g., neural networks) to determine an optimized scan chain 320 layout.

[0071] By considering factors such as the shortest total physical length of connections between flip - flops 302 in the scan chain layer 300, a design process, scan chain layout tool, or mechanism can determine an optimized scan chain 320 layout. Other factors can include the shortest total distance between the next several or more flip - flops. For example, a series of five flip - flops to be sorted within a scan chain may have different total scan chain path distances depending on how the flip - flops are sorted. The next closest flip - flop may ultimately cause the remaining three flip - flops to be far from the remaining flip - flops to be sorted. Thus, in this example, sorting the other three flip - flops into the scan chain before the next closest flip - flop can result in a shorter total scan chain distance. Other factors that can determine how the scan chain is sorted may include the total number of flip - flops in a specified physical area of the SoC, whether certain flip - flops are connected to certain combinational logic with shared functionality, or whether any flip - flops are located in an area where minimal or no error is expected, or whether any expected error is trivial for in - field testing and monitoring purposes.

[0072] For example, Figure 3 The scan chain 320 of the illustrated scan chain layer 300 has been manually sorted at least in part based on physical - aware scan stitching. As an example of a part of the scan chain 320, the scan chain 320 can include a flip - flop 310 having a logical connection 316 to a flip - flop 312, and the flip - flop 312 can have a logical connection 318 to a flip - flop 314.

[0073] After any initial scan stitching, the scan chain 320 can be reassembled based on a scan chain grid for thermal characterization. In some embodiments, the scan chain can be assembled using the scan chain grid without any prior scan stitching (e.g., physical - aware scan stitching). In some embodiments, reassembling the scan chain after any initial scan stitching can include reorganizing the initial scan stitching. For Figure 3 the illustrated example, the scan chain 320 can be separated into logically - located grid segments corresponding to the physical profile of the SoC 322. For example, during the physical design phase of the SoC 322, the physical profile of the SoC 322 can be decomposed into a grid 304 with different grid parts (represented as intersecting vertical dashed lines different from the dashed lines of the illustrated scan chain 320). Each grid part can be logically overlaid on top of the physical profile of the SoC 322 such that each grid part can be logically associated with various flip - flops located on the physical profile of the SoC 322. For example, the grid part 306 can be logically associated with the flip - flops 310, 312 that are physically located in the SoC 322 and correspond to the grid part 306 of the grid 304. As another example, the grid part 308 can be logically associated with the flip - flop 314.

[0074] In some embodiments, the grid partitions can be selected manually or via software (e.g., via algorithms, artificial intelligence / neural networks, etc.). For example, the number of grid partitions and the size and / or shape of the grid partitions can be selected or determined. In some embodiments, the partitions can be in a non-grid configuration, which may be useful for testing non-uniform SoCs or for concentrating testing on specific regions of the SoC. For example, the design can implement partitioning based on circuit functions (such as power circuits or memories) or any specific physical regions within the SoC where errors may be expected to occur. For example, the partitions can be any shape or size within the SoC profile to group any number of flip-flops associated with a logic scan chain segment.

[0075] In some embodiments, the grid partitions can be based on a predefined number of flip-flops to be associated with each grid partition. For example, the maximum number of flip-flops can be assigned to one grid partition, and then the next flip-flop can be assigned to the same or a different maximum number of flip-flops to the next grid partition, and so on. In some embodiments, the grid 304 can be selected based on the physical distance between flip-flops and overlaid onto the SoC 322. For example, the maximum or minimum distance between flip-flops can be preset or determined by software instructions to group flip-flops within various grid partitions. For example, flip-flops that are less than 20 nanometers (nm) apart can be grouped together in a separate partition, and the next flip-flop that is more than 20 nm apart can start a new grid partition.

[0076] By implementing grid reassembly or reorganization, the scan chain 320 can be used to define the thermal characterization of the SoC 322 described herein. Separating the scan chain into grids or segments can allow the flip-flops associated within each segment to be activated separately from the flip-flops in all other segments. When a segment of the grid is activated, the thermal response and electrical response can be measured using temperature sensors and voltage sensors located at every other segment of the grid. For example, the grid portion 306 can be activated (i.e., clocked as described Figure 4 above) to shift the generated test data into the flip-flop 310 and out of the flip-flop 312. The thermal response and electrical response can be measured across each grid portion, including the grid portion 308, while the data is being shifted through the flip-flop 310 and the flip-flop 312 at a high rate. Each group of flip-flops corresponding to each segment of the grid can be activated sequentially to produce a complete characterization of the thermal response and electrical response measured throughout the SoC. This allows for a complete and continuous in-situ monitoring of the thermal and electrical characterization of the SoC.

[0077] Figure 4Illustrated is an overview of a scan chain layer 400 with embedded clock gating for implementing various embodiments. A clock gate can be assigned to each grid section to provide a clock to each set of flip - flops spatially associated with each grid section. A flip - flop (sometimes referred to as a latch) is a circuit that implements at least two logic gates to store state information. Thus, a set of logic gates can be used to form one or more flip - flops such that each flip - flop contains at least two logic gates. During the design process, clock gates can be inserted into the SoC 322 circuitry to gate off clock propagation to downstream logic and upstream logic (i.e., other flip - flops and their associated combinational logic in other parts of the grid). A clock gate controller 414 can be used to individually control or switch the condition of each clock gate associated with each grid section. Although shown outside the physical contour of the SoC 322 for illustrative purposes, it is understood that the clock gate controller 414 can be a circuit component located within the physical contour of the SoC 412.

[0078] Clock gating and the clock gate controller 414 can be integrated into the circuit design of the SoC 322 during the design process. The SoC 322 with the grid 304 can have clock gating embedded into the SoC 322 design such that the clock gates can be spatially associated with a portion of the grid 304. The clock gating can then be configured or switched via the clock gate controller 414 to forward or provide a clock signal to the flip - flops associated with a particular grid section. Providing a clock signal to a set of flip - flops activates the flip - flops and then shifts any input data (e.g., scan_in) through the flip - flops associated with that grid section.

[0079] Based on the shifted - in data, the flip - flops can produce an output (e.g., scan_out) based on the functionality of the combinational logic associated with those flip - flops. This is illustrated in Figure 4 grid section 416 in Figure 4 shown as having flip - flops 420 and 422. A clock gate 418 can be inserted into the circuit system design of the SoC 322. The clock gate 418 can be configured or switched by the clock gate controller 414 (connections not shown) to allow the clock gate 418 to forward the clock signal to the flip - flops 420 and 422. In response to receiving the forwarded clock signal, the flip - flops 420 and 422 can begin shifting test data for thermal and electrical characterization of the SoC 322.

[0080] When a section of a trigger associated with a portion of a grid is shifting test data (i.e., a section of a trigger activated by clock gating provided by a clock gate), the remaining triggers in the entire SoC 322 may remain clock gated off (i.e., no clock is provided), and thus are inactive. For example, the SoC 322 may have a grid that separates triggers into grid portions 402, 406, and 410 and other grid portions not shown. The grid portions 402, 406, and 410 may be designed to include clock gates 404, 408, and 412, respectively.

[0081] During any DFT or in-field monitoring of the SoC 322, the clock gate controller 414 may sequentially switch the clock gates 404, 408, and 412 to provide high-speed clock signaling to the triggers associated with each of the grid portions 402, 406, and 410. The clock gate controller 414 may configure the clock gate 404 to provide a clock signal to the triggers associated with the grid portion 402, while configuring the clock gates 408 and 412 to prevent the clock signal from being provided to the triggers associated with the grid portions 406 and 410. By activating a single portion of the grid 304 while clock gating off most (if not all) of the other portions, in-field characteristics (e.g., thermal and electrical characteristics) may be measured by sensors at each clock gated portion of the grid 304. For example, activating the triggers in the grid portion 402 by the clock gate controller 414 and the clock gate 404 may generate thermal and electrical responses to the high-speed shifted test data measurable in the grid portions 406 and 410 and all other grid portions of the grid 304. The responses may be measured by thermal sensors and voltage sensors located within the grid portions 406 and 410 and all other grid portions.

[0082] Once sufficient test data has been shifted through the flip - flops associated with grid section 402 for a sufficient amount of time to measure the response of the entire SoC 322, the clock gating controller 414 can configure the clock gate 404 and stop the clock gate 404 from providing the clock signal to the flip - flops associated with grid section 402. Each section of the grid 304 can then be serially activated by software implemented in a similar manner on the SoC 322. For example, after activating grid section 402 and configuring the clock gate 404 to stop forwarding the clock signal, the clock gating controller 414 can configure the clock gate 408 to forward the clock signal to the flip - flops associated with grid section 406. Test data can be shifted through the flip - flops associated with grid section 406, and the response can be measured at all other grid sections, including grid sections 402 and 410. Then the clock gating controller 414 can configure the clock gate 408 and stop the clock gate 408 from providing the clock signal to the flip - flops associated with grid section 406. After activating grid section 406 and configuring the clock gate 408 to stop forwarding the clock signal, the clock gating controller 414 can configure the clock gate 412 to forward the clock signal to the flip - flops associated with grid section 410. This process can be repeated serially and sequentially for each grid section of the SoC 322 until each grid has been activated.

[0083] In some embodiments, the serial and sequential testing of each grid section can be repeated to start the testing at a first grid location (e.g., grid section 402). This allows for continuous and in - situ testing of the SoC. Such testing may be beneficial for detecting errors, attacks, or hardware degradation (e.g., aging power delivery network, increasing IR drop values, on - chip or off - chip power attacks, hard errors, etc.), which may be more easily identified through repeated testing. For example, by performing multiple iterations of the sequential grid section testing, thermal issues caused by circuit / wire degradation can be more easily detected, enabling the observation of changes in thermal characteristics over time or changes between sequential tests that may be caused by problems arising in specific grid sections.

[0084] In some embodiments, test data (e.g., scan_in) can be shifted into the flip-flops at a high frequency (e.g., the turbo frequency, 3.2 GHz, etc.) to create a large power traveling through a circuit system of a set of flip-flops and corresponding combinational logic. By shifting the test data through the flip-flops at a high frequency, the thermal and electrical responses may be more easily observable and measurable at other grid locations compared to shifting data at normal or operating frequencies. Heating the (multiple) active portions of the grid more than in normal operation may allow for in-situ measurements of the thermal characterization of the SoC, which may indicate various potential errors or attacks (e.g., an aging power delivery network, an increased IR drop value, on-chip or off-chip power attacks, hard errors, etc.). Due to the speed of the high-speed shift and for in-situ monitoring of the thermal and electrical characterization of the SoC, the scan_out data may be ignored in some embodiments.

[0085] In some embodiments, in addition to the unactivated grid portions, the thermal and electrical responses can also be measured by temperature and voltage sensors located within the active grid portions. For example, while the flip-flops of grid portion 402 are activated via a forwarded clock signal from clock gate 404, the temperature sensor (e.g., TSENS) and voltage sensor spatially located within grid portion 402 can measure the thermal and electrical responses based on the actively shifted test data.

[0086] In some embodiments, more than one section of grid 304 can be active at a given time. For example, the clock gate controller 414 can configure the clock gates 404, 408, and 412 to forward the clock signal to the flip-flops associated with grid portions 402, 406, and 410. Then the test data can be shifted through the flip-flops of each of the grid portions 402, 406, and 410, and the thermal and electrical responses can be measured at all other grid locations. This test method may be useful in characterizing portions of the SoC 322 associated with specific circuit functionality. For example, if grid portions 406 and 410 and the corresponding combinational logic provide power control functionality, it may be desirable to activate and test grid portions 406 and 410 simultaneously. In some embodiments, all sections of the grid can be activated to perform a "full load" test, and the in-situ characteristics can be measured from all parts of the grid.

[0087] In some embodiments, clock gating may not be inserted into the circuit system at some grid positions. For example, a grid section may have few or no flip-flops, such as when the design layout results in a region of the SoC having little or no combinational logic. As another example, certain combinational logic and / or circuit-specific functionality may be of little interest for DFT or in-field monitoring, such as a circuit system / transistor logic that has been proven effective, has no hardware issues, and / or is not vulnerable to attacks. In these examples, it may be beneficial not to include clock gating in the corresponding grid section to reduce the total time for monitoring in-field characteristics. Reducing the number of grid sections activated for sequential testing of the SoC can reduce the total test time and simplify the SoC design.

[0088] Figure 5 An overview 500 of two example scan chain grid sections of a scan chain layer for implementing various embodiments is illustrated. A flip-flop (sometimes called a latch) is a circuit that implements at least two logic gates to store state information. Thus, a set of logic gates can be used to form one or more flip-flops such that each flip-flop contains at least two logic gates. The SoC may include a grid section 502 associated with flip-flops 510a to 510e and a clock gate 506, and a grid section 504 associated with flip-flops 512a to 512c and a clock gate 508. The clock gates 506 and 508 can be switched by a clock gate controller via different clock configuration signals (e.g., CLK CTRL1, CLK CTRL2). Configuring the clock gate 506 to forward the clock signal to the flip-flops 510a to 510e can cause the flip-flops 510a to 510e to sequentially shift test data through the flip-flops 510a to 510e. Configuring the clock gate 508 to forward the clock signal to the flip-flops 512a to 512c can cause the flip-flops 512a to 512c to sequentially shift test data through the flip-flops 512a to 512c.

[0089] As described above, the implementation of a grid configuration or any other configuration for splitting flip-flops into groups can re-align or re-assemble an initially developed scan chain, assuming the scan chain layout was developed prior to implementing the grid configuration. For example, the scan chain may have been developed prior to implementing the grid configuration. Based at least in part on the previously described physically aware scan stitching, such a scan chain can sequentially sort all flip-flops to create a single long scan chain. For example, referring to Figure 5, the scan chain may initially be designed to logically connect flip - flops 510a to 510e and flip - flops 512a to 512c. Assuming that the grid configuration for in - field monitoring is not implemented and thus there is no grid clock control, the scan chain will sequentially shift test data (e.g., scan_in) into flip - flop 510a through flip - flops 510b to 510e and 512a, 512b, and output the response (e.g., scan_out) from flip - flop 512c.

[0090] Implementing the scan chain grid and inserting clock gating can re - configure the initially designed scan chain (e.g., a scan chain based on netlist or physically - aware scan stitching) such that each group of flip - flops for each corresponding grid section 502 and 504 is electrically inserted between a decompressor and a compressor. Re - configuring the initially designed scan chain based on the grid configuration can be performed manually, algorithmically, or through a neural network. Implementing the grid configuration can allow each group of flip - flops associated with each grid section of the SoC to be inserted between one or more sets of decompressors and compressors. Re - configuring the scan chain based on the grid configuration can include connecting the first flip - flop within the grid section to the output of the decompressor and connecting the last flip - flop within the grid section to the input of the compressor. The first flip - flop can be defined as the flip - flop that starts the scan chain or the flip - flop that will receive shifted test data from the last flip - flop of the previous grid section. The last flip - flop can be defined as the flip - flop that ends the scan chain or the flip - flop that will shift test data to the first flip - flop of the next grid section.

[0091] For example, triggers 510a through 510e associated with grid section 502 can be connected to decompressor output 514 and compressor input 516. The decompressor can insert shifted test data into trigger 510a (i.e., the first trigger of grid section 502) via decompressor output 514, and when clock gate 506 is configured to forward the clock signal, triggers 510a through 510e can serially shift the test data. Based on the grid configuration, the test data can be shifted out (e.g., scan_out) from trigger 510e (i.e., the last trigger of grid section 502) to compressor input 516, rather than the test data being shifted through trigger 512a along the originally designed scan chain (i.e., because triggers 512a through 512c are not activated / clocked). In a similar manner, triggers 512a through 512c associated with grid section 504 can be connected to decompressor output 518 and compressor input 520. The decompressor can insert shifted test data into trigger 512a via decompressor output 518, rather than trigger 512a receiving test data shifted from trigger 510e along the originally designed scan chain. When clock gate 508 is configured to forward the clock signal, triggers 512a through 512c can serially shift the test data. Based on the grid configuration, the test data is shifted out (e.g., scan_out) from trigger 512c (i.e., the last trigger of grid section 504) to compressor input 520, rather than the test data being shifted through another trigger at another grid section along the originally designed scan chain.

[0092] In some embodiments in which physical-aware scan stitching or some other scan stitching method that prioritizes an efficient scan chain layout has been applied during the design process, implementing the grid configuration can reconstruct the existing scan chain based on the size and shape of the grid sections. For example, triggers 510a through 510e and triggers 512a through 512c may have been sorted based on physical-aware scan stitching that prioritizes the shortest total scan chain length in order to minimize test time (e.g., reduce the total physical distance electrical signals carrying the shifted test data). However, in the grid configuration, considering the total scan chain length through all grid sections may be immaterial or different compared to the total scan chain length within an individual grid section defined by the distance from the trigger to the compressor between decompressors.

[0093] When applying a grid configuration to a pre - existing scan chain layout, the logical connections can be re - organized in any possible way suitable for reducing the total test time. Thus, when applying the grid configuration, any existing scan chain ordering can be used as a basis and adjusted or completely rewritten. For example, the logical ordering of flip - flops 510a to 510e might have been based on the shortest total scan chain length before implementing the grid configuration. By applying a manual implementation of an algorithm or neural network or an automated placement tool mechanism, the scan chain ordering of the illustrated flip - flops 510a to 510e can be re - configured to swap the order of flip - flop 510d with that of 510e such that 510d is the last flip - flop in grid section 502. This will allow for a shorter total scan chain length within grid section 502 and thus reduce the test time for in - field monitoring.

[0094] In some embodiments, the grid configuration can implement a first instance of scan stitching such that no prior scan stitching was implemented during the design process. The grid configuration can apply scan stitching using physical - aware scan stitching or some other scan - stitching method that prioritizes an efficient scan chain layout. Grid - configuration scan stitching can provide stitched layouts that are efficient for individual grid sections, groups of grid sections, and / or the entire profile of the SoC.

[0095] Figure 6 Block diagram 600 is illustrated having a scan chain grid section 504 with flip - flops 512a to 512c for implementing various embodiments. A series of flip - flops sharing the same clock signal is referred to as a shift register. A flip - flop (sometimes called a latch) is a circuit that implements at least two logic gates to store state information. Thus, a set of logic gates can be used to form one or more flip - flops such that each flip - flop contains at least two logic gates. Figure 6 The flip - flops 512a to 512c in illustrate an example of a scan chain segment or grid section 504 for testing combinational logic 604, where the combinational logic is associated with the functional circuitry of the SoC.

[0096] Take Figure 5 the example described in. Grid section 504 is represented as a block diagram. As previously described, implementing a grid configuration with grid - aware scan stitching can insert a series of flip - flops associated with the grid section between the decompressor and the compressor. For example, grid section 504 can have flip - flops 512a to 512c, where flip - flop 512a receives test data (e.g., scan_in) from decompressor output 518, and flip - flop 512c outputs test data (e.g., scan_out) to compressor input 520.

[0097] The multiplexer 602 can be used to switch between a regular speed shift clock and a high speed or turbo shift clock. The output of the multiplexer 602 can be communicated to the clock gate 508. The clock gate controller 414 can configure the clock gate 508 to communicate the clock signal from the multiplexer 602 to the flip-flops 512a through 512c, as previously described. Once the flip-flops 512a through 512c are activated (i.e., clocked), test data from the decompressor output can be shifted through the flip-flops 512a through 512c at a rate defined by the frequency of the applied clock signal. More specifically, the output of flip-flop 512a is used as the input to flip-flop 512b, and the output of flip-flop 512b is used as the input to flip-flop 512c. The result is that the shift register circuit shifts the stored bit array one position with each transition of the clock signal provided by the multiplexer 602.

[0098] Combinational logic can be connected at the input and output of each of the flip-flops 512a through 512c. Thus, the output of each flip-flop in the grid-aware scan stitching configuration can become the primary input to the combinational logic, and the input of each flip-flop can allow registering the output of the combinational logic. This improves the controllability of the combinational logic, such as through predefined or randomly generated test data, and improves the observability reported to the compressor input 520.

[0099] The shift clock or high speed shift clock communicated to the clock gate 508 through the multiplexer 602 can be derived from a phase locked loop, or otherwise from a phase locked loop. This allows increasing the activity level exhibited by the flip-flops and the combinational logic within the grid sections, which can increase the electrical and thermal responses observable and measurable at various parts of the grid for in-field monitoring and diagnostic purposes.

[0100] Figure 7 Block diagram 700 illustrates multiple scan chain grid sections between a decompressor and a compressor for implementing various embodiments. The SoC can include multiple decompressors and compressors, distributing test data across various scan chains and scan chain segments.

[0101] The multiplexer 706 can be used to convey normal DFT data 704 (e.g., device scan_ins) or data from the pattern generator 702. The pattern generator 702 can be a pseudo-random pattern generator or any other specific pattern generator, such as a fixed pattern generator that can be used to generate test data for shift register testing. The pattern generator 702 can generate test data suitable for in-field monitoring of thermal characteristics (e.g., thermal mode scan_in). In an example where the pattern generator is a fixed pattern generator, the test pattern can be predefined as an alternating binary pattern (e.g., 101010… etc.) to maximize the activity of the combinational logic circuit system.

[0102] The decompressor 708a can be used to convey the generated test data to one or more scan chains and / or scan chain segments. The decompressor 708a can simultaneously decompress and / or repeat test data across multiple scan chains. Referring to Figure 5 and 6 the example described in Figure 6 As illustrated, the shift register including flip-flops 512a through 512c located between the decompressor output 518 and the compressor input 520 can correspond to a single scan chain segment 701b. As another example, the mesh portion 502 having flip-flops 510a through 510e coupled between the decompressor output 514 and the compressor input 516 can correspond to the scan chain segment 701b. Thus, the decompressor 708a can simultaneously convey test data to multiple scan chain segments, and the compressor 710a can simultaneously compress the received test data into scan_out data 712 (i.e., after XOR reduction).

[0103] Although Figure 7 two scan chain segments 701a and 701b corresponding to the mesh portions 502 and 504 are illustrated, it is important to note that more scan chain segments can be implemented, and thus additional scan chain segments can be illustrated corresponding to additional mesh portions of the scan chain layer. For example, the scan chain layer including scan chain segments 701a and 701b can include additional scan chain segments corresponding to additional mesh portions, where the additional scan chain segments will be illustrated as being separately inserted between the decompressor 708a and the compressor 710a. As another example, different scan chain layers can be separated into a mesh having four mesh portions, where each mesh portion corresponds to scan chain segments 714a through 714d.

[0104] In some embodiments, the SoC may include any number of decompressors and compressors, depending on the number of scan chains designed and the number of scan chain segments corresponding to each scan chain. For example, test data may be input to decompressors 708a and 708b. In addition to the two scan chains having scan chain segments 701a and 701b and scan chain segments 714a through 714d, decompressor 708b may include any number of scan chain segments corresponding to any number of scan chains and / or scan chain layers. For example, the SoC may have scan chain segments 716a and 716b corresponding to one scan chain grid configuration and may also have scan chain segments 718a and 718b corresponding to another scan chain grid configuration. During the grid-aware scan stitching design process, scan chain segments 716a, 716b, 718a, and 718b may be inserted between decompressor 708a and compressor 710b. As previously described, during the design process, each of scan chain segments 716a, 716b, 718a, and 718b may be assigned a clock gate.

[0105] In some embodiments, multiple scan chain segments of one or more scan chains may be activated or clocked so as to be tested simultaneously. For example, because scan chain segment 714a may be part of a different grid configuration and thus a different grid-aware stitching configuration than scan chain segment 701a, testing the SoC may include simultaneously activating two scan chain segments to measure various thermal and electrical responses at other grid locations. This can reduce the overall test duration in cases where scan chain segments 701a and 714a are in different physical locations (e.g., on different scan chain layers, at different locations within the SoC profile) such that scan chain segment 701a is not close to scan chain segment 714a. The simultaneous activation of one or more segments can reduce test time where the activation of two or more segments may not interfere with the measurement of the thermal characterization attributed to each activated segment.

[0106] In some embodiments, multiple scan chain segments of one or more scan chains may be activated or clocked to provide increased power dispersed throughout the SoC for more rigorous testing. For example, two or more of scan chain segments 701a, 701b, 714a through 714d, 716a, 716b, 718a, and 718b may be activated simultaneously. This may be useful when characterizing portions of the SoC 322 associated with specific circuit functionality. For example, if the corresponding combinational logic provides power control functionality or some other shared functionality, it may be desirable to activate and test scan chain segments 716a, 718b, and 701b. In some embodiments, all scan chain segments may be activated to perform a "full load" test, and on-site characteristics may be measured from all parts of the SoC.

[0107] Figure 8 is a process flow diagram illustrating an example method 800 for monitoring characteristics of a system-on-chip according to various embodiments. Referring to Figures 1 - 8 , method 800 may be implemented in a processor (e.g., 14) that may be configured with processor-executable instructions stored in a non-transitory processor-readable medium (e.g., 16) to perform the operations of the method. The order of operations performed in blocks 802 through 808 is merely illustrative, and the operations of blocks 802 through 808 may be performed in any order and partially simultaneously in various embodiments. In some embodiments, method 800 may be performed by a processor independent of but in conjunction with computing device 10. For example, method 800 may be implemented as a software module that executes within a processor (e.g., 14) of the SoC or in dedicated hardware within the SoC that monitors data and commands from / within computing device 10 and is configured to take actions and store data as described. For ease of reference, the various elements performing the operations of method 800 are referred to as "processor" in the following method description.

[0108] In block 802, the processor may input test data from a test data input connection into a first scan chain segment that includes a first set of logic gates located within a first region of the SoC. A flip-flop (sometimes called a latch) is a circuit that implements at least two logic gates to store state information. Thus, a set of logic gates may be used to form one or more flip-flops such that each flip-flop contains at least two logic gates. As Figure 6 illustrated, a group of flip-flops may be used to form a shift register that communicates directly with the combinational logic of the SoC (e.g., 12). The shift register may be configured to serially shift the test data through a set of serially connected flip-flops. For a set of logic gates forming more than one flip-flop, the test data may be received by a first flip-flop in the shift register chain, where the output of the first flip-flop is connected to the next flip-flop in the shift register chain.

[0109] In some embodiments, the logic gates in the first set of logic gates may be grouped at least in part based on physical-aware scan stitching. The flip-flops associated with each set of logic gates may be spatially located within the physical profile of the SoC (e.g., 12) as referred to Figure 3 described. The flip-flops and logic gates may be grouped manually, or by an algorithm or by a neural network applying a set of rules or factors. The grouping of the logic gates may be based in part on the shortest total scan chain distance. The grouping of the logic gates may be stored in a memory (e.g., 16) and used for further design processing (e.g., grid-aware scan stitching) performed by the processor.

[0110] In some embodiments, test data can be input to the first set of logic gates and any other set of logic gates simultaneously. The test data can be input from the scan chain layer of the SoC (e.g., 12). The scan chain layer can include one or more decompressors and one or more corresponding compressors to input the test data into the first set of logic gates and any other set of logic gates, where the decompressors and compressors shift the test data in the direction of the processor.

[0111] In some embodiments, the test data can be generated by a pattern generator coupled to the test data input connection. The pattern generator can be a component of the scan chain layer within the SoC (e.g., 12) that generates test data according to the instructions of the processor. The test data can be generated by the pattern generator, stored in a memory (e.g., 16), and later relayed to the decompressor for inputting the test data into the first set of logic gates and any other set of logic gates. The pattern generator can be a fixed pattern generator or a pseudo-random pattern generator. In some embodiments, the logic gates in the first set of logic gates can be serially connected, and the test data can be serially shifted through the first set of logic gates.

[0112] In block 804, the processor can provide a clock signal from a first clock gate associated with the first region of the SoC to the first set of logic gates. The clock signal can be a clock signal generated by the SoC (e.g., 12), a computing device including the SoC (e.g., 10), or any other clock generating device capable of relaying the clock signal from the external to the computing device (e.g., 22). The clock signal can be a phase-locked loop clock signal. After configuring the first clock gate to relay the clock signal, as Figure 5 and 6 illustrated, the clock signal can be used to activate the first set of logic gates so that the test data can start being serially shifted into and through the first set of logic gates.

[0113] In some embodiments, the clock signal can be a high-speed clock or a turbo shift clock (e.g., turbo shift clock, 3.2 GHz clock). Shifting the input of test data into each set of logic gates at a high frequency may cause the SoC (e.g., 12) to require a high power level (e.g., a higher power level than normal operation) to implement the combinational logic associated with each triggered flip-flop, as Figure 6 illustrated. By increasing the power requirements for shifting data at high speed into the flip-flops, the thermal and electrical responses generated at other sections of the SoC may be easier to measure, and thus any associated errors or attacks may be easier to identify. In some embodiments, the clock signal can be provided to the first clock gate from a clock gate controller, where the clock gate controller is provided with a clock signal (e.g., from a clock generator, a crystal device, etc.).

[0114] In some embodiments, the first set of logic gates and the first clock gate may be spatially associated with the first scan chain segment. The first scan chain segment may correspond to a scan chain segment, subsection, or grid portion or region, as Figure 4 and 5 illustrated. Grid-aware scan stitching of the scan chain layer may group the first set of logic gates from all other logic gates within the SoC (e.g., 12) into separate spatially identifiable grid portions or scan chain subsections. The process of grouping the first set of logic gates may be performed by a processor, a computing device (e.g., 10), or any other computing device implementing a design process layout tool or application. The logic gates associated with each grid region may be mapped and stored as a grid-aware scan chain layer within a memory (e.g., 16) for fabrication purposes (e.g., fabricating a SoC not for developing the initial grid-aware scan stitching).

[0115] In some embodiments, the processor may configure the first clock gate to provide a clock signal to the first set of logic gates. As Figure 5 and 6 illustrated, a clock gate controller may be used to configure or switch the condition of the first clock gate. Configuring the first clock gate to convey a clock signal to the first set of logic gates may initiate shifting test data through the first set of logic gates from the scan chain layer (e.g., a pattern generator controlled by the processor).

[0116] In some embodiments, the condition of the first clock gate may be stored in a memory (e.g., 16) to be conveyed to the processor to determine which clock gates to configure. In some embodiments, the processor may issue a command to the clock gate controller to configure each clock gate within the scan chain layer of the SoC (e.g., 12) (i.e., sequentially activate each set of logic gates by clock gating other groups of logic gates associated with different grid portions).

[0117] In block 806, in response to providing a clock signal to the first set of logic gates, the processor may cause the first sensor to measure a characteristic at a second region of the SoC. The on-site characteristic may be a thermal and electrical characteristic exhibited by the SoC (e.g., 12) during on-site testing or operation. In some embodiments, the electrical characteristic may include voltage drop and / or grid characteristic. Such measurements may be performed in thermal sensors and / or voltage sensors located throughout the SoC. In some embodiments, in response to providing a clock signal to the first set of logic gates, additional measurements may be performed using sensors associated with other regions of the SoC.

[0118] As described with reference to block 804, configuring the first clock gate to provide a clock signal to the first set of logic gates can initiate the shifting of test data through the first set of logic gates. Activating the first set of logic gates to apply test data to the associated combinational logic may cause thermal and electrical responses in other sections of the overall SoC. Characteristics generated by activating and shifting test data through the first set of flip-flops in the first scan chain section can be measured at a second region, which is a physical region of the SoC different from the first region or any other definable region of the SoC.

[0119] In some embodiments, in-situ characteristics can be measured by temperature sensors and / or voltage sensors (e.g., 28) located within the second region. Temperature and voltage measurements taken by the temperature and voltage sensors can be stored within a memory (e.g., 16) for determining whether any errors or attacks have occurred or may occur.

[0120] In block 808, the processor can process or analyze the measurements of the in-situ characteristics to determine the test results. Performing in-situ testing of the SoC using various embodiment methods can be used to achieve various test objectives. For example, in-situ testing can be performed to monitor the aging or performance degradation of the SoC. As another example, in-situ testing can be performed to determine whether any faults exist or may exist within the SoC. As another example, in-situ testing can be performed to detect inappropriate functionality or malware. Further, in-situ testing can be performed to measure and detect a combination of performance trends, current or possible faults, and inappropriate functionality. For example, the processor can compare the characteristics to thresholds, where the thresholds are associated with specific conditions, faults, or inappropriate functionality of the combinational logic associated with the first scan chain section.

[0121] In some embodiments, a memory (e.g., 16) can store multiple predefined thresholds associated with each grid region of the SoC (e.g., 12). The thresholds can correspond to maximum and / or minimum values of in-situ characteristics (e.g., temperature values, voltage drops, grid characteristics, etc.) measured at each grid section in response to activating the logic gates of another grid section. Depending on the allowed tolerance levels and the SoC (e.g., 12) design layout, the first region can be assigned the same or different thresholds as the second region. For example, the first region associated with the first scan chain may exhibit higher thermal characteristics during normal operation and may be associated with a higher design threshold for allowable operating temperature.

[0122] In some embodiments, the in-situ characteristics measured by temperature and voltage sensors (e.g., sensor 28) at the first and second regions may be stored in a memory (e.g., 16). A processor (e.g., 14) may compare the stored measured in-situ characteristics with thresholds corresponding to each region associated with each scan chain segment.

[0123] In some embodiments, the processor may identify an error in the SoC based on a comparison between the measured characteristics at a second region of an SoC threshold associated with a second region of the SoC. If the measured in-situ characteristics exceed the threshold, the error may be identified by the processor (e.g., 14). The memory (e.g., 16) may include a repository that can identify errors or attacks, at least in part based on which in-situ characteristics exceed the threshold, the degree to which they exceed the threshold, and which scan chain segment has malfunctioned. Other factors (e.g., an aging power delivery network, an increasing IR drop value, an on-chip or off-chip power attack, a hard error, etc.) may be considered when determining whether an error can be identified as a potential problem within the SoC.

[0124] In some embodiments, the processor may execute or otherwise implement a remedial action in response to identifying a fault, inappropriate functionality, or error. Depending on the circumstances, various remedial actions may be taken if any fault, inappropriate functionality, or error is identified to prevent further damage or further security vulnerabilities. For example, if the fault, inappropriate functionality, or error is related to grid degradation, the processor may issue a command via a communication component (e.g., 22) to an external computing device to provide notice of a replacement SoC. As another example, if a power attack is identified, the processor may reboot, lock all functionality, or perform any other type of preventive measure against current and future power attacks. In other examples, if a hard error is identified, the processor may issue a command to an external power grid to cycle power or cut power to the computing device to issue a hard reset.

[0125] Although Figure 8 illustrates providing a clock signal and measuring in-situ characteristics for only one scan chain segment, the operations in blocks 802 through 808 may be performed on any number of scan chain segments within the SoC, and as described, the measured in-situ characteristics are processed or analyzed for all scan chain segments in block 808.

[0126] As mentioned above, the various embodiments enable the transient activation of individual grid portions while characteristic measurement values (e.g., temperature, voltage, current, etc.) are obtained in other grid portions, and the process can be quickly repeated for many or all individual grid portions, such that the measured characteristics are on average consistent with normal operation (where many grids are activated), while enabling the variation in the measurement values to be associated with a particular one or several grid portions. Figure 9 is a process flow diagram illustrating an example method 900 for monitoring the characteristics of a system-on-chip by sequentially activating a first scan chain and a second scan chain section while measuring characteristics. Although Figure 9 illustrates the process of activating only two scan chain sections, similar operations can be performed on the remaining scan chains on the SoC.

[0127] Referring to Figures 1 - 9 , method 900 can be implemented in a processor (e.g., 14) that can be configured with processor-executable instructions stored in a non-transitory processor-readable medium (e.g., 16) to perform the operations of the method. The order of the operations performed in blocks 902 to 916 is merely illustrative, and in various embodiments, the operations of blocks 902 to 916 can be performed in any order and partially simultaneously. In some embodiments, the operations of blocks 902 to 916 can be performed in any order and partially simultaneously with respect to Figure 8 the blocks 802 to 808 of. In some embodiments, method 900 can be executed by a processor independent of but in combination with computing device 10. For example, method 900 can be implemented as a software module that executes within the processor (e.g., 14) of the SoC or in dedicated hardware within the SoC, which monitors data and commands from / within computing device 10 and is configured to act and store data as described. For ease of reference, the various elements performing the operations of method 900 are referred to as "processor" in the following method description.

[0128] In block 902, the processor can configure a first clock gate via a clock gating controller to supply a clock signal to a first set of logic gates. As Figure 5 and 6 illustrated, the clock gating controller can be used to configure or switch the condition of the first clock gate. Configuring the first clock gate to convey the clock signal to the first set of logic gates can initiate the shifting of test data from the scan chain layer (e.g., a pattern generator controlled by the processor) through the first set of logic gates.

[0129] In block 904, the processor may configure a second clock gating associated with a second region of the SoC via a clock gating controller to gate a clock signal from entering a second set of logic gates in response to configuring a first clock gating to provide a clock signal to a first set of logic gates. By gating off the clock to the second set of logic gates in response to the process described in block 902, the first clock gating may provide the clock signal to the first set of logic gates while preventing the clock signal from being provided to the second set of logic gates. Accordingly, the combinational logic connected to the first set of logic gates may be activated while the combinational logic connected to the second set of logic gates may remain deactivated. This may allow testing of a specific region of the SoC via measurements taken throughout the SoC such that the measurement values are the result of a specific scan chain segment corresponding to the associated combinational logic.

[0130] In block 906, the processor may connect test data from a test data input connection to a second scan chain segment. The second scan chain segment includes a second set of logic gates located within a second region of the SoC. A flip-flop (sometimes referred to as a latch) is a circuit that implements at least two logic gates to store state information. Thus a set of logic gates may be used to form one or more flip-flops such that each flip-flop includes at least two logic gates. As Figure 6 illustrated, a flip-flop bank may be used to form a shift register that communicates directly with the combinational logic of the SoC (e.g., 12). The shift register may be configured to serially shift test data through a set of serially connected flip-flops. For a set of logic gates that form more than one flip-flop, the test data may be received by a first flip-flop in a shift register chain where the output of the first flip-flop is connected to the next flip-flop in the shift register chain.

[0131] In some embodiments, the logic gates in the second set of logic gates may be grouped at least in part based on physically aware scan stitching. The flip-flops associated with each set of logic gates may be spatially located within the physical profile of the SoC (e.g., 12) as referenced Figure 3 described. The flip-flops and logic gates may be grouped manually, or by an algorithm or by a neural network that applies a set of rules or factors. The grouping of the logic gates may be based in part on the shortest total scan chain distance. The grouping of the logic gates may be stored in a memory (e.g., 16) and used for further design processing (e.g., grid aware scan stitching) performed by the processor.

[0132] In some embodiments, test data can be input into the second set of logic gates and any other set of logic gates simultaneously. The test data can be input from the scan chain layer of the SoC (e.g., 12). The scan chain layer can include one or more decompressors and one or more corresponding compressors to input the test data into the second set of logic gates and any other set of logic gates, where the decompressors and compressors shift the test data in the direction of the processor.

[0133] In some embodiments, the test data can be generated by a pattern generator coupled to the test data input connection. The pattern generator can be a component of the scan chain layer within the SoC (e.g., 12) that generates test data according to instructions from the processor. The test data can be generated by the pattern generator, stored in a memory (e.g., 16), and later relayed to the decompressor for inputting the test data into the first set of logic gates, the second set of logic gates, and any other set of logic gates. The pattern generator can be a fixed pattern generator or a pseudo-random pattern generator. In some embodiments, the logic gates in the second set of logic gates can be serially connected, and the test data can be serially shifted through the second set of logic gates.

[0134] In block 908, the processor can configure the second clock gate via the clock gate controller to provide a clock signal to the second set of logic gates. As Figure 5 and 6 illustrated, the clock gate controller can be used to configure or switch the condition of the second clock gate. Configuring the second clock gate to convey the clock signal to the second set of logic gates can initiate shifting the test data from the scan chain layer (e.g., a pattern generator controlled by the processor) through the second set of logic gates.

[0135] In some embodiments, the condition of each clock gate (e.g., the first clock gate, the second clock gate, any other clock gate within the SoC) can be stored in a memory (e.g., 16) to be communicated to the processor to determine which clock gate to configure. In some embodiments, the processor can issue commands to the clock gate controller to configure each clock gate within the scan chain layer of the SoC (e.g., 12) (i.e., to sequentially activate the first set of logic gates and the second set of logic gates by clock gating off the second clock gate and the first clock gate respectively).

[0136] In block 910, in response to configuring a second clock gate to provide a clock signal to a second set of logic gates, the processor may configure a first clock gate via a clock gate controller to gate the clock signal from entering a first set of logic gates. By gating off the clock to the first set of logic gates in response to the process described in block 908, the second clock gate provides the clock signal to the second set of logic gates while preventing the clock signal from being provided to the first set of logic gates. Accordingly, the combinational logic connected to the second set of logic gates may be activated while the combinational logic connected to the first set of logic gates may remain deactivated. This may allow specific regions of the SoC to be tested via measurements taken across the SoC such that the measurement values are the result of the specific scan chain segments associated with the combinational logic.

[0137] In block 912, the processor may provide a clock signal from the second clock gate to the second set of logic gates. The clock signal may be a clock signal generated by any other clock generating device of the SoC (e.g., 12), a computing device including the SoC (e.g., 10), or a communication component (e.g., 22) capable of relaying the clock signal from an external source to the computing device. The clock signal may be a phase-locked loop clock signal. After configuring the second clock gate to relay the clock signal, as Figure 5 and 6 illustrated, the clock signal may be used to activate the second set of logic gates such that test data may begin to be serially shifted into and through the second set of logic gates.

[0138] In some embodiments, the clock signal may be a high-speed clock or a turbo shift clock (e.g., a turbo shift clock, a 3.2 GHz clock). Shifting test data inputs into each set of logic gates at a high frequency may cause the SoC (e.g., 12) to achieve a high power level (e.g., a higher power level than normal operation) during a service test to implement the combinational logic associated with each clocked flip-flop, as Figure 6 illustrated. By increasing the power requirements for shifting data into flip-flops at high speed, the thermal and electrical responses generated at other segments of the SoC may be more easily measured and thus any associated errors or attacks may be more easily identified while allowing one or more sources of such issues to be localized to specific scan chain segments. In some embodiments, the clock signal may be provided from a clock gate controller to the first clock gate and the second clock gate, where the clock gate controller is provided with a clock signal (e.g., from a clock generator, a crystal device, etc.).

[0139] In some embodiments, the second set of logic gates and the second clock gate may be spatially associated with a second scan chain segment. The second scan chain segment may correspond to a scan chain segment, section, or grid portion or region, as Figure 4 and 5As illustrated. Grid-aware scan stitching of the scan chain layer can group a second set of logic gates from all other logic gates (including the first set of logic gates) within the SoC (e.g., 12) into separate spatially identifiable grid regions (corresponding to separate scan chain segments). The process of grouping the second set of logic gates can be performed by a processor, a computing device (e.g., 10), or any other computing device implementing a design process layout tool or application. The logic gates associated with each grid portion can be mapped and stored as a grid-aware scan chain layer within a memory (e.g., 16) for fabrication purposes (e.g., manufacturing an SoC not for developing the initial grid-aware scan stitching). In some embodiments, a first region of the SoC and a second region of the SoC can be logically arranged in a grid configuration, where multiple scan chain segments correspond to multiple regions of the SoC.

[0140] The second scan chain segment can be a different SoC portion, region, or area than another SoC portion, region, or area that includes the second scan chain segment, such that the first set of logic gates and the second set of logic gates are located in different physical regions of the SoC (e.g., 12) layout.

[0141] In block 914, the processor can cause the second sensor to measure a characteristic at a first region of the SoC in response to providing a clock signal to the second set of logic gates. The on-site characteristic can be thermal and electrical characteristics exhibited by the SoC (e.g., 12) during on-site testing or operation. In some embodiments, the electrical characteristics can include voltage drop and / or power grid characteristics. Such measurements can be made in thermal sensors and / or voltage sensors located throughout the SoC. In some embodiments, additional measurements can be made using sensors associated with other regions of the SoC in response to providing a clock signal to the second set of logic gates.

[0142] As described with reference to block 908, configuring the second clock gate to provide a clock signal to the second set of logic gates can initiate the shifting of test data through the second set of logic gates. Activating the second set of logic gates to apply test data to the associated combinational logic may cause thermal and electrical responses in other segments of the entire SoC. The characteristics generated by activating and shifting test data through the second set of flip-flops in the second scan chain segment can be measured at a first region that is a different physical region of the SoC than the first region or any other definable region of the SoC.

[0143] In some embodiments, the in-field characteristics can be measured by temperature sensors and / or voltage sensors (e.g., 28) located in the first region or any other region. The temperature and voltage measurements taken by the temperature and voltage sensors can be stored in a memory (e.g., 16) for determining whether any errors or attacks have occurred or are likely to occur. In some embodiments, the first sensor and the second sensor can be temperature and / or voltage sensors, where the measured characteristics are the temperature and / or voltage in the corresponding regions of the SoC.

[0144] In block 916, the processor can process or analyze the measurements of the in-field characteristics to determine the test results. Performing in-field testing on the SoC using various embodiment methods can be used to achieve various test objectives. For example, in-field testing can be performed to monitor the aging or performance degradation of the SoC. As another example, in-field testing can be performed to determine whether any faults exist or are likely to exist within the SoC. As another example, in-field testing can be performed to detect inappropriate functionality or malware. Further, in-field testing can be performed to measure and detect a combination of performance trends, current or possible faults, and inappropriate functionality. For example, the processor can compare the characteristics measured by the first sensor with a threshold associated with the second region, and / or can compare the characteristics measured by the second sensor with a threshold associated with the first region, where the threshold is associated with a specific condition, fault, or inappropriate functionality of the combinational logic associated with the first scan chain segment and / or the second scan chain segment.

[0145] In some embodiments, the memory (e.g., 16) can store a plurality of predefined thresholds associated with each grid region of the SoC (e.g., 12). The thresholds can correspond to the maximum and / or minimum values of the in-field characteristics (e.g., temperature values, voltage drops, grid characteristics, etc.) measured at each grid portion in response to activating the logic gates of another grid portion. Depending on the allowed tolerance level and the SoC (e.g., 12) design layout, the first region can be assigned the same or different thresholds as the second region. For example, the first region associated with the first scan chain may exhibit higher thermal characteristics during normal operation than the second region and may be associated with a higher design threshold for the allowed operating temperature.

[0146] In some embodiments, the in-field characteristics measured by the temperature and voltage sensors (e.g., sensor 28) at the first region and the second region can be stored in the memory (e.g., 16). The processor (e.g., 14) can compare the stored measured in-field characteristics with the thresholds corresponding to each region associated with each scan chain segment.

[0147] In some embodiments, based on a comparison between characteristics measured at a second region of the SoC threshold associated with a second region of the SoC, the processor may identify an error in the SoC. If the measured in-field characteristic exceeds the threshold, the error may be identified by the processor (e.g., 14). The memory (e.g., 16) may include a repository that can identify errors or attacks, which is at least partially based on which in-field characteristics exceed the threshold, the degree to which they exceed the threshold, and which scan chain segment has failed. Other factors may be considered when determining whether an error can be identified as a potential problem within the SoC (e.g., an aging power delivery network, an increased IR drop value, an on-chip or off-chip power attack, a hard error, etc.).

[0148] In some embodiments, the processor may perform or otherwise implement a remedial action in response to identifying a fault, inappropriate functionality, or error. Depending on the circumstances, various remedial actions may be taken to prevent further damage or further security vulnerabilities if any fault, inappropriate functionality, or error is identified. For example, if the fault, inappropriate functionality, or error is related to grid degradation, the processor may issue a command via a communication component (e.g., 22) to an external computing device to provide notification of a replacement SoC. As another example, if a power attack is identified, the processor may reboot, lock all functionality, or perform any other type of preventive measure against current and future power attacks. In other examples, if a hard error is identified, the processor may issue a command to an external grid to cycle power or cut the power of the computing device to issue a hard reset.

[0149] Although Figure 9 it is illustrated that clock signals are provided only for two scan chain segments and the in-field characteristics are measured, the operations in blocks 902 to 916 may be performed on any number of scan chain segments within the SoC, and the measured in-field characteristics are processed or analyzed for all scan chain segments in block 916, as described.

[0150] Various embodiments (including but not limited to the embodiments described above with reference to Figures 1 - 9 can be implemented in a variety of computing systems including motor vehicles or other mobile computing devices, examples of which suitable for use with the various embodiments are illustrated in Figure 10 Reference is made to Figures 1 - 10, the mobile computing device 1000 may include a processor 1002 and an internal memory 1006 that are coupled to a touchscreen controller 1004. The processor 1002 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 1006 may be volatile or non-volatile memory, and may also be secure and / or encrypted memory or insecure and / or unencrypted memory or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller 1004 and the processor 1002 may also be coupled to a touchscreen panel 1012, such as a resistive sensing touchscreen, a capacitive sensing touchscreen, an infrared sensing touchscreen, etc. Additionally, the display of the mobile computing device 1000 need not have touchscreen capabilities.

[0151] The mobile computing device 1000 may have one or more radio signal transceivers 1008 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennas 1010 for sending and receiving communications, coupled to each other and / or to the processor 1002. The transceivers 1008 and the antennas 1010 may be used with the above-described circuitry to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1000 may include a cellular network wireless modem chip 1016 that is capable of communicating via a cellular network and is coupled to the processor.

[0152] The mobile computing device 1000 may include a peripheral device connection interface 1018 that is coupled to the processor 1002. The peripheral device connection interface 1018 may be individually configured to accept one type of connection, or may be configured to accept various types of common or proprietary physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1018 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0153] The mobile computing device 1000 may also include a speaker 1014 for providing audio output. The mobile computing device 1000 may also include a housing 1020 made of plastic, metal, or a combination of materials, which is used to contain all or some of the components described herein. The mobile computing device 1000 may include a power source 1022 coupled to the processor 1002, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to a peripheral device connection port to receive a charging current from a source external to the mobile computing device 1000. The mobile computing device 1000 may also include physical buttons 1024 for receiving user input. The mobile computing device 1000 may also include a power button 1026 for turning the mobile computing device 1000 on and off.

[0154] Various embodiments (including but not limited to the embodiments described above with reference to Figures 1 - 9 may be implemented in a variety of computing systems including a laptop computer 1100, an example of which is illustrated in Figure 11 . Referring to Figures 1 - 11 , the laptop computer may include a touchpad touch surface 1117 that serves as a pointing device for the computer, and thus may receive drag, scroll, and flick gestures similar to those implemented on a computing device equipped with a touch screen display and as described above. The laptop computer 1100 will typically include a processor 1102 coupled to volatile memory 1112 and a mass non-volatile memory, such as a disk drive 1113 of flash memory. Additionally, the computer 1100 may have one or more antennas 1108 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or a cellular phone transceiver 1116 coupled to the processor 1102. The computer 1100 may also include a floppy disk drive 1114 and a compact disc (CD) drive 1115 coupled to the processor 1102. The laptop computer 1100 may include a touchpad 1117, a keyboard 1118, and a display 1119, all of which are coupled to the processor 1102. Other configurations of computing devices may include a computer mouse or trackball coupled to a processor (e.g., via a USB input), which, as is well known, may also be used in conjunction with various embodiments.

[0155] Various embodiments (including but not limited to the embodiments described above with reference to Figures 1 - 9 may also be implemented in fixed computing systems, such as any of a variety of commercially available servers. Referring to Figures 1 - 12 , an example server 1200 is illustrated in Figure 12 . Such a server 1200 typically includes one or more multi-core processor components 1201 coupled to volatile memory 1202 and a mass non-volatile memory, such as a disk drive 1204. As Figure 12As illustrated, the multi-core processor component 1201 can be added to the server 1200 by inserting it into a rack of components. The server 1200 may also include a floppy disk drive, a compact disc (CD) or digital versatile disc (DVD) drive 1206 coupled to the processor 1201. The server 1200 may also include a network access port 1203 coupled to the multi-core processor component 1201 for establishing a network interface connection with a network 1205, such as a local area network, the Internet, the public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0156] Computer program code, or “program code,” for performing operations of the various embodiments on a programmable processor may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or various other programming languages. Program code or programs stored on a computer-readable storage medium as used in this application may refer to machine language code (such as object code) whose format can be understood by a processor.

[0157] The various embodiments illustrated and described are provided only as examples to illustrate the various features of the claims. However, the features shown and described with respect to any given embodiment are not necessarily limited to the associated embodiment and may be used or combined with other embodiments shown and described. Further, the claims are not intended to be limited to any one example embodiment.

[0158] The foregoing method descriptions and process flow diagrams are provided only as illustrative examples and are not intended to require or imply that the blocks of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of the blocks in the foregoing embodiments may be performed in any order. Words such as “thereafter,” “then,” “next,” etc. are not intended to limit the order of the blocks; these words are merely used to guide the reader through the description of the method. Further, any reference to claim elements in the singular (e.g., using the articles “a,” “an,” or “the”) should not be construed as limiting the element to the singular.

[0159] The various illustrative logical blocks, modules, circuits, and algorithmic blocks described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and boxes have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the various embodiments.

[0160] The hardware for implementing the various illustrative logics, logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some of the blocks and methods may be performed by circuitry that is specific to a given function.

[0161] In various embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. Operations of the methods or algorithms disclosed herein may be implemented in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that can be accessed by a computer or a processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and optical disks include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks utilize lasers to optically reproduce data. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, operations of a method or algorithm may reside as one or any combination or set of codes and / or instructions on a non-transitory processor-readable medium and / or a computer-readable medium, which may be incorporated into a computer program product.

[0162] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of the embodiments. Thus, the various embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the following claims, principles, and novel features disclosed herein.

Claims

1. An on-chip system (SoC) configured to monitor a characteristic, comprising: A first scan chain section, including a first set of logic gates located within a first grid portion of the SoC; A first clock gate, configurable to provide a clock signal to the first set of logic gates, wherein the first clock gate is associated with the first grid portion; A second clock gate, configurable to provide the clock signal to a second set of logic gates, wherein the second clock gate is associated with a second grid portion; A test data input connection, configured to input test data into the first scan chain section; A clock gate controller, configured to control the first clock gate to provide the clock signal to the first set of logic gates, while controlling the second clock gate to gate the clock signal from entering the second set of logic gates; and to control the second clock gate to provide the clock signal to the second set of logic gates, while controlling the first clock gate to gate the clock signal from entering the first set of logic gates; and A first sensor, located within the second grid portion, and configured to measure the characteristic at the second grid portion of the SoC in response to the clock signal provided to the first set of logic gates.

2. The SoC according to claim 1, further comprising: A second scan chain section, including the second set of logic gates located within the second grid portion of the SoC; A second sensor, configured to measure the characteristic at the first grid portion of the SoC, wherein the test data input connection is configured to input the test data into the second scan chain section, and wherein the second sensor is configured to measure the characteristic at the first grid portion in response to the clock signal provided to the second set of logic gates.

3. The SoC according to claim 2, wherein The first sensor and the second sensor are temperature sensors, and the characteristic is the temperature of the corresponding grid portion.

4. The SoC according to claim 2, wherein The first sensor and the second sensor are voltage sensors, and the characteristic is the voltage in the corresponding grid portion.

5. The SoC according to claim 2, wherein The SoC is configured to: Compare the characteristic measurement values from the first sensor and the second sensor with thresholds corresponding to the respective grid portions; Identify an error in the SoC in response to the measured characteristic exceeding the threshold; and Implement a remedial action in response to identifying the error.

6. The SoC according to claim 5, wherein The error is an indication of an aging power delivery network, an on-chip or off-chip power attack, or a hard error.

7. The SoC according to claim 2, wherein The characteristic includes thermal characteristics, voltage drop, and power grid characteristics.

8. The SoC according to claim 2, wherein The logic gates in the first set of logic gates are serially connected, wherein the logic gates in the second set of logic gates are serially connected, and wherein the test data is input into the first scan chain section and the second scan chain section by serially shifting the test data through the first set of logic gates and the second set of logic gates.

9. The SoC according to claim 2, further comprising a pattern generator coupled to the test data input connection and configured to generate the test data input to the first scan chain section and the second scan chain section.

10. The SoC according to claim 2, wherein The clock gate controller is provided with a high-speed clock or a turbo shift clock.

11. The SoC according to claim 2, wherein The first grid portion and the second grid portion are arranged in a grid configuration of logic, the grid configuration having a plurality of scan chain sections corresponding to a plurality of grid portions of the SoC.

12. A method for monitoring a characteristic of an on-chip system (SoC), comprising: Input test data into a first scan chain section from a test data input connection, the first scan chain section including a first set of logic gates located within a first grid portion of the SoC; Configure a first clock gate via a clock gate controller to provide a clock signal to the first set of logic gates; In response to configuring the first clock gate to provide the clock signal to the first set of logic gates, configure a second clock gate associated with a second grid portion of the SoC via the clock gate controller to gate the clock signal from entering a second set of logic gates; Provide the clock signal from the first clock gate associated with the first grid portion of the SoC to the first set of logic gates; And In response to providing the clock signal to the first set of logic gates, measure a characteristic at a second grid portion of the SoC using a first sensor.

13. The method according to claim 12, further comprising: Input the test data into a second scan chain section from the test data input connection, wherein the second scan chain section includes the second set of logic gates located within the second grid portion of the SoC; Configure the second clock gate via the clock gate controller to provide the clock signal to the second set of logic gates; In response to configuring the second clock gate to provide the clock signal to the second set of logic gates, configure the first clock gate via the clock gate controller to gate the clock signal from entering the first set of logic gates; Provide the clock signal from the second clock gate to the second set of logic gates; and In response to providing the clock signal to the second set of logic gates, measure the characteristic at the first grid portion of the SoC using a second sensor.

14. The method according to claim 13, wherein, The first sensor and the second sensor are temperature sensors, and the characteristic is the temperature of the corresponding grid portion.

15. The method according to claim 13, wherein, The first sensor and the second sensor are voltage sensors, and the characteristic is the voltage in the corresponding grid portion.

16. The method according to claim 13, further comprising: Compare the measured characteristic values by the first sensor and the second sensor with a threshold corresponding to the respective grid portion; Identify an error in the SoC in response to the measured characteristic exceeding the threshold, wherein the error is an indication of an aging power delivery network, an on-chip or off-chip power attack, or a hard error; and Implement a remedial action in response to identifying the error.

17. The method according to claim 13, further comprising: Generate the test data input into the first scan chain section and the second scan chain section by a pattern generator coupled to the test data input connection, wherein the logic gates in the first set of logic gates are serially connected, wherein the logic gates in the second set of logic gates are serially connected, and wherein the inputting the test data into the first scan chain section and the second scan chain section further includes: serially shifting the test data through the first set of logic gates and the second set of logic gates.

18. The method according to claim 13, wherein, The clock gate controller is provided with a high-speed clock or a turbo shift clock.

19. The method according to claim 13, wherein, The first grid portion and the second grid portion are logically arranged in a grid configuration having a plurality of scan chain sections corresponding to a plurality of grid portions of the SoC.

20. A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processor of a system-on-chip (SoC) to perform operations for monitoring a field characteristic, including: Input test data into the first scan chain section from the test data input connection, where the first scan chain section includes a first set of logic gates located within a first grid portion of the SoC; Configure a first clock gate via a clock gate controller to supply a clock signal to the first set of logic gates; In response to configuring the first clock gate to supply the clock signal to the first set of logic gates, configure a second clock gate associated with a second grid portion of the SoC via the clock gate controller to gate the clock signal from entering a second set of logic gates; Supply the clock signal from the first clock gate associated with the first grid portion of the SoC to the first set of logic gates; And In response to supplying the clock signal to the first set of logic gates, measure the characteristic at the second grid portion of the SoC using a first sensor.

21. The non-transitory processor-readable medium according to claim 20, wherein, The stored processor-executable instructions are configured to cause the processor to perform operations further including the following: Input the test data into a second scan chain section from the test data input connection, where the second scan chain section includes the second set of logic gates located within the second grid portion of the SoC; Configure the second clock gate via the clock gate controller to supply the clock signal to the second set of logic gates; In response to configuring the second clock gate to supply the clock signal to the second set of logic gates, configure the first clock gate via the clock gate controller to gate the clock signal from entering the first set of logic gates; Supply the clock signal from the second clock gate to the second set of logic gates; and In response to supplying the clock signal to the second set of logic gates, measure the characteristic at the first grid portion of the SoC using a second sensor.

22. The non-transitory processor-readable medium according to claim 21, wherein, The first sensor and the second sensor are a temperature sensor and a voltage sensor, and the characteristic is the temperature of the corresponding grid portion and the voltage in the corresponding grid portion.

23. The non-transitory processor-readable medium according to claim 21, wherein, The stored processor-executable instructions are configured to cause the processor to perform operations further including the following: Compare the characteristic measurement values from the first sensor and the second sensor with thresholds corresponding to the respective grid portions; In response to the measured characteristic exceeding the threshold, identify an error in the SoC, where the error is an indication of an aging power delivery network, an on-chip or off-chip power attack, or a hard error; and In response to identifying the error, implement a remedial action.

24. The non-transitory processor-readable medium according to claim 21, wherein, The stored processor-executable instructions are configured to cause the processor to perform operations further including: Generate the test data input to the first scan chain section and the second scan chain section by a pattern generator coupled to the test data input connection, where the logic gates in the first set of logic gates are serially connected, where the logic gates in the second set of logic gates are serially connected, and Among them, the step of inputting the test data into the first scan chain section and the second scan chain section further includes: serially shifting the test data through the first set of logic gates and the second set of logic gates.

25. The non-transitory processor-readable medium according to claim 21, wherein, The clock gating controller is provided with a high-speed clock or a turbo shift clock.

26. The non-transitory processor-readable medium according to claim 21, wherein, The first grid portion and the second grid portion are logically arranged in a grid configuration, and the grid configuration has a plurality of scan chain sections corresponding to the plurality of grid portions of the SoC.

27. A system on chip (SoC), comprising: A component for inputting test data into a first scan chain section from a test data input connection, where the first scan chain section includes a first set of logic gates located within a first grid portion of the SoC; A component for configuring a first clock gate via the clock gating controller to provide a clock signal to the first set of logic gates; A component for, in response to configuring the first clock gate to provide the clock signal to the first set of logic gates, configuring a second clock gate associated with a second grid portion of the SoC via the clock gating controller to gate the clock signal from entering the second set of logic gates; A component for providing the clock signal from the first clock gate associated with the first grid portion of the SoC to the first set of logic gates; And A component for, in response to providing the clock signal to the first set of logic gates, measuring a characteristic at the second grid portion of the SoC using a first sensor.

28. The system on chip according to claim 27, further comprising: A component for inputting the test data into a second scan chain section from the test data input connection, where the second scan chain section includes the second set of logic gates located within the second grid portion of the SoC; A component for configuring the second clock gate via the clock gating controller to provide the clock signal to the second set of logic gates; A component for, in response to configuring the second clock gate to provide the clock signal to the second set of logic gates, configuring the first clock gate via the clock gating controller to gate the clock signal from entering the first set of logic gates; A component for providing the clock signal from the second clock gate to the second set of logic gates; and A component for, in response to providing the clock signal to the second set of logic gates, measuring the characteristic at the first grid portion of the SoC using a second sensor.

29. The system on chip according to claim 28, wherein, The first sensor and the second sensor are a temperature sensor and a voltage sensor, and the characteristic is the temperature of the corresponding grid portion and the voltage in the corresponding grid portion.

30. The system on chip according to claim 28, further comprising: A component for comparing the characteristic measurement values from the first sensor and the second sensor with thresholds corresponding to the respective grid portions; A component for identifying an error in the SoC in response to the measured characteristic exceeding the threshold, where the error is an indication of an aging power delivery network, an on-chip or off-chip power attack, or a hard error; and A component for implementing a remedial action in response to identifying the error.

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