Positioning mark structure, exposure area and wafer for wafer testing

Abstract

The application provides a positioning mark structure for wafer testing, an exposure area and a wafer. The positioning mark structure for wafer testing is located in a test structure of an exposure area on a wafer, and comprises a plurality of positioning mark units. Each positioning mark unit is arranged between two pads, and comprises a fuse device, a diode and a resistor in series. Before cutting and packaging the exposure area, a preset voltage is loaded to each positioning mark unit to mark the state of the positioning mark unit. The state combination of the positioning mark units constitutes mark information of the positioning mark structure, so as to represent the position of the test structure on the wafer. The mark and identification process using the positioning mark structure is simple. In the reliability test, the position identification information of the packaged sample can be quickly and conveniently known by acquiring the mark information, the accuracy is high, the traceability is good, manual marking is not needed, human errors are avoided, the numbering information is not lost due to abrasion or wiping, and the accuracy and efficiency of the test are improved.

Description

Technical Field

[0001] This specification relates to the field of semiconductor testing, specifically to a positioning mark structure, exposure area, and wafer for wafer testing. Background Technology

[0002] The repeating units on a wafer are called exposure areas (Shots), and a single wafer has multiple Shots arranged in a regular pattern. Depending on the size of the Shots and the wafer itself, the wafer is divided into patterns with different arrangements and numbers.

[0003] Reliability test devices, as basic test units, are also placed in these shots in the form of test keys. Reliability test results reflect the distribution of shots on the wafer, helping to identify and analyze process problems. Therefore, it is necessary to clearly know the location of each test sample on the wafer during the testing process. After the wafer is diced and packaged, each shot needs to be manually numbered, and the correspondence between the number and the shot's location on the wafer needs to be recorded. This is labor-intensive, inefficient, prone to human error, and has poor traceability. Summary of the Invention

[0004] In view of this, embodiments of this specification provide a positioning mark structure, an exposure area, and a wafer for wafer testing. The positioning mark structure for wafer testing can record marking information, which is easily read during subsequent testing to reflect the position of the shot on the wafer, providing good traceability, high accuracy, and improved testing efficiency.

[0005] The embodiments in this specification provide the following technical solutions:

[0006] A positioning mark structure for wafer testing, wherein the positioning mark structure is located in a test structure in an exposure area on the wafer and includes multiple positioning mark units;

[0007] The positioning mark unit is disposed between two gaskets and includes a fuse, a diode, and a resistor connected in series;

[0008] Before cutting the exposure area, a first voltage or a second voltage is applied to each positioning mark unit to mark each positioning mark unit as a first state or a second state. The combination of the states of the positioning mark units constitutes the marking information of the positioning mark structure to characterize the position of the exposure area on the wafer.

[0009] Using the aforementioned positioning mark structure for wafer testing, before cutting the exposure area during testing, a corresponding voltage is applied to the positioning mark unit to either fuse or retain the fused device, thereby marking the status of each positioning mark unit. The positioning mark structure contains multiple positioning mark units, and the combination of different states of these positioning mark units constitutes the unique marking information of the positioning mark structure. In subsequent reliability testing, the location of the shot on the wafer can be easily identified by reading the marking information. Using this positioning mark structure, the marking and identification process is simple, efficient, and has good traceability. It avoids manual marking and prevents the loss of marks due to wear or wiping from manual marking. The marking accuracy is high; by identifying the identification information fixed in the test structure, the position information of the exposure area on the wafer can be accurately and conveniently obtained, ensuring accuracy and effectiveness.

[0010] This specification also provides an embodiment in which the fusible device includes one of a fuse and a capacitor.

[0011] This specification also provides an embodiment in which the positioning mark unit includes a first branch and a second branch connected in parallel. Both the first branch and the second branch include a fuse, a diode, and a resistor connected in series, wherein the diodes in the first branch and the second branch are in opposite directions.

[0012] This specification also provides an embodiment in which at least two of the positioning mark units share a single pad at their first ends.

[0013] This specification also provides an embodiment in which the first end of all the positioning mark units shares a single pad.

[0014] This specification also provides an embodiment in which the positioning mark unit is disposed between two adjacent pads.

[0015] This specification also provides an exposure area, which includes a positioning mark structure for wafer testing as described in any of the preceding embodiments.

[0016] This specification also provides a wafer comprising an exposure area as described in any of the preceding embodiments.

[0017] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least:

[0018] The positioning mark structure for wafer testing provided by this invention allows for the application of different voltages to the positioning mark units via an automated testing machine during wafer reliability testing. This causes the fuses to blow or remain in place, resulting in different states being input and retained at each positioning mark unit. The combination of these states constitutes the marking information of the test structure, providing identification information for the exposure area. This identification information reflects the location on the wafer, making the exposure area within the test sample easily identifiable. This allows for quick and convenient identification of the packaged sample's position on the wafer, aiding in the discovery and analysis of process problems. Using this positioning mark structure simplifies the marking and identification process, saving time spent on marking during packaging. It also provides good traceability. By using a limited number of pads to fix the marking information within the test structure, the process of marking and identifying positioning information is accurate and efficient. It eliminates the need for manual numbering, reducing manpower consumption and avoiding human error and loss of numbers, thus improving the efficiency and accuracy of wafer testing. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the exposure area on the wafer;

[0021] Figure 2 This is a schematic diagram of the exposure area on an automatic testing machine.

[0022] Figure 3 This is a schematic diagram of a packaged sample with a manual number;

[0023] Figure 4 This is a schematic diagram of the layout of a positioning mark structure used for single-fuse type wafer testing.

[0024] Figure 5 This is a schematic diagram of the layout of two sets of positioning mark structures used for testing fuse-type wafers;

[0025] Figure 6 This is a status description of two sets of positioning marker units used for fuse-type wafer testing;

[0026] Figure 7 This is a schematic diagram of the layout of two sets of positioning mark structures used for capacitor-type wafer testing.

[0027] Figure 8 This is a status description of the positioning marker units used for two sets of capacitive wafer testing;

[0028] Figure 9 This is a diagram showing the wafer testing sequence of an automated testing machine. Detailed Implementation

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0032] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] It should be understood that "the connection between component A and component B" means that component A is directly connected to component B, or that component A is indirectly connected to component B through other components. The directional terms such as "upper," "lower," "inner," "outer," and "side" described in the exemplary embodiments of this specification are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this specification.

[0034] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0035] The repeating units on a wafer are called exposure areas (Shots), and a single wafer contains multiple Shots arranged in a regular pattern. Based on the size of the Shots and the wafer itself, the wafer is divided into different arrangements and numbers of patterns. For example... Figure 1 As shown, reliability testing devices, as basic test units, are also placed in these shots in the form of test keys. The distribution of reliability test results on the wafer helps in the discovery and analysis of process problems, which requires a clear understanding of the location of each test sample on the wafer during testing.

[0036] For wafer-level testing, the position of the test sample can be recorded by the program of the automated machine (e.g., Figure 2 As shown in the image, each test sample has coordinates corresponding to its location on the wafer. However, many reliability tests require wafer dicing and packaging. For packaged samples, if manual marking or numbering is not performed at each step (e.g., dicing, die picking, chip mounting, wire bonding, etc.), the reliability testing process becomes inefficient. Figure 3 As shown in the figure, and if each step is executed flawlessly, then these packaged test samples will not be effectively traceable; moreover, the manual numbering process is inconvenient, labor-intensive, reduces testing efficiency, and is prone to human error in numbering; wear and tear, damage, etc. may also occur, resulting in the loss of numbering information, causing many inconveniences in the testing process.

[0037] Through repeated experiments and research, the inventors first proposed a positioning mark structure that can automatically identify test structures. This positioning mark structure contains multiple positioning mark units, each equipped with a series-connected fuse, diode, and resistor. When the wafer undergoes wafer-level testing on an automated testing machine, a preset voltage is applied to each positioning mark unit via a probe, causing the fuse to either blow or remain in a normal state, thus inputting marking information for the positioning mark unit. By applying different preset voltages to multiple positioning mark units, each unit is marked with its own information. This combined marking information constitutes the positioning mark structure's unique "identity information," which indicates the location of the packaged shot on the wafer, facilitating the discovery and analysis of process problems.

[0038] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0039] This invention provides a positioning mark structure for wafer testing, such as... Figure 4As shown, the positioning mark structure is set in the test structure, the test structure is located in the exposure area (Shot) on the wafer, and the positioning mark structure includes multiple positioning mark units with the same structure.

[0040] The positioning marker unit is positioned between two pads of the test structure. The positioning marker unit includes a series-connected fuse, diode, and resistor.

[0041] Before cutting the exposure area, for example when the wafer is being tested on an automated test machine, or when the wafer is loaded onto an automated test machine, the positioning mark unit is applied a first voltage or a second voltage by contacting the pads at both ends of the positioning mark unit with the probe, thereby marking the positioning mark unit as a first state or a second state respectively.

[0042] For example, such as Figure 4 As shown, the fusible device is a fuse. Applying a first voltage exceeding the rated voltage of the fuse to the pad causes the fuse to blow; or applying a second voltage (e.g., applying a second voltage below the rated voltage, or applying 0V, or applying no voltage) keeps the fuse in a normal state. After obtaining the test sample from the package shot, a small voltage that allows the diode to turn on is applied to the pad, and in one of the pads (e.g. Figure 4 A 0V voltage is applied to padN as shown in the figure, and a measurement is performed. If the fuse has blown, the resistance of the positioning mark unit is measured to be infinite. If the fuse is working normally, the resistance value is measured, thereby obtaining the status of the positioning mark unit.

[0043] The positioning marker structure has multiple positioning marker units, and each positioning marker unit is set to a different state by applying voltage. Let the number of positioning marker units be 'a', and the combination of 'a' positioning marker units can provide 2... a Different combinations of states can be used to assign different marking information. In other words, by combining the individual states of all positioning marking units, unique marking information can be set for different test units on the same wafer, serving as "identity information" to characterize the position of the packaged exposure area on the wafer.

[0044] Following the same design concept, the fuse device can also be a capacitor (not shown in the figure) instead of the aforementioned fuse. In the marked state, a first voltage exceeding the breakdown voltage of the capacitor is applied; or a second voltage below the breakdown voltage is applied (or 0V is applied, or no voltage is applied), so that the capacitor remains in a normal state. After obtaining the test sample through packaging, the positioning mark unit is measured in the same way as the method described above for testing the fuse-type positioning mark unit. If the capacitor is broken down, the resistance value is measured; if the capacitor is working normally, the resistance is measured to be infinite, thereby obtaining the state of the positioning mark unit. Similarly, by combining the individual states of all positioning mark units, unique marking information is obtained to characterize the position of the exposed area on the wafer.

[0045] It should be noted that the aforementioned fuses, capacitors, diodes, and resistors can be fabricated in the test structure using photolithography, and any fuse, capacitor, diode, or resistor of any material, form, size, and specification is suitable for the wafer testing positioning mark structure proposed in this invention.

[0046] It should also be noted that in the same positioning mark structure, a series structure containing fuses and a series structure containing capacitors can be used together for status marking.

[0047] During wafer testing, using the aforementioned positioning mark structure, a corresponding voltage is applied to the positioning mark unit before the exposure area is cut. For example, an automated testing machine sets different marks and wafer position correspondences for different shots (exposure areas), and the probe either blows or retains the fuse, thereby marking the status of each positioning mark unit. The positioning mark structure contains multiple positioning mark units, and the combination of different states of these positioning mark units constitutes the unique marking information of the positioning mark structure, such as numbering information. This numbering information reflects the position of the shot on the wafer (e.g., ...). Figure 9 (As shown). In subsequent reliability testing, the location of the shot on the wafer can be easily identified by reading the marking information. Using this positioning marking structure, the marking and identification process is simple, saving time spent on marking during packaging. It offers good traceability, and by using a limited number of pads to fix the marking information in the test structure, manual marking is avoided, and the markings will not be lost due to wear or wiping from manual marking, ensuring the accuracy and effectiveness of positioning.

[0048] In some implementations, the positioning marker unit is disposed between two adjacent pads.

[0049] It should be noted that a set of two pads constitutes a set of pads, and multiple sets of pads can be adjacent to each other or not. For example, the positioning mark unit can be placed on an empty pad in the test structure.

[0050] In some implementations, at least two positioning marker units share a single pad at their first ends to save on the number of pads used.

[0051] In some implementations, such as Figure 5 and Figure 7 As shown, the positioning mark unit includes a first branch and a second branch connected in parallel. Both the first branch and the second branch include a fuse, a diode, and a resistor connected in series, and the diodes in the two branches are in opposite directions. Figure 5 The fuse is the device that breaks the circuit. Figure 7 The fuse in this circuit is a capacitor. The connection and structural composition can be referenced from the aforementioned implementation of fuses or capacitors as fuses, and will not be repeated here. Similarly, the first and second branches use different voltages for status marking, for example, in a circuit structure with two sets of fuses (such as...). Figure 5 As shown, a first voltage greater than the rated voltage or a second voltage lower than the rated voltage is applied to the pads at both ends of the positioning mark unit to mark different states for the positioning mark unit; for example, for a circuit structure with two sets of capacitors (such as... Figure 7 As shown, a first voltage greater than the breakdown voltage or a second voltage lower than the breakdown voltage is applied to the pads at both ends of the positioning mark unit to mark different states for the positioning mark unit. The specific state markings are described below.

[0052] When using a fuse as a fusible device, during testing of the connection pad (e.g.) Figure 5 In the test, forward and reverse voltages are applied to the two pads (padN, padN+1), respectively. These voltages are small enough to turn on the diode. Taking an example where the resistance in both the first and second branches is 100 ohms, the following can be measured: Figure 6 The four different states are shown; similarly, when a capacitor is used as a fuse, the following can also be measured: Figure 8 The four different states shown are: that is, the positioning mark unit obtains four different states by applying voltage for marking.

[0053] In summary of the above solutions, compared to Figure 4 The single-channel serial structure of the positioning mark unit can achieve more combination forms when the positioning mark units are combined with each other, i.e., 4 n There are several combinations, where n is the number of positioning marker units, thereby reducing the number of substrates used.

[0054] It should be noted that, Figure 5 and Figure 7The English labels are: Fuse, Diode, Resistor, Capacitor, and pad.

[0055] It should also be noted that the circuit structure for the two sets of fuses (such as...) Figure 5 The second voltage applied to the pads at both ends of the positioning mark unit (as shown) can be 0V or no voltage applied, to keep the fuse in the first branch or the second DC in a normal state; the circuit structure of the two sets of capacitors (as shown) Figure 7 The second voltage applied to the pads at both ends of the positioning mark unit (as shown) can be 0V or no voltage applied, in order to keep the capacitor in the first branch or the second DC in a normal state.

[0056] In some embodiments, at least two of the above-mentioned positioning mark units having a first branch and a second branch share a single pad at their first ends, thereby saving the number of pads used.

[0057] In some implementations, the first end of all positioning marker units shares a single pad. For example, Figure 5 and Figure 7 All the positioning mark units shown share a common pad N at their first ends, and the positioning mark units are disposed between adjacent pads, as shown. Figure 5 and Figure 7 As shown, the first positioning marker unit is set between padN and padN+1; the second positioning marker unit is set between padN and padN+2; the third positioning marker unit is set between padN and padN+3...

[0058] In the above scheme, the pads (padN) provided with 0V voltage are shared during testing. In this case, adding one pad to the positioning mark structure adds 4 states; adding two pads adds 16 states, for a total of 4... m-1 There are 128 possible states, where m is the number of pads. For example, a 200mm wafer typically has only about 30 shots; a 300mm wafer typically has only about 70 shots. This means that by using a total of 5 pads, including shared pads, 128 possible state combinations can be obtained to distinguish different shots on the wafer.

[0059] Based on the same inventive concept, embodiments of this specification also provide an exposure area, which includes the positioning mark structure for wafer testing described in any of the preceding embodiments.

[0060] The technical effects that the exposure area provided in the above embodiments can bring can be referred to the technical effects provided in the various embodiments of the positioning mark structure for wafer testing, which will not be repeated here.

[0061] Based on the same inventive concept, embodiments of this specification also provide a wafer, the wafer including the exposure area as described in any of the preceding embodiments.

[0062] The technical effects that the wafers provided in the above embodiments can bring can be referred to the technical effects provided in the various embodiments of the positioning mark structure for wafer testing, which will not be repeated here.

[0063] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments described later are relatively simple in description because they correspond to the system; relevant parts can be referred to the descriptions in the system embodiments.

[0064] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A positioning mark structure for wafer testing, characterized by, The positioning mark structure is located in a test structure of an exposure area on a wafer, and includes a plurality of positioning mark units; The positioning mark unit is arranged between two pads, and includes a fuse device, a diode and a resistor in series; Before the exposure area is cut, a first voltage or a second voltage is loaded to each positioning mark unit to mark each positioning mark unit as a first state or a second state, and a combination of states of the positioning mark units constitutes mark information of the positioning mark structure to represent a position of the exposure area on the wafer. The combination of states of the positioning mark units is used to quickly identify the position of the exposure area on the wafer after packaging.

2. The positioning mark structure according to claim 1, wherein The fuse device includes one of a fuse and a capacitor.

3. The positioning mark structure according to claim 1, wherein The positioning mark unit includes a first branch and a second branch in parallel, and the first branch and the second branch each include a fuse device, a diode and a resistor in series, wherein the diodes of the first branch and the second branch are in opposite directions.

4. The positioning mark structure according to claim 3, wherein First ends of at least two positioning mark units share one pad.

5. The positioning mark structure according to claim 4, wherein First ends of all positioning mark units share one pad.

6. The positioning mark structure according to claim 1, wherein The positioning mark unit is arranged between two adjacent pads.

7. An exposure area, characterized by The exposure area includes the positioning mark structure for wafer test as claimed in any one of claims 1 to 6.

8. A wafer, characterized by, The wafer includes the exposure area as claimed in claim 7.

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