System and method for reducing layout size using non-orthogonal process recipes

Abstract

The present disclosure relates generally to systems and methods for reducing layout size using non-perpendicular process recipes. A semiconductor processing system includes a layout database that stores a plurality of layouts indicative of features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and determines, for each layout, whether a non-perpendicular particle bombardment process should be used in conjunction with a photolithography process to form the features of the layout in the wafer.

Description

TECHNICAL FIELD

[0001] The present disclosure generally relates to systems and methods for reducing layout size using a non-vertical process recipe. BACKGROUND

[0002] There is a continuing demand to increase computing power in electronic devices, including smart phones, tablets, desktop computers, laptop computers, and many other types of electronic devices. One way to increase computing power in integrated circuits is to increase the number of transistors and other integrated circuit features that can be included in a given area of a semiconductor substrate.

[0003] To continually reduce the size of features in integrated circuits, various thin film deposition techniques, etching techniques, and other processing techniques are implemented. Many etching processes involve depositing a layer of photoresist and patterning the photoresist by exposing the photoresist to ultraviolet light through a photomask. The mask includes a pattern to be formed in the photoresist. However, as the size of the desired features decreases, it can be difficult to pattern the photoresist in the desired manner. SUMMARY

[0004] According to a first embodiment of the present disclosure, a semiconductor processing method is provided, comprising: storing layout data associated with a first layout of a wafer; extracting, from the layout data, feature data indicative of a size associated with a feature of the first layout; comparing the feature data to a selection rule; and responsive to the feature data satisfying the selection rule, selecting a non- perpendicular particle bombardment process for use in implementing the first layout in the wafer.

[0005] According to a second embodiment of the present disclosure, a semiconductor processing method is provided, comprising: analyzing a layout associated with wafer processing; selecting, for the layout, a non-perpendicular particle bombardment process based on a size associated with a feature of the layout; defining, according to a pattern of the layout, a first trench and a second trench in a mask on a wafer using a photolithography process; and adjusting a size of the first trench and the second trench by performing the non- perpendicular particle bombardment process on the wafer.

[0006] According to a third embodiment of the present disclosure, there is provided a semiconductor device, comprising: a substrate; a first metal line extending in a first direction in the substrate and having a first rounded end; a second metal line extending in the first direction in the substrate in line with the first metal line and having a second rounded end separated from the first rounded end by an end-to-end separation distance; and a third metal line extending in the first direction in the substrate and separated from the first metal line by a side-to-side separation distance in a second direction, the side-to-side separation distance being greater than or equal to the end-to-end separation distance, the second direction being perpendicular to the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure can be best understood with reference to the following specific description when considered in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale. In fact, the dimensions can have been arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a block diagram of a semiconductor processing system according to some embodiments.

[0009] Figure 2A and Figure 2B is a top view of a layout according to some embodiments.

[0010] Figures 3A-3I is a cross-sectional view and a top view of a wafer at various processing stages according to some embodiments.

[0011] Figure 4 is a top view of metal lines in a wafer according to some embodiments.

[0012] Figure 5A and Figure 5B is a top view of a wafer according to some embodiments.

[0013] Figure 6A and Figure 6B is a top view of a wafer according to some embodiments.

[0014] Figure 7A and Figure 7B is a cross-sectional view of a wafer according to some embodiments.

[0015] Figures 8A-8C is an isometric view of a wafer according to some embodiments.

[0016] Figure 9 is an illustration of a non-perpendicular particle bombardment system according to some embodiments.

[0017] Figure 10is a flowchart of a method for operating a semiconductor processing system according to some embodiments.

[0018] Figure 11 is a flowchart of a method for operating a semiconductor processing system according to some embodiments. DETAILED DESCRIPTION

[0019] In the following description, numerous specific details are set forth to provide a thorough understanding of the various embodiments of the present disclosure. However, those skilled in the art will recognize that the various embodiments of the present disclosure can be practiced without the specific details given herein. In other instances, well-known structures and components are not described in detail in order to avoid obscuring aspects of the various embodiments of the present disclosure.

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Each of the following embodiments is described in enough detail to provide a complete understanding of at least one example of the various embodiments. Other embodiments can be utilized and derived without departing from the scope of the disclosure, which is defined solely by the claims and equivalents thereof. Such embodiments of the inventive subject matter can be referred to, individually or collectively, herein as “specific embodiments” to convey the reader that a given embodiment described does not include all embodiments. It is also noted that the specific embodiments described herein can be implemented in combination with other specific embodiments.

[0021] Furthermore, spatially relative terms (for example, “beneath”, “below”, “lower”, “above”, “upper”, and the like) can be used herein for ease of describing one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will recognize that the disclosure can be practiced without one or more of these specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures associated with electronic components and manufacturing technology have not been described in order to avoid obscuring aspects of the embodiments of the disclosure.

[0023] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an open, inclusive sense, as op posed to an exclusive or exhaustive sense.

[0024] The use of ordinal numbers such as first, second, and third does not necessarily mean an ordinal ordering sense, but can merely distinguish multiple instances of a behavior or structure.

[0025] Reference throughout this specification to “some embodiments” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, the appearances of the phrases “in some embodiments” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0026] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and / or” unless the content clearly dictates otherwise.

[0027] Embodiments of the present disclosure provide a semiconductor processing system that selects between different patterning processes for each of a plurality of layouts to be used in processing a semiconductor wafer. The semiconductor processing system includes a layout database and a layout analyzer. The layout database includes layout data associated with various stages of semiconductor processing. The layout analyzer analyzes a distribution and size of features associated with each layout. The layout analyzer compares the layout feature data to selection rule data. The selection rule data determines whether a non-normal particle bombardment process is used in addition to a photolithography process to define features associated with the layout. If a non-normal particle bombardment process is selected for the layout, the layout is adjusted to reduce a size between some features.

[0028] The layout analysis and process selection has various benefits. For example, a non-normal ion bombardment process can be used to overcome pattern scaling limitations of a photolithography process. The result is that the layout is improved, layout features are correctly and reliably transferred to the wafer, and wafer yield is increased.

[0029] Figure 1 is a block diagram of a semiconductor processing system 100 in accordance with some embodiments. The semiconductor processing system 100 can correspond to a system that processes a wafer 102. The semiconductor processing system 100 performs a plurality of semiconductor processes on the wafer 102 to form semiconductor layers, dielectric layers, conductive layers, and various other structures or components to produce a functional integrated circuit.

[0030] The semiconductor processing system 100 includes a photolithography system 106. The photolithography system 106 can be used to form a mask on the wafer 102. The mask has a pattern selected to implement various feature layouts.

[0031] In a lithography process, the lithography system 106 can deposit photoresist on the wafer 102. The lithography system 106 can then illuminate the wafer with lithography light via a reticle. The reticle has a mask pattern to be formed in the photoresist. The lithography system 106 can direct the lithography light to reflect off the reticle onto the wafer 102. After the lithography light has reflected off the reticle, the lithography light carries the pattern of the reticle. The lithography light illuminates the photoresist on the wafer 102 with the pattern of the reticle. The portions of the photoresist that are illuminated by the lithography light undergo a structural change, such that a subsequent etching process removes either the exposed photoresist or the unexposed photoresist, depending on the type of photoresist. The remaining photoresist corresponds to a mask having the pattern of the reticle.

[0032] In some embodiments, the lithography system 106 transfers a pattern onto photoresist for forming metal interconnect structures in the wafer 102. The metal interconnect structures can include metal lines that extend in a first direction. Some of the metal lines are spaced apart from each other in a second direction perpendicular to the first direction by a side-to-side separation distance. Some of the metal lines are spaced apart from each other in the first direction by an end-to-end separation distance. In some cases, the lithography system 106 can not be able to generate an end-to-end separation distance that is as small as the side-to-side separation distance. In other words, the lithography system 106 can not be able to generate a separation distance between features in the first direction that is as small as a separation distance between features in the second direction.

[0033] In one example, the lithography system 106 can be able to make the side-to-side separation distance greater than or equal to 15 nm. The lithography system 106 can only be able to make the end-to-end separation distance greater than or equal to 30 nm. The larger end-to-end separation distance corresponds to a larger wafer area consumption.

[0034] In some embodiments, lithography system 106 is an extreme ultraviolet (EUV) lithography system. EUV lithography systems generate EUV light. As used herein, the terms “EUV light” and “EUV radiation” can be used interchangeably. In some embodiments, EUV light has a wavelength between 10 nm and 15 nm. In one example, EUV light has a central wavelength of 13.5 nm. In a lithography process, one of the factors that affects the size of features that can be formed in a wafer is the wavelength of the light used in the lithography process. Because EUV light has a very small wavelength, EUV light can be utilized to define very small features on wafer 102. Different EUV generation processes can provide EUV light in different wavelength ranges and different central wavelengths. Thus, without departing from the scope of the present disclosure, EUV light can have different wavelength ranges and different central wavelengths than those described above. Without departing from the scope of the present disclosure, lithography system 106 can include a lithography system other than an EUV lithography system.

[0035] In some cases, even EUV lithography systems can have difficulty generating features with an end-to-end separation distance of less than 30 nm. Thus, compared to the case described earlier where the end-to-end separation distance is as small as the side-to-side separation distance, a greater wafer area can be wasted in the end-to-end space between features.

[0036] To reduce the end-to-end separation distance between features, semiconductor processing system 100 includes a non-normal particle bombardment system 108. Non-normal particle bombardment system 108 can be used in conjunction with lithography system 106 to reduce the end-to-end distance between features, or to otherwise reduce the width of mask structures after a lithography process. Specifically, after a lithography process has been performed and a patterned mask has been formed on wafer 102, non-normal particle bombardment system 108 can be utilized to reduce the width of the mask structure, thereby reducing the end-to-end distance between features to be formed in wafer 102.

[0037] In some embodiments, particle bombardment system outputs particles at a selected angle relative to a normal direction to wafer 102. The normal direction is perpendicular to the surface of wafer 102. Thus, the particles travel at a non-normal angle relative to the surface of wafer 102. In this sense, the particles travel at a non-normal angle.

[0038] After the photoresist is patterned, the particles bombard or impact the sidewalls of the remaining photoresist structure. The impact of the particles on the sidewalls of the remaining photoresist structure removes a portion of the remaining photoresist structure. This reduces the lateral width of the remaining photoresist structure. This reduction in lateral photoresist size by directional particle bombardment can be referred to as a directional push. The particles can include atoms, molecules, compounds, ions, or other particles.

[0039] In some embodiments, the non-normal particle bombardment system 108 is a particle bombardment system. In this case, the particles are ions. The particle bombardment system outputs a beam of ions toward the wafer 102. The beam of ions impinges the wafer 102 with a trajectory having an angle relative to the normal, i.e., a non-normal angle. The ions cause material to detach from the sidewalls of the mask structure, thereby reducing the lateral dimension of the mask structure.

[0040] In some embodiments, the non-normal particle bombardment system 108 is a directed plasma etching system. The directed plasma etching system generates a plasma that emits high-energy ions or other charged particles that cause material on the lateral surface of the mask structure to decompose. The trajectory of the high-energy ions or other charged particles can be selected by tilting the wafer relative to the normal, or by otherwise generating a plasma sheath that emits particles with a selected trajectory.

[0041] As used herein, a mask feature corresponds to a trench or a hole to be formed in a photoresist or other mask layer. Thus, an end-to-end separation distance between two features corresponds to the lateral width of the photoresist or other mask layer separating the two features. By reducing the lateral width of the photoresist or other mask layer using a particle bombardment process, the end-to-end separation distance between features can be reduced, thereby enabling more full utilization of the available wafer area.

[0042] In one example, the reduction in end-to-end separation distance enables contact vias to be placed closer together. If two features in a mask correspond to two metal lines separated by an initial end-to-end distance, and if the layout design calls for a conductive via to contact each metal line, then with a reduction in the end-to-end distance between the metal lines, the two contacts can be placed closer together. Thus, reducing the end-to-end distance between features can enable more densely formed other interconnect structures in the wafer 102.

[0043] In some embodiments, the particle bombardment system 108 bombards the photoresist structure with particles in multiple steps. In a first particle bombardment step, the particles travel at an angle relative to the normal, with an energy and a dose level. In a subsequent second particle bombardment step, one or more aspects of the particle beam are changed relative to the first particle bombardment step. Thus, in the second particle bombardment step, one or more of the angle of travel, the energy, or the dose level of the particle beam are changed relative to the first particle bombardment step. Having two particle bombardment steps with different characteristics enables more efficient reduction in the width of the remaining photoresist features, as compared to performing only a single particle bombardment step, or the same as the second particle bombardment step and the first particle bombardment step.

[0044] The semiconductor processing system 100 includes a layout database 110. The layout database 110 includes a plurality of layouts 112. Each layout 112 indicates a pattern of features to be formed in the wafer 102 at a particular processing stage. For example, a first layout can indicate an area of a semiconductor substrate where an N-well is to be formed. A second layout can indicate an area of a semiconductor substrate where a P-well is to be formed. A third layout 112 can indicate an area where a trench is to be etched to define a semiconductor fin. Another layout can indicate an area where metal lines and conductive vias are to be formed in a first interlayer dielectric layer. Another layout can indicate an area where metal lines and conductive vias are to be formed in a second interlayer dielectric layer. A large number of layouts 112 can be used in processing the wafer 102 (from start to finish).

[0045] Generally, one or more photolithography processes can be associated with each layout 112. One or more reticles can be generated for each layout 112. The reticles carry the patterns or seed patterns of the layouts 112 from which the layouts are realized after various semiconductor processes have been performed. The photolithography processes transfer the patterns of the reticles onto photoresist on the wafer 102.

[0046] One example of a layout 112 is a GDS (Graphics Database System) layout, although other types or formats of layouts can be used. The layouts 112 can be generated with one or more specialized software programs (for generating layouts for semiconductor processing) from which photolithography reticles can be generated according to the layouts.

[0047] The semiconductor processing system 100 includes a layout analyzer 114. The layout analyzer 114 is configured to analyze each layout 112. The layout analyzer 114 is configured to select, for each layout 112, whether to utilize the particle bombardment system 108 to reduce the end-to-end distance between mask features after initial photolithographic patterning.

[0048] When the layout analyzer 114 analyzes a layout 112, the layout analyzer 114 extracts layout feature data 116 associated with the layout 112. The layout feature data 116 can include data relating to the size, shape, and location of features in the layout 112. The layout analyzer 114 determines whether the particle bombardment system 108 should be used after performing the photolithography system associated with the layout 112 based on the layout feature data 116 that the layout analyzer 114 extracts from the layout 112.

[0049] The layout feature data 116 can include edge-to-edge separation distances associated with adjacent features of the layout 112. As previously described, for two adjacent features extending in line with each other in a first direction, the end-to-end separation distance corresponds to a distance between adjacent ends of the two features in the first direction. Thus, the end-to-end separation distance can correspond to a distance between two adjacent ends of two features of the layout 112.

[0050] In some embodiments, the layout feature data 116 includes pitch data. The pitch data includes data regarding one or more pitches associated with the layout 112. A pitch can correspond to a distance between like portions of two adjacent features. For example, if the layout 112 includes two adjacent metal lines, a pitch associated with the two metal lines can be a distance between an edge of a first metal line and a like edge of a second adjacent metal line.

[0051] The layout feature data 116 can include end-to-end separation distances and edge-to-edge separation distances for a large number of adjacent features in the layout. In some cases, the layout feature data 116 can include every edge-to-edge separation distance and end-to-end separation distance associated with the layout 112. In other cases, the layout feature data 116 can include edge-to-edge separation distances and end-to-end separation distances associated with a sample feature (and the layout 112). In some cases, the layout feature data 116 can include separation distances associated with features in a selected region of the layout 112. In one example, the layout analyzer 114 extracts separation distance data associated with a 5 pm x 5 pm portion of the layout 112, although other area values can be used without departing from the scope of the present disclosure. The layout feature data 116 can include pitch data for all pitches of the layout 112, a sample pitch of the layout 112, or all pitches of a selected region of the layout 112.

[0052] The feature data 116 can include threshold data for various types of feature measurements. For example, the feature data 116 can include a threshold end-to-end separation distance. The layout feature data 116 can indicate whether each end-to-end separation distance in the layout is less than or greater than the threshold end-to-end separation distance. The feature data 116 can include a threshold edge-to-edge separation distance and can indicate whether each edge-to-edge separation distance in the layout 112 is less than, greater than, or equal to the threshold edge-to-edge separation distance. The feature data 116 can include threshold pitch values and threshold critical dimension values, as well as corresponding data for each pitch in a critical dimension of the layout 112.

[0053] In some embodiments, the layout feature data 116 includes critical dimension (CD) data. The CD data includes data related to one or more CDs associated with the layout 112. A CD associated with a feature can correspond to a smallest dimension associated with the feature. For example, if the layout 112 includes a metal line having a length of 100 nm and a width of 15 nm, the CD associated with the metal line can be the 15 nm associated with the width, as the width is the smallest lateral dimension of the metal line.

[0054] The layout analyzer 114 can include selection rule data 118. The selection rule data 118 can include rules or guidelines for determining whether the particle bombardment system 108 should be used with a particular layout 112. The layout analyzer 114 compares the layout feature data 116 to the selection rule data 118. The layout analyzer 114 determines whether the particle bombardment system should be used with the layout based on the comparison of the selection rule data 118 to the layout feature data 116.

[0055] In some embodiments, the selection rule data 118 can determine whether the particle bombardment system 108 should be implemented based on whether one or more end-to-end separation distances of the layout 112 are greater than a threshold end-to-end separation distance. In this case, if any of the end-to-end separation distances are greater than the threshold end-to-end separation distance, the layout analyzer 114 determines that the non-vertical particle bombardment system 108 should be used in association with the layout. Otherwise, the lithography system 106 can be used without the particle bombardment system 108.

[0056] In one example, the threshold end-to-end separation distance is 30 nm. This threshold end-to-end separation distance can be useful in cases where the lithography system 106 itself is not capable of producing end-to-end separation distances less than 30 nm. Other threshold end-to-end separation distances can be used without departing from the scope of the present disclosure.

[0057] In some embodiments, the selection rule data 118 can determine whether the particle bombardment system 108 should be implemented based on whether one or more edge-to-edge separation distances of the layout 112 are greater than a threshold edge-to-edge separation distance. In this case, if any of the edge-to-edge separation distances are less than the threshold end-to-end separation distance, the layout analyzer 114 determines that the EUV lithography system 106 should be used for a lithography process associated with the layout. Otherwise, the lithography system 106 can be used without the particle bombardment system 108.

[0058] In one example, the threshold edge-to-edge separation distance is 15 nm. This threshold edge-to-edge separation distance can be useful in cases where the lithography system 106 itself is not capable of producing edge-to-edge separation distances less than 15 nm. Other threshold edge-to-edge separation distances can be used without departing from the scope of the present disclosure.

[0059] In some embodiments, selection rules data 118 can determine whether particle bombardment system 108 should be implemented based on whether a percentage of end-to-end separation distances that are less than a threshold end-to-end separation distance is less than a threshold percentage. For example, the threshold percentage can be between 45% and 55%. If the percentage of end-to-end separation distances that are less than the threshold end-to-end separation distance is less than the threshold percentage, layout analyzer 114 can select to use particle bombardment system 108 after a lithography process.

[0060] In some embodiments, selection rules data 118 can include rules related to both end-to-end separation distances and edge-to-edge separation distances. Selection rules data 118 can indicate that layout analyzer 114 should select to utilize particle bombardment system 108 after a lithography process associated with a layout if one or more edge-to-edge separation distances are less than a threshold edge-to-edge separation distance and if one or more end-to-end separation distances are greater than a threshold end-to-end separation distance.

[0061] In some embodiments, selection rules data 118 can include multiple rules related to end-to-end separation distances, edge-to-edge separation distances, pitch, CD, and other characteristics. Selection rules data 118 can indicate that layout analyzer 114 should select to use particle bombardment system 108 based on adherence to or violation of the various selection rules.

[0062] In some embodiments, layout analyzer 114 generates a layout score based on layout feature data 116 and selection rules data 118. The score can be based on a number of selection rules data that is satisfied (or violated) by layout feature data 116. Selection of particle bombardment system 108 can be based on the layout score. For example, a layout score associated with a layout can be compared to a threshold layout score, and particle bombardment system 108 can be selected based on the comparison of the layout score to the threshold layout score.

[0063] Semiconductor processing system 100 can also include a layout adjustment system 122. Layout adjustment system can adjust layout 112 after layout analyzer 114 determines that a non- perpendicular particle bombardment process should be used. In one example, a non- perpendicular particle bombardment process can produce the ability to place conductive vias closer together in a layout due to the reduction in end-to-end separation distances that results from using a particle bombardment process. The layout that defines the placement of these conductive vias can need to be adjusted. Furthermore, the layout 112 of features above and below the conductive vias in the wafer can also need to be adjusted in view of the newly placed conductive vias. Thus, layout adjustment system 122 can automatically adjust the layout to achieve compatibility after the selection of a non-perpendicular particle bombardment system 108 results in changes to some feature placements.

[0064] Semiconductor processing system 100 includes semiconductor processing equipment 104. Typically, semiconductor wafers 102 undergo a number of processes during fabrication. These processes may include thin film deposition, etching, dopant implantation, annealing, epitaxial growth, chemical mechanical planarization (CMP), and other types of processes. Semiconductor processing equipment 104 includes tools and other equipment for performing semiconductor processes on the wafers. In practice, photolithography system 106 and non-vertical particle bombardment system 108 may be part of semiconductor processing equipment 104.

[0065] Figure 2A Layout 112 is shown in accordance with some embodiments. Layout 112 corresponds to a top view of a desired pattern of features to be achieved in wafer 102 at a particular stage of processing. Figure 2A In the example of FIG, layout 112 corresponds to a top view of metal lines to be formed in a substrate (e.g., an interlayer dielectric layer). Layout 112 is not the actual wafer, but rather the pattern of features to be implemented in the wafer. Thus, layout 112 is a visual representation of the layout plan stored in layout database 110, as described with respect to FIG. Figure 1 described.

[0066] Layout 112 includes metal lines 130, 132, 134, and 136. Metal line 130 is located at Figure 2A The metal line 132 also extends continuously along the X direction in the view of FIG. Figure 2A . Metal line 134 is located between metal lines 130 and 132 and extends along the X direction. Metal line 136 is located between metal lines 130 and 132 and extends along the X direction. Metal lines 134 and 136 are aligned with each other along the X direction.

[0067] Edge 142 of metal line 130 is closest to metal lines 134 and 136. Edge 144 of metal line 134 is closest to edge 142 of metal line 130. Edge 145 of metal line 136 is farthest from edge 142 of metal line 130. Metal line 134 has end 146. Metal line 136 has end 148.

[0068] Metal line 134 is separated from metal line 130 by an edge-to-edge (or edge-to-edge) separation distance D S . Separation distance D S The lateral distance along the Y direction corresponds to the distance between the edge 144 of the metal line 134 and the edge 142 of the metal line 130. Although not explicitly detailed, the metal line 136 is also separated from the metal line 130 by the same separation distance D. S .

[0069] The metal line 134 and the metal line 136 are separated by an end-to-end separation distance D E . End-to-end separation distance DE corresponds to the distance between the end 146 of the metal line 134 and the end 148 of the metal line 136. Since the ends 148 and 146 of the metal lines 136 and 134 are circular, the separation distance D E corresponds to the distance between the closest points of the ends 146 and 148.

[0070] The metal line 136 and the metal line 130 define a metal line spacing P L . The spacing P L corresponds to the distance between the edge 142 of the metal line 130 and the edge 145 of the metal line 136. Although not detailed in Figure 2A , the spacing between the metal line 130 and the metal line 134 is the same as the spacing P L .

[0071] The metal line 136 has a critical dimension CD. The critical dimension CD corresponds to the smallest dimension of the metal line 136. In this example, CD corresponds to the width of the metal line 136 in the Y direction.

[0072] Figure 2A The layout 112 defines the locations of the conductive vias 138 and 140. The conductive via 138 contacts the metal line 134 near the end 146 of the metal line 134. The conductive via 140 contacts the metal line 136 near the end 148 of the metal line 136. The conductive vias 138 and 140 can correspond to conductive vias that extend from a higher layer to contact the metal lines 134 and 136. Alternatively, the conductive vias 138 and 140 can correspond to conductive vias that extend downward from the metal lines 134 and 136 to a more underlying conductive structure. The conductive vias are separated by a via spacing P V . The via spacing P V may correspond to the distance from the center of the conductive via 138 to the center of the conductive via 140.

[0073] The layout 112 corresponds to a layout in which the metal lines 130, 132, 134, and 136 are patterned with a photolithography process but without a non- perpendicular particle bombardment process. As such, the end-to-end separation distance D E is greater than the edge-to-edge separation distance D S . This can be due to limitations of the photolithography system 106 or other factors.

[0074] In one example, the edge-to-edge distance D S is between 10 nm and 20 nm. The end-to-end separation distance D E is between 25 nm and 35 nm. The via spacing P V is between 35 nm and 45 nm. The line spacing P LBetween 25 nm and 35 nm. The CD is between 10 nm and 15 nm. Distances other than these can be used for the layout 112 without departing from the scope of the present disclosure.

[0075] In some embodiments, the layout analyzer 114 can analyze the layout 112 and can extract layout feature data 116. The layout feature data includes the edge-to-edge separation distance D S , the end-to-end separation distance D E , the via pitch P V , the line pitch P L , and the CD for each of the metal lines 130, 132, 134, and 136. The layout analyzer 114 compares the layout feature data 116 to selection rule data 118. The selection rule data can indicate that the particle bombardment system 108 should be used to reduce the end-to-end separation distance D E in the presence of an end-to-end distance greater than a threshold distance (e.g., 30 nm). The layout analyzer 114 can use other separation rules or sets of separation rules to determine whether the particle bombardment system 108 should be used in conjunction with the layout 112.

[0076] In the example of Figure 2A , the layout analyzer 114 determines that the particle bombardment system 108 should be used to reduce the end-to-end separation distance D E . After the layout analyzer 114 determines that the particle bombardment system 108 should be used to reduce the end-to-end separation distance D E , the layout adjustment system 122 adjusts the layout 112. The adjusted layout 112 is shown in Figure 2B .

[0077] Figure 2B is a visual representation 112 of the layout after the layout adjustment system 122 adjustment according to the layout analyzer 114 selection to utilize the particle bombardment system 108 of Figure 2A . Although not shown in Figure 2B , the layout adjustment system 122 can adjust the layout of other layers below and above the layout 112 of Figure 2B in response to adjusting the layout 112.

[0078] In Figure 2B , the layout 112 takes into account the particle bombardment process to be performed by the particle bombardment system 108. The particle bombardment process has the effect of pushing the end 146 of the metal line 134 toward the end 148 of the metal line 136 and pushing the end 148 of the metal line 136 toward the end 146 of the metal line 134. The result is a greatly reduced end-to-end separation distance D E . In addition, the via pitch P VAlso greatly reduced. The result is that the area of the wafer 102 is more efficiently utilized. Details of the particle bombardment process are further set forth below.

[0079] In Figure 2A the separation distance D E In examples between 25 nm and 35 nm, Figure 2B the separation distance D E Now can be between 10 nm and 15 nm. The via pitch P V Now is between 20 nm and 25 nm. Other distances and distance variations can be used without departing from the scope of the present disclosure. In Figure 2A and Figure 2B In examples, the dimension in the Y direction does not change as a result of the particle bombardment process. However, in practice, a particle bombardment process can also be performed to reduce the separation distance in the Y direction.

[0080] Figure 3A is a cross-sectional view of a wafer 102 at an intermediate processing stage according to one embodiment. The wafer 102 includes a substrate 150 and a layer of photoresist 152 on the substrate 150. The substrate 150 can include a dielectric layer, a conductive layer, a semiconductor layer, or other types of materials. In one example, the substrate 150 is an interlayer dielectric layer, such as silicon oxide, silicon nitride, or other suitable dielectric material.

[0081] In Figure 3B the photolithography process has been performed. The photoresist 152 has been irradiated by photolithography light carrying a mask with a pattern according to the layout 112. After being irradiated by the photolithography light, the unirradiated portions of the photoresist 152 are removed.

[0082] The photoresist 152 is a remnant of a photoresist layer that has been patterned with an initial patterning process. The initial patterning process can include standard photolithographic patterning, such as exposure to ultraviolet light to a mask, and removal of the exposed or unexposed photoresist. The patterning forms trenches 154 in the photoresist 152. Figure 3B The photoresist structure 152 remaining in

[0083] The trenches 154 are separated by an end-to-end separation distance D E The end-to-end separation distance corresponds to the width of the photoresist 152 at the narrowest point between the trenches 154.

[0084] Figure 3C is a top view of the wafer 102 at a processing stage of Figure 3B Figure 3C Also shown is a cross-section taken Figure 3B ​cutting line B of the cross-section. Figure 3C is a top view showing four trenches 154 formed in photoresist 152. Figure 3C Also shown is how the ends of trenches 154 are rounded. This is a result of the photolithography process often creating rounded ends in features formed in photoresist. These rounded ends are often transferred to features formed based on the pattern of photoresist 152.

[0085] Figure 3D is a cross-sectional view of wafer 102 during a particle bombardment process according to some embodiments. The particle bombardment process can be performed by Figure 1 non-normal particle bombardment system 108. Figure 3D A particle bombardment step on sidewalls 156 of photoresist 152 is shown. Particles 162 are emitted from an ion source of particle bombardment system 108. Particles 162 travel at an angle Θ relative to the normal. The particle bombardment process can be considered a non-normal particle bombardment process.

[0086] In some embodiments, angle Θ relative to the normal is between 35° and 65°. Other angles of Θ can be used without departing from the scope of the present disclosure. Particles 162 can have an energy between 0.5 keV and 8.0 keV. The particle bombardment process can have a dose between 1E15 and 1E16 particles. Particles 162 can include ions. In one example, the ions are argon ions. Other angles, energies, doses, and types of particles can be used without departing from the scope of the present disclosure.

[0087] Figure 3D is shown after the particle bombardment step on sidewalls 156 of photoresist 152. Compared to Figure 3B it can be seen that photoresist material has been removed from sidewalls 156 of photoresist 152 and from top surface 160 of photoresist 152. This removal is a result of the bombardment by particles 162.

[0088] Figure 3E is a cross-sectional view of wafer 102 during a particle bombardment process on sidewalls 158 of photoresist 152 according to some embodiments. The particle bombardment process on sidewalls 158 can have the same angle, energy, dose, and ion species as the particle bombardment process on sidewalls 156. For clarity, Figure 3E trajectories of particles 162 are shown as coming from a different direction than Figure 3D However, in practice, between Figure 3D and Figure 3E wafer 102 is rotated 180° in the XY plane. The rotation of wafer 102 allows the particle source to bombard sidewalls 158 of photoresist 152 without needing to move the particle source.

[0089] exist Figure 3D and Figure 3E After the particle bombardment process, the photoresist 152 becomes narrower between the trenches 154. This corresponds to a larger Figure 3B Smaller end-to-end separation distance D E .exist Figure 3D and Figure 3E After the particle bombardment process, the thickness of the photoresist 152 is reduced. In some examples, the particle bombardment process can reduce the end-to-end separation distance by between 15 nm and 20 nm, but other variations in separation distance are possible without departing from the scope of the present disclosure.

[0090] Figure 3F is in Figure 3E A top view of wafer 102 is shown at a processing stage. Figure 3F The top view shows the end-to-end separation distance D of the groove 154 E Relative to Figure 3C In addition, the size of the groove 154 in the Y direction has not changed significantly. After the particle bombardment process, the end of the groove 154 remains rounded.

[0091] exist Figure 3G In the embodiment of the present invention, an etching process has been performed. The etching process etches the substrate 150 using the pattern of the photoresist 152. Specifically, the trench 150 in the photoresist 152 extends downward into the substrate 150. The etching process is an anisotropic etching process that etches downward. The etching process may include wet etching, dry etching, or other types of etching. Figure 3G The effect of the etching process is to transfer the pattern of the photoresist 152 to the substrate 150.

[0092] exist Figure 3H 154. After depositing the conductive material, a planarization process is performed to remove the remaining portion of the photoresist 152 and the conductive material from the outside of the trench 154. As a result, the conductive material remains only in the trench 154 and the substrate 150. The conductive material may include tungsten, aluminum, titanium, copper, gold, tantalum, or other conductive materials. The deposition process may include ALD, PVD, CVD, or other suitable deposition processes.

[0093] The deposition of conductive material causes metal lines 134 and 136 to be formed in trenches 154. The layout of the metal lines in wafer 102 corresponds to Figure 2B Layout 112. This can be Figure 3I It is easier to see in the top view.

[0094] Figure 3I is in Figure 3Ha top view of wafer 102 at a processing stage. Figure 3I A top view of layout 112 shows that metal lines 130, 132, 134, and 136 have been formed by depositing conductive material in trenches 154 and substrate 150. Although not evident in Figure 3I end-to-end separation distance D E may be less than or equal to edge-to-edge separation distance D S . Figure 2B The layout of 112 has been achieved by utilizing a non-orthogonal particle bombardment process after the initial photolithography process. The reduction of end-to-end separation distance D E may be achieved without using additional masks. Thus, including the particle bombardment process is inexpensive in terms of processing time and resources because no additional photolithography process is used. Figure 3I Also shown are locations where conductive vias 138 and 140 will contact metal lines 134 and 136 from above.

[0095] In one example, edge-to-edge distance D S is between 10 nm and 20 nm. End-to-end separation distance D E is between 10 nm and 20 nm. Via pitch P V is between 15 nm and 25 nm. Line pitch P L is between 25 nm and 35 nm. CD is between 10 nm and 15 nm. Distances other than these can also be used for layout 112 without departing from the scope of the present disclosure.

[0096] Figure 4 is a zoomed-in top view of metal line 134 of wafer 102 according to some embodiments. Figure 4 The view of 114 corresponds to metal line 134 after both a photolithography process and a particle bombardment process have been performed. The ends of metal line 134 remain circular after the particle bombardment process has been performed. In other words, the trenches in the mask layer remain with circular ends after the particle bombardment process on the mask layer. Corresponding trenches are etched in the substrate below the mask. Metal line 134 is then formed in the trenches in the substrate. The trenches in the substrate have the circular ends of the mask layer after the particle bombardment process on the mask layer. Metal line 134 also has circular ends.

[0097] In some embodiments, metal line 134 formed according to the particle bombardment process is such that the minimum distance R between the circular edge of metal line 134 and hypothetical point P is greater than or equal to the CD of metal line 134 divided by four. Thus, distance R can be given by the following relationship:

[0098] R > CD / 4

[0099] Point P corresponds to the point at which a vertical line drawn from end 146 of metal line 134 intersects a horizontal line continued from edge 144 of metal line 134. R can have other characteristics or relationships without departing from the scope of the present disclosure.

[0100] At an end-to-end distance D E less than or equal to the edge-to-edge separation distance D S , metal line 134 can have a distance R given by the above relationship. This can be different from other processes used to form an end-to-end distance less than or equal to D S . For example, another process that can be used to form an end-to-end distance D S less than or equal to D E is to perform two photolithography processes. After the first photolithography process, metal lines 134 and 136 will be a single continuous metal line. A second photolithography process is then used to etch a break that electrically separates metal lines 134 and 136. However, in this case, the ends of metal lines 134 and 136 will not be circular, but rather rectangular. While this can result in a smaller end-to-end separation distance D E , performing a single photolithography process in combination with a particle bombardment process as described above is more cost effective (as compared to performing two photolithography processes). This is due to the additional time and cost associated with a photolithography process, as well as the potential for overlay / alignment errors associated with a second mask.

[0101] Since a photolithography process can only be able to achieve an end-to-end separation distance of 30 nm, it is beneficial to use a non-perpendicular bombardment process to reduce the end-to-end separation to about 15 nm or less. Furthermore, a non-perpendicular particle bombardment process can result in an end-to-end separation that is less than or equal to the edge-to-edge separation distance.

[0102] Figure 5A is a top view of wafer 102 after an initial photolithography process according to some embodiments. The photolithography process includes patterning trenches 154 in a layer of photoresist 152. Alternatively, the top view of wafer 102 can include trenches 154 formed in a different mask layer than photoresist 152, or in a layer of photoresist 152, and in substrate 150. The trenches have an end-to-end separation distance D E , an edge-to-edge separation distance D S , and a line pitch P L . In one example, the edge-to-edge separation distance D S is about 15 nm, the end-to-end separation distance D E is about 30 nm, and the line pitch is about 30 nm. Other dimensions can be used for the layout shown in Figure 5A without departing from the scope of the present disclosure.

[0103] Figure 5B is a top view of wafer 102 after a particle bombardment process has been performed Figure 5A . Particle bombardment process has the effect of reducing end-to-end separation distance D E between trenches 154. Edge-to-edge separation distance D S and line spacing P L are substantially unchanged. Particle bombardment process has the effect of making end-to-end separation distance D E a data value less than or equal to edge-to-edge separation distance D S . Alternatively, end-to-end separation distance D E may still be slightly greater than edge-to-edge separation distance D S .

[0104] In one example, after particle bombardment process, end-to-end separation distance D E is about 14 nm, edge-to-edge separation distance D S is about 14 nm, and line spacing P L is about 30 nm. Other dimensions can be achieved with particle bombardment process without departing from the scope of the present disclosure.

[0105] Figure 6A and Figure 6B shows use of multiple particle bombardment processes according to some embodiments. In Figure 6A , an initial photolithography process is shown according to some embodiments. Photolithography process includes patterning trenches 154 in a layer of photoresist 152. In Figure 6A , a first particle bombardment process is performed. During first particle bombardment process, wafer 102 is bombarded with particles having a first energy, a first angle relative to vertical, and a first dose (or elapsed time). Ion characteristics of first particle bombardment process can be selected so that end-to-end separation distance D E changes little or not at all. Characteristics of first particle bombardment process can be selected to prepare photoresist 152 for a second particle bombardment process.

[0106] In Figure 6B , a second step of a particle bombardment process is performed. In second step of particle bombardment process, wafer 102 is bombarded with particles having a second energy, a second angle relative to vertical, and a second dose (or elapsed time). Ion characteristics of second particle bombardment step can be selected to significantly reduce end-to-end separation distance D E . During second particle bombardment step, one or more of second energy, second angle, and second dose (or elapsed time) is different from first energy, first angle, and first dose (or elapsed time). The result of combining first and second particle bombardment processes is that end-to-end separation distance D Erelative to the end-to-end separation distance D prior to the first and second particle bombardment processes E greatly reduced.

[0107] The particle bombardment system 108 bombards the wafer 102 with particles in multiple steps. In a first particle bombardment step, the particles are output from the particle bombardment system 108 toward the wafer 102 at an angle relative to the vertical, with an energy and a dose level. In a subsequent second particle bombardment step, one or more aspects of the ion beam are changed relative to the first particle bombardment step. Thus, in the second particle bombardment step, one or more of the angle of travel, the energy, or the dose level of the ion beam is changed relative to the first particle bombardment step. Having two particle bombardment steps with different characteristics makes for more effective reduction of the width of the remaining photoresist features compared to the case where only a single particle bombardment step is performed, or the second particle bombardment step and the first particle bombardment step are the same.

[0108] In one example, in the first particle bombardment step, the particles are output toward the wafer 102 at a first angle relative to the vertical. In the subsequent second particle bombardment step, the particles are output toward the wafer 102 at a second angle different from the first angle. This combination of different particle bombardment angles reduces the effects of shadowing and makes for effective photoresist removal. Shadowing can reduce the effectiveness of the particle bombardment process.

[0109] In one example, in the first particle bombardment step, the particles are output toward the wafer 102 at a first energy. In the subsequent second particle bombardment step, the particles are output toward the wafer 102 at a second energy different from the first energy. This combination of different particle bombardment energies reduces hardening and results in effective photoresist removal. The energy of an ion corresponds to the kinetic energy of the ion. For two particles of the same mass, an ion with more energy will have a higher velocity than an ion with less energy.

[0110] In one example, in the first particle bombardment step, a first dose of particles is output from the particle bombardment system 108 to the wafer 102. In the subsequent second particle bombardment step, a second dose of particles different from the first dose is output from the particle bombardment system 108 to the wafer 102. As used herein, a dose corresponds to the number of particles that bombard the wafer 102 in a given particle bombardment step. A higher particle bombardment dose corresponds to a greater number of particles that bombard the wafer 102. If the number of particles per second is constant for both particle bombardment steps, a higher dose can correspond to a longer time period in which the wafer 102 is bombarded.

[0111] In practice, two particle bombardment steps will be performed for each side of the photoresist structure. If the photoresist structure is considered to be a vertical wall having two perpendicular sides and a top surface, in one embodiment, the two particle bombardment steps will be performed first on one perpendicular side and then on the other perpendicular side. Thus, after the two particle bombardment steps have been performed on the first perpendicular side, the two particle bombardment steps will then be performed on the second perpendicular side. To accomplish this, after the first two particle bombardment steps, the wafer 102 is rotated 180° in the X-Y plane. The last two particle bombardment steps are then performed after the rotation.

[0112] In one embodiment, a first particle bombardment step is performed first on a first perpendicular side of the photoresist structure. The wafer is then rotated 180° in the X-Y plane and the first particle bombardment step is then performed on a second perpendicular side of the photoresist structure. A second particle bombardment step is then performed on the second perpendicular side of the photoresist structure. The wafer is then rotated 180° in the X-Y plane and the second particle bombardment step is performed on the first perpendicular side of the photoresist structure.

[0113] Figure 7A is a cross-sectional view of a wafer 102 at an intermediate processing stage according to some embodiments. In Figure 7A the layer of photoresist 152 has been patterned to form a mask in a first lithography process. The patterning process forms a plurality of trenches 154 in the photoresist 152. A mask is formed on the substrate 150. The substrate 150 can include a plurality of layers.

[0114] In Figure 7A the substrate 150 includes a first layer 164, a second layer 166, a third layer 168, and a fourth layer 170. In one example, the layer 164 includes tetraethyl orthosilicate (TEOS), the layer 166 includes titanium nitride, the layer 168 includes TEOS, and the layer 170 includes an organic polymer material or other type of dielectric layer. Other materials, number of layers, and layer combinations can be used for the substrate 150 without departing from the scope of the disclosure.

[0115] In Figure 7B a particle bombardment process is performed. The particle bombardment process removes material from the photoresist structure 152 that separates the trenches 154. The particle bombardment process has the effect of reducing the lateral width of the photoresist structure 152. In some embodiments, the particle bombardment process is performed on only one side of the photoresist structure 152. The particle bombardment process on a single side of the photoresist structure 152 can result in sufficient reduction of the width of the photoresist structure 152 such that a particle bombardment process on the other side of the photoresist structure 152 is not used. Alternatively, the particle bombardment process can be performed on both sides of the photoresist structure 152.

[0116] Figure 8A is an isometric view of wafer 102 after an initial photolithography process according to some embodiments. The photolithography process includes patterning trenches 154 in a layer of photoresist 152. Photoresist 152 is on a substrate 150. Substrate 150 can include silicon oxide or other materials. Alternatively, wafer 102 can include trenches 154 formed in a masking layer different from photoresist 152, or in a layer of photoresist 152, and in substrate 150. Substrate 150 can correspond to a hard mask layer.

[0117] In Figure 8B , a particle bombardment process is performed. Particles 162 bombard photoresist 152 at a non-normal angle as previously described. Figure 8C is a view of wafer 102 after the particle bombardment process has been performed. The particle bombardment process removes photoresist material and widens trenches 154. Trenches 154 maintain rounded ends after the particle bombardment process.

[0118] Figure 9 is an illustration of particle bombardment system 108 according to some embodiments. Particle bombardment system 108 is an ion bombardment system. Ion bombardment systems can correspond to similar systems as ion implantation systems. Ion bombardment systems are one example of particle bombardment system 108 that can be used with the processes, systems, and components described with respect to Figures 1-8B . Particle bombardment system 108 includes an ion source 172. The ion source emits a stream of ions 162. In one example, the ions are argon ions, but other types of particles can be used without departing from the scope of the present disclosure.

[0119] System 108 includes an ion selection magnet 174. The ion selection magnet changes the trajectory of particles 162 by establishing a magnetic field. Because particles 162 carry a net charge, the trajectory of particles 162 changes as particles 162 pass through the magnetic field. Particles with a particular mass-to-charge ratio will be successfully directed by the ion selection magnet into an ion selection aperture 176. Particles that do not carry a net charge will not be redirected by ion selection magnet 174. Particles that do not carry the selected mass-to-charge ratio will not be directed into ion selection aperture 176. Particle bombardment system 108 can include various apertures, filters, and equipment for directing the ribbon beam of ions 162 onto wafer 102.

[0120] The system 108 includes a wafer support 178. The wafer support 178 is configured to hold the wafer 102. The wafer support 178 can also be tilted, translated, and rotated. The tilt angle of the wafer support 178 defines the particle bombardment angle Θ. In other words, adjusting the tilt angle of the wafer support 178 corresponds to adjusting the particle bombardment angle Θ. The translation of the wafer support 178 corresponds to moving the wafer support 178 up or down or from left to right. The translation of the wafer support 178 enables different portions of the wafer 102 to be bombarded by particles. The rotation of the wafer support 178 enables opposite sides of the photoresist structure to be bombarded. For example, referring to Figure 3D and Figure 3E In Figure 3D , the particles bombard a first side 156 of the photoresist 152. In Figure 3E , the wafer support 178 rotates the wafer 180° so that the particles bombard a second side 158 of the photoresist 152. Other configurations of the particle bombardment system 108 can be used without departing from the scope of the present disclosure.

[0121] Figure 10 is a flowchart of a method 1000 according to some embodiments. The method 1000 can utilize the systems, processes, and structures described with respect to Figures 1-9 . At 1002, the method 1000 includes storing layout data associated with a first layout of a wafer. One example of layout data is the layout data 110 of Figure 1 . One example of a wafer is the wafer 102 of Figure 1 . At 1004, the method 1000 includes extracting feature data from the layout data that indicates a dimension associated with a feature of the first layout. One example of feature data is the feature data 116 of Figure 1 . At 1006, the method 1000 includes comparing the feature data to a selection rule. One example of a selection rule is the selection rule data 118 of Figure 1 . At 1008, the method 1000 includes selecting a non-normal particle bombardment process for implementing the layout in the wafer in response to the feature data satisfying the selection rule.

[0122] Figure 11 is a flowchart of a method 1100 according to some embodiments. The method 1100 can utilize the systems, processes, and structures described with respect to Figures 1-10 . At 1102, the method 1100 includes analyzing a layout associated with a wafer process. One example of a layout is the layout 108 of Figure 1of layout 112. At 1104, the method 1100 includes selecting, for the layout, a non- perpendicular particle bombardment process based on dimensions associated with features of the layout. At 1106, the method 1100 includes defining, in a mask on a wafer, first and second trenches according to a pattern of the layout using a lithography process. One example of the first and second trenches is Figure 3C trenches 154 of FIG. 1. One example of the mask is Figure 3C photoresist 152 of FIG. 1. One example of the wafer is Figure 1 wafer 102 of FIG. 1. At 1108, the method 1100 includes adjusting dimensions of the first and second trenches by performing a non-perpendicular particle bombardment process on the wafer.

[0123] Embodiments of the present disclosure provide a semiconductor processing system that selects between different patterning processes for each of a plurality of layouts to be used in processing a semiconductor wafer. The semiconductor processing system includes a layout database and a layout analyzer. The layout database includes layout data associated with various stages of semiconductor processing. The layout analyzer analyzes a distribution and dimensions of features associated with each layout. The layout analyzer compares the layout feature data to selection rule data. The selection rule data determines whether to use a non-perpendicular particle bombardment process in addition to a lithography process to define features associated with the layout. If a non-perpendicular particle bombardment process is selected for the layout, the layout is adjusted to reduce dimensions between some features.

[0124] Layout analysis and process selection has various benefits. For example, a non- perpendicular ion bombardment process can be used to overcome pattern scaling limitations of a lithography process. The result is that the layout is improved, layout features are correctly and reliably transferred to the wafer, and wafer yield is increased.

[0125] In some embodiments, a method includes storing layout data associated with a first layout of a wafer and extracting, from the layout data, feature data indicative of dimensions associated with features of the first layout. The method includes comparing the feature data to a selection rule and, in response to the feature data satisfying the selection rule, selecting a non-perpendicular particle bombardment process for implementing the first layout in the wafer.

[0126] In some embodiments, a method includes analyzing a layout associated with wafer processing and selecting, for the layout, a non-perpendicular particle bombardment process based on dimensions associated with features of the layout. The method includes defining, in a mask on a wafer, first and second trenches according to a pattern of the layout using a lithography process and adjusting dimensions of the first and second trenches by performing a non-perpendicular particle bombardment process on the wafer.

[0127] In some embodiments, a device includes a substrate, a first metal line extending in a first direction in the substrate and having a first rounded end, and a second metal line extending in the first direction in the substrate in line with the first metal line and having a second rounded end separated from the first rounded end by an end-to-end separation distance. The device includes a third metal line extending in the first direction in the substrate and separated from the first metal line by a side-to-side separation distance in a second direction perpendicular to the first direction, the side-to-side separation distance being greater than or equal to the end-to-end separation distance.

[0128] The foregoing summary has outlined rather broadly the features of several embodiments in order that the detailed description can be better understood and in order that the present disclosure can be better appreciated. Those skilled in the art will appreciate that they can readily use the conception and the specific embodiments disclosed as a basis for design or modification of other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments presented in this document. Those skilled in the art will realize and / or appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

[0129] Example 1 is a semiconductor processing method comprising: storing layout data associated with a first layout of a wafer; extracting feature data indicative of a dimension associated with a feature of the first layout from the layout data; comparing the feature data to a selection rule; and responsive to the feature data satisfying the selection rule, selecting a non- perpendicular particle bombardment process for use in implementing the first layout in the wafer.

[0130] Example 2 is the method of Example 1, further comprising: adjusting the first layout responsive to selecting the non-perpendicular particle bombardment process.

[0131] Example 3 is the method of Example 2, further comprising: adjusting a second layout corresponding to a wafer processing stage preceding or following the first layout responsive to selecting the non-perpendicular particle bombardment process for the first layout.

[0132] Example 4 is the method of Example 2, wherein adjusting the first layout comprises bringing a first conductive via location and a second conductive via location closer together.

[0133] Example 5 is the method of Example 1, wherein the selection rule comprises a threshold end-to-end separation distance for adjacent layout features aligned with each other in a first direction.

[0134] Example 6 is the method of example 1, wherein the selectivity rule comprises a threshold edge-to-edge separation distance for adjacent layout features that extend in a first direction and are separated from each other in a second direction, the second direction being perpendicular to the first direction.

[0135] Example 7 is the method of example 1, wherein the non-normal particle bombardment process is a directional plasma etch process.

[0136] Example 8 is the method of example 1, wherein the non-normal particle bombardment process is an ion bombardment process.

[0137] Example 9 is a method of semiconductor processing, comprising: analyzing a layout associated with a wafer process; selecting, for the layout, a non-normal particle bombardment process based on dimensions associated with features of the layout; defining, according to a pattern of the layout, a first trench and a second trench in a mask on a wafer with a lithography process; and adjusting dimensions of the first trench and the second trench by performing the non-normal particle bombardment process on the wafer.

[0138] Example 10 is the method of example 9, wherein the non-normal particle bombardment process comprises reducing an end-to-end separation distance between an end of the first trench and an end of the second trench by bombarding the wafer with particles at a non-normal angle.

[0139] Example 11 is the method of example 10, wherein the end of the first trench and the end of the second trench are circular prior to the non-normal particle bombardment process.

[0140] Example 12 is the method of example 11, wherein the end of the first trench and the end of the second trench are circular after the non-normal particle bombardment process.

[0141] Example 13 is the method of example 10, further comprising: extending the first trench and the second trench down into a substrate below the mask by performing an etch process; and forming a first metal line in the first trench in the substrate and a second metal line in the second trench in the substrate by depositing a conductive material in the first trench and the second trench in the substrate.

[0142] Example 14 is the method of example 13, wherein the first metal line comprises a circular end and the second metal line comprises a circular end, wherein the circular end of the first metal line is separated from the circular end of the second metal line in a first direction by the end-to-end separation distance.

[0143] Example 15 is the method of example 14, wherein the first metal line is separated from a third metal line adjacent to the first metal line in a second direction by an edge-to-edge separation distance, the edge-to-edge separation distance being greater than or equal to the end-to-end separation distance, the second direction being perpendicular to the first direction.

[0144] Example 16 is the method of example 15, wherein the end-to-end separation distance is less than or equal to 15 nm.

[0145] Example 17 is the method of example 9, wherein the mask comprises photoresist.

[0146] Example 18 is a semiconductor device comprising: a substrate; a first metal line extending in a first direction in the substrate and having a first rounded end; a second metal line extending in the first direction in the substrate in line with the first metal line and having a second rounded end separated from the first rounded end by an end-to-end separation distance; and a third metal line extending in the first direction in the substrate and separated from the first metal line in a second direction by an edge-to-edge separation distance, the edge-to-edge separation distance being greater than or equal to the end-to-end separation distance, the second direction being perpendicular to the first direction.

[0147] Example 19 is the device of example 18, wherein the end-to-end separation distance is less than or equal to 15 nm.

[0148] Example 20 is the device of example 19, wherein the first metal line comprises: a width in the second direction; and an edge adjacent to the third metal line and extending in the first direction, wherein a minimum distance between the first rounded end and a point of convergence of a first line extending from the edge in the first direction and a second line extending from a tip of the first rounded end is greater than or equal to one quarter of the width of the first metal line.

Claims

1. A semiconductor processing method comprising: storing layout data associated with a first layout of a wafer; extracting, from the layout data, feature data indicating dimensions associated with features of the first layout; comparing the characteristic data with selection rules; In response to the characteristic data satisfying the selection rule, selecting a non-vertical particle bombardment process for implementing the first layout in the wafer; as well as The first layout is adjusted in response to selecting the non-vertical particle bombardment process, wherein adjusting the first layout includes moving a first conductive via location and a second conductive via location closer together.

2. The method according to claim 1, further comprising: In response to selecting the non-vertical particle bombardment process for the first layout, a second layout corresponding to a wafer processing stage before or after the first layout is adjusted.

3. The method according to claim 1, wherein The selection rule includes a threshold end-to-end separation distance for adjacent layout features aligned with each other in a first direction.

4. The method according to claim 1, wherein The selection rule includes a threshold edge-to-edge separation distance for adjacent layout features extending in a first direction and spaced apart from each other in a second direction, the second direction being perpendicular to the first direction.

5. The method according to claim 1, wherein The non-vertical particle bombardment process is a directional plasma etching process.

6. The method according to claim 1, wherein The non-vertical particle bombardment process is an ion bombardment process.

7. A semiconductor processing method comprising: analyzing layouts associated with wafer processing; selecting, for the layout, a non-vertical particle bombardment process based on dimensions associated with features of the layout; Defining a first trench and a second trench in a mask on a wafer using a photolithography process according to the pattern of the layout; as well as The sizes of the first trench and the second trench are adjusted by performing the non-vertical particle bombardment process on the wafer, wherein adjusting the sizes of the first trench and the second trench includes: moving the first trench and the second trench closer together.

8. The method according to claim 7, wherein: The non-perpendicular particle bombardment process includes reducing an end-to-end separation distance between an end of the first trench and an end of the second trench by bombarding the wafer with particles at a non-perpendicular angle.

9. The method according to claim 8, wherein Ends of the first trench and ends of the second trench are rounded before the non-vertical particle bombardment process.

10. The method according to claim 9, wherein: Ends of the first trench and ends of the second trench are rounded after the non-vertical particle bombardment process.

11. The method according to claim 8, further comprising: extending the first trench and the second trench downward into the substrate beneath the mask by performing an etching process; as well as A first metal line is formed in the first trench in the substrate and a second metal line is formed in the second trench in the substrate by depositing a conductive material in the first trench and the second trench in the substrate.

12. The method according to claim 11, wherein The first metal wire includes a rounded end and the second metal wire includes a rounded end, wherein the rounded end of the first metal wire is separated from the rounded end of the second metal wire by the end-to-end separation distance in a first direction.

13. The method according to claim 12, wherein: The first metal line is separated from a third metal line adjacent to the first metal line by an edge-to-edge separation distance in a second direction that is perpendicular to the first direction. The edge-to-edge separation distance is greater than or equal to the end-to-end separation distance.

14. The method according to claim 13, wherein The end-to-end separation distance is less than or equal to 15 nm.

15. The method according to claim 7, wherein: The mask includes photoresist.

16. A semiconductor device manufactured according to the method of claim 1, comprising: substrate; a first metal line extending in a first direction in the substrate and having a first rounded end; a second metal line extending in the substrate in the first direction in a straight line with the first metal line and having a second rounded end separated from the first rounded end by an end-to-end separation distance, wherein the end-to-end separation distance is less than or equal to 15 nm; as well as A third metal line extends in the substrate in the first direction and is separated from the first metal line by an edge-to-edge separation distance in a second direction, the edge-to-edge separation distance being greater than or equal to the end-to-end separation distance, the second direction being perpendicular to the first direction.

17. The device according to claim 16, wherein The first metal wire includes: width, in the second direction; and an edge adjacent to the third metal line and extending in the first direction, wherein a minimum distance between the first rounded end and a point of convergence of a first line extending from the edge in the first direction and a second line extending from a tip of the first rounded end is greater than or equal to one quarter of the width of the first metal line.

Images