Semiconductor structure and preparation method, peripheral circuit, memory and storage system

Abstract

The present application provides a semiconductor structure and a preparation method thereof, a peripheral circuit, a memory and a storage system. The preparation method comprises: forming a substrate including a first well region and a second well region; forming a first gate oxide layer above the first well region, forming a second gate oxide layer above the second well region, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer in a first direction perpendicular to the substrate; covering the first gate oxide layer and the second gate oxide layer with a gate layer; removing part of the gate layer to form a first gate located in the first well region and a second gate located in the second well region, wherein the top of the first gate and the top of the second gate are located at different heights in the first direction, and the first gate and the second gate have the same height. The preparation method can reduce the defects that may occur in the process of forming high and low voltage gates, improve the consistency of the high and low voltage gates in terms of sidewall morphology and height, and thus improve the yield and reliability of semiconductor devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for preparing a semiconductor structure, a peripheral circuit, a memory, and a storage system. Background Art

[0002] As one of the core components of the three-dimensional memory, the peripheral circuit is mainly used for logical operations and to control and detect the switching state of each storage unit in the three-dimensional storage unit through metal connections to realize data storage and reading.

[0003] The peripheral circuit includes a large number of peripheral high-voltage devices and a large number of low-voltage logic devices. For example, the peripheral circuit may include an analog circuit composed of HVMOS (High Voltage Metal Oxide Semiconductor) devices and LVMOS (Low Voltage Metal Oxide Semiconductor) devices. Peripheral high-voltage devices can usually adopt symmetrical or asymmetrical double-diffused MOS devices, and in order to improve the reading and writing speed, the peripheral circuit also needs to run faster low-voltage devices, which requires the low-voltage logic devices (for example, the intelligent control circuit of the microprocessor MCU, etc.) and the high-voltage devices (for example, analog or high-voltage circuits, etc.) to be integrated on a chip. Summary of the invention

[0004] The present application provides a semiconductor structure and a method for preparing the same, a peripheral circuit, a memory, and a storage system that can at least partially solve the problems existing in the related art or other problems in the art.

[0005] On the one hand, the present application provides a method for preparing a semiconductor structure, the method comprising: forming a substrate including a first well region and a second well region; forming a first gate oxide layer above the first well region and a second gate oxide layer above the second well region, wherein in a first direction perpendicular to the substrate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer; covering the first gate oxide layer and the second gate oxide layer with a gate layer; and removing part of the gate layer to form a first gate located in the first well region and a second gate located in the second well region, wherein in the first direction, the top of the first gate and the top of the second gate are located at different heights, and the first gate and the second gate have the same height.

[0006] In one embodiment of the present application, the sidewall of the first gate and the sidewall of the second gate have the same morphology.

[0007] In one embodiment of the present application, in the first direction, a bottom of the first gate and a bottom of the second gate are located at different heights.

[0008] In one embodiment of the present application, a sidewall of the first gate is perpendicular to the substrate in the first direction.

[0009] In one embodiment of the present application, a sidewall of the second gate is perpendicular to the substrate in the first direction.

[0010] In one embodiment of the present application, the morphology parameter value of the side wall of the first gate is less than or equal to the morphology threshold of the side wall of the first gate, wherein the morphology parameter value of the side wall of the first gate includes: an angle value between a portion of the side wall of the first gate close to the substrate and the substrate and at least one of a local surface flatness of a portion of the side wall of the first gate close to the substrate.

[0011] In one embodiment of the present application, the morphology parameter value of the side wall of the second gate is less than or equal to the morphology threshold of the side wall of the second gate, wherein the morphology parameter value of the side wall of the second gate includes: at least one of an angle value between a portion of the side wall of the second gate close to the substrate and the substrate and a local surface flatness of a portion of the side wall of the second gate close to the substrate.

[0012] In one embodiment of the present application, forming a first gate oxide layer above the first well region and forming a second gate oxide layer above the second well region includes: forming an initial sacrificial layer on the substrate; removing a portion of the initial sacrificial layer above the first well region to form a sacrificial layer; forming the first gate oxide layer above the first well region; removing the sacrificial layer and forming the second gate oxide layer above the second well region.

[0013] In one embodiment of the present application, removing part of the gate layer includes: before removing part of the gate layer, forming a mask layer on the gate layer; transferring the pattern of the photolithography mask to the mask layer using a photolithography process; and using the patterned mask layer as a mask to remove part of the gate layer using anisotropic etching, wherein the gate layer has an etching selectivity ratio greater than a set value relative to the mask layer, so as to retain the gate layer during the process of forming the patterned mask layer.

[0014] In one embodiment of the present application, the method further includes: forming a mask layer on the gate layer before removing a portion of the gate layer; forming an initial composite layer on the mask layer; and flattening the initial composite layer to form a flatness adjustment layer; and after removing a portion of the gate layer, removing the mask layer and the flatness adjustment layer.

[0015] In one embodiment of the present application, the flatness adjustment layer includes a silicon oxynitride layer and a spin-on carbon layer.

[0016] In one embodiment of the present application, after forming the first gate oxide layer and the second gate oxide layer on the substrate, the method further includes: forming an isolation structure in the substrate, wherein the first well region includes a plurality of high-voltage wells of different doping types, the second well region includes a plurality of low-voltage wells of different doping types, and the isolation structure is formed between each of the high-voltage wells, between each of the low-voltage wells, and between the high-voltage well and the low-voltage well.

[0017] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, and the method also includes: forming a first groove in the first well region, and forming a first insulating dielectric layer in the first groove to form the first isolation structure, wherein the thickness of the first insulating dielectric layer in the first direction is greater than the depth of the first groove in the first direction; and forming a second groove in the second well region, and forming a second insulating dielectric layer in the second groove to form the second isolation structure, wherein the thickness of the second insulating dielectric layer in the first direction is less than the depth of the second groove in the first direction.

[0018] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, and the method also includes: forming a first groove in the first well region, and forming a first insulating dielectric layer in the first groove to form the first isolation structure, wherein the thickness of the first insulating dielectric layer in the first direction is less than the depth of the first groove in the first direction; and forming a second groove in the second well region, and forming a second insulating dielectric layer in the second groove to form the second isolation structure, wherein the thickness of the second insulating dielectric layer in the first direction is greater than the depth of the second groove in the first direction.

[0019] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, and the method also includes: forming a first groove in the first well region, and forming a first insulating dielectric layer in the first groove to form the first isolation structure, wherein the thickness of the first insulating dielectric layer in the first direction is less than the depth of the first groove in the first direction; and forming a second groove in the second well region, and forming a second insulating dielectric layer in the second groove to form the second isolation structure, wherein the thickness of the second insulating dielectric layer in the first direction is less than the depth of the second groove in the first direction.

[0020] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, and the method also includes: forming a first groove in the first well region, and forming a first insulating dielectric layer in the first groove to form the first isolation structure, wherein the thickness of the first insulating dielectric layer in the first direction is greater than the depth of the first groove in the first direction; and forming a second groove in the second well region, and forming a second insulating dielectric layer in the second groove to form the second isolation structure, wherein the thickness of the second insulating dielectric layer in the first direction is greater than the depth of the second groove in the first direction.

[0021] On the other hand, the present application provides a semiconductor structure prepared based on the above method, the semiconductor structure comprising: a substrate, comprising a first well region and a second well region; a first gate oxide layer, located on the first well region; a second gate oxide layer, located on the second well region; a first gate, located on the first gate oxide layer; and a second gate, located on the second gate oxide layer, wherein in a first direction perpendicular to the substrate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the top of the first gate and the top of the second gate are located at different heights, and the first gate and the second gate have the same height.

[0022] In one embodiment of the present application, a sidewall of the first gate is perpendicular to the substrate in the first direction.

[0023] In one embodiment of the present application, a sidewall of the second gate is perpendicular to the substrate in the first direction.

[0024] In one embodiment of the present application, the sidewall of the first gate and the sidewall of the second gate have the same morphology.

[0025] In one embodiment of the present application, the morphology parameter value of the side wall of the first gate is less than or equal to the morphology threshold of the side wall of the first gate, wherein the morphology parameter value of the side wall of the first gate includes: an angle value between a portion of the side wall of the first gate close to the substrate and the substrate and at least one of a local surface flatness of a portion of the side wall of the first gate close to the substrate.

[0026] In one embodiment of the present application, the morphology parameter value of the side wall of the second gate is less than or equal to the morphology threshold of the side wall of the second gate, wherein the morphology parameter value of the side wall of the second gate includes: at least one of an angle value between a portion of the side wall of the second gate close to the substrate and the substrate and a local surface flatness of a portion of the side wall of the second gate close to the substrate.

[0027] In one embodiment of the present application, the semiconductor structure also includes an isolation structure located in the substrate, wherein the first well region includes a plurality of high-voltage wells of different doping types, the second well region includes a plurality of low-voltage wells of different doping types, and the isolation structure is located between each of the high-voltage wells, between each of the low-voltage wells, and between the high-voltage well and the low-voltage well.

[0028] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, wherein the semiconductor structure also includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is greater than the depth of the first groove in the first direction; and the semiconductor structure also includes a second groove located in the second well region, the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is less than the depth of the second groove in the first direction.

[0029] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, wherein the semiconductor structure also includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is less than the depth of the first groove in the first direction; and the semiconductor structure also includes a second groove located in the second well region, the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is greater than the depth of the second groove in the first direction.

[0030] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, wherein the semiconductor structure also includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is less than the depth of the first groove in the first direction; and the semiconductor structure also includes a second groove located in the second well region, the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is less than the depth of the second groove in the first direction.

[0031] In one embodiment of the present application, the isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, wherein the semiconductor structure also includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is greater than the depth of the first groove in the first direction; and the semiconductor structure also includes a second groove located in the second well region, the second isolation structure includes and fills the second insulating dielectric layer in the second groove, and the thickness of the second insulating dielectric layer in the first direction is greater than the depth of the second groove in the first direction.

[0032] On the other hand, the present application provides a peripheral device, which includes a semiconductor structure, and the semiconductor structure is prepared by any method for preparing a semiconductor structure provided in one aspect of the present application or any semiconductor structure provided in another aspect of the present application.

[0033] Another aspect of the present application provides a three-dimensional memory, which includes any peripheral device as provided in another aspect of the present application, and a storage array device coupled to the peripheral device.

[0034] Another aspect of the present application provides a storage system, which includes a controller and any one of the three-dimensional memories provided in the other aspect of the present application, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0036] Figure 1 is a schematic diagram of the structure of a storage system according to an embodiment of the present application;

[0037] Figure 2A is a partial cross-sectional schematic diagram of a memory according to an embodiment of the present application;

[0038] Figure 2B is a partial cross-sectional schematic diagram of a peripheral circuit according to an embodiment of the present application;

[0039] Figures 3 to 6 is a schematic diagram of an exemplary process of forming a first gate and a second gate corresponding to a first well region and a second well region in a semiconductor structure;

[0040] Figure 7 is a flow chart of a method for preparing a semiconductor structure according to one embodiment of the present application;

[0041] Figure 8 is a schematic cross-sectional view of a structure formed after an initial gate layer is formed on a substrate according to a preparation method of an embodiment of the present application;

[0042] Figures 9 to 12 They are schematic cross-sectional views of a structure formed after a first gate oxide layer and a second gate oxide layer are formed on a substrate according to a preparation method in one embodiment of the present application;

[0043] Fig.13 is a schematic cross-sectional view of a structure formed after forming an initial composite layer according to a preparation method in one embodiment of the present application; and

[0044] Fig.14 It is a cross-sectional schematic diagram of a structure formed after forming a first gate and a second gate according to a preparation method in one embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first gate discussed in this application may also be referred to as the second gate, the first well region may also be referred to as the second well region, and vice versa.

[0047] In the drawings, the widths, sizes and shapes of components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0048] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0049] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0050] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0051] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0052] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0053] Figure 1 FIG. 1 is a schematic diagram of the structure of a storage system 1 according to an embodiment of the present application. Figure 1 As shown, the storage system 1 may include a controller 3 and at least one three-dimensional memory 2, and the controller 3 is coupled to the three-dimensional memory 2 to control the storage data of the three-dimensional memory 2. The storage system 1 can be integrated into a variety of memory cards such as personal computer memory card international association (PCMCIA or PC), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD), universal flash storage (UFS) and solid state drives (SSD).

[0054] The controller 3 may be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0055] Furthermore, the controller 3 may also be configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablet computers, laptop computers, and enterprise storage arrays.

[0056] As an option, the controller 3 may also be configured to manage the data stored in the three-dimensional memory 2 and communicate with the external device according to a specific communication protocol. The communication protocol may include at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-E (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a firewire protocol.

[0057] In addition, the controller 3 may be further configured to control the operation of the three-dimensional memory 2, such as read, erase, and program operations. In some embodiments, the controller 3 may be further configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 2, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 3 may be further configured to process error correction codes regarding data read from or written to the three-dimensional memory 2. In addition, the controller 3 may also perform any other suitable functions, such as formatting the three-dimensional memory 2.

[0058] Figure 2A It is a cross-sectional schematic diagram of a memory 2 according to an embodiment of the present application. Figure 2B is a partial cross-sectional schematic diagram of a peripheral circuit 10 according to an embodiment of the present application.

[0059] like Figure 2A and Figure 2B As shown, the three-dimensional memory 2 may include a peripheral device 10 and a memory array device 20. The peripheral device 10 and the memory array device 20 may be electrically connected to implement the peripheral device 10 to support the memory array device 20, such as reading, writing and erasing data of a memory cell.

[0060] The memory array device 20 may include a memory cell string array 21 and an array interconnect layer 22. The array interconnect layer 22 is disposed on a side of the memory cell string array 21 close to the peripheral device 10, and the memory cell string array 21 and the array interconnect layer 22 may be electrically connected. The peripheral device 10 may include a peripheral circuit 11 and a peripheral interconnect layer 12. The peripheral interconnect layer 12 is disposed on a side of the peripheral circuit 11 close to the memory array device 20, and the peripheral circuit 11 may be electrically connected to the peripheral interconnect layer 12. The memory array device 20 and the peripheral device 10 may be electrically connected through the array interconnect layer 22 and the peripheral interconnect layer 12, so that the memory cell string array 21 and the peripheral circuit 11 are electrically connected.

[0061] The peripheral device 10 includes a peripheral circuit in the three-dimensional memory 2 for controlling and detecting the switch state of each storage cell string array 21 and realizing data storage and reading. Optionally, the peripheral device 10 can be a peripheral circuit near cell (PNC) architecture, a peripheral circuit under cell (PUC) architecture or an inverted X-tacking peripheral circuit architecture, which is not limited in the embodiment of the present application.

[0062] As an option, the peripheral device 10 may include a peripheral circuit 11 such as a page buffer, a decoder, a sense amplifier, a driver, a charge pump, a current or voltage reference, etc. The peripheral circuit 11 may include a semiconductor structure 100 (eg, Figure 2B As shown), the specific structure of the semiconductor structure 100 will be described in detail below.

[0063] Figures 3 to 6 1 is a schematic diagram of an exemplary process of forming a first gate 141 and a second gate 142 corresponding to a first well region 101 and a second well region 102 in a semiconductor structure 100 .

[0064] like Figures 3 to 6 As shown, semiconductor structure 100 may include substrate 110, first gate oxide layer 121, second gate oxide layer 122, first gate 141 and second gate 142. Due to the particularity of memory chips, substrate 110 may include first well region 101 and second well region 102 different from first well region 101.

[0065] Specifically, Figure 3As shown, in one embodiment of the present application, the first well region 101 may be a high voltage (High Voltage, HV) well region, and the second well region 102 may be a low voltage (Low Voltage, LV) well region, wherein the high voltage well region may be understood as a semiconductor device formed in this region having a turn-on voltage or a threshold voltage greater than 5 volts; the low voltage well region may be understood as a semiconductor device formed in this region having a turn-on voltage or a threshold voltage less than or equal to 5 volts.

[0066] As an option, the first well region 101 may include a high voltage well region and an ultra-high voltage well region, and the second well region 102 may include a low voltage well region and an ultra-low voltage (LLV) well region. Optionally, the ultra-low voltage well region may be understood as a semiconductor device formed in the region whose turn-on voltage or threshold voltage is less than or equal to 1.6 volts.

[0067] In one embodiment of the present application, the first well region 101 may include a plurality of high-voltage wells of doping types, wherein the plurality of high-voltage wells may have the same doping type, for example, the plurality of high-voltage wells are all P-type doped, or the plurality of high-voltage wells are all N-type doped; in addition, the plurality of high-voltage wells may also have different doping types, for example, at least one of the plurality of high-voltage wells is P-type doped, and at least one of the plurality of high-voltage wells is N-type doped. Similarly, the second well region 102 may include a plurality of low-voltage wells of doping types, wherein the plurality of low-voltage wells may have the same doping type, for example, the plurality of low-voltage wells are all P-type doped, or the plurality of low-voltage wells are all N-type doped; in addition, the plurality of low-voltage wells may also have different doping types, for example, at least one of the plurality of low-voltage wells is P-type doped, and at least one of the plurality of low-voltage wells is N-type doped. Optionally, the P-type doping ions may be, for example, indium ions, boron ions, gallium ions, aluminum ions, boron fluoride ions, etc.; the N-type doping ions may be, for example, arsenic ions, phosphorus ions, antimony ions, etc. The present application does not limit the number, size, depth in the substrate, and doping type of the first well region and the second well region, and those skilled in the art may make any changes based on the embodiments of the present application.

[0068] A first gate oxide layer 121 is formed above the first well region 101; and a second gate oxide layer 122 is formed above the second well region 102. The thickness D1 of the first gate oxide layer 121 formed above the first well region 101 is different from the thickness D2 of the second gate oxide layer 122 formed above the second well region 102. Specifically, in the first direction (Z direction) perpendicular to the substrate 110, the thickness D1 of the first gate oxide layer 121 formed above the first well region 101 is greater than the thickness D2 of the second gate oxide layer 122 formed above the second well region 102. In other words, the thickness of the gate oxide layer above the high-voltage well region is greater than the thickness of the gate oxide layer above the low-voltage well region, and the thickness of the gate oxide layer is related to the turn-on voltage or threshold voltage of the semiconductor device formed in the region. In other words, the thickness of the gate oxide layer generally increases with the increase of the turn-on voltage or threshold voltage of the semiconductor device corresponding thereto.

[0069] In addition, an isolation structure (not shown) is also formed in the substrate 110. As an option, the isolation structure can be formed after the first gate oxide layer 121 and the second gate oxide layer 122 are formed; as another option, the first gate oxide layer 121 and the second gate oxide layer 122 can be formed after the isolation structure is formed.

[0070] After forming the isolation structure, the first gate oxide layer 121 and the second gate oxide layer 122, the initial gate layer 140 may be covered on the first gate oxide layer 121 and the second gate oxide layer 122. The initial gate layer 140 is used to form the first gate 141 and the second gate 142 (eg, Figure 6 As shown). Optionally, the initial gate layer 140 may be a semiconductor material layer, such as a polysilicon layer.

[0071] In such Figure 4 In the steps shown, the initial gate layer 140 may be subjected to a planarization process such as a buffer chemical mechanical polishing (Buffer CMP) process with a relatively low grinding rate, thereby obtaining a gate layer 140' having a flat surface 140'-1. The flattened surface 140'-1 is conducive to subsequent etching processes such as removing a portion of the gate layer 140' to form a first gate 141 (such as Figure 6 as shown) and the second gate 142 (as shown Figure 6 shown).

[0072] After the gate layer 140' is formed, a height difference Δh (in the Z direction) is formed between a portion of the gate layer 140' located on the first gate oxide layer 121 and a portion of the gate layer 140' located on the second gate oxide layer 122, wherein the height difference Δh can be understood as the difference between the thickness D1 of the first gate oxide layer 121 and the thickness D2 of the second gate oxide layer 122.

[0073] exist Figure 5 In the steps shown, a patterned mask layer 150 may be formed on the gate layer 140'. Optionally, the patterned mask layer 150 may be a composite structure, which may include a barrier layer and a photoresist (PR) layer located above the barrier layer, wherein the material forming the barrier layer may be silicon nitride or silicon oxynitride.

[0074] exist Figure 6 In the steps shown, a first gate 141 located in the first well region 101 and a second gate 142 located in the second well region 102 may be formed by, for example, an etching process.

[0075] However, reference Figure 4 and Figure 6 It can be seen that the morphology of the sidewalls of the first gate 141 and the second gate 142 formed by the above technical solution is not consistent, wherein the sidewalls can be understood as multiple surfaces of the first gate 141 or the second gate 142 perpendicular to the substrate 110 in an ideal state; in addition, each gate (for example, the first gate 141, the second gate 142) can include a bottom surface and a sidewall connected to the bottom surface, wherein the bottom surface is the surface of the gate in contact with the substrate 110. Therefore, the sidewall of the first gate 141 is the surface of the first gate 141 connected to its bottom surface; the sidewall of the second gate 142 is the surface of the second gate 142 connected to its bottom surface. Optionally, the sidewalls of the first gate 141 and the second gate 142 may include an uneven surface or a surface with an inclined angle relative to the Z direction, etc. Since a height difference Δh is formed between the portion of the gate layer 140' located on the first gate oxide layer 121 and the portion of the gate layer 140' located on the second gate oxide layer 122, after the above etching process, the first gate 141 located in the first well region 101 is prone to "over" etching due to the portion of its sidewall close to the substrate 110. Figure 6 The "side-digging" defect shown in the middle square dotted box is caused by the "under" etching of the second gate 142 located in the second well region 102, and the side wall of the second gate 142 near the substrate 110 is prone to Figure 6 The "bottom foot" defect shown in the dotted oval box. The above defects that may occur during the formation of high and low voltage gates will cause differences in the morphology of the side walls of the high and low voltage gates, resulting in a decrease in the yield and reliability of the final semiconductor device.

[0076] In addition, since a step Δh is formed between the portion of the gate layer 140' located on the first gate oxide layer 121 and the portion of the gate layer 140' located on the second gate oxide layer 122, the height H1 of the first gate 141 in the Z direction is not equal to the height H2 of the second gate 142 in the Z direction. Specifically, since the thickness of the second gate oxide layer 122 is less than the thickness of the first gate oxide layer 121, and in the Z direction, the top surface of the first gate oxide layer 121 and the top surface of the second gate oxide layer 122 are located at different heights, the height H2 of the second gate 142 is greater than the height H1 of the first gate 141. Similarly, the difference in height between the high and low voltage gates may reduce the yield and reliability of the semiconductor device finally formed.

[0077] In response to the above problems, at least one embodiment of the present application provides a semiconductor structure and preparation method, a peripheral circuit, a memory and a storage system, wherein no planarization treatment is performed after the gate layer is formed, and the high and low voltage gates are formed directly by removing part of the gate layer, which can reduce the defects that may occur in the process of forming the high and low voltage gates, thereby improving the consistency of the high and low voltage gates in side wall morphology and height, and improving the yield and reliability of semiconductor devices.

[0078] In addition, the method for preparing the semiconductor structure omits the planarization process of the gate layer, which can effectively reduce the cost of preparing the semiconductor structure, the manufacturing time, and the process difficulty of forming high and low voltage gates.

[0079] Figure 7 FIG. 1 is a flow chart of a method 1000 for preparing a semiconductor structure according to one embodiment of the present application. Figure 7 As shown, the method 1000 for preparing a semiconductor structure may include:

[0080] S1, forming a substrate including a first well region and a second well region.

[0081] S2, forming a first gate oxide layer on the first well region and forming a second gate oxide layer on the second well region, wherein in a first direction perpendicular to the substrate, a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer.

[0082] S3, covering the first gate oxide layer and the second gate oxide layer with a gate layer, and removing part of the gate layer to form a first gate located in the first well region and a second gate located in the second well region, wherein in a first direction, a top of the first gate and a top of the second gate are located at different heights, and the first gate and the second gate have the same height.

[0083] The following will be combined Figures 8 to 14 The specific process of each step of the above-mentioned preparation method 1000 is described in detail.

[0084] Step S1

[0085] Figure 8 It is a schematic cross-sectional view of a structure formed after an initial gate layer 140 is formed on a substrate 110 according to a preparation method in one embodiment of the present application.

[0086] like Figure 8 As shown, step S1 of forming a substrate including a first well region and a second well region may, for example, include: preparing a substrate 110 ; and forming a first well region 101 and a second well region 102 in the substrate 110 .

[0087] The material for preparing the substrate 110 may be various semiconductor materials well known to those skilled in the art, such as silicon substrate (Si), germanium substrate (Ge), silicon germanium substrate (SiGe), silicon on insulator (SOI) or germanium on insulator (GOI). Taking the silicon substrate as an example, the silicon substrate may include a single crystal silicon substrate, a polycrystalline silicon substrate, etc. The present application does not limit the material for preparing the substrate.

[0088] According to device design requirements, a plurality of predetermined regions (not shown), such as the first well region 101 and the second well region 102 , may be formed in the substrate 110 by processes such as furnace diffusion or ion implantation.

[0089] As an option, the first well region 101 may be a high-voltage well region, and the second well region 102 may be a low-voltage well region, wherein the high-voltage well region may be understood as a semiconductor device formed in this region having a turn-on voltage or a threshold voltage greater than 5 volts; and the low-voltage well region may be understood as a semiconductor device formed in this region having a turn-on voltage or a threshold voltage less than or equal to 5 volts.

[0090] As another option, the first well region 101 may include a high-voltage well region and an ultra-high-voltage well region, and the second well region 102 may include a low-voltage well region and an ultra-low-voltage well region. Optionally, the ultra-low-voltage well region may be understood as a semiconductor device having a turn-on voltage or a threshold voltage less than or equal to 1.6 volts formed in the region.

[0091] In addition, in one embodiment of the present application, the first well region 101 may include a plurality of high-voltage wells of doping types, wherein the plurality of high-voltage wells may have the same doping type, for example, the plurality of high-voltage wells are all P-type doped, or the plurality of high-voltage wells are all N-type doped; in addition, the plurality of high-voltage wells may also have different doping types, for example, at least one of the plurality of high-voltage wells is P-type doped, and at least one of the plurality of high-voltage wells is N-type doped. Similarly, the second well region 102 may include a plurality of low-voltage wells of doping types, wherein the plurality of low-voltage wells may have the same doping type, for example, the plurality of low-voltage wells are all P-type doped, or the plurality of low-voltage wells are all N-type doped; in addition, the plurality of low-voltage wells may also have different doping types, for example, at least one of the plurality of low-voltage wells is P-type doped, and at least one of the plurality of low-voltage wells is N-type doped. Optionally, the P-type doping ions may be, for example, indium ions, boron ions, gallium ions, aluminum ions, boron fluoride ions, etc.; the N-type doping ions may be, for example, arsenic ions, phosphorus ions, antimony ions, etc. The present application does not limit the number, size, depth in the substrate, and doping type of the first well region and the second well region. Those skilled in the art may make any changes based on the embodiments of the present application.

[0092] Step S2

[0093] like Figure 3 As shown, in one embodiment of the present application, step S2 of forming a first gate oxide layer on the first well region and forming a second gate oxide layer on the second well region may, for example, include: forming an initial gate oxide layer (not shown) on the surface of the substrate 110, wherein the thickness of the initial gate oxide layer is greater than or equal to a predetermined thickness of the first gate oxide layer 121; forming a protective layer (not shown) on a portion of the initial gate oxide layer opposite to the first well region 101; thinning a portion of the initial gate oxide layer opposite to the second well region 102 to form a second gate oxide layer 122; and removing the protective layer to form the first gate oxide layer 121.

[0094] Specifically, in this embodiment, a process such as Rapid Thermal Oxidation (RTO) or In-Situ Stream Generation (ISSG) can be used to form the initial gate oxide layer. Optionally, the initial gate oxide layer can be a silicon oxide layer. The thickness of the initial gate oxide layer is greater than or equal to the predetermined thickness of the first gate oxide layer 121, wherein the predetermined thickness of the first gate oxide layer 121 can be determined according to the characteristics of the semiconductor device to be formed by the first well region 101.

[0095] After the initial gate oxide layer is formed, a protective layer may be formed on the initial gate oxide layer, and the protective layer is located on the portion of the initial gate oxide layer opposite to the first well region 101. Optionally, the protective layer may be a photoresist layer (not shown), for example, the initial photoresist layer (not shown) may be formed on the initial gate oxide layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof; the portion of the initial photoresist layer located on the second well region 102 is removed by a process such as photolithography and development, to form a photoresist layer to expose the portion of the initial gate oxide layer located on the second well region 102.

[0096] After forming the protective layer, the thickness of the portion of the initial gate oxide layer opposite to the second well region 102 can be thinned by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed, until a predetermined thickness of the second gate oxide layer 122 is reached to form a second gate oxide layer 122, wherein the predetermined thickness of the second gate oxide layer 122 can be determined based on the characteristics of the semiconductor device to be formed by the second well region 102.

[0097] After the second gate oxide layer 122 is formed, the protection layer may be removed, and a portion of the initial gate oxide layer located below the protection layer may be trimmed using a process such as a planarization process to form the first gate oxide layer 121 .

[0098] The thickness of the gate oxide layer above the high-voltage well region is greater than the thickness of the gate oxide layer above the low-voltage well region. The thickness of the gate oxide layer is related to the turn-on voltage or threshold voltage of the semiconductor device formed in the region. The thicker the gate oxide layer, the greater the turn-on voltage or threshold voltage of the corresponding semiconductor device. Therefore, in this embodiment, in the first direction (Z direction) perpendicular to the substrate 110, the thickness D1 of the first gate oxide layer 121 formed in the first well region 101 is different from the thickness D2 of the second gate oxide layer 122 formed above the second well region 102.

[0099] Specifically, in the Z direction, the thickness D1 of the first gate oxide layer 121 is greater than the thickness D2 formed on the second gate oxide layer 122. In addition, since the substrate 110 has a flat top surface (which can be understood as the surface of the substrate 110 in contact with the first gate oxide layer 121 and the second gate oxide layer 122), through this embodiment, in the Z direction, the bottom surfaces of the first gate oxide layer 121 and the second gate oxide layer 122 formed on the flat top surface of the substrate 110 (which can be understood as the surface in contact with the substrate 110) are located at the same height; a step is formed between the top surfaces of the first gate oxide layer 121 and the second gate oxide layer 122 (which can be understood as the surface on which the subsequent gate layer 140 is formed), and the step is the difference between the thickness D1 of the first gate oxide layer 121 and the thickness D2 of the second gate oxide layer 122.

[0100] like Figure 4 As shown, in the subsequent steps, the gate layer 140 formed on the top surfaces of the first gate oxide layer 121 and the second gate oxide layer 122 also forms a step Δh between the portion located on the first gate oxide layer 121 and the portion located on the second gate oxide layer 122 due to the presence of the above-mentioned step. In this embodiment, the step of the gate layer 140 in the Z direction is approximately equal to the difference between the thickness D1 of the first gate oxide layer 121 and the thickness D2 of the second gate oxide layer 122. It is known to those skilled in the art that the term "equal to" should be understood as completely equal and slightly equal to or substantially equal to within the range of process or measurement errors.

[0101] In addition, if Figure 8 As shown, in another embodiment of the present application, in order to reduce the height difference of the above-mentioned gate layer 140 in the Z direction, so as to improve the consistency of the high and low voltage gates subsequently formed on the first gate oxide layer 121 and the second gate oxide layer 122 in terms of side wall morphology and height, step S2 forms a first gate oxide layer on the first well region and a second gate oxide layer on the second well region, which may, for example, include: forming an initial sacrificial layer (not shown) on the substrate 110; removing a portion of the initial sacrificial layer located above the first well region 101 to form a sacrificial layer (not shown); forming a first gate oxide layer 121 above the first well region 101; and removing the sacrificial layer and forming a second gate oxide layer 122 above the second well region 102.

[0102] Specifically, in the present embodiment, an initial sacrificial layer may be formed on the substrate 110 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The thickness of the initial sacrificial layer may be greater than or equal to a predetermined thickness of an initial gate oxide layer formed in a subsequent step.

[0103] After the initial sacrificial layer is formed, the portion of the initial sacrificial layer located above the first well region 101 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed to form a sacrificial layer and expose a portion of the top surface of the substrate 110 located in the first well region 101.

[0104] An initial gate oxide layer (not shown) is formed on the exposed portion of the top surface of the substrate 110 by a process such as thermal oxidation or in-situ steam generation. Alternatively, the initial gate oxide layer may be a silicon oxide layer. The predetermined thickness of the initial gate oxide layer is greater than or equal to the predetermined thickness of the first gate oxide layer 121, wherein the predetermined thickness of the first gate oxide layer 121 may be determined according to the characteristics of the semiconductor device to be formed in the first well region 101.

[0105] The thickness of the initial gate oxide layer can be thinned by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., until a predetermined thickness of the first gate oxide layer 121 is reached to form the first gate oxide layer 121.

[0106] The sacrificial layer can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can also be performed to expose a portion of the top surface of the substrate 110 located in the second well region 102.

[0107] A second gate oxide layer 122 is formed on the exposed portion of the top surface of the substrate 110 by using processes such as thermal oxidation and in-situ steam generation. Alternatively, the second gate oxide layer 122 may be a silicon oxide layer. The predetermined thickness of the second gate oxide layer 122 may be determined according to the characteristics of the semiconductor device to be formed in the second well region 102.

[0108] like Figure 8 As shown, in the present embodiment, the first gate oxide layer 121 and the second gate oxide layer 122 are formed in different steps by using processes such as thermal oxidation and in-situ steam generation. Since the thickness D1 of the first gate oxide layer 121 formed above the first well region 101 is greater than the thickness D2 of the second gate oxide layer 122 formed above the second well region 102, during the process of forming the first gate oxide layer 121 and the second gate oxide layer 122, a first portion of the substrate 110 located below the first gate oxide layer 121 is consumed relatively more in the process, and a second portion of the substrate 110 located below the second gate oxide layer 122 is consumed relatively less in the process.

[0109] In other words, in this embodiment, the bottom surfaces of the first gate oxide layer 121 and the second gate oxide layer 122 (which can be understood as the surface in contact with the substrate 110) are located at different heights in the Z direction, wherein the bottom surface of the first gate oxide layer 121 is lower than the bottom surface of the second gate oxide layer 122 in the Z direction, and there is a difference h1 between the two. Therefore, although a step is formed between the top surfaces of the first gate oxide layer 121 and the second gate oxide layer 122 (which can be understood as the surface on which the subsequent gate layer 140 is formed), the step is less than the difference Δh between the thickness D1 of the first gate oxide layer 121 and the thickness D2 of the second gate oxide layer 122 (such as Figure 4 shown).

[0110] By reducing the height difference between the top surfaces of the first gate oxide layer 121 and the second gate oxide layer 122, in subsequent steps, the height difference in the Z direction between different parts of the gate layer 140 formed on the top surfaces of the first gate oxide layer 121 and the second gate oxide layer 122 can be reduced accordingly, so that the height difference is less than the difference Δh, which is approximately equal to the difference between the difference Δh and the difference h1. By reducing the height difference in the Z direction between different parts of the gate layer 140, in the subsequent process of forming high and low voltage gates in the gate layer by, for example, an etching process, "over" etching and "under" etching can be effectively reduced, thereby facilitating the improvement of the consistency of the high and low voltage gates in terms of sidewall morphology and height.

[0111] In addition, refer again Figure 8 , the semiconductor structure 100 also includes an isolation structure, such as a first isolation structure 131 located in the first well region 101 and a second isolation structure 132 located in the second well region 102. The isolation structure is used to isolate the active area (AA) in the substrate 110, and is also used to isolate the first well region 101 and the second well region 102. Optionally, the isolation structure may be a shallow trench isolation structure (STI). In other words, the first well region 101 includes a plurality of high-voltage wells of different doping types, the second well region 102 includes a plurality of low-voltage wells of different doping types, and the isolation structure is formed between each high-voltage well, between each low-voltage well, and between the high-voltage well and the low-voltage well.

[0112] In one embodiment of the present application, the isolation structure may be formed after the first gate oxide layer 121 and the second gate oxide layer 122 are formed; alternatively, the first gate oxide layer 121 and the second gate oxide layer 122 may be formed after the isolation structure is formed.

[0113] After forming the first gate oxide layer 121 and the second gate oxide layer 122, an isolation structure is formed. The first gate oxide layer 121 and the second gate oxide layer 122 can serve as a transition and buffer layer between the subsequently formed isolation mask layer and the substrate 110, and can protect the first well region 101 and the second well region 102 in the substrate 110 from contamination during the subsequent process of forming the isolation trench of the isolation structure.

[0114] Fig. 9 It is a cross-sectional schematic diagram of a structure formed after a first gate oxide layer 121 and a second gate oxide layer 122 are formed on a substrate 110 according to a preparation method in one embodiment of the present application. Fig.10 It is a cross-sectional schematic diagram of a structure formed after forming a first gate oxide layer 121 and a second gate oxide layer 122 on a substrate 110 according to a preparation method in another embodiment of the present application. Fig.11 It is a cross-sectional schematic diagram of a structure formed after forming a first gate oxide layer 121 and a second gate oxide layer 122 on a substrate 110 according to a preparation method in another embodiment of the present application. Fig.12 It is a cross-sectional schematic diagram of a structure formed after forming a first gate oxide layer 121 and a second gate oxide layer 122 on a substrate 110 according to a preparation method in another embodiment of the present application.

[0115] like Figures 8 to 12 As shown, taking the formation of an isolation structure after forming the first gate oxide layer 121 and the second gate oxide layer 122 as an example, the formation of the isolation structure in the substrate 110 may include: forming a patterned isolation mask layer (not shown) on the surface of the first gate oxide layer 121 and the second gate oxide layer 122; using the patterned isolation mask layer as a mask, removing a portion of the first gate oxide layer 121, a portion of the second gate oxide layer 122 and a portion of the substrate 110 to form a first groove 1311 and a second groove 1321; filling the first isolation groove 1311 and the second isolation groove 1321 with an isolation material; and etching back a portion of the isolation material to form a first isolation structure 131 and a second isolation structure 132.

[0116] Specifically, an initial isolation mask layer (not shown) may be formed on the surface of the first gate oxide layer 121 and the second gate oxide layer 122 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The material forming the isolation mask layer may be, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, and silicon oxycarbide. The thickness of the portion of the isolation mask layer located on the first gate oxide layer 121 is less than the thickness of the portion of the isolation mask layer located on the second gate oxide layer 122.

[0117] After the initial isolation mask layer is formed, a chemical mechanical polishing (CMP) process, for example, may be performed to flatten the surface of the initial isolation mask layer. A photoresist layer may be formed on the flattened surface of the isolation mask layer, and photolithography processes such as exposure and development may be performed to define the positions of the first groove 1311 and the second groove 1321 in the photoresist layer. The defined photoresist layer is formed by, for example, a plasma etching process, etc., to form a patterned isolation mask layer. Similarly, the positions of the first groove 1311 and the second groove 1321 are defined in the patterned isolation mask layer. In addition, the present application does not limit the number and depth of the first groove and the second groove.

[0118] With the patterned isolation mask layer as a mask, a portion of the first gate oxide layer 121, a portion of the second gate oxide layer 122 and a portion of the substrate 110 are removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, etc., to form an isolation trench (not shown), the isolation trench including a first groove 1311 and a second groove 1321. The isolation trench can be formed between each high-voltage well, between each low-voltage well, and between a high-voltage well and a low-voltage well. In other words, the area between the isolation structures can be defined as an active area, and the isolation trench for forming the isolation structure is set between the active areas in the substrate 110, and between the first well region 101 and the second well region 102. In addition, as shown in the figure, the bottom of the first groove 1311 of the first well region 101 is lower than the bottom of the second groove 1321 of the second well region 102 in the Z direction, and there is a difference h2 between the two.

[0119] The first groove 1311 and the second groove 1321 are filled with an isolation material by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. A chemical mechanical polishing process or other etching process is used to remove the portion of the isolation material located on the patterned isolation mask layer to form a first insulating dielectric layer 1321 and a second insulating dielectric layer 1322, and the patterned isolation mask layer is removed. A back etching process is used to remove a portion of the first insulating dielectric layer 1321 or a portion of the second insulating dielectric layer 1322 to form a first isolation structure 131 and a second isolation structure 132.

[0120] like Fig. 9 In the semiconductor structure 100 shown, in subsequent process steps, a plurality of planar transistors may be formed on the first well region 101 of the substrate 110 ; and a plurality of fin field-effect transistors (Fin-FET) may be formed on the second well region 102 of the substrate 110 .

[0121] Specifically, the first isolation structure 131 and the second isolation structure 132 can be formed through the above process, wherein the second insulating dielectric layer 1322 located in the second groove 1321 can be etched back so that the thickness h5 of the second insulating dielectric layer 1322 formed on the second well region 102 is less than the depth h6 of the second groove 1321, so that in the subsequent process, a plurality of fin field effect transistors can be formed on the second well region 102. In addition, the thickness h3 of the first insulating dielectric layer 1312 formed on the first well region 101 is greater than the depth h4 of the first groove 1311, so that in the subsequent process, a plurality of planar transistors can be formed on the first well region 101.

[0122] like Fig.10 In the semiconductor structure 100 shown, a plurality of planar transistors may be formed on the substrate 110 in subsequent process steps.

[0123] Specifically, the first isolation structure 131 and the second isolation structure 132 can be formed through the above process, so that the thickness h3 of the first insulating dielectric layer 1312 formed on the first well region 101 is greater than the depth h4 of the first groove 1311, and the thickness h5 of the second insulating dielectric layer 1322 formed on the second well region 102 is greater than the depth h6 of the second groove 1321, so that in the subsequent process steps, multiple planar transistors can be formed on the first well region 101 and the second well region 102.

[0124] like Fig.11 In the semiconductor structure 100 shown, a plurality of fin field effect transistors may be formed on the substrate 110 in subsequent process steps.

[0125] Specifically, the first isolation structure 131 and the second isolation structure 132 can be formed through the above process, wherein the first insulating dielectric layer 1312 located in the first groove 1311 can be etched back so that the thickness h3 of the first insulating dielectric layer 1312 formed on the first well region 101 is smaller than the depth h4 of the first groove 1311, so that in the subsequent process, a plurality of fin field effect transistors can be formed on the first well region 101; the second insulating dielectric layer 1322 located in the second groove 1321 can be etched back so that the thickness h5 of the second insulating dielectric layer 1322 formed on the second well region 102 is smaller than the depth h6 of the second groove 1321, so that in the subsequent process, a plurality of fin field effect transistors can be formed on the second well region 102.

[0126] like Fig.12 In the semiconductor structure 100 shown in the figure, in the subsequent process, a plurality of fin field effect transistors can be formed on the first well region 101 of the substrate 110; a plurality of planar transistors can be formed on the second well region 102 of the substrate 110.

[0127] Specifically, the first isolation structure 131 and the second isolation structure 132 can be formed through the above process, wherein the first insulating dielectric layer 1312 located in the first groove 1311 can be etched back so that the thickness h3 of the first insulating dielectric layer 1312 formed on the first well region 101 is less than the depth h4 of the first groove 1311, so that in the subsequent process, a plurality of fin field effect transistors can be formed on the first well region 101. In addition, the thickness h5 of the second insulating dielectric layer 1322 formed on the second well region 102 is greater than the depth h6 of the second groove 1321, so that in the subsequent process, a plurality of planar transistors can be formed on the second well region 102.

[0128] Step S3

[0129] Fig.13 It is a schematic cross-sectional view of a structure formed after forming an initial composite layer 160 according to a preparation method in one embodiment of the present application. Fig.14 It is a cross-sectional schematic diagram of a structure formed after forming a first gate 141 and a second gate 142 according to a preparation method in one embodiment of the present application.

[0130] like Figure 8 , Fig.13 and Fig.14 As shown, in one embodiment of the present application, step S3 covers the gate layer on the first gate oxide layer and the second gate oxide layer, removes part of the gate layer, so as to form the first gate located in the first well region and the second gate located in the second well region, which may include, for example: covering the gate layer 140 on the first gate oxide layer 121 and the second gate oxide layer 122; forming a patterned mask layer 150 on the gate layer 140; forming a flatness adjustment layer 160 on the patterned mask layer 150; and removing part of the gate layer 140 to form the first gate 141 and the second gate 142, wherein the top of the first gate 141 and the top of the second gate 142 are located at different heights, and the first gate 141 and the second gate 142 have the same height. In addition, it is known to those skilled in the art that "having the same height" should be understood as the exact same height and the approximately same height or substantially the same height within the range of process or measurement error. The top of the first gate 141 can be understood as the portion of the first gate 141 away from the substrate 110; and the top of the second gate 142 can be understood as the portion of the second gate 142 away from the substrate 110.

[0131] Specifically, the gate layer 140 may be covered on the first gate oxide layer 12 and the second gate oxide layer 122 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Optionally, the gate layer 140 may be a semiconductor material layer, such as a polysilicon layer. Further, the semiconductor material layer may be doped to improve the electrical characteristics of the semiconductor structure finally formed.

[0132] like Fig.13 As shown, in one embodiment of the present application, before removing a portion of the gate layer 140, a mask layer (not shown) may be formed on the gate layer 140; a photolithography process is used to transfer the pattern of the photolithography mask to the mask layer to form a patterned mask layer 150; and the patterned mask layer 150 is used as a mask to remove a portion of the gate layer 140 using an anisotropic etching method, wherein the gate layer 140 has an etching selectivity greater than a set value relative to the mask layer, so as to retain the gate layer during the process of forming the patterned mask layer 150.

[0133] For example, a mask layer may be formed on the gate layer 140 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The material forming the mask layer may be, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. After the mask layer is formed, a photoresist layer (not shown) may be formed on the surface of the mask layer, and the pattern of the photolithography mask is transferred to the photoresist layer by photolithography processes such as exposure and development, and a patterned mask layer 150 is formed by, for example, a plasma etching process. The positions of the first gate 141 and the second gate 142 are defined in the patterned mask layer 150.

[0134] In the process of forming the patterned mask layer 150, the gate layer 140 can be set to have an etching selectivity greater than a set value relative to the mask layer, so that the gate layer is retained in the process of forming the patterned mask layer 150. Avoiding the removal of the gate layer by an etching process or the like in this process can reduce the debris of the gate layer in the finally formed semiconductor structure, thereby improving the performance of the finally formed semiconductor structure.

[0135] In addition, in order to effectively remove part of the gate layer 140 in the subsequent steps, a flatness adjustment layer 160 may be formed on the mask layer after the mask layer is formed. The flatness adjustment layer 160 can replace the function of the above-mentioned photoresist layer on the one hand; on the other hand, it can effectively fill the uneven surface of the gate layer 140, and provide a flat surface for the subsequent step of removing part of the gate layer 140. Through the flat surface, the effective removal of part of the gate layer 140 can be achieved.

[0136] Optionally, before removing a portion of the gate layer 140, an initial composite layer (not shown) may be formed on the mask layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. After the initial composite layer is formed, a chemical mechanical polishing process is performed, for example, to flatten the surface of the initial composite layer, thereby forming the flatness adjustment layer 160.

[0137] As an option, the flatness adjustment layer 160 may be a composite structure, for example, the flatness adjustment layer 160 may include a silicon oxynitride layer and a spin-on carbon layer. In the process of forming the spin-on carbon layer, the generation of pores in the process of depositing the film layer can be prevented by the spinning process, thereby forming a high-quality film layer with good coverage, density, and uniformity to fill the uneven surface of the gate layer 140. In addition, the spin-on carbon layer can also be effectively and quickly removed by a cleaning process such as ashing.

[0138] After the flatness adjustment layer 160 is formed, the pattern of the photolithography mask is transferred to the flatness adjustment layer 160 through photolithography processes such as exposure and development, and a plasma etching process is used to form a patterned mask layer 150. The positions of the first gate 141 and the second gate 142 are defined in the patterned mask layer 150.

[0139] After forming the patterned mask layer 150 , the patterned mask layer 150 may be used as a mask to remove part of the gate layer 140 by, for example, anisotropic etching to form a first gate 141 located in the first well region 101 and a second gate 142 located in the second well region 102 .

[0140] refer to Fig.14 Although the thickness of the first gate oxide layer 121 is greater than that of the second gate oxide layer 122, in at least one embodiment of the present application, after forming the gate layer 140, no planarization process is performed, so that the portion of the gate layer 140 on the first gate oxide layer 121 and the portion thereof on the second gate oxide layer 122 have the same thickness, and then by removing part of the gate layer 140 to form high and low voltage gates, the first gate 141 and the second gate 142 can have the same height H3. The high and low voltage gates have the same height, which can improve the yield and reliability of the finally formed semiconductor device.

[0141] In addition, since the portion of the gate layer 140 on the first gate oxide layer 121 and the portion thereof on the second gate oxide layer 122 have the same thickness, in the process of forming high and low voltage gates by removing part of the gate layer 140, defects caused by "over" etching or "under" etching can be reduced, thereby improving the consistency of the sidewall morphology of the high and low voltage gates, thereby improving the yield and reliability of semiconductor devices.

[0142] In addition, through the above-mentioned method 1000 for preparing a semiconductor structure, the sidewall morphology of the high and low voltage gates can have a high degree of consistency with their expected morphology. Specifically, the morphology parameter value of the sidewall of the first gate 141 can be less than or equal to the morphology threshold of the sidewall of the first gate, wherein the morphology parameter value of the sidewall of the first gate may include: at least one of the angle value between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110 and the local surface flatness of the portion of the sidewall of the first gate 141 close to the substrate 110.

[0143] Accordingly, the morphology parameter value of the side wall of the second gate 142 may be less than or equal to the morphology threshold of the side wall of the second gate, wherein the morphology parameter value of the side wall of the second gate may include: at least one of: an angle value between a portion of the side wall of the second gate 142 close to the substrate 110 and the substrate 110 and a local surface flatness of a portion of the side wall of the second gate 142 close to the substrate 110.

[0144] Optionally, in one embodiment of the present application, the morphology threshold of the sidewall of the first gate may include at least one of an angle threshold of the sidewall of the first gate 141 and a local surface flatness threshold of the sidewall of the first gate 141. The angle threshold may be a range of expected angle values ​​between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110. For example, if the expected angle value between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110 is 90°, the angle threshold may be 80° to 90°, or 85° to 90°. The local surface flatness threshold is a range of local surface flatness of the portion of the sidewall of the first gate 141 close to the substrate 110. The local surface flatness range may reflect the degree of protrusion or depression in the local plane. For example, the height of the protrusion or the depth of the depression in the local surface of the portion of the sidewall of the first gate 141 close to the substrate 110 is less than or equal to the expected value, wherein the expected value may be 1nm, 2nm, 3nm, 4nm or 5nm.

[0145] Optionally, in one embodiment of the present application, the morphology threshold of the sidewall of the second gate may include at least one of an angle threshold of the sidewall of the second gate 142 and a local surface flatness threshold of the sidewall of the second gate 142. The angle threshold may be a range of expected angle values ​​between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110. For example, if the expected angle value between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110 is 90°, the angle threshold may be 80° to 90°, or 85° to 90°. The local surface flatness threshold is a range of local surface flatness of the portion of the sidewall of the second gate 142 close to the substrate 110. The local surface flatness range may reflect the degree of protrusion or depression in the local plane. For example, the height of the protrusion or the depth of the depression in the local surface of the portion of the sidewall of the second gate 142 close to the substrate 110 is less than or equal to the expected value, wherein the expected value may be 1nm, 2nm, 3nm, 4nm or 5nm.

[0146] In addition, in one embodiment of the present application, the sidewall of the first gate 141 may be perpendicular to the substrate 110 in the Z direction. For example, the angle between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110 is between 85° and 90°, wherein the angle is 87°, 88°, 89° or 90°.

[0147] In addition, in one embodiment of the present application, the sidewall of the second gate 142 may be perpendicular to the substrate 110 in the Z direction. For example, the angle between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110 is between 85° and 90°. For example, the angle is 87°, 88°, 89° or 90°.

[0148] In addition, in the Z direction, the bottom of the first gate 141 and the bottom of the second gate 142 are located at different heights. The bottom of the first gate 141 can be understood as the portion of the first gate 141 close to the substrate 110; and the bottom of the second gate 142 can be understood as the portion of the second gate 142 close to the substrate 110.

[0149] In addition, the method for preparing the semiconductor structure omits the planarization process of the gate layer, which can effectively reduce the cost of preparing the semiconductor structure, the manufacturing time, and the process difficulty of forming high and low voltage gates.

[0150] Reference again Figure 2B and Fig.14On the other hand, the present application also provides a semiconductor structure 100 prepared by the method provided by any of the above embodiments, and the semiconductor structure 100 may include: a substrate 110, a first gate oxide layer 121, a second gate oxide layer 122, a first gate 141 and a second gate 142, wherein the substrate 110 includes a first well region 101 and a second well region 102, the first gate oxide layer 121 is located on the first well region 101, the second gate oxide layer 122 is located on the second well region 102, the first gate 141 is located on the first gate oxide layer 121, and the second gate 142 is located on the second gate oxide layer 122, in a first direction (Z direction) perpendicular to the substrate 110, the thickness of the first gate oxide layer 121 is greater than the thickness of the second gate oxide layer 122, the top of the first gate 141 and the top of the second gate 142 are located at different heights, and the first gate 141 and the second gate 142 have the same height. It is known to those skilled in the art that "having the same height" should be understood as completely the same height and approximately the same height or substantially the same height within the range of process or measurement errors. The top of the first gate 141 is a portion of the first gate 141 away from the substrate 110 ; and the top of the second gate 142 is a portion of the second gate 142 away from the substrate 110 .

[0151] Further, in one embodiment of the present application, the sidewall of the first gate 141 and the sidewall of the second gate 142 have the same morphology. Those skilled in the art will appreciate that "having the same morphology" should be understood as completely identical morphology and approximately the same morphology or substantially the same morphology within the range of process or measurement errors.

[0152] In addition, the sidewall morphology of the first gate 141 and the second gate 142 can have a high degree of consistency with their expected morphology. Specifically, the morphology parameter value of the sidewall of the first gate 141 can be less than or equal to the morphology threshold of the sidewall of the first gate, wherein the morphology parameter value of the sidewall of the first gate may include: at least one of the angle value between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110 and the local surface flatness of the portion of the sidewall of the first gate 141 close to the substrate 110. Correspondingly, the morphology parameter value of the sidewall of the second gate 142 can be less than or equal to the morphology threshold of the sidewall of the second gate, wherein the morphology parameter value of the sidewall of the second gate may include: at least one of the angle value between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110 and the local surface flatness of the portion of the sidewall of the second gate 142 close to the substrate 110.

[0153] Optionally, in one embodiment of the present application, the morphology threshold of the sidewall of the first gate may include at least one of an angle threshold of the sidewall of the first gate 141 and a local surface flatness threshold of the sidewall of the first gate 141. The angle threshold may be a range of expected angle values ​​between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110. For example, if the expected angle value between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110 is 90°, the angle threshold may be 80° to 90°, or 85° to 90°. The local surface flatness threshold is a range of local surface flatness of the portion of the sidewall of the first gate 141 close to the substrate 110. The local surface flatness range may reflect the degree of protrusion or depression in the local plane. For example, the height of the protrusion or the depth of the depression in the local surface of the portion of the sidewall of the first gate 141 close to the substrate 110 is less than or equal to the expected value, wherein the expected value may be 1nm, 2nm, 3nm, 4nm or 5nm.

[0154] Optionally, in one embodiment of the present application, the morphology threshold of the sidewall of the second gate may include at least one of an angle threshold of the sidewall of the second gate 142 and a local surface flatness threshold of the sidewall of the second gate 142. The angle threshold is the range of expected angle values ​​between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110. For example, if the expected angle value between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110 is 90°, the angle threshold may be 80° to 90°, or 85° to 90°. The local surface flatness threshold is the range of local surface flatness of the portion of the sidewall of the second gate 142 close to the substrate 110. The local surface flatness range may reflect the degree of protrusion or depression in the local plane. For example, the height of the protrusion or the depth of the depression in the local surface of the portion of the sidewall of the second gate 142 close to the substrate 110 is less than or equal to the expected value, wherein the expected value may be 1nm, 2nm, 3nm, 4nm or 5nm.

[0155] In addition, in one embodiment of the present application, the sidewall of the first gate 141 may be perpendicular to the substrate 110 in the Z direction. For example, the angle between the portion of the sidewall of the first gate 141 close to the substrate 110 and the substrate 110 is between 85° and 90°, wherein the angle is 87°, 88°, 89° or 90°.

[0156] In addition, in one embodiment of the present application, the sidewall of the second gate 142 may be perpendicular to the substrate 110 in the Z direction. For example, the angle between the portion of the sidewall of the second gate 142 close to the substrate 110 and the substrate 110 is between 85° and 90°. For example, the angle is 87°, 88°, 89° or 90°.

[0157] In addition, in the Z direction, the bottom of the first gate 141 and the bottom of the second gate 142 are located at different heights. The bottom of the first gate 141 can be understood as the portion of the first gate 141 close to the substrate 110; and the bottom of the second gate 142 can be understood as the portion of the second gate 142 close to the substrate 110. Therefore, according to the semiconductor structure provided by at least one embodiment of the present application, after the gate layer is formed, no planarization treatment is performed, and high and low voltage gates are formed directly by removing part of the gate layer, which can reduce the defects that may occur in the process of forming the high and low voltage gates, thereby improving the consistency of the high and low voltage gates in terms of sidewall morphology and height, and improving the yield and reliability of semiconductor devices.

[0158] Specifically, in one embodiment of the present application, the semiconductor structure 100 further includes an isolation structure (not shown) located in the substrate 110, such as a first isolation structure 131 located in the first well region 101 and a second isolation structure 132 located in the second well region 102. The first well region 101 may include a plurality of high-voltage wells of different doping types, the second well region may include a plurality of low-voltage wells of different doping types, and the isolation structure may be located between each high-voltage well, between each low-voltage well, and between a high-voltage well and a low-voltage well.

[0159] Furthermore, various semiconductor devices, such as various planar transistors and various fin field effect transistors, may be formed in the semiconductor structure 100 .

[0160] Specifically, Fig. 9 and Fig.14 As shown, in one embodiment of the present application, a plurality of planar transistors may be formed on the first well region 101 of the substrate 110; and a plurality of fin field effect transistors may be formed on the second well region 102 of the substrate 110. The first isolation structure 131 includes a first groove 1311 and a first insulating dielectric layer 1312 filled in the first groove 1311, and the thickness h3 of the first insulating dielectric layer 1312 in the Z direction is greater than the depth h4 of the first groove 1211 in the Z direction. The second isolation structure 132 includes a second groove 1321 and a second insulating dielectric layer 1322 filled in the second groove 1321, and the thickness h5 of the second insulating dielectric layer 1322 in the Z direction is less than the depth h6 of the second groove 1321 in the Z direction.

[0161] like Fig.10 and Fig.14As shown, in one embodiment of the present application, a plurality of planar transistors may be formed on the substrate 110. The first isolation structure 131 includes a first groove 1311 and a first insulating dielectric layer 1312 filled in the first groove 1311, and the thickness h3 of the first insulating dielectric layer 1312 in the Z direction is greater than the depth h4 of the first groove 1211 in the Z direction. The second isolation structure 132 includes a second groove 1321 and a second insulating dielectric layer 1322 filled in the second groove 1321, and the thickness h5 of the second insulating dielectric layer 1322 in the Z direction is greater than the depth h6 of the second groove 1321 in the Z direction.

[0162] like Fig.11 and Fig.14 As shown, in one embodiment of the present application, a plurality of fin field effect transistors may be formed on the substrate 110. The first isolation structure 131 includes a first groove 1311 and a first insulating dielectric layer 1312 filled in the first groove 1311, and the thickness h3 of the first insulating dielectric layer 1312 in the Z direction is less than the depth h4 of the first groove 1211 in the Z direction. The second isolation structure 132 includes a second groove 1321 and a second insulating dielectric layer 1322 filled in the second groove 1321, and the thickness h5 of the second insulating dielectric layer 1322 in the Z direction is less than the depth h6 of the second groove 1321 in the Z direction.

[0163] like Fig.12 and Fig.14 As shown, in one embodiment of the present application, a plurality of fin field effect transistors may be formed on the first well region 101 of the substrate 110; and a plurality of planar transistors may be formed on the second well region 102 of the substrate 110. The first isolation structure 131 includes a first groove 1311 and a first insulating dielectric layer 1312 filled in the first groove 1311, and the thickness h3 of the first insulating dielectric layer 1312 in the Z direction is less than the depth h4 of the first groove 1211 in the Z direction. The second isolation structure 132 includes a second groove 1321 and a second insulating dielectric layer 1322 filled in the second groove 1321, and the thickness h5 of the second insulating dielectric layer 1322 in the Z direction is greater than the depth h6 of the second groove 1321 in the Z direction.

[0164] In addition, if Figure 1 and Figure 2A As shown, at least one embodiment of another aspect of the present application further provides a peripheral device 10, a three-dimensional memory 2 and a storage system 1. The present application provides a peripheral circuit, a memory and a storage system, which have the same beneficial effects as the semiconductor structure provided by the present application due to the provision of the semiconductor structure provided by the present application, and are not described in detail here.

[0165] In addition, although the exemplary method for preparing the semiconductor structure and the exemplary semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the above method or structure. In addition, the materials of each layer exemplified are only exemplary.

[0166] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: forming a substrate including a first well region and a second well region; forming a first gate oxide layer above the first well region and forming a second gate oxide layer above the second well region, wherein in a first direction perpendicular to the substrate, a thickness of the first gate oxide layer is greater than a thickness of the second gate oxide layer; A gate layer is covered on the first gate oxide layer and the second gate oxide layer, and a portion of the gate layer is removed to form a first gate located in the first well region and a second gate located in the second well region, Wherein, in the first direction, the top of the first gate and the top of the second gate are located at different heights, and the first gate and the second gate have the same height.

2. The method according to claim 1, wherein: Forming a first gate oxide layer above the first well region and forming a second gate oxide layer above the second well region comprises: forming an initial sacrificial layer on the substrate; removing a portion of the initial sacrificial layer located above the first well region to form a sacrificial layer; forming the first gate oxide layer above the first well region; The sacrificial layer is removed, and the second gate oxide layer is formed above the second well region.

3. The method according to claim 1, wherein: Removing part of the gate layer includes: Before removing a portion of the gate layer, forming a mask layer on the gate layer; Using a photolithography process to transfer the pattern of the photolithography mask to the mask layer; and Using the patterned mask layer as a mask, anisotropic etching is used to remove part of the gate layer. The gate layer has an etching selectivity ratio greater than a set value relative to the mask layer, so as to retain the gate layer during the process of forming the patterned mask layer.

4. The method according to claim 3, wherein: The method further comprises: Before removing a portion of the gate layer, forming an initial composite layer on the mask layer; and performing a planarization process on the initial composite layer to form a flatness adjustment layer; and After removing part of the gate layer, the flatness adjustment layer and the mask layer are removed.

5. The method according to claim 4, wherein: The flatness adjustment layer includes a silicon oxynitride layer and a spin-on carbon layer.

6. A semiconductor structure, characterized in that: The semiconductor structure comprises: A substrate including a first well region and a second well region; A first gate oxide layer, located on the first well region; a second gate oxide layer, located on the second well region; A first gate is located on the first gate oxide layer; and A second gate, located on the second gate oxide layer, Wherein, in a first direction perpendicular to the substrate, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer, the top of the first gate and the top of the second gate are located at different heights, and the first gate and the second gate have the same height.

7. The semiconductor structure according to claim 6, wherein: A sidewall of the first gate is perpendicular to the substrate in the first direction.

8. The semiconductor structure according to claim 6, wherein: A sidewall of the second gate is perpendicular to the substrate in the first direction.

9. The semiconductor structure according to claim 6, wherein: The sidewall of the first gate and the sidewall of the second gate have the same morphology.

10. The semiconductor structure according to claim 6, wherein: The morphology parameter value of the side wall of the first gate is less than or equal to the morphology threshold of the side wall of the first gate, The morphology parameter value of the side wall of the first gate includes the local surface flatness of a portion of the side wall of the first gate close to the substrate.

11. The semiconductor structure according to claim 6, wherein: The morphology parameter value of the side wall of the second gate is less than or equal to the morphology threshold of the side wall of the second gate, The morphology parameter value of the side wall of the second gate includes the local surface flatness of a portion of the side wall of the second gate close to the substrate.

12. The semiconductor structure according to claim 8, wherein: In the first direction, a bottom of the first gate and a bottom of the second gate are located at different heights.

13. The semiconductor structure according to any one of claims 8 to 12, wherein: The semiconductor structure further includes an isolation structure located in the substrate, The first well region includes a plurality of high-voltage wells of different doping types, the second well region includes a plurality of low-voltage wells of different doping types, and the isolation structure is located between the high-voltage wells, between the low-voltage wells, and between the high-voltage well and the low-voltage well.

14. The semiconductor structure according to claim 13, wherein: The isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, The semiconductor structure further includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is greater than the depth of the first groove in the first direction; and The semiconductor structure also includes a second groove located in the second well region, and the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is smaller than the depth of the second groove in the first direction.

15. The semiconductor structure according to claim 13, wherein: The isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, The semiconductor structure further includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is less than the depth of the first groove in the first direction; and The semiconductor structure also includes a second groove located in the second well region, and the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is greater than the depth of the second groove in the first direction.

16. The semiconductor structure according to claim 13, wherein: The isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, The semiconductor structure further includes a first groove located in the first well region, the first isolation structure includes a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is less than the depth of the first groove in the first direction; and The semiconductor structure also includes a second groove located in the second well region, and the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is smaller than the depth of the second groove in the first direction.

17. The semiconductor structure according to claim 13, wherein: The isolation structure includes a first isolation structure located in the first well region and a second isolation structure located in the second well region, The semiconductor structure further includes a first groove located in the first well region, the first isolation structure includes the first groove and a first insulating dielectric layer filled in the first groove, and the thickness of the first insulating dielectric layer in the first direction is greater than the depth of the first groove in the first direction; and The semiconductor structure also includes a second groove located in the second well region, and the second isolation structure includes a second insulating dielectric layer filled in the second groove, and the thickness of the second insulating dielectric layer in the first direction is greater than the depth of the second groove in the first direction.

18. A peripheral device, characterized in that: The invention comprises a semiconductor structure, wherein the semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 5 or the semiconductor structure according to any one of claims 6 to 17.

19. A three-dimensional memory, characterized in that: include: The peripheral device as claimed in claim 18; as well as A memory array device is coupled to the peripheral device.

20. A storage system, characterized in that: The device comprises a controller and the three-dimensional memory as claimed in claim 19, wherein the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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