Encapsulated warpage reduction for semiconductor die assemblies and associated methods and systems

Abstract

Encapsulant warpage reduction for semiconductor die assemblies and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a semiconductor die stack attached to a surface of the interface die, where the semiconductor die stack has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the semiconductor die stack, where the encapsulant includes a sidewall having a first portion extending from the surface to a second height that is less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture that is different than the first texture.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor die assemblies, and more specifically, to encapsulation warpage reduction and related methods and systems for semiconductor die assemblies. Background Technology

[0002] Semiconductor packages typically comprise semiconductor dies (e.g., memory chips, microprocessor chips, imager chips) mounted on a substrate and encapsulated within a protective cover (e.g., encapsulation material). The semiconductor die may contain functional features, such as memory cells, processor circuitry, or imager devices, and bonding pads electrically connected to these functional features. The bonding pads may be electrically connected to corresponding conductive structures on the substrate, and may couple to terminals outside the protective cover, allowing the semiconductor die to be connected to higher-level circuitry.

[0003] Market pressures are constantly driving semiconductor manufacturers to reduce the size of semiconductor packages to fit the space constraints of electronic devices. In some semiconductor packages, direct chip attachment methods (e.g., flip-chip bonding between a semiconductor die and a substrate) can be used to reduce the footprint of the semiconductor package. Such direct chip attachment methods involve directly connecting multiple conductive pillars electrically coupled to the semiconductor die to corresponding conductive structures (e.g., conductive bumps) on the substrate. In this regard, solder structures can be formed over individual conductive pillars to bond the conductive pillars to the corresponding conductive structures—for example, forming an interconnect (which may be referred to as a connector) comprising conductive pillars, solder structures, and conductive bumps. Furthermore, an encapsulating material can be applied to protect the semiconductor die. Summary of the Invention

[0004] In one aspect, this application provides a semiconductor die assembly comprising: an interface die; a semiconductor die attached to a surface of the interface die, the semiconductor die having a first height from the surface; and an encapsulant above the surface and surrounding the semiconductor die, the encapsulant including sidewalls having: a lower segment extending from the surface to a second height less than the first height, the lower segment having a first surface texture; and an upper segment extending from the second height to the first height, the upper segment having a second surface texture different from the first surface texture.

[0005] In another aspect, this application provides a mold frame comprising: a horizontal member having an outer surface and an inner surface opposite to the outer surface; and a wall member connected to a peripheral region of the inner surface, the wall member having a first length from the inner surface and including a cylindrical inner sidewall, wherein: the inner surface of the horizontal member and the inner sidewall of the wall member form a cavity configured to cover a plurality of semiconductor dies attached to a substrate; and the inner surface corresponding to the cavity includes a group of protruding spacers having a second length from the inner surface, the second length being less than the first length.

[0006] In another aspect, this application provides a method comprising: attaching a semiconductor die stack to an interface substrate, the semiconductor die stack being aligned with a cleavage of the interface substrate; positioning a mold frame over the semiconductor die stack such that the semiconductor die stack is enclosed within a cavity of the mold frame, wherein an inner surface of the mold frame corresponding to the cavity includes a group of protruding spacers extending from the inner surface toward the interface substrate; applying an encapsulant through the mold frame onto the interface substrate and the semiconductor die stack such that the encapsulant fills a space between the stacks, the space corresponding to the cleavage; and displacing at least a portion of the encapsulant from the space. Attached Figure Description

[0007] Referring to the accompanying drawings will provide a better understanding of many aspects of this technology. The components in the drawings are not necessarily to scale. Rather, the focus should be on clearly illustrating the principles of this technology.

[0008] Figure 1 This is a diagram of an interface chip with a stack of semiconductor dies.

[0009] Figures 2A to 2E Describe the stages of the process used to form semiconductor die assemblies.

[0010] Figures 3A to 3F This describes the stages of a process for forming a semiconductor die assembly according to embodiments of the present technology.

[0011] Figure 4 This describes the stages of a process for forming a semiconductor die assembly according to embodiments of the present technology.

[0012] Figure 5A and 5B This describes an example mold frame according to an embodiment of the present technology.

[0013] Figure 5C and 5D This describes an example semiconductor die assembly according to an embodiment of the present technology.

[0014] Figure 6 It is a semiconductor die assembly according to an embodiment of the present technology.

[0015] Figure 7 This is a block diagram illustrating, schematically, a system comprising a semiconductor die assembly configured according to embodiments of the present technology.

[0016] Figure 8 This is a flowchart of a method for forming a semiconductor die assembly according to an embodiment of the present technology. Detailed Implementation

[0017] The following describes specific details of several embodiments relating to reducing wafer warpage in semiconductor die assemblies and associated systems and methods. Wafer-level packaging (WLP) provides a scaled-down form factor for semiconductor die assemblies (semiconductor device assemblies). WLP technology utilizes an interface wafer to which semiconductor dies or stacks of semiconductor dies (e.g., active dies, referred to as good dies, memory dies) are attached. Individual semiconductor dies (or stacks of semiconductor dies) are aligned with and electrically connected to a corresponding interface die on the interface wafer. The interface die may comprise semiconductor dies of a different type than semiconductor dies (e.g., logic dies that control semiconductor dies) or interposer dies having redistribution layers (RDLs) configured to route electrical signals between semiconductor dies (or stacks of semiconductor dies) and higher-level circuitry.

[0018] For certain semiconductor die assemblies, the size of individual logic dies and / or interposer dies is larger than the area occupied by the corresponding semiconductor die (or semiconductor die stack), allowing additional terminals (e.g., balls in a ball grid array (BGA) positioned outside the occupied area of ​​the semiconductor die) to be available for the semiconductor die (or semiconductor die stack). In this way, the semiconductor die can transmit / receive signals via the additional terminals to efficiently handle high-bandwidth signals; this can be called a fan-out packaging (FOP) scheme. Therefore, there is space between adjacent semiconductor dies (or adjacent semiconductor die stacks), and this space corresponds to a scribe line (also called a dicing lane / dicingstreet, cutting line, or the like) for the interface die. The ratio between the total area occupied by the semiconductor dies and the total area of ​​the interface wafer is called the die ratio.

[0019] After the semiconductor dies (or stacks of semiconductor dies) have been attached to the interface wafer (which may be referred to as chip-on-wax (CoW)), an encapsulation material (such as molding compound material, epoxy molding compound (EMC)) is placed on the interface wafer, immersing the semiconductor dies (or stacks of semiconductor dies) in the encapsulation material. Furthermore, the spaces between the semiconductor dies are filled with the encapsulation material. Subsequently, the encapsulation material is cured at high temperature to harden it and provide protection for the semiconductor dies. Excess encapsulation material on the semiconductor dies (or stacks of semiconductor dies) can then be removed using a polishing process. The process of using encapsulation material to protect the semiconductor dies is called a molding process.

[0020] Following the molding process, one or more dicing steps can be performed to dic (e.g., cut, separate) individual semiconductor die assemblies along a dividing line. In some embodiments, the dicing step utilizes a dicing saw (dicing blade or saw) to cut the encapsulation material in the space between the interface wafer and the semiconductor die to dic the individual semiconductor die assemblies, each containing an interface die and a semiconductor die (or semiconductor die stack) attached to the interface die.

[0021] Encapsulation materials typically have a different coefficient of thermal expansion (CTE) than the semiconductor die and / or interposer die—for example, silicon. Silicon has a CTE of 2.6 ppm / °C, while encapsulation materials can have a CTE three (3) to four (4) times greater—for example, ranging from 7 to 10 ppm / °C or even higher. Due to this CTE mismatch, the interface wafer carrying the semiconductor die stack experiences stress as the encapsulation material is cured, which can cause the interface wafer to deform (e.g., bend, warp, twist). In some cases, wafer warpage can be exacerbated if the die-to-surface ratio (the ratio between the total area occupied by the semiconductor dies and the total area of ​​the interface wafer) decreases due to a relatively increased amount of encapsulation material on top of the interface wafer. In some cases, wafer warpage can be so severe that it causes difficulties in downstream process steps. For example, wafer warpage can make vacuum clamping of the interface wafer more difficult for polishing processes.

[0022] This technology is designed to reduce (e.g., mitigate) wafer warpage by reducing the amount of encapsulation material on the interface wafer during the molding process. For example, the mold frame (mold encapsulation) may include protruding spacers (e.g., ridges, fins, blades, fences, separators, or the like) aligned with the dividing lines of the interface substrate (and therefore with the space between the semiconductor dies). As described in more detail herein, the protruding spacers reduce the volume of the cavity in the mold frame, corresponding to the amount of encapsulation material on the interface wafer. In some embodiments, the protruding spacers displace portions of the encapsulation material from the space between the semiconductor dies (e.g., ejection, extrusion, extrusion, pressing).

[0023] Therefore, the encapsulation material will contain grooves (e.g., imprints, indentations, trenches) along at least some dividing lines after the molding process. In this way, the amount of encapsulation material can be reduced to mitigate wafer warpage issues originating from CTE mismatch during encapsulation material curing. In some embodiments, the cavities and separators of the mold frame are coated with a material having low surface energy (e.g., paralyne). In some embodiments, a release film may be inserted between the encapsulation material and the mold frame to facilitate release of the interface wafer from the mold frame or vice versa. In some embodiments, the mold frame includes one or more openings to provide vacuum suction for the release film.

[0024] The term "semiconductor device or die" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, or diodes. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. Furthermore, the term "semiconductor device or die" may refer to a finished device or an assembly or other structure of various processing stages prior to becoming a finished device. Depending on its context, the term "substrate" may refer to a wafer-level substrate or a single-cut die-level substrate. Moreover, a substrate may include a semiconductor wafer, a package support substrate, an interposer, a semiconductor device or die, or the like. Those skilled in the art will recognize that appropriate steps of the methods described herein can be performed at the wafer or die level.

[0025] Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Some techniques can be combined with photolithography processes. Those skilled in the art will also understand that this technique may have additional embodiments and may be implemented without reference to this document. Figure 2AThe present technology is practiced in the context of several details in the embodiments described in section 5.

[0026] As used herein, the terms “vertical,” “horizontal,” “downward,” “upward,” “above,” and “below” can refer to the relative orientation or position of features in a semiconductor die assembly given the orientation shown in the figures. For example, “above” or “topmost” can mean that one feature is positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations.

[0027] Figure 1 This is a diagram of an interface substrate 105 (or interface wafer) with a stack of semiconductor dies 110. The interface substrate 105 carrying the stack of semiconductor dies 110 may be referred to as a reconstituted wafer (or chip-on-wafer) in the context of WLP technology, given that the individually diced semiconductor dies 110 are aligned and attached to corresponding interface dies 106 on the interface substrate 105. Although this technology is described herein with reference to a semiconductor device assembly comprising a stack of semiconductor dies (e.g., a stack of semiconductor dies 110) attached to an interface die (e.g., interface die 106), it should be understood that the principles of this technology are not limited thereto. For example, a semiconductor device assembly according to this technology may comprise a single semiconductor die attached to an interface die.

[0028] In some embodiments, interface die 106 is a semiconductor die of a different type (e.g., logic die, controller die) than the stacked semiconductor dies 110 (e.g., memory dies). The logic die may be configured to exchange electrical signals with the semiconductor die 110 and higher-level circuitry (e.g., a host device) coupled to the logic die. In some embodiments, interface die 106 is an interposer die having various conductive structures (e.g., redistribution layers, pathways, interconnects) configured to route electrical signals between the stack of semiconductor dies 110 and higher-level circuitry—e.g., a central processing unit (CPU) coupled to the stack of semiconductor dies 110 via the interposer die.

[0029] The stack of semiconductor dies 110 includes semiconductor dies 110 stacked on top of each other. Each semiconductor die 110 in the stack has a front side facing the interface die 106 (e.g., an active side having an active side of an integrated circuit, a bonding pad connected to the integrated circuit, a conductive pillar connected to the bonding pad, etc.) and a back side opposite the front side. The uppermost semiconductor die 110 in the stack may be referred to as the top die, and one or more semiconductor dies 110 positioned between the top die and the interface die 106 may be referred to as the core die.

[0030] In some embodiments, after front-side wafer processing (e.g., forming conductive pillars) is completed, the core wafer (the wafer containing the core die) is temporarily bonded to the carrier wafer such that the core wafer can be thinned to expose the core die's pathways (e.g., through-silicon vias (TSVs)) from the back side. Subsequently, various back-side conductive structures for the core die (e.g., conductive bumps connected to the exposed pathways) are formed. Next, the core die is diced and stacked together with the top die on the interface substrate 105 (e.g., using a thermo-press bonding step) to produce... Figure 1 The reconstructed wafer described herein. Process steps for generating interconnect structures (e.g., forming conductive pillars on the front side, thinning the wafer from the back side, forming conductive bumps on the back side) can be applied to the interface substrate 105, such that suitable interconnect structures can be formed on the front and / or back sides of the interface die 106. However, the stacked top die may be thinner than the core die and may not have a back-side conductive structure (or TSV).

[0031] Because the stack of semiconductor dies 110 is aligned with the interface die 106 of the interface substrate 105, the space between the stacks of semiconductor dies 110 (in) Figure 1 The symbol “S” corresponds to the dividing line 115 of the interface substrate 105. Dividing line 115 includes a horizontal dividing line 115a along the x-direction and a vertical dividing line 115b along the y-direction. Therefore, the space between the stacks of semiconductor dies 110 can form channels in both the x and y directions for the encapsulation material to flow during the molding process, as described below. Figure 2A and 3A describe.

[0032] The die ratio can be defined as the ratio between the total area occupied by the stack of semiconductor dies 110 attached to the interface substrate 105 and the total area of ​​the interface substrate 105. If the space between the stacks increases, the die ratio decreases. Therefore, if the die ratio decreases, the amount of encapsulation material on the interface substrate 105 increases, thereby increasing the risk of wafer warpage during the molding process. In the context of the FOP (Fan-in Package) scheme, the die ratio can be proportionally adjusted (reduced) due to the area difference between the stack of semiconductor dies 110 and the interface die 106. Thus, the wafer warpage problem in the FOP scheme can be exacerbated when compared to a fan-in package (FIP) scheme where the area difference between the stack of semiconductor dies 110 and the interface die 106 is relatively small. In some cases, independent of the FOP or FIP scheme, the die ratio is determined based on the size difference between the stack of semiconductor dies 110 (e.g., DRAM dies) and the interface die (which may be related to the customer's package size requirements).

[0033] Figure 1A peripheral region 120 of the interface substrate 105 is also depicted, which is located between the outermost stack of the semiconductor die 110 and the edge of the interface substrate 105. It is desirable to reduce the encapsulation material above the peripheral region 120 to alleviate wafer warpage issues.

[0034] Figures 2A to 2E Describe the stages of the process used to form semiconductor die assemblies. Figure 2A This is a cross-sectional view illustrating the support substrate 205 of the interface substrate 105 temporarily bonded to the stacked interface substrate 105 that carries the attached semiconductor die 110. The interface substrate 105 can be referenced as above. Figure 1 It was thinned out as described. Figure 2A A mold frame 210 is also described, having a cavity 220 disposed on an interface substrate 105 and an encapsulating material 225. The mold frame 210 may be configured to bring the cavity 220 toward the interface substrate 105 (as indicated by the dark vertical arrow) such that the encapsulating material 225 may be pressed to distribute across the interface substrate 105 (as indicated by the light horizontal arrow). In some embodiments, the encapsulating material 225 may be heated to promote the distribution of the encapsulating material 225 across the interface substrate 105.

[0035] Figure 2B The encapsulation material 225 is pressed by the mold frame 210 such that the stack of semiconductor dies 110 is completely encapsulated within the encapsulation material 225, and the space S between the stacks of semiconductor dies 110 (corresponding to the dividing line 115) is filled with the encapsulation material 225. As the mold frame 210 presses the encapsulation material 225, the encapsulation material 225 can be extended through the space S between the stacks of semiconductor dies 110 (e.g., along the reference line 115). Figure 1 The channels in both the x and y directions are described and distributed across the interface substrate 105.

[0036] Figure 2C The description explains that after the mold frame 210 is removed (i.e., after the interface substrate 105 is released from the mold frame 210), the encapsulating material 225 covers the stack of semiconductor dies 110 attached to the interface substrate 105. During this process, the stack of semiconductor dies 110 is completely submerged beneath the surface 226 of the encapsulating material 225. Surface 226 is flat, without any surface features, and the encapsulating material 225 covers the entire interface substrate 105 except for the edges. Subsequently, the encapsulating material 225 can be cured at high temperature to harden it and provide protection for the stack of semiconductor dies 110. The interface substrate 105 may be subjected to wafer warpage problems, at least in part, due to stress introduced by the CTE mismatch between the encapsulating material 225 and the interface substrate 105.

[0037] Figure 2DThe interface substrate 105 carries the stack of semiconductor dies 110 after an polishing process removes excess encapsulating material 225 over the stack to expose the top die of the stack. In some embodiments, a portion of the top die may also be removed during the polishing process. In some cases, wafer warping may be severe enough to make polishing process tools difficult to handle the interface substrate 105—for example, wafer clamping problems due to deteriorated vacuum suction. Such difficulties can create non-uniform process conditions within the interface substrate 105, resulting in yield losses—for example, due to uneven removal of the encapsulating material 225. In some cases, the interface substrate 105 may be discarded (scrapped).

[0038] Figure 2E The interface substrate 105 carries a stack of semiconductor dies 110 that are separate from the support substrate 205 and placed on the mounting strip 230. Subsequently, individual interface dies 106 attached to the corresponding stack of semiconductor dies 110 can be individually cut along the cutting line using a single-cut blade 235 (or a dicing blade).

[0039] Figures 3A to 3F This describes the stages of the process for forming a semiconductor die assembly according to the present technology. Figure 3A illustrate Figure 2A They share largely similar characteristics. For example, Figure 3A A cross-sectional view illustrating a temporary bonding (e.g., via an adhesive material not shown) to a support substrate 205 (e.g., a carrier wafer) of an interface substrate 105 that carries a stack of semiconductor dies 110 to which it is attached. The interface substrate 105 may be referenced as described above. Figure 1 It was thinned out as described.

[0040] Figure 3A It also describes the mold frame 310 (which may include references) Figure 2A The mold frame 210 described herein includes an encapsulating material 225 (e.g., epoxy molding compound (EMC), molding compound material). The mold frame 310 includes a cavity 320, which may have a depth of approximately 1.1 mm from the interface substrate 105. In some embodiments, after the mold frame 310 is positioned on the interface substrate 105, the encapsulating material 225 is injected into the cavity 320 through an opening 315 in the mold frame 310. In this respect, the opening 315 extends from the outer surface of the mold frame 310 to the cavity 320 such that the opening 315 can supply the encapsulating material 225 into the cavity 320. Thereafter, it can be as follows Figure 3AThe diagram illustrates the blocking of the opening 315. In other embodiments, the encapsulating material 225 is applied to the interface substrate 105 before the mold frame 310 is positioned above the encapsulating material 225. The mold frame 310 may be configured to bring the cavity 320 toward the interface substrate 105 (as indicated by the dark vertical arrow) such that the encapsulating material 225 can be pressed to spread across the interface substrate 105 (as indicated by the light horizontal arrow). In some embodiments, the encapsulating material 225 may be heated to promote the spreading of the encapsulating material 225 across the interface substrate 105.

[0041] In addition, the mold frame 310 includes a plurality of partitions 340 (also individually identified as 340a and 340b) extending from the top of the cavity 320 toward the interface substrate 105. Figure 3A Depicts a mold frame 310 including partitions 340a having a width W1, wherein each partition 340a corresponds to a reference. Figure 1 One of the dividing lines 115 between the stacks of the semiconductor dies 110 described. Figure 3A The image also depicts a separator 340b with a width W2 (different from the width W1), which corresponds to the reference. Figure 1 The peripheral region 120 of the described interface substrate 105. The spacer 340b can be merged with the inner sidewall of the cavity 320. It should be understood that, due to the spacers 340a and 340b, the cavity 320 has a smaller volume compared to the cavity 220 of the mold frame 210. Moreover, the total amount of encapsulating material 225 can be estimated to match the volume of the cavity 320. Therefore, the amount of encapsulating material 225 present in the cavity 320 is less than the amount of encapsulating material 225 present in the cavity 220, thereby mitigating wafer warpage during the molding process.

[0042] Figure 3B The encapsulation material 225 is pressed by the mold frame 310 so that the stack of semiconductor dies 110 is completely encapsulated within the encapsulation material 225. As the mold frame 310 presses the encapsulation material 225, the encapsulation material 225 can be opened through the space S between the stacks of semiconductor dies 110 (e.g., reference 1). Figure 1 The channels described along both the x and y directions are distributed across the interface substrate 105. Furthermore, the space S between the stacks of semiconductor dies 110 (corresponding to the dividing line 115) is partially extruded from the encapsulation material 225 due to the protruding separator 340a (if the encapsulation material 225 has already filled the space, such as...). Figure 2A (as depicted in the text) or partially occupies the space (if the encapsulating material 225 flows into the space) while being partially filled with the encapsulating material 225.

[0043] In this respect, the separator 340a has a length L, which is determined to position the end of the separator 340a at a distance D above the interface substrate 105, passing over the top die of the stack of semiconductor dies 110. In some embodiments, the distance D is determined such that the encapsulation material 225 is distributed across the interface substrate 105 through a gap corresponding to the distance D between the interface substrate 105 and the end of the separator 340a. The distance D can range from ten (10) to three hundred (300) micrometers. In some embodiments, a release film (e.g., referenced) Figure 5B The release film 565 described herein may be placed between the cavity 320 and the encapsulating material 225. The release film facilitates the release from the mold frame 310 of the stacked interface substrate 105 carrying the semiconductor die 110.

[0044] Figure 3C The description explains that after the mold frame 310 is removed (i.e., after the interface substrate 105 is released from the mold frame 310), the encapsulating material 225 covers (and surrounds) the stack of semiconductor dies 110 attached to the interface substrate 105. During this process, the surface 226 of the encapsulating material 225 has markings (e.g., trenches, grooves, indentations) left by the protruding spacers 340. Subsequently, the encapsulating material 225 can be cured at high temperature (e.g., cross-linked) to harden the encapsulating material 225 and provide protection for the stack of semiconductor dies 110. Wafer warpage is mitigated because the amount of encapsulating material 225 over the interface substrate 105 is less than that due to the protruding spacers 340 occupying a portion of the cavity 320 of the mold frame 310. Figure 2C The amount of the encapsulation material is 225.

[0045] Figure 3D The interface substrate 105 carries the stack of semiconductor dies 110 after the grinding process removes excess encapsulating material 225 above the stack of semiconductor dies 110 to expose the top die of the stack. In some embodiments, a portion of the top die may also be removed during the grinding process. Due to reduced warpage during the molding process based on the reduction in the amount of encapsulating material 225, wafer clamping problems are avoided (e.g., at the grinding process, the tool holds the interface substrate 105 by vacuum suction).

[0046] Figure 3E The interface substrate 105 carries a stack of semiconductor dies 110, separate from the support substrate 205 and placed on the mounting strip 230. Subsequently, individual semiconductor die assemblies 350 (i.e., the interface die 106 attached to the stack of semiconductor dies 110 and the encapsulation material 225 surrounding the stack of semiconductor dies 110) can be diced using one or more dicing process steps. In some embodiments, the dicing blade 235 can be used along a reference... Figure 1The described cleaving line 115 cuts the encapsulation material 225 and then the interface substrate 105. Furthermore, it should be understood that the distance the single-blade 235 moves to cut the individual semiconductor die assembly 350 is reduced (e.g., compared to...). Figure 2E (When the cutting distance is depicted in the diagram), this is because the space between the stacks of semiconductor dies 110 is partially filled by the encapsulating material 225 (e.g., when the space is completely filled by the encapsulating material 225, such as...). Figure 2E (Depicted in Chinese).

[0047] In an alternative embodiment, the mounting strip 230 may be positioned to contact the stack of semiconductor dies 110 (i.e., the interface substrate 105 carrying the stack of semiconductor dies 110 is rotated 180 degrees or "flipped"), such as Figure 3F The description continues. Subsequently, individual semiconductor die assemblies 350 can be individually diced using a single-cutting blade 235 along the reference. Figure 1 The described dividing line 115 cuts the interface substrate 105 and then cuts the encapsulation material 225.

[0048] refer to Figures 3A to 3F The described process can be considered to include aspects of molding, given that encapsulating material 225 is pressed into available space within the cavity 320 not occupied by the stack and spacers 340 of the semiconductor die 110. By reducing the volume of the cavity 320 and the amount of encapsulating material 225 during the molding process, wafer warpage can be reduced (mitigated). Furthermore, this technique facilitates the deployment of different encapsulating materials for the semiconductor die assembly 350—for example, molding compound materials with other advantages but a larger CTE.

[0049] While the foregoing description of this technology illustrates a single stack of semiconductor dies 110 between spacers 340, the technology is not limited thereto. For example, two or more stacks of semiconductor dies 110 may be positioned between spacers 340—e.g., 1x2, 2x2, 3x3, 1x2, 1x3, 2x3, etc. Furthermore, the mold frame 310 may include more than one opening (e.g., opening 315) to facilitate the injection of encapsulation material 225 into the cavity 320. In some embodiments, a single semiconductor die (rather than a stack of semiconductor dies 110) may be attached to the interface die 106.

[0050] Figure 4 This describes the stages of a process for forming a semiconductor die assembly according to embodiments of the present technology. Figure 4 illustrate Figure 3A They share largely similar characteristics. For example, Figure 4This is a cross-sectional view illustrating a support substrate 205 (e.g., a carrier wafer) that is temporarily bonded to a stacked interface substrate 105 that supports the attached semiconductor die 110. The interface substrate 105 may be referenced above. Figure 1 It was thinned as described. Moreover, Figure 4 The description may include references. Figure 3A The mold frame 310 described is an aspect of the mold frame 410. For example, the mold frame 410 includes a separator 440 (also individually identified as 440a and 440b) and a cavity 420.

[0051] Compared to the mold frame 310 configured to bring the cavity 320 toward the interface substrate 105, the mold frame 410 can be locked in a position above the interface substrate 105 such that the spacer 440a occupies a portion of the space between the stacks of semiconductor dies 110. Encapsulation material 225 can then be injected into the cavity 420, as indicated by the light-colored horizontal arrow. Once the encapsulation material 225 fills the available space within the cavity 420 not occupied by the stacks of semiconductor dies 110 and the spacer 440, the interface substrate 105 carrying the stacks of semiconductor dies 110 can be followed according to reference... Figures 3C to 3F The described process steps. Therefore, refer to... Figure 4 The molding process described can be considered to include aspects of the transfer molding process.

[0052] Figure 5A and 5B This describes a mold frame (which may be referred to as a mold enclosure) according to an embodiment of the present technology. Figure 5A The description may include references. Figure 3A and 4 The mold frame 510 is described as an aspect of the mold frame 310 and / or 410. The mold frame 510 includes a horizontal member 550 comprising an outer surface 551 and an inner surface 552 opposite to the outer surface 551. The mold frame 510 also includes a wall member 555 connected to a peripheral region of the inner surface 552. The wall member 555 has a first length (designated "L1") from the inner surface 552 and includes a cylindrical inner sidewall 556. The inner surface 552 of the horizontal member 550 and the inner sidewall 556 of the wall member 555 form a cavity 520, which is configured to cover a stack of semiconductor dies (e.g., a stack of semiconductor dies 110) attached to a substrate (e.g., an interface substrate 105). Furthermore, the inner surface 552 corresponding to the cavity 520 includes a group of protruding partitions 540 (also individually identified as 540a) having a second length (designated “L2”) from the inner surface 552, wherein the second length (L2) is less than the first length (L1).

[0053] In some embodiments, at least one of the protruding spacers 540 corresponds to a dividing line on the substrate—for example, dividing line 115 described with reference to FIG. 1. In some embodiments, at least one subgroup of the protruding spacers is arranged to intersect each other orthogonally to form a rectangular pattern (e.g., Figure 5C and 5D (The grid pattern depicted in the image). Furthermore, each rectangle of the pattern (or a single unit of the grid pattern) may correspond to a reference. Figure 5C and 5D A more detailed description of one or more semiconductor die stacks. In some embodiments, the inner surface 552 of the cavity 520, the inner sidewall 556 of the wall member 555, and the protruding spacers of the group are coated with a material having low surface energy (e.g., Paralyne).

[0054] In some embodiments, the inner surface 552 corresponding to the cavity 520 further includes at least one protruding spacer (e.g., 540c) having a third length (designated "L3") from the inner surface 552, wherein the third length (L3) is less than the second length (L2). In some cases, the third length (L3) may be determined to further facilitate the distribution of encapsulation material (e.g., encapsulation material 225) in a specific region of the substrate—for example, the central region of the interface substrate 105 where the encapsulation material is initially positioned, as shown in FIG3A. In some embodiments, the inner surface 552 corresponding to the cavity 520 further includes at least one protruding spacer reaching the surface of the substrate to which the semiconductor die is stacked and attached.

[0055] In some embodiments, at least one of the protruding spacers 540 has a width (denoted as "W") less than or equal to the width of a single-blade cutter (e.g., single-blade cutter 235). For example, if the interface die 106 has approximately the same width (or length) as the stack of semiconductor dies 110 (e.g., as in a FIP scheme), then maintaining the width of the protruding spacer less than or equal to the width of the single-blade cutter will help avoid increasing the width of the kerf. In other embodiments, at least one of the protruding spacers has a width greater than the width of the single-blade cutter (e.g., single-blade cutter 235). For example, if the interface die 106 has a greater width (or length) than the stack of semiconductor dies 110 (e.g., as in a FOP scheme), then the width of the protruding spacer may be greater than the width of the single-blade cutter, allowing for a reduction in the amount of encapsulation material above the interface substrate 105 (e.g., between the stacks of semiconductor dies 110).

[0056] In some embodiments, the mold frame 510 may be modified to include descriptions of the mold frame 511. Figure 5BThe opening 560 shown is illustrated in the figure. In this respect, a portion of the inner surface 522 corresponding to the rectangle (a unit of the grid pattern) of the pattern includes at least one opening 560 configured to provide vacuum suction for a release film 565 positioned within the rectangle. The release film 565 facilitates the release of a substrate carrying a stack of semiconductor dies after the encapsulation material has filled the cavity, as shown in the reference figure. Figure 3B And 3C description. In some embodiments, the release film 565 may be used with the mold frame 510 (e.g., without opening 560).

[0057] Figure 5C and 5D Semiconductor die assemblies 501 and 502 according to embodiments of the present technology are described respectively. Furthermore, Figure 5C and 5D Each describes a region of the stacked interface wafer that carries the semiconductor die 110 - for example, refer to Figure 1 The interface substrate 105 is described. Semiconductor die assemblies 501 and 502 may be referenced. Figure 3E and 3F Examples of the described semiconductor die assembly 350 or aspects comprising the semiconductor die assembly are described herein. For example, semiconductor die assemblies 501 and 502 each comprise a stack of semiconductor dies 110 attached to an interface die 106 and an encapsulant 570. The encapsulant 570 may have a first height (designated "H1") from the surface of the interface die 106, which may correspond to the height of the stack of semiconductor dies 110. As described herein, the encapsulant 570 may have different sidewall configurations based on different arrangements of mold frames with protruding spacers.

[0058] In some embodiments, the mold frame (e.g., mold frames 310, 410, 510, 511) includes protruding dividers, each corresponding to a dividing line (e.g., Figure 5C The dividing lines 115a in the x-direction and 115b in the y-direction are aligned such that the orthogonally intersecting protruding dividers form a grid pattern—for example, as shown in... Figure 5C The image depicts a grid pattern formed by protruding separators. Therefore, a single unit of the grid pattern corresponds to a single semiconductor die assembly (e.g., semiconductor die assembly 501). For example, Figure 5C A shaded segment 580 is depicted corresponding to one of the cells in the grid pattern, which includes a stacked semiconductor die assembly 501 having an interface die 106 and a semiconductor die 110.

[0059] In this manner, the semiconductor die assembly 501 has been referenced. Figure 3E and 3FAfter being diced as described, each of the four (4) sidewalls of the encapsulant 570 of the semiconductor die assembly 501 comprises: a first portion 571 (or lower segment) extending from the surface of the interface die 106 to a second height (denoted as "H2") less than the first height (H1); and a second portion 572 (or upper segment) extending from the second height to the first height. Furthermore, the first portion 571 may include a first surface texture formed by one or more dicing process steps for dicing the interface die 106 (and the encapsulant material between the semiconductor die stacks). In contrast, the second portion 572 may include a second surface texture formed through contact between the encapsulant 570 and a die frame (e.g., die frames 310, 410, 510, 511).

[0060] In alternative embodiments, the mold frame (e.g., mold frames 310, 410, 510, 511) includes protruding spacers aligned with a subset of the cutting lines such that a single cell of the grid pattern created by the orthogonally intersecting protruding spacers corresponds to more than one semiconductor die assembly (e.g., 1x2, 2x2, 1x3, 2x3, 3x3 semiconductor die assemblies or the like). For example, Figure 5D A subset of the dividing lines aligned with the protruding separators (e.g., dividing lines 115a-1 and 115b-1) is depicted with solid lines, and a subset of other dividing lines not present in the protruding separators (e.g., dividing lines 115a and 115b) is depicted with dashed lines. Thus, one of the cells in the grid pattern corresponds to the six (6) semiconductor die assemblies contained in the shaded segment 581. Figure 5D The semiconductor die assembly 502 corresponds to one of such semiconductor die assemblies.

[0061] When the semiconductor die assembly is cut along the dividing line 115a-1 or 115b-1, the cutting blade 235 cuts off the encapsulation material occupying the space between the semiconductor die assemblies, as shown in the reference. Figure 3E and 3F Description. However, when the semiconductor die assembly is cut individually along the dividing lines 115a or 115b (i.e., the cutting lines of the corresponding protruding dividers without a mold frame), the cutting blade 235 cuts off the encapsulation material that completely occupies the space between the semiconductor die assemblies, as referenced. Figure 2E Description. In this manner, the semiconductor die assembly may have an encapsulant (e.g., encapsulant 570 of semiconductor die assembly 502) having sidewalls with different configurations.

[0062] For example, in addition to a first sidewall comprising a first portion 571 (or lower segment) and a second portion 572 (or upper segment) similar to a semiconductor die assembly 502, the semiconductor die assembly 502 also includes a second sidewall extending vertically upward from the interface die 106 to a first height (H1). The second sidewall may have a first surface texture formed by one or more single-cutting process steps for single-cutting the interface die 106 (and the encapsulation material between the semiconductor die stacks). The first and second sidewalls may not be in the same plane. In other words, the first sidewall is in a first plane, and the second sidewall is in a second plane different from the first plane.

[0063] Figure 6 This is a semiconductor die assembly 600 according to an embodiment of the present technology. The semiconductor die assembly 600 may be referenced. Figure 3E , 3F Examples of semiconductor die assemblies 350, 501, or 502 described in 5C and 5D, or aspects including said semiconductor die assemblies. For example, semiconductor die assembly 600 includes an interface die (e.g., interface die 106) and a stack of semiconductor dies (e.g., a stack of semiconductor dies 110) attached to the surface of the interface die. In some embodiments, interface die 106 corresponds to a logic die or an interposer die, and the stacked semiconductor dies correspond to memory dies (e.g., DRAM dies).

[0064] The semiconductor die stack has a first height (denoted as "H1") from the surface of the interposer die. The semiconductor die assembly 600 also includes an encapsulant 670 (e.g., encapsulating material 225) above and surrounding the semiconductor die stack. The total height of the encapsulant 670 may be determined by reference to... Figure 3D The described grinding process corresponds to a first height from the surface. Furthermore, the encapsulant 670 includes sidewalls 660 having a first portion 671 (or lower segment) extending from the surface to a second height (denoted as "H2") less than the first height (H1) and a second portion 672 (or upper segment) extending from the second height to the first height. Although for the sake of clarity illustrating the general features of this technology, Figure 6 The sidewalls of the encapsulating agent 670 are described as straight, but... Figure 6 Schematic diagrams 601 to 603 depict further details of the side view of the sidewall 660 to describe the features of the first and second parts (lower and upper sections).

[0065] Schematic diagram 601 can correspond to Figure 3EThe semiconductor die assembly 350 is depicted in the diagram, wherein an interface substrate 105 is attached to a mounting tape 230 when a cleaver 235 cleaves the semiconductor die assembly 350. Schematic diagram 601 illustrates that the cleaver 235 cuts the encapsulating agent 670 (e.g., encapsulating material 225) between the stacks of semiconductor dies 110 and then cuts the interface substrate 105 to cleave the interface die 106 (and thus cleave the semiconductor die assembly 600). As depicted in schematic diagram 601, when the cleaving process is complete, the cleaver 235 leaves the second portion 672 unchanged.

[0066] Schematic diagram 602 can correspond to Figure 3F The semiconductor die assembly 350 is depicted in the diagram, wherein a stack of semiconductor dies 110 is attached to a mounting tape 230 when a cleaver 235 cleaves the semiconductor die assembly 350. Schematic diagram 602 illustrates that the cleaver 235 cuts the interface substrate 105 and then cuts the encapsulating agent 670 (e.g., encapsulating material 225) between the stacks of semiconductor dies 110 to cleave the interface die 106 (and thus cleave the semiconductor die assembly 600). As depicted in schematic diagram 602, when the cleaving process is complete, the cleaver 235 leaves the second portion 672 unchanged.

[0067] Similarly, schematic diagram 603 can correspond to Figure 3F The semiconductor die assembly 350 depicted in the image includes a stack of semiconductor dies 110 attached to a mounting strip 230 when a cleaver 235 cleaves the assembly 350 individually. The cleaver 235 (formed from the reference image) Figure 3D The described groove or trench offset in the encapsulation material 225 cuts the interface substrate 105 and then cuts the encapsulation 670 (e.g., encapsulation material 225) between the stacks of semiconductor dies 110 to single-cut the interface die 106 (and thus single-cut the semiconductor die assembly 600). Since the cutting is completed when the encapsulation material 225 between the stacks of semiconductor dies 110 is removed, the cutting blade 235 leaves the second portion 672 unchanged.

[0068] In this manner, the sidewall 660 of the encapsulating agent 670 has a lower section (e.g., a first portion 671) extending from the surface to a second height (e.g., H2) less than a first height (e.g., H1) and an upper section (e.g., a second portion 672) extending from the second height to the first height. Furthermore, the lower section may have a first surface texture (e.g., surface finishing, surface roughness, etc.), and the upper section may have a second surface texture different from the first surface texture. As depicted in schematic diagrams 601 to 603, the lower section is in a first plane and the upper section is in a second plane different from the first plane and parallel to the first plane.

[0069] As described herein, the first surface texture can be formed through one or more single-cutting process steps for single-cutting the interface die (and for cutting the encapsulation material 225 between adjacent stacks of semiconductor die 110), and the second surface texture can be formed through contact between a die frame (e.g., die frames 310, 410, 510, 511) and the encapsulant 670. Thus, the second surface texture can exhibit a relatively cleaner die frame imprint (or embossing) than the first surface texture, which can exhibit a relatively rougher trace from the cleaving blade 235 cutting the encapsulant 670. In this way, the second surface texture can generally be smoother than the first surface texture. Furthermore, when the cleaving blade 235 cuts the first portion 671 of the encapsulant 670 along with the interface die 106, the first portion 671 (lower segment) of the encapsulant 670 is aligned with the edge of the interface die 106.

[0070] refer to Figure 3E , 3F The semiconductor die assemblies 350, 501, 502, and 600 described in 5C, 5D, and 6 can be incorporated into any of numerous larger and / or more complex systems, with representative examples being... Figure 7 The system 770 is schematically shown in the diagram. System 770 may include semiconductor die assemblies 350, 501, 502, or 600, a power supply 772, a driver 774, a processor 776, and / or other subsystems or components 778. Semiconductor die assemblies 350, 501, 502, or 600 may include features generally similar to the wafer warp reduction features described above. In other words, semiconductor die assemblies 350, 501, 502, or 600 include an encapsulant having at least one sidewall with two portions having different surface finishes (e.g., surface roughness). The resulting system 770 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative systems 770 may include (unlimited) handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, and appliances. The components of system 770 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of system 770 may also include remote devices and any of a variety of computer-readable media.

[0071] Figure 8 This is a flowchart 800 of a method for forming a semiconductor die assembly (e.g., semiconductor die assembly 350 or 600) according to embodiments of the present technology. Flowchart 800 may include references to... Figures 3A to 3F Aspects of the described method.

[0072] The method includes attaching a semiconductor die stack to an interface substrate, the semiconductor die stack being aligned with a scribe line of the interface substrate (block 810). The method further includes positioning a mold frame over the semiconductor die stack such that the semiconductor die stack is enclosed within a cavity of the mold frame, wherein an inner surface of the mold frame corresponding to the cavity includes a group of protruding spacers extending from the inner surface toward the interface substrate (block 815). The method further includes applying an encapsulant through the mold frame onto the interface substrate and the semiconductor die stack such that the encapsulant fills a space between the stacks corresponding to a scribe line (block 820). The method further includes displacing at least a portion of the encapsulant from the space (block 825).

[0073] In some embodiments, displacing at least said portion of the encapsulant comprises pressing a mold frame toward an interface substrate such that protruding spacers expel at least said portion of the encapsulant from the space. In some embodiments, the method further comprises placing a release film between the cavity and the encapsulant, wherein the protruding spacers are arranged to intersect each other orthogonally to form patterns corresponding to rectangles of one or more semiconductor die stacks, and portions of the inner surface of the rectangles corresponding to the patterns include at least one opening configured to provide vacuum suction to the release film.

[0074] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined. Moreover, it should be understood that specific embodiments of the technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure.

[0075] The devices discussed herein (including semiconductor devices) can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0076] As used herein, the word "or" in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") encompasses the contents of the claims, indicating an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0077] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details are set forth in the foregoing description to provide a thorough and feasible description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations commonly associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are also within the scope of the present technology.

Claims

1. A semiconductor die assembly comprising: Interface bare die; A semiconductor die attached to the surface of the interface die, the semiconductor die having a first height from the surface; and An encapsulating agent is disposed on the surface and surrounding the semiconductor die, the encapsulating agent comprising an outer wall having: A lower segment in the first plane, extending from the surface to a second height less than the first height, the lower segment having a first surface texture; and An upper segment in a second plane, different from and parallel to the first plane, extending from the second height to the first height, the upper segment having a second surface texture different from the first surface texture, wherein the distance between the second plane and the center of the semiconductor die assembly is greater than the distance between the first plane and the center of the semiconductor die assembly. The first surface texture is formed by one or more single-cutting process steps for single-cutting the interface die, and the second surface texture is formed by contact between a mold frame and the encapsulating agent, wherein the inner surface of the mold frame includes a group of protruding separators extending from the inner surface toward the interface die.

2. The semiconductor die assembly of claim 1, wherein the outer sidewall is a first sidewall of the encapsulating agent, the encapsulating agent further comprising: A second sidewall extends from the surface to the first height, and the second sidewall has the texture of the first surface.

3. The semiconductor die assembly according to claim 2, wherein: The first sidewall is in the first plane; and The second sidewall is in a second plane that is different from the first plane.

4. The semiconductor die assembly of claim 1, wherein the second surface texture is generally smoother than the first surface texture.

5. The semiconductor die assembly of claim 1, wherein the lower segment is aligned with the edge of the interface die.

6. The semiconductor die assembly according to claim 1, wherein: The interface die corresponds to a logic die or an intermediary layer die; and The semiconductor die corresponds to the memory die.

7. A method comprising: A stack of semiconductor dies is attached to the surface of an interface substrate, the stack of semiconductor dies being aligned with the cleavage of the interface substrate; The mold frame is positioned on the semiconductor die stack such that the semiconductor die stack is enclosed within a cavity of the mold frame, wherein the inner surface of the mold frame corresponding to the cavity includes a group of protruding spacers extending from the inner surface toward the interface substrate; Encapsulating agent is applied to the interface substrate and the semiconductor die stack via the mold frame, such that the encapsulating agent fills the space between the stacks, the space corresponding to the dicing path; wherein the encapsulating agent includes an outer wall, the outer wall having: A lower segment in the first plane, extending from the surface to a second height less than the first height, the lower segment having a first surface texture; and An upper segment in a second plane, different from and parallel to the first plane, extending from the second height to the first height, has a second surface texture different from the first surface texture. The first surface texture is formed by one or more single-cutting process steps for single-cutting the interface substrate, and the second surface texture is formed by the contact between the mold frame and the encapsulating agent. The distance between the second plane and the center of the semiconductor die assembly is greater than the distance between the first plane and the center of the semiconductor die assembly; and At least a portion of the encapsulating agent is displaced from the space.

8. The method of claim 7, wherein displacing at least a portion of the encapsulating agent comprises: Pressing the mold frame toward the interface substrate causes the protruding separator to expel at least the portion of the encapsulating agent from the space.

9. The method of claim 7, further comprising: The release film is placed between the cavity and the encapsulating agent, wherein: The protruding spacers are arranged to intersect each other orthogonally to form a rectangular pattern corresponding to one or more semiconductor die stacks; and The portion of the inner surface of the rectangle corresponding to the pattern includes at least one opening configured to provide vacuum suction to the release film.

Images