Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: providing a first substrate, the first substrate including opposite first and second surfaces; forming a first device layer on the first surface of the first substrate, the first device layer including a device structure and a plurality of first electrical interconnect layers located on the device structure and electrically interconnected with the device structure; forming an interconnect structure in the first substrate; after forming the interconnect structure, forming a second device layer on the second surface, the second device layer including a plurality of second electrical interconnect layers, any one of the second electrical interconnect layers being electrically connected to any one of the first electrical interconnect layers through the interconnect structure; forming a dielectric layer on the second device layer and an opening in the dielectric layer, the opening exposing a part of the topmost second electrical interconnect layer; forming a solder pad in the opening. It can improve the signal transmission speed, generate more design solutions, and optimize the logic circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] The rapid development of integrated circuit (IC) technology has put forward higher requirements for metal interconnect technology. The traditional Al metal interconnect technology can no longer meet the needs of the development of modern interconnect technology. Metal interconnect refers to forming connections through conductive materials to connect different devices according to the design requirements to form a complete circuit and system. At the same time, it can also transmit external electrical signals to different parts inside the chip, thereby forming a chip with certain functions.

[0003] With the improvement of integration, metal interconnect technology has also developed from simple to complex and from single-layer to multi-layer. In large-scale integrated circuits, two-layer and above metal wirings have been widely used. As the number of metal wiring layers increases, metal interconnect occupies a quite large area of the chip, which is often the main contradiction restricting the current speed.

[0004] In summary, the existing metal interconnect process needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a first substrate, the first substrate including opposite first and second surfaces; a first device layer on the first surface of the first substrate, the first device layer including a device structure and a plurality of first electrical interconnect layers located on the device structure and electrically interconnected with the device structure; a second device layer on the second surface, the second device layer including a plurality of second electrical interconnect layers; an interconnect structure in the first substrate, the interconnect structure being electrically interconnected with any one of the first electrical interconnect layers and the second electrical interconnect layers respectively; a dielectric layer on the second device layer and an opening in the dielectric layer, the opening exposing a part of the topmost second electrical interconnect layer; and a solder pad in the opening.

[0007] Optionally, the interconnect structure includes a first conductive plug, the first conductive plug being located in the first substrate, and electrically interconnecting any one of the first electrical interconnect layers and the second electrical interconnect layer through the first conductive plug.

[0008] Optionally, the device structure includes one or more combinations of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure.

[0009] Optionally, it further includes a second substrate bonded to the surface of the first device layer of the first substrate.

[0010] Optionally, the surface of the second substrate has an oxide layer, and the oxide layer is located between the second substrate and the first substrate.

[0011] The technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a first substrate, the first substrate including an opposite first surface and a second surface; forming a first device layer on the first surface of the first substrate, the first device layer including a device structure and several first electrical interconnection layers located on the device structure and electrically interconnected with the device structure; forming an interconnection structure in the first substrate; after forming the interconnection structure, forming a second device layer on the second surface, the second device layer including several second electrical interconnection layers, and any one of the second electrical interconnection layers is electrically connected to any one of the first electrical interconnection layers through the interconnection structure; forming a dielectric layer and an opening located in the dielectric layer on the second device layer, the opening exposing a part of the topmost second electrical interconnection layer; forming a solder pad in the opening.

[0012] Optionally, the interconnection structure includes a first conductive plug.

[0013] Optionally, the method for forming the interconnection structure includes: forming a first conductive plug in the first substrate, and the first conductive plug is located on the surface of any one of the first electrical interconnection layers.

[0014] Optionally, a second substrate is also provided. Before forming the interconnection structure, it further includes: bonding the first substrate to the second substrate through the surface of the first device layer.

[0015] Optionally, before forming the interconnection structure, the first surface of the first substrate is oriented towards the second substrate for bonding; after bonding, the first substrate is thinned from the second surface to the first surface to a target thickness value.

[0016] Optionally, before performing the bonding, it further includes: forming an oxide layer on the surface of the second substrate; bonding the surface of the first device layer and the surface of the oxide layer.

[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0018] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first device layer is formed on the first surface of the first substrate. The first device layer includes a device structure and a plurality of first electrical interconnection layers located on the device structure and electrically interconnected with the device structure. An interconnection structure is formed in the first substrate. After forming the interconnection structure, a second device layer is formed on the second surface. The second device layer includes a plurality of second electrical interconnection layers, and any one of the second electrical interconnection layers is electrically connected to any one of the first electrical interconnection layers through the interconnection structure. It can change the single transmission path in which the signal starts to be transmitted from the top electrical interconnection layer and finally reaches the device structure, improve the signal transmission speed, and at the same time, more design schemes can be generated to optimize the logic circuit.

[0019] In the semiconductor structure provided by the technical solution of the present invention, the interconnection structure located in the first substrate is electrically interconnected with any one of the first electrical interconnection layers and the second electrical interconnection layer respectively. It can change the single transmission path in which the signal starts to be transmitted from the top electrical interconnection layer and finally reaches the device structure, improve the signal transmission speed, and at the same time, more design schemes can be generated to optimize the logic circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic cross-sectional view of a semiconductor structure;

[0021] Figures 2 to 8 is a schematic structural view of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0023] As described in the background art, the existing metal interconnection process needs to be further improved. The formation process of a semiconductor structure is now described and analyzed in combination.

[0024] Figure 1 is a schematic cross-sectional view of a semiconductor structure.

[0025] Please refer to Figure 1 , the semiconductor structure includes: a substrate, the substrate includes a substrate 101 and a device structure 102 on the surface of the substrate 101; a dielectric layer 103 located on the surface of the substrate, the dielectric layer 103 has multiple metal layers, the metal layers include a first metal layer 104, a second metal layer 105, a third metal layer 106 and a top metal layer 107, and between each metal layer and between the first metal layer 104 and the device structure 102 are electrically connected through conductive plugs 108, and the top metal layer 107 is located at the topmost end of the semiconductor structure.

[0026] In the above structure, the top metal layer 107 is used to transmit external electrical signals to different parts inside the chip. The electrical signals need to be transmitted through the top metal 107 to the third metal layer 106, the second metal layer 105, and finally to the first metal layer 104. The signal transmission speed direction is relatively single, and it cannot be directly transmitted from the top metal 107 to the first metal layer 104, which will cause the signal transmission speed to slow down.

[0027] To solve the above problems, in a method for a semiconductor structure provided by the present invention, a first device layer is formed on the first surface of the first substrate. The first device layer includes a device structure; an interconnect structure is formed in the first substrate; after forming the interconnect structure, a second device layer is formed on the second surface. The second device layer includes several second electrical interconnect layers, and any one of the second electrical interconnect layers is electrically connected to any one of the first electrical interconnect layers through the interconnect structure. It can change the single transmission path where the signal starts to be transmitted from the top electrical interconnect layer and finally reaches the device structure, improve the signal transmission speed, and at the same time, more design schemes can be generated to optimize the logic circuit.

[0028] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0029] Figures 2 to 8 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0030] Please refer to Figure 2 , a first substrate 201 is provided. The first substrate 201 includes opposite first surface 201a and second surface 201b.

[0031] In this embodiment, the material of the first substrate 201 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0032] In this embodiment, a second substrate 301 is also provided.

[0033] In this embodiment, the material of the second substrate 301 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0034] Subsequently, the second substrate 301 is used to bond with the first substrate 201 as a support substrate for the formed device.

[0035] In this embodiment, before the bonding, an oxide layer 302 is further formed on the surface of the second substrate 301.

[0036] Please refer toFigure 3 On the first surface 201a of the first substrate 201, a first device layer 202 is formed. The first device layer 202 includes a device structure 203 and a plurality of first electrical interconnection layers 204 located on the device structure 203 and electrically interconnected with the device structure 203.

[0037] In this embodiment, between different first electrical interconnection layers 204, they are electrically interconnected through second conductive plugs 300 according to actual circuit design requirements.

[0038] In this embodiment, the first electrical interconnection layer 204 has a three-layer structure. In other embodiments, the number of layers of the first electrical interconnection layer 204 can be adjusted according to actual circuit design needs, so no requirements are made for the number of layers of the first electrical interconnection layer 204.

[0039] The material of the first electrical interconnection layer 204 includes metal, and the metal includes one or a combination of more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0040] Specifically, the first device layer 202 is located in a first dielectric layer 205, and the first dielectric layer 205 is used for electrical insulation between the device structures 203 and between the first electrical interconnection layers 204.

[0041] The material of the first dielectric layer 205 includes dielectric materials, and the dielectric materials include one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first dielectric layer 205 is silicon oxide.

[0042] The device structure 203 includes one or a combination of more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure. It should be noted that in this embodiment, the specific structure of the device structure 203 is not shown.

[0043] Subsequently, an interconnection structure is formed in the first substrate 200; after forming the interconnection structure, a second device layer is formed on the second surface 200b. The second device layer includes a plurality of second electrical interconnection layers, and any one of the second electrical interconnection layers is electrically connected to any one of the first electrical interconnection layers 204 through the interconnection structure.

[0044] Please refer to Figure 4 , before forming the interconnection structure, it further includes: bonding the first substrate 201 to the second substrate 301 through the surface of the first device layer 202.

[0045] Specifically, bond the first surface 201a of the first substrate 201 to the second substrate 301.

[0046] More specifically, bond the surface of the first device layer 202 and the surface of the oxide layer 302.

[0047] Please refer to Figure 5 , after bonding, thin the first substrate 201 from the second surface 201b to the first surface 201a to a target thickness value.

[0048] Subsequently, form a second device layer on the second surface 201b. In this embodiment, specifically, form a second device layer on the thinned second surface 201b. The thinning process is used to make the first substrate 201 reach the target thickness value. If the target thickness value is too high, it is not conducive to forming an interconnect structure in the first substrate 100 subsequently. If the target thickness value is too thin, it is not conducive to forming a good isolation between the first device layer 202 and the subsequently formed second device layer.

[0049] Please refer to Figure 6 , form an interconnect structure in the first substrate 201.

[0050] Specifically, when forming the interconnect structure, for ease of operation, it is necessary to invert the structure, that is, the second substrate 301 is located below the first substrate 201.

[0051] In this embodiment, the interconnect structure includes a first conductive plug 206, and the first conductive plug 206 is located on the surface of the first electrical interconnect layer 204 closest to the first substrate 201. In another embodiment, the first conductive plug 206 can be located on the surface of any of the first electrical interconnect layers 204.

[0052] The method for forming the interconnect structure includes: forming a first conductive plug 206 in the first substrate 201, and the first conductive plug 206 is located on the surface of any of the first electrical interconnect layers.

[0053] Subsequently, after forming the interconnect structure, form a second device layer on the second surface 201b. The second device layer includes several layers of second electrical interconnect layers, and any of the second electrical interconnect layers is electrically connected to any of the first electrical interconnect layers 204 through the interconnect structure.

[0054] Please refer to Figure 7 , after forming the interconnect structure, form a second device layer on the second surface 201b. The second device layer includes several layers of second electrical interconnect layers 207, and any of the second electrical interconnect layers 207 is electrically connected to any of the first electrical interconnect layers 204 through the interconnect structure 206.

[0055] By forming the first device layer 202 and the second device layer on the opposite two sides of the first substrate 201 respectively, and electrically connecting the first device layer 202 and the second device layer through the interconnect structure 206, the single transmission path in which the signal starts to be transmitted from the top-layer electrical interconnect layer and finally reaches the device structure can be changed, the signal transmission speed can be increased, and at the same time, more design schemes can be generated to optimize the logic circuit.

[0056] Between different first electrical interconnect layers 204, they are electrically interconnected through the third conductive plug 303 according to the actual circuit design requirements.

[0057] In this embodiment, the second electrical interconnect layer 207 closest to the first substrate 201 is electrically connected to the first electrical interconnect layer 204 closest to the first substrate through the interconnect structure 206. In other embodiments, any second electrical interconnect layer 207 is electrically connected to any first electrical interconnect layer 204 through the interconnect structure 206. The single transmission path in which the signal starts to be transmitted from the top-layer electrical interconnect layer and finally reaches the bottom-layer electrical interconnect layer closest to the substrate can be changed, the signal transmission speed can be increased, and at the same time, more design schemes can be generated to optimize the logic circuit.

[0058] The material of the second electrical interconnect layer 207 includes metal, and the metal includes one or a combination of more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0059] The number of the second electrical interconnect layers 207 is related to the circuit design and is not specifically limited here. In this embodiment, the second electrical interconnect layer 207 is two layers.

[0060] The second device layer further includes a second dielectric layer 208, and the second electrical interconnect layer 207 is located within the second dielectric layer 208. The second dielectric layer 208 is used for electrical insulation between different second electrical interconnect layers 207 and between the second electrical interconnect layer 207 and the substrate 201.

[0061] The material of the second dielectric layer 208 includes dielectric materials, and the dielectric materials include one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second dielectric layer 208 is silicon oxide.

[0062] In this embodiment, the second dielectric layer 208 exposes the surface of the topmost second electrical interconnect layer 207 to prepare for subsequent electrical interconnection between the second electrical interconnect layer 207 and an external circuit.

[0063] Please refer to Figure 8, a dielectric layer 209 and an opening (not marked in the figure) located within the dielectric layer 209 are further formed on the second device layer, and the opening exposes a part of the topmost second electrical interconnection layer 207; a solder pad 210 is formed within the opening.

[0064] The formed semiconductor structure is electrically interconnected with an external circuit through the solder pad 210.

[0065] The material of the dielectric layer 209 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 209 includes silicon oxide.

[0066] The material of the solder pad 210 includes a metal, and the metal includes one or a combination of more of copper, aluminum, tungsten, cobalt, nickel, and tantalum. In this embodiment, the material of the solder pad 210 is aluminum.

[0067] In this embodiment, a connection layer 211 is further formed on the surface of the solder pad 210. The connection layer 211 is used to interconnect the solder pad 210 with an external circuit through a connection wire in a subsequent wire bonding process.

[0068] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above forming method. Please continue to refer to Figure 8 , including: a first substrate 201, the first substrate 201 includes opposite first and second surfaces 201a and 201b; a first device layer 202 located on the first surface 201a of the first substrate 201, the first device layer 202 includes a device structure 203 and several layers of first electrical interconnection layers 204 located on the device structure 203 and electrically interconnected with the device structure 203; a second device layer located on the second surface 201b, the second device layer includes several layers of second electrical interconnection layers 207; an interconnection structure located within the first substrate 201, the interconnection structure is electrically interconnected with any one of the first electrical interconnection layers 204 and the second electrical interconnection layers 207 respectively; a dielectric layer 209 located on the second device layer and an opening (not marked in the figure) within the dielectric layer 209, the opening exposes a part of the topmost second electrical interconnection layer 207; a solder pad 210 located within the opening.

[0069] In this embodiment, the device structure 203 includes one or a combination of more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure.

[0070] Through the semiconductor structure, the single transmission path of the signal starting from the top-layer electrical interconnection layer and finally reaching the device structure can be changed, improving the signal transmission speed. At the same time, more design schemes can be generated to optimize the logic circuit.

[0071] The interconnection structure includes a first conductive plug 206 located in the first substrate 201, and any one of the first electrical interconnection layers 204 and the second electrical interconnection layer 207 is electrically interconnected through the first conductive plug 206.

[0072] The semiconductor structure further includes: a second substrate 301 bonded to the surface of the first substrate 201 on the first device layer 202.

[0073] In this embodiment, the surface of the second substrate 301 has an oxide layer 302, and the oxide layer 302 is located between the second substrate 301 and the first substrate 201. Specifically, the oxide layer 302 is located between the second substrate 301 and the first device layer 202.

[0074] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, it comprises: a first substrate, the first substrate comprising opposite first and second surfaces; a first device layer located on the first surface of the first substrate, the first device layer comprising a device structure and a plurality of first electrical interconnect layers located on and electrically interconnected with the device structure; a second device layer located on the second surface, the second device layer comprising a plurality of second electrical interconnect layers; an interconnect structure located within the first substrate, the interconnect structure comprising a first conductive plug located on the surface of any one of the first electrical interconnect layers to electrically interconnect any one of the first electrical interconnect layers and the second electrical interconnect layers; a dielectric layer located on the second device layer and an opening within the dielectric layer, the opening exposing a portion of the topmost second electrical interconnect layer; a pad located within the opening.

2. The semiconductor structure according to claim 1, characterized in that, the device structure comprises one or a combination of more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure.

3. The semiconductor structure according to claim 1, characterized in that, it further comprises a second substrate bonded to the first substrate on the surface of the first device layer.

4. The semiconductor structure according to claim 3, characterized in that, the surface of the second substrate has an oxide layer, and the oxide layer is located between the second substrate and the first substrate.

5. A method for forming a semiconductor structure, characterized in that, it comprises: providing a first substrate, the first substrate comprising opposite first and second surfaces; forming a first device layer on the first surface of the first substrate, the first device layer comprising a device structure and a plurality of first electrical interconnect layers located on and electrically interconnected with the device structure; forming an interconnect structure within the first substrate, the interconnect structure comprising a first conductive plug located on the surface of any one of the first electrical interconnect layers; after forming the interconnect structure, forming a second device layer on the second surface, the second device layer comprising a plurality of second electrical interconnect layers, and any one of the second electrical interconnect layers is electrically connected to any one of the first electrical interconnect layers through the interconnect structure; forming a dielectric layer on the second device layer and an opening within the dielectric layer, the opening exposing a portion of the topmost second electrical interconnect layer; forming a pad within the opening.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, the method for forming the interconnect structure comprises: forming a first conductive plug within the first substrate, the first conductive plug being located on the surface of any one of the first electrical interconnect layers.

7. The method for forming a semiconductor structure according to claim 5, characterized in that, a second substrate is further provided, and before forming the interconnect structure, it further comprises: bonding the first substrate to the second substrate through the surface of the first device layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, Before forming the interconnect structure, bond the first surface of the first substrate to the second substrate; after bonding, thin the first substrate from the second surface to the first surface to a target thickness value.

9. The method for forming a semiconductor structure according to claim 8, wherein, before performing the bonding, further comprising: forming an oxide layer on the surface of the second substrate; bonding the surface of the first device layer and the surface of the oxide layer.

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