Parallel testing method for semiconductor wafers and multiple chips

Abstract

The present invention provides a method for parallel testing of a semiconductor wafer and multiple chips. The semiconductor wafer includes multiple chips, multiple test pads, and a test control circuit. The multiple test pads receive multiple test signals from a test fixture. The test control circuit electrically connects the chips and the test pads, selects at least one selected test signal from the test signals, generates multiple broadcast test signals based on the selected test signal, and provides these broadcast test signals in parallel to the multiple chips.

Description

Technical Field

[0001] The present invention relates to a wafer test, and in particular to a semiconductor wafer and chip testing method suitable for testing a plurality of chips in parallel. Background Art

[0002] Before integrated circuit chips are packaged, each chip in the wafer must be subjected to a chip probe (CP) test procedure to filter out defective chips, thereby reducing production costs. The CP test procedure utilizes the probes of a test fixture (such as a probe card) to contact the test pads (such as solder pads or bumps) on the wafer to transmit the test signal to the chip through the probe, thereby testing the electrical function of the chip. With the advancement of semiconductor technology, the number of chips on a single wafer has increased, but this has also led to a relative increase in the time and cost required for CP testing of each wafer. Currently, some testing methods have been proposed to reduce testing costs, such as reducing testing time by increasing the number of parallel tests. The basic concept of increasing the number of parallel tests is to provide the same test signal to multiple chips on the wafer so as to test multiple chips at the same time.

[0003] Figure 1 A schematic diagram of a conventional chip testing system is shown. Conventional test system 10 includes a test machine 110 and a test fixture 120. This system increases the number of parallel tests performed by improving test fixture 120. Specifically, the drive signal generated by test machine 110 is limited. However, by designing signal sharing circuits on test fixture 120, a single drive test signal DR1 can be expanded into n test signals DR1_1 through DR1_n that are provided to multiple chips 130_1 through 130_n. These n test signals DR1_1 through DR1_n are then provided to chips 130_1 through 130_n via probes on test fixture 120.

[0004] However, this method of expanding a single drive test signal DR1 into multiple test signals DR1_1-DR1_n using the test fixture 120 requires sacrificing signal integrity. As the number of test signals DR1_1-DR1_n increases, the frequency of the test signals DR1_1-DR1_n decreases, and their rising / falling times increase, thereby slowing down the test speed. Furthermore, if the test signal input terminal of one of the chips 130_1-130_n is connected to a short-circuit path or a leakage current path, it will interfere with other test signals, thereby affecting the test results of other chips and causing an overkill problem. For example, if one of the chips 130_1-130_n is an ugly die located at the edge of the wafer, one of the test signals DR1_1-DR1_n may short-circuit to the reference voltage or couple to a leakage current path, thereby interfering with other test signals. To reduce interference between test signals, the signal sharing circuit of the existing test fixture 120 is configured with multiple isolation resistors R1-Rn. However, if the resistance of the isolation resistors R1 - Rn is designed to be too small, the anti-interference capability will be poor. If the resistance of the isolation resistors R1 - Rn is designed to be too large, the signal frequency of the test signals DR1_1 - DR1_n will be reduced and the test speed will be slowed down. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor wafer and chip testing method, which can improve test accuracy and reduce test costs.

[0006] An embodiment of the present invention provides a semiconductor wafer comprising a plurality of chips, a plurality of test pads, and a test control circuit. The plurality of test pads receive a plurality of test signals from a test fixture. The test control circuit electrically connects the chips and the test pads, selects at least one selected test signal from the test signals, generates a plurality of broadcast test signals based on the selected test signal, and provides these broadcast test signals in parallel to the plurality of chips.

[0007] An embodiment of the present invention provides a multi-chip parallel testing method, comprising the following steps: A plurality of test pads receive a plurality of test signals from a test fixture; a test control circuit formed on a semiconductor wafer selects at least one selected test signal from the test signals; and the test control circuit generates a plurality of broadcast test signals based on the selected test signal and provides these broadcast test signals in parallel to the plurality of chips.

[0008] Based on the above, in an embodiment of the present invention, a test control circuit formed on a semiconductor wafer can, after receiving multiple test signals generated by a tester, select uninterrupted test signals and, based on the selected test signals, generate multiple broadcast test signals for parallel distribution to multiple chips. This allows multiple chips on the semiconductor wafer to be tested in parallel based on their respective received broadcast test signals, thereby improving test efficiency and reducing the possibility of misjudgment. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Shown is a schematic diagram of an existing chip testing system;

[0010] Figure 2 is a top view schematically showing a semiconductor wafer according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a chip testing system according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of a chip testing system according to an embodiment of the present invention;

[0013] Figure 5 is a block diagram of a test control circuit according to an embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of a test control circuit formed on a dicing street according to an embodiment of the present invention;

[0015] Figure 7 is a schematic diagram of a chip test area and a plurality of test pads according to an embodiment of the present invention;

[0016] Figure 8 is a flow chart of a chip testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Please refer to Figure 2 In one embodiment of the present invention, a semiconductor wafer 20 includes a plurality of chips 22, a plurality of test pads 26, and a test control circuit 28. In some embodiments, the semiconductor wafer 20 is separated along scribe lines 24 by a wafer dicing process to separate the chips 22 from each other. The semiconductor wafer 20 can be made of silicon or other semiconductor materials. The chips 22 can include logic circuits, memory circuits, analog component circuits, the like, or a combination thereof, but the present invention is not limited thereto. For example, the chips 22 can be dynamic random access memory chips.

[0019] In some embodiments, the test pad 26 may be disposed within the cutting path 24. The material of the test pad 26 is a metal material, such as aluminum, aluminum alloy, or a combination thereof. The test pad 26 may be interconnected with the metal circuit layer within the semiconductor wafer 20, so that the test pad 26 can be electrically connected to the components within the chip 22. The test fixture of the test machine (such as the probe on the probe card) can contact the corresponding test pad 26 of the semiconductor wafer 20 to perform electrical testing on the chip 22. In other words, the test pad 26 can receive the test signal provided by the test machine from the test fixture. In some embodiments, the test fixture does not have a signal sharing function, but directly transmits multiple independent test signals generated by the test machine to these test pads 26, so that the test pad 26 can receive test signals with higher signal integrity.

[0020] In this embodiment, test control circuitry 28 may be formed on dicing streets 24 between chips 22. However, in alternative embodiments, test control circuitry 28 may be formed within at least one of these chips 22. Test control circuitry 28 may receive test signals generated by a test machine via a test fixture and test pads 26. Test control circuitry 28 is configured to expand a test signal received by a test pad 26 into M broadcast test signals. Thus, M chips 22 can simultaneously receive corresponding broadcast test signals for parallel chip testing, where M is an integer greater than 1.

[0021] Please refer to Figure 3 A chip testing system according to an embodiment of the present invention includes a test machine 30, a test fixture 32, and a semiconductor wafer 20. The test machine 30 generates N test signals st1_1 to stN_1, and the test fixture 32 transmits the test signals st1_1 to stN_1 to N test pads 26(1)_1 to 26(N)_1. More specifically, the test machine 30 can generate N test signals st1_1 to stN_1 having the same waveform, where N is an integer greater than 1.

[0022] The test control circuit 28 electrically connects the M chips 22_1-22_M and the N test pads 26(1)_1-26(N)_1. The test control circuit 28 can select at least one selected test signal (e.g., a test signal determined to be undisturbed) from the test signals st1_1-stN_1, generate M broadcast test signals bt1_1-btM_1 based on the selected test signal, and provide the broadcast test signals bt1_1-btM_1 to the chips 22_1-22_M. Specifically, the test control circuit 28 can replicate the selected test signal into the M broadcast test signals bt1_1-btM_1. For example, the test control circuit 28 can generate the M broadcast test signals bt1_1-btM_1 using its internal unity-gain buffer circuit. The signal waveforms of the broadcast test signals bt1_1 ˜btM_1 are identical to each other, and the signal waveforms of the broadcast test signals bt1_1 ˜btM_1 are identical to the selected test signal.

[0023] like Figure 3 As shown, chip 22_1 receives broadcast test signal bt1_1, chip 22_2 receives broadcast test signal bt2_1, and so on. Thus, each chip 22_1-22_M can perform chip testing based on a corresponding one of the broadcast test signals bt1_1-btM_1 and report the test results to test equipment 30. In some embodiments, because test control circuit 28 replicates selected test signals via buffer circuits, even if one of chips 22_1-22_M couples a corresponding one of the broadcast test signals bt1_1-btM_1 to a short circuit path or leakage current path, the test results of other chips will not be affected.

[0024] Please refer to Figure 4The test machine 30 of the chip test system of one embodiment of the present invention can generate N test signal groups G_1~G_N, each test signal group G_1~G_N includes k test signals, that is, generating N×k test signals st1_1~st1_k (i.e., multiple first test signals), st2_1~st2_k (i.e., multiple second test signals), ..., stN_1~stN_k, where k is a positive integer. The test fixture 32 transmits the test signals st1_1~st1_k, st2_1~st2_k, ..., stN_1~stN_k to N×k test pads 26(1)_1~26(1)_k (i.e., multiple first test pads), 26(2)_1~26(2)_k (i.e., multiple second test pads), ..., 26(N)_1~26(N)_k respectively. For example, the test pad 26(1)_1 can receive the test signal st1_1 from the test fixture 32. Each test signal group G_1-G_N is used to perform the same test item. That is, the signal waveform of each test signal in each test signal group G_1-G_N is the same as the signal waveform of the corresponding test signal in other test signal groups. For example, the signal waveform of test signal st1_1 is the same as the signal waveform of test signal st2_1.

[0025] In this embodiment, the test control circuit 28 can select one of the N test signal groups G_1-G_N and use the test signals in the selected group as the selected test signals. For example, the test control circuit 28 can select test signals st1_1-st1_k from the test signals st1_1-st1_k belonging to the test signal group G_1 and the test signals st2_1-st2_k belonging to the test signal group G_2 as the selected test signals. Thus, the test control circuit 28 can generate M×k broadcast test signals bt1_1-bt1_k, bt2_1-bt2_k, ..., btM_1-btM_k based on the test signals st1_1-st1_k, and provide the broadcast test signals bt1_1-bt1_k, bt2_1-bt2_k, ..., btM_1-btM_k to the chips 22_1-22_M. More specifically, test control circuit 28 can generate M broadcast signal groups BG_1 through BG_M based on test signal group G_1 and the signal replication circuit. Each broadcast signal group BG_1 through BG_M includes k broadcast test signals. For example, test control circuit 28 can replicate test signal st1_1 into M broadcast test signals bt1_1, bt2_1, ..., btM_1.

[0026] like Figure 4As shown, chip 22_1 receives the broadcast test signals bt1_1~bt1_k of the broadcast signal group BG_1, chip 22_2 receives the broadcast test signals bt2_1~bt2_k of the broadcast signal group BG_2, and so on. In this way, each chip 22_1~22_M can perform chip testing according to the corresponding one of the broadcast signal groups BG_1~BG_M, and report the test results to the test machine 30. It is worth mentioning that in some embodiments, even if one of the chips 22_1~22_M couples the received broadcast test signal to a short circuit path or a leakage current path, it will not affect the test results of other chips. Moreover, in the case where there is at least one correct test signal group, the test results of chips 22_1~22_M can perform chip detection based on the test signals that meet the expectations. Furthermore, based on Figure 3 and Figure 4 As can be seen from the embodiment, the M chips 22_1 to 22_M on the semiconductor wafer can be tested in parallel to save testing time.

[0027] The following examples will illustrate the detailed implementation of the test control circuit 28 selecting the selected test signal, wherein the test control circuit 28 selects the selected test signal based on the following examples. Figure 4 The structure of FIG and k=4 is an example. However, the present invention is not limited thereto.

[0028] Please refer to Figure 5 The test control circuit 28 of one embodiment of the present invention may include N signal receiving and decoding circuits 281_1 to 281_N and an input selection and broadcasting circuit 282. The signal receiving and decoding circuits 281_1 to 281_N are configured to receive N×4 test signals st1_1 to st1_4, st2_1 to st2_4, ..., stN_1 to stN_4 from test pads 26(1)_1 to 26(1)_4, 26(2)_1 to 26(2)_4, ..., 26(N)_1 to 26(N)_4, and are configured to output selected test signals and N channel confirmation signals CR1 to CRN. The input selection and broadcast circuit 282 is electrically connected to the signal receiving and decoding circuits 281_1-281_N and the chips 22_1-22_M, and is configured to receive the selected test signal and N channel confirmation signals CR1-CRN, and output the generated output enable signals EN1-ENN and broadcast test signals bt1_1-bt1_4, bt2_1-bt2_4, ..., btM_1-btM_4 to the signal receiving and decoding circuits 281_1-281_N and the chips 22_1-22_M, respectively.

[0029] Input selection and broadcasting circuit 282 selects four selected test signals from the N×4 test signals st1_1-st1_4, st2_1-st2_4, ..., stN_1-stN_4 based on the levels of the channel confirmation signals CR1-CRN. Based on these selected test signals, it generates broadcast test signals bt1_1-bt1_4, bt2_1-bt2_4, ..., btM_1-btM_4. These broadcast test signals bt1_1-bt1_4, bt2_1-bt2_4, ..., btM_1-btM_4 are then provided in parallel to chips 22_1-22_M. Specifically, input selection and broadcasting circuit 282 selects a plurality of uninterrupted selected test signals from the N test signal groups G_1-G_N based on the levels of the channel confirmation signals CR_1-CRN, and determines the output levels of output enable signals EN1-ENN based on the selection results.

[0030] In some embodiments, the input selection and broadcasting circuit 282 may refer to the truth table shown in Table 1 to determine the levels of the output enable signals EN1 -ENN according to the levels of the channel confirmation signals CR_1 -CRN, but the present invention is not limited thereto.

[0031] Table 1

[0032]

[0033] Where "1" represents a high logic level, and "0" represents a low logic level. In the example of Table 1, when the channel confirmation signal CR1 is at a high logic level, regardless of whether the levels of the other channel confirmation signals CR2-CRN are at a high logic level or a low logic level, the input selection and broadcasting circuit 282 generates the output enable signal EN1 at a low logic level and the output enable signals EN2-ENN at a high logic level. When the channel confirmation signal CR1 is at a low logic level and the channel confirmation signal CR2 is at a high logic level, regardless of whether the levels of the other channel confirmation signals CR3-CRN are at a high logic level or a low logic level, the input selection and broadcasting circuit 282 generates the output enable signal EN2 at a low logic level and the output enable signals EN1, EN3-ENN at a high logic level, and so on.

[0034] In this embodiment, the signal receiving and decoding circuits 281_1 to 281_N determine the levels of the channel confirmation signals CR1 to CRN based on whether the test signals st1_1 to st1_4, st2_1 to st2_4, ..., stN_1 to stN_4 conform to a preset waveform. For example, the signal receiving and decoding circuit 281_1 is electrically connected to the test pads 26(1)_1 to 26(1)_4 and includes input circuits in1_1 to in1_4 to receive the corresponding test signals st1_1 to st1_4. The signal receiving and decoding circuit 281_1 determines the level of the channel confirmation signal CR1 based on whether each test signal st1_1 to st1_4 conforms to the corresponding preset waveform required for the test. For example, the signal receiving and decoding circuit 281_1 may include a decoding circuit coupled to the output of the input circuits in1_1 to in1_4 to determine whether the test signals st1_1 to st1_4 conform to the corresponding preset waveform required for the test, thereby generating the channel confirmation signal CR1. When each of the test signals st1_1-st1_4 conforms to the corresponding preset waveform required for testing, the signal receiving and decoding circuit 281_1 determines that the level of the channel confirmation signal CR1 is a high logic level. When one of the test signals st1_1-st1_4 does not conform to the corresponding preset waveform, the signal receiving and decoding circuit 281_1 determines that the level of the channel confirmation signal CR1 is a low logic level. The operation of each of the signal receiving and decoding circuits 281_1-281_N is similar and will not be further described here. Thus, each signal receiving and decoding circuit 281_1-281_N can determine whether the received set of test signals has been interfered with and, accordingly, output a channel confirmation signal CR1-CRN having a corresponding level to the input selection and broadcasting circuit 282.

[0035] In this embodiment, the input selection and broadcasting circuit 282 can utilize output enable signals EN1-ENN to control the activation of one of the signal receiving and decoding circuits 281_1-281_N to obtain one of the test signal groups G_1-G_N (i.e., the selected test signal). For example, the signal receiving and decoding circuit 281_1 may include a delay circuit and output control circuits out1_1-out1_4. The delay circuit is disposed between the output control circuits out1_1-out1_4 and the input circuits in1_1-in1_4 to delay the test signals st1_1-st1_4. The delay circuit may be coupled to the outputs of the input circuits in1_1-in1_4 in parallel with the decoding circuit. The output control circuits out1_1-out1_4 are disposed between the delay circuit and the input selection and broadcasting circuit 282 and are activated by the output enable signal EN1 to output the delayed test signals st1_1-st1_4 as the selected test signal.

[0036] In this embodiment, when the output enable signal EN1 is at a high logic level, the output control circuit of the signal receiving and decoding circuit 281_1 is disabled, preventing it from outputting the test signals st1_1 through st1_4. Conversely, when the output enable signal EN1 is at a low logic level, the output control circuit of the signal receiving and decoding circuit 281_1 is enabled, causing the test signals st1_1 through st1_4 to be output to the input selection and broadcasting circuit 282. For example, Table 2 shows an example truth table for determining whether the signal receiving and decoding circuit 281_1 blocks or outputs a test signal. The other signal receiving and decoding circuits 281_2 through 281_N can output or block their respective received test signals using the same principle, and are not further described here.

[0037] Table 2

[0038]

[0039] Among them, "HZ" stands for high impedance (ie, open circuit state).

[0040] Please refer to Figure 6 , assuming N=2, the signal receiving and decoding circuit 281_1 can receive the test signals st1_1~st1_4 via the test pads 26(1)_1~26(1)_4, and the signal receiving and decoding circuit 281_2 can receive the test signals st2_1~st2_4 via the test pads 26(2)_1~26(2)_4. In some embodiments, the signal receiving and decoding circuits 281_1~281_2 can be formed on the cutting path between the chips 22_1~22_M. The signal receiving and decoding circuits 281_1~281_2 can respectively determine whether the test signals st1_1~st1_4, st2_1~st2_4 meet the preset waveforms, and output the channel confirmation signals CR1~CR2 respectively accordingly. In some embodiments, the input selection and broadcasting circuit 282 can be formed on the cutting path between the chips 22_1~22_M. The chips 22_1~22_M are arranged in an array on the semiconductor wafer.

[0041] like Figure 6As shown, the input selection and broadcast circuit 282 receives channel confirmation signals CR1-CR2 from the signal receiving and decoding circuits 281_1-281_2 and determines the levels of the output enable signals EN1-EN2 accordingly. The input selection and broadcast circuit 282 provides the output enable signals EN1-EN2 to the signal receiving and decoding circuits 281_1-281_2, respectively, so that the signal receiving and decoding circuits 281_1-281_2 can determine whether to output the test signals st1_1-st1_4 and st2_1-st2_4 to the input selection and broadcast circuit 282. When the input selection and broadcast circuit 282 receives the test signals st1_1-st1_4, it copies them into broadcast test signals bt1_1-bt1_4, bt2_1-bt2_4, ..., btM_1-btM_4. Input selection and broadcast circuit 282 can provide broadcast test signals bt1_1-bt1_4, bt2_1-bt2_4, ..., btM_1-btM_4 to corresponding chips 22_1-22_M via the internal metal wiring layers of the semiconductor wafer. For example, input selection and broadcast circuit 282 can provide broadcast test signals bt1_1-bt1_4 to corresponding chip 22_1. In this way, when the tester provides two sets of test signals st1_1-st1_4 and st2_1-st2_4, the M chips 22_1-22_M can receive one of them for parallel chip testing.

[0042] Please refer to Figure 7 In some embodiments, the semiconductor wafer 20 may be divided into a plurality of chip test areas (e.g., chip test area R1). Each chip test area may include a plurality of chips. The present invention does not impose any restrictions on the manner in which the chip test areas are divided, which may be determined based on test requirements. The test machine may use a test fixture to test each chip test area in sequence, and the test machine may use a test fixture to test a plurality of chips in each chip test area in parallel. In some embodiments, a plurality of chips in the same chip test area may receive a broadcast test signal generated based on the same one or more selected test signals from a corresponding test control circuit.

[0043] like Figure 7 As shown, the chip test area R1 is used for illustration. It is assumed that the chip test area R1 includes 16 chips 22_1 to 22_16, that is, M=16. In addition, it is assumed that the test machine can generate 4 test signal groups, that is, N=4. In this case, 16 chips 22_1 to 22_16 and 4×4 test pads 26(1)_1 to 26(1)_4, 26(2)_1 to 26(2)_4, 26(3)_1 to 26(3)_4, 26(4)_1 to 26(4)_4 can be formed in the chip test area R1. The test control circuit of the chip test area R1 (not shown) Figure 7 ) can generate multiple broadcast test signals to chips 22_1-22_16, allowing the test machine to simultaneously test 16 chips 22_1-22_16. The test control circuit can be formed on the dicing streets within chip test region R1. Alternatively, the test control circuit can be formed within at least one of the chips 22_1-22_16 within chip test region R1.

[0044] In this embodiment, the test pads 26(1)_1 to 26(1)_4 for receiving multiple test signals of the first test signal group can be set in the upper left corner area of ​​the chip test area R1; the test pads 26(2)_1 to 26(2)_4 for receiving multiple test signals of the second test signal group can be set in the upper right corner area of ​​the chip test area R1; the test pads 26(3)_1 to 26(3)_4 for receiving multiple test signals of the third test signal group can be set in the lower left corner area of ​​the chip test area R1; and the test pads 26(4)_1 to 26(4)_4 for receiving multiple test signals of the fourth test signal group can be set in the lower right corner area of ​​the chip test area R1. In this way, multiple test pads corresponding to different test signal groups can be set in different corners of the chip test area to ensure as much as possible that the test control circuit on the semiconductor wafer can receive at least one group of undisturbed test signals, thereby avoiding the situation where the chip test area only receives bad test signals due to the inclusion of defective dies, being located at the edge of the wafer or having local process defects.

[0045] Please refer to Figure 8 In a chip testing method according to an embodiment of the present invention, in step S801, a plurality of test pads receive a plurality of independent test signals from a test fixture. In step S802, a test control circuit on a semiconductor wafer selects at least one selected test signal from the test signals. In step S803, a plurality of broadcast test signals are generated by the test control circuit according to the at least one selected test signal, and these broadcast test signals are provided in parallel to a plurality of chips on the semiconductor wafer. The relevant implementation details of the chip testing method according to this embodiment can be referred to in the above description of the embodiment. Figures 1 to 7 Sufficient teachings and suggestions are obtained from the description of each embodiment of the present invention, which will not be repeated here.

[0046] In summary, according to an embodiment of the present invention, multiple test signal groups generated by the test machine can be directly input into the test pads on the semiconductor wafer. The test control circuit on the semiconductor wafer can select a reliable test signal group from the multiple test signal groups, and copy the selected test signals in the selected test signal group into multiple broadcast test signals, so that multiple chips can simultaneously receive the corresponding broadcast test signals to perform chip testing. Therefore, each chip can not only receive a test signal with higher signal integrity, but also the test signal will not have the problem of signal frequency reduction. Moreover, through the setting of the test control circuit, not only the number of parallel tests can be expanded to improve the chip testing efficiency, but also the complexity and cost of the test fixture can be reduced. In addition, the accuracy of chip testing can be improved and the probability of error can be reduced.

[0047] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of the present invention and are not intended to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they may modify the technical solutions described in the above embodiments or replace some or all of the technical features therein with equivalents; and such modifications or replacements do not deviate from the essence of the corresponding technical solutions within the scope of the technical solutions of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection defined by the claims.

Claims

1. A semiconductor wafer, characterized in that: include: Multiple chips; a plurality of test pads, receiving a plurality of test signals from a test machine through a test fixture, wherein the number of the plurality of test pads is equal to the number of the plurality of test signals provided by the test machine; as well as The test control circuit electrically connects the plurality of chips and the plurality of test pads, selects at least one selected test signal from the plurality of test signals, generates a plurality of broadcast test signals according to the at least one selected test signal, and provides the plurality of broadcast test signals in parallel to the plurality of chips.

2. The semiconductor wafer according to claim 1, wherein The plurality of test pads include a plurality of first test pads and a plurality of second test pads, the plurality of test signals include a plurality of first test signals and a plurality of second test signals, the plurality of first test pads receive the plurality of first test signals, and the plurality of second test pads receive the plurality of second test signals. The test control circuit selects the first test signals from the first test signals and the second test signals, and generates the broadcast test signals according to the first test signals.

3. The semiconductor wafer according to claim 1, wherein The plurality of test pads receive the plurality of test signals independent of each other from the test fixture. The semiconductor wafer includes a plurality of chip test areas, and the plurality of test pads are arranged at different corners of the plurality of chip test areas.

4. The semiconductor wafer according to claim 1, wherein The test control circuit includes an input selection and broadcast circuit electrically connected to the multiple chips, and the input selection and broadcast circuit is configured to receive multiple channel confirmation signals, select the at least one selected test signal from the multiple test signals according to the level of each of the multiple channel confirmation signals, and generate the multiple broadcast test signals according to the at least one selected test signal.

5. The semiconductor wafer according to claim 4, wherein: wherein the test control circuit comprises a plurality of signal receiving and decoding circuits electrically connected to the plurality of test pads, the plurality of signal receiving and decoding circuits being configured to receive the plurality of test signals, The levels of the channel confirmation signals are determined according to whether the test signals conform to a preset waveform, and the channel confirmation signals are output to the input selection and broadcast circuit accordingly.

6. The semiconductor wafer according to claim 5, wherein: The input selection and broadcast circuit is configured to generate multiple output enable signals based on the levels of the multiple channel confirmation signals, and provide the multiple output enable signals to the multiple signal receiving and decoding circuits, and the multiple signal receiving and decoding circuits output the at least one selected test signal to the input selection and broadcast circuit based on the multiple output enable signals.

7. The semiconductor wafer according to claim 5, wherein: Each of the plurality of signal receiving and decoding circuits comprises: an input circuit configured to receive at least one of the plurality of test signals; a decoding circuit coupled to the output of the input circuit, the decoding circuit being configured to determine whether at least one of the plurality of test signals conforms to a predetermined waveform and generate one of the plurality of channel confirmation signals; a delay circuit coupled to an output of the input circuit in parallel with the decoding circuit, the delay circuit being configured to delay at least one of the plurality of test signals; and The output control circuit is configured between the delay circuit and the input selection and broadcast circuit, and is configured to be enabled according to an output enable signal to output at least one of the delayed multiple test signals as the at least one selected test signal to the input selection and broadcast circuit.

8. The semiconductor wafer according to claim 7, wherein: When the output control circuit receives the output enable signal with a low logic level, the output control circuit is enabled; when the output control circuit receives the output enable signal with a high logic level, the output control circuit is disabled to block the output of the multiple test signals received by the corresponding ones of the multiple signal receiving and decoding circuits.

9. The semiconductor wafer according to claim 1, wherein: The test control circuit is formed on the dicing streets between the multiple chips.

10. The semiconductor wafer according to claim 1, wherein The test control circuit is formed inside one of the plurality of chips.

11. A multi-chip parallel testing method, characterized in that: include: A plurality of test pads on a semiconductor wafer receive a plurality of test signals from a test machine through a test fixture, wherein the number of the plurality of test pads is equal to the number of the plurality of test signals provided by the test machine; selecting, by a test control circuit on the semiconductor wafer, at least one selected test signal from the plurality of test signals; as well as The test control circuit generates a plurality of broadcast test signals according to the at least one selected test signal, and provides the plurality of broadcast test signals to a plurality of chips on the semiconductor wafer in parallel.

12. The multi-chip parallel testing method according to claim 11, characterized in that: The plurality of test pads include a plurality of first test pads and a plurality of second test pads, the plurality of test signals include a plurality of first test signals and a plurality of second test signals, the plurality of first test pads receive the plurality of first test signals, and the plurality of second test pads receive the plurality of second test signals. The step of selecting the selected test signal from the plurality of test signals by the test control circuit includes: The test control circuit selects the plurality of first test signals from the plurality of first test signals and the plurality of second test signals, The step of generating the plurality of broadcast test signals by the test control circuit according to the selected test signal and providing the plurality of broadcast test signals to the plurality of chips in parallel comprises: The test control circuit generates the plurality of broadcast test signals according to the plurality of first test signals.

13. The multi-chip parallel testing method according to claim 11, characterized in that: The step of selecting the at least one selected test signal from the plurality of test signals by the test control circuit comprises: The input selection and broadcast circuit receives a plurality of channel confirmation signals, and selects the at least one selected test signal from the plurality of test signals according to the level of each of the plurality of channel confirmation signals.

14. The multi-chip parallel testing method according to claim 13, characterized in that: The step of selecting, by the test control circuit, the at least one selected test signal from the plurality of test signals further comprises: A plurality of signal receiving and decoding circuits determine the levels of the plurality of channel confirmation signals according to whether the plurality of test signals conform to a preset waveform, and output the plurality of channel confirmation signals to the input selection and broadcasting circuit accordingly.

15. The multi-chip parallel testing method according to claim 14, characterized in that: The step of selecting, by the test control circuit, the at least one selected test signal from the plurality of test signals further comprises: The input selection and broadcast circuit generates a plurality of output enable signals according to the levels of the plurality of channel confirmation signals, and provides the plurality of output enable signals to the plurality of signal receiving and decoding circuits; and The signal receiving and decoding circuits output the at least one selected test signal to the input selecting and broadcasting circuit according to the output enabling signals.

16. The multi-chip parallel testing method according to claim 15, characterized in that: The steps of determining the levels of the plurality of channel confirmation signals by each of the plurality of signal receiving and decoding circuits based on whether the plurality of test signals conform to the predetermined waveforms, and outputting the plurality of channel confirmation signals to the input selection and broadcasting circuit accordingly include: receiving at least one of the plurality of test signals through an input circuit of each of the plurality of signal receiving and decoding circuits; Determining, by a decoding circuit of each of the plurality of signal receiving and decoding circuits, whether at least one of the plurality of test signals conforms to the predetermined waveform, and generating one of the plurality of channel confirmation signals; delaying at least one of the plurality of test signals by a delay circuit of each of the plurality of signal receiving and decoding circuits; and The output control circuit of each of the plurality of signal receiving and decoding circuits is enabled according to the output enable signal to output at least one of the plurality of delayed test signals as the at least one selected test signal to the input selection and broadcasting circuit.

17. The multi-chip parallel testing method according to claim 16, characterized in that: When the output control circuit receives the output enable signal with a low logic level, the output control circuit is enabled; when the output control circuit receives the output enable signal with a high logic level, the output control circuit is disabled to block the output of the multiple test signals received by the corresponding ones of the multiple signal receiving and decoding circuits.

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