Array substrate, preparation method thereof and display panel

Abstract

The embodiment of the present application discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, an active layer arranged on one side of the substrate, a first insulating layer arranged on one side of the substrate and covering the active layer, wherein the first insulating layer is provided with a first opening and a second opening corresponding to the active layer, the first opening corresponds to an edge of the active layer, and the second opening corresponds to a middle part of the active layer; a first metal layer is arranged in the first opening and connected with the active layer; a floating metal layer is arranged in the second opening and connected with the active layer, wherein the first metal layer and the floating metal layer are insulated from each other; and a first passivation layer is arranged on a side of the first insulating layer away from the substrate and covers the first metal layer and the floating metal layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the display field, and in particular to an array substrate, a preparation method thereof and a display panel. BACKGROUND

[0002] In the process of fringe field switching (FFS) technology, after the deposition of the active layer, the step of depositing and etching the metal layer is performed, which will cause damage to the channel of the active layer, resulting in an increase in channel defects and damage to the electrical properties of the device, and will also cause IGZO CD Loss (active layer strip width loss); in the process of etching the metal layer, undercut or beak problems will occur due to the multi-layer structure, which will cause poor bonding and film layer fracture problems, and high requirements for acid and process. SUMMARY

[0003] The embodiments of the present application provide an array substrate, a preparation method thereof and a display panel, which can solve the technical problem that the channel of the active layer is prone to defects in the prior art.

[0004] The embodiments of the present application provide an array substrate, which comprises a substrate, an active layer arranged on one side of the substrate, a first insulating layer arranged on one side of the substrate and covering the active layer, wherein the first insulating layer is provided with a first opening and a second opening corresponding to the active layer, the first opening corresponds to the edge of the active layer, and the second opening corresponds to the middle part of the active layer, a first metal layer arranged in the first opening and connected with the active layer, a floating metal layer arranged in the second opening and connected with the active layer, wherein the first metal layer and the floating metal layer are insulated from each other, and a first passivation layer arranged on the side of the first insulating layer away from the substrate and covering the first metal layer and the floating metal layer.

[0005] Optionally, in some embodiments of the present application, the active layer comprises a conductorized region and a channel, the conductorized region is arranged at the edge of the channel, and the floating metal layer corresponds to the channel.

[0006] Optionally, in some embodiments of the present application, the array substrate further comprises a light shielding unit arranged on one side of the substrate, and a buffer layer arranged on one side of the substrate and covering the light shielding unit, the active layer is arranged on one side surface of the buffer layer and corresponds to the light shielding unit.

[0007] Optionally, in some embodiments of the present application, the array substrate further comprises a second insulating layer disposed on a side surface of the first passivation layer away from the first insulating layer; a common electrode trace disposed on a side surface of the second insulating layer away from the first passivation layer; a second passivation layer disposed on a side surface of the second insulating layer away from the first passivation layer and covering the common electrode trace; and a pixel electrode disposed on a side surface of the second passivation layer away from the second insulating layer, penetrating through the second passivation layer, the second insulating layer and the first passivation layer, and connected to the first metal layer.

[0008] Correspondingly, the present application further provides a preparation method of an array substrate, comprising the following preparation steps:

[0009] providing a substrate;

[0010] preparing a semiconductor material on the substrate to form an active layer after patterning;

[0011] depositing an organic insulating material on the substrate and the active layer, etching the organic insulating material to form a first insulating layer, the first insulating layer being provided with a first opening and a second opening corresponding to the active layer, the first opening corresponding to an edge of the active layer, and the second opening corresponding to a middle part of the active layer;

[0012] preparing a metal material in the first opening and the second opening to form a first metal layer and a floating metal layer, the first metal layer being provided in the first opening, and the floating metal layer being provided in the second opening;

[0013] preparing a first passivation layer on the first insulating layer, the first metal layer and the floating metal layer.

[0014] Optionally, in some embodiments of the present application, the inkjet printing technology is used to prepare the metal material in the first opening and the second opening to form the first metal layer and the floating metal layer.

[0015] Optionally, in some embodiments of the present application, the organic insulating material comprises a silicon oxide material.

[0016] Optionally, in some embodiments of the present application, the step of preparing the semiconductor material on the substrate is specifically as follows:

[0017] preparing a semiconductor material on the substrate, and forming the active layer after partially conducting the semiconductor material, the active layer comprising a conductive region and a channel, and the floating metal layer corresponding to the channel.

[0018] Optionally, in some embodiments of the present application, after the step of preparing the first passivation layer, the method further comprises the following preparation steps:

[0019] a second insulating layer is prepared on the first passivation layer;

[0020] a conductive material is prepared on the second insulating layer, and the conductive material is patterned to form a common electrode;

[0021] a second passivation layer is prepared on the second insulating layer.

[0022] Correspondingly, the embodiment of the present application further provides a display panel, comprising the array substrate.

[0023] The array substrate and the preparation method thereof and the display panel provided in the embodiment of the present application have the floating metal layer arranged above the active layer, which effectively enhances the plasmonic concentration of the channel in the active layer and simultaneously replenishes the channel, thereby improving the stability of the array substrate. The first insulating layer is prepared by etching the barrier layer structure to form a plurality of openings on the active layer, and the first metal layer and the floating metal layer are formed by the inkjet printing process, thereby avoiding the damage to the active layer caused by the conventional process. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0025] Figure 1 is a structural schematic diagram of the array substrate provided by the embodiment of the present application;

[0026] Figure 2 is a structural schematic diagram after the first opening and the second opening are etched in the embodiment of the present application;

[0027] Figure 3 is a structural schematic diagram after the first metal layer and the floating metal layer are prepared in the embodiment of the present application;

[0028] Figure 4 is a flow chart of the preparation method of the array substrate provided by the embodiment of the present application.

[0029] Explanation of reference signs:

[0030] array substrate 10; substrate 100;

[0031] active layer 200; first insulating layer 300;

[0032] first metal layer 400; floating metal layer 500;

[0033] first passivation layer 600; second insulating layer 700;

[0034] a common electrode trace 800; and a second passivation layer 900.

[0035] a light shielding unit 110; and a buffer layer 120.

[0036] a conductorized region 201; and a channel 202.

[0037] a first opening 310; and a second opening 320.

[0038] a pixel electrode 910. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device.

[0040] The present application provides an array substrate, a preparation method thereof and a display panel. The following will be described in detail.

[0041] Embodiment

[0042] The present embodiment is mainly used to explain the array substrate 10 and the preparation method thereof and the display panel, wherein the main technical features and all technical effects of the display panel are concentrated on the array substrate 10. For other components of the display panel, the present embodiment will not be described one by one, such as Figure 1 As shown in the figure, the array substrate 10 includes a substrate 100, an active layer 200, a first insulating layer 300, a first metal layer 400, a floating metal layer 500, a first passivation layer 600, a second insulating layer 700, a common electrode trace 800, and a second passivation layer 900.

[0043] The substrate 100 is a hard glass substrate, mainly used to support various film layers and isolate external water and oxygen impurities. Since the glass material has light transmission properties, in order to avoid light passing through the substrate 100 and irradiating the metal traces above, a plurality of light shielding units 110 are arranged on the substrate 100, and a buffer layer 120 is arranged on the light shielding units 110. The buffer layer 120 has the technical effect of leveling the surface, facilitating subsequent film layer preparation, and can isolate the light shielding units 110 from other metal traces to avoid signal crosstalk.

[0044] The active layer 200 is arranged on the side of the buffer layer 120 away from the substrate 100. The active layer 200 is a semiconductor material. In this embodiment, amorphous indium gallium zinc oxide (IGZO) is used as the material of the active layer 200. Amorphous indium gallium zinc oxide is an excellent semiconductor material that can exhibit conductor properties under the action of an electric field, thereby transmitting electrical signals, and can exhibit insulating properties under the action of a non-electric field. In this embodiment, the active layer 200 includes a conductorized region 201 at the edge and a non-conductorized region, i.e., a channel 202, in the middle. The conductorized region is used to connect the source-drain electrode, i.e., the first metal layer 400.

[0045] The first insulating layer 300 is arranged on the upper surfaces of the buffer layer 120 and the active layer 200. In this embodiment, the array substrate 10 is an etching stop layer (ESL) structure array substrate 10. The first insulating layer 300 is made of an organic insulating material that has good barrier properties against hydrogen atoms and water molecules. This can effectively prevent hydrogen atoms and water molecules in the first passivation layer 600 from entering the active layer 200 during subsequent preparation of the first passivation layer 600, thereby affecting the device stability of the active layer 200.

[0046] In this embodiment, silicon oxide is used as the material of the first insulating layer 300. As shown in FIG. 2, a first opening 310 and a second opening 320 are etched on the first insulating layer 300 by etching. The first opening 310 corresponds to the conductorized region 201 of the active layer 200, and the second opening 320 corresponds to the channel 202 of the active layer 200. Figure 2

[0047] The first metal layer 400 is arranged in the first opening 310 and fills the gap of the first opening 310. Since the conductorized region 201 of the active layer 200 is partially exposed at the bottom of the first opening 310, the first metal layer 400 is connected to the conductorized region 201 of the active layer 200 through the first opening 310. The first metal layer 400 is the source-drain electrode in the thin film transistor unit.

[0048] ​The floating metal layer 500 is arranged in the second opening 320 and fills the gap of the second opening 320. Since the channel 202 of the active layer 200 is partially exposed at the bottom of the second opening 320, the floating metal layer 500 is connected with the channel 202 of the active layer 200 through the second opening 320. Since the channel 202 is prone to have a low plasma concentration and a lack of oxygen atoms in actual use, the floating metal layer 500 is connected with the channel 202, thereby enhancing the plasma concentration of the channel 202 and supplementing the channel.

[0049] The first passivation layer 600 is arranged on the upper surface of the first insulating layer 300, the first metal layer 400 and the floating metal layer 500. The second insulating layer 700 is arranged on the upper surface of the first passivation layer 600. In this embodiment, the material of the second insulating layer 700 is plastic material, specifically, a copolymer of perfluoropropyl perfluorovinyl ether and polytetrafluoroethylene, which has good insulation effect. The common electrode trace 800 is arranged on the upper surface of the second insulating layer 700. The common electrode trace 800 is made of transparent conductive material. In this embodiment, the common electrode trace 800 is made of indium tin oxide material, which has conductive ability and does not affect the light transmission effect.

[0050] The pixel electrode 910 is arranged on the upper surface of the second passivation layer 900 and penetrates the second passivation layer 900, the second insulating layer 700 and the first passivation layer 600 to be connected to the first metal layer 400. The pixel electrode 910 is made of indium tin oxide material, which has conductive ability and does not affect the light transmission effect.

[0051] In order to better explain the present application, the embodiment also provides a preparation method of the array substrate, as shown in Figure 4 The specific steps are as follows:

[0052] S1) providing a substrate 100, preparing a light shielding unit 110 and a buffer layer 120 on the substrate 100, wherein the buffer layer 120 covers the light shielding unit 110.

[0053] S2) preparing a layer of semiconductor material on the buffer layer 120. In this embodiment, the semiconductor material is amorphous indium gallium zinc oxide material. The semiconductor material is patterned and locally conductive to form an active layer 200. The active layer 200 is divided into a conductive region 201 and a channel 202 according to whether it is conductive. The conductive region 201 is located at the edge of the active layer 200, and the channel 202 is located in the middle of the active layer 200.

[0054] S3) An organic insulating material is prepared on the buffer layer 120 and the active layer 200 to form a first insulating layer 300. The organic insulating material has a good ability to block hydrogen atoms and water molecules. In this embodiment, the organic insulating material is silicon oxide. The organic insulating material is etched to form a first opening 310 and a second opening 320 on the corresponding active layer 200. The first opening 310 corresponds to the conductive region 201, and the second opening 320 corresponds to the channel 202. In this embodiment, an opening is also etched on the buffer layer 120 to expose the light-shielding unit 110 that does not correspond to the active layer 200. The first insulating layer 300 is connected to the light-shielding unit 110 through the opening.

[0055] S4) as Figure 3 As shown, metal material is filled into the first opening 310 and the second opening 320. In this embodiment, inkjet printing is used to fill the metal material into the first opening 310 and the second opening 320, forming a first metal layer 400 in the first opening 310 and a floating metal layer 500 in the second opening 320. The formed first metal layer 400 is connected to the conductor region 201 of the active layer 200, and the floating metal layer 500 is connected to the channel 202 of the active layer 200. In this embodiment, inkjet printing is used to prepare the first metal layer 400 and the floating metal layer 500, which not only allows for precise control of the shape of the first metal layer 400 and the floating metal layer 500, but also avoids damage to the active layer 200, especially the channel 202 in the active layer 200, caused by conventional processes (film formation, exposure, etching, and stripping).

[0056] S5) A layer of plastic material is prepared on the first insulating layer 300, the first metal layer 400 and the floating metal layer 500 to form a second insulating layer 700. In this embodiment, the plastic material is a copolymer of perfluoropropyl perfluorovinyl ether and polytetrafluoroethylene, which has a good insulating effect.

[0057] S6) A transparent conductive material is prepared on the second insulating layer 700, and after patterning, a common electrode trace 800 is formed. A second passivation layer 900 is prepared on the second insulating layer 700.

[0058] The beneficial effects of this embodiment are that the array substrate and its preparation method, and the floating metal layer disposed above the active layer of the display panel, effectively enhance the plasma concentration of the channel in the active layer, and at the same time, can supplement the channel and improve the stability of the array substrate. The first insulating layer is prepared by etching the barrier layer structure, and multiple openings are formed on the active layer. The first metal layer and the floating metal layer are formed by inkjet printing process, avoiding damage to the active layer caused by conventional processes.

[0059] The array substrate and the preparation method thereof and the display panel provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and the core idea thereof. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application. In conclusion, the content of the present description should not be understood as a limitation of the present application.

Claims

1. An array substrate, characterized in that, include substrate; An active layer is disposed on one side of the substrate; the active layer is made of amorphous indium gallium zinc oxide. A first insulating layer is disposed on one side of the substrate and covers the active layer. The first insulating layer has a first opening and a second opening at the location corresponding to the active layer. The first opening corresponds to the edge of the active layer, and the second opening corresponds to the middle of the active layer. A first metal layer is disposed within the first opening and connected to the active layer; A floating metal layer is disposed within the second opening and connected to the active layer, wherein the first metal layer and the floating metal layer are insulated from each other; the active layer includes a conductive region and a channel, the conductive region is disposed at the edge of the channel, and the floating metal layer corresponds to the channel; A first passivation layer is disposed on the side of the first insulating layer away from the substrate, and covers the first metal layer and the floating metal layer.

2. The array substrate according to claim 1, characterized in that, Also includes A light-shielding unit is disposed on one side of the substrate; A buffer layer is disposed on one side of the substrate and covers the light-shielding unit, and an active layer is disposed on one side surface of the buffer layer and corresponds to the light-shielding unit.

3. The array substrate according to claim 1, characterized in that, Also includes The second insulating layer is disposed on the surface of the first passivation layer away from the first insulating layer; The common electrode trace is located on the surface of the second insulating layer away from the first passivation layer. The second passivation layer is disposed on the surface of the second insulating layer away from the first passivation layer and covers the common electrode trace; A pixel electrode is disposed on the surface of the second passivation layer away from the second insulating layer, penetrates the second passivation layer, the second insulating layer and the first passivation layer, and is connected to the first metal layer.

4. A method for fabricating an array substrate, characterized in that, The preparation steps include the following: Provide a substrate; A semiconductor material is fabricated on the substrate and then patterned to form an active layer; the active layer is made of amorphous indium gallium zinc oxide. An organic insulating material is deposited on the substrate and the active layer, and the organic insulating material is etched to form a first insulating layer. The first insulating layer has a first opening and a second opening corresponding to the active layer. The first opening corresponds to the edge of the active layer, and the second opening corresponds to the middle of the active layer. Metal materials are prepared in a first opening and a second opening to form a first metal layer and a floating metal layer. The first metal layer is disposed in the first opening and the floating metal layer is disposed in the second opening. The active layer includes a conductive region and a channel. The conductive region is disposed at the edge of the channel and the floating metal layer is disposed in the channel. The floating metal layer is connected to the channel of the active layer through the second opening; A first passivation layer is prepared on the first insulating layer, the first metal layer, and the floating metal layer.

5. The method for fabricating an array substrate according to claim 4, characterized in that, Metal materials are prepared in the first and second openings using inkjet printing technology to form a first metal layer and a floating metal layer.

6. The method for fabricating an array substrate according to claim 4, characterized in that, The organic insulating material includes silicon dioxide.

7. The method for fabricating an array substrate according to claim 4, characterized in that, The specific steps for preparing the semiconductor material on the substrate are as follows: A semiconductor material is prepared on the substrate, and the active layer is formed by partially conductor-forming the semiconductor material.

8. The method for fabricating an array substrate according to claim 4, characterized in that, Following the step of preparing the first passivation layer, the following preparation steps are also included: A second insulating layer is prepared on the first passivation layer; A conductive material is prepared on a second insulating layer, and the conductive material is patterned to form a common electrode. A second passivation layer is prepared on the second insulating layer.

9. A display panel, characterized in that, The array substrate includes any one of claims 1-3.

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