A control method for eliminating narrow pulses in a PWM modulation signal

Abstract

The present invention discloses a control method for eliminating narrow pulses in a PWM modulation signal, which relates to the technical field of narrow pulse elimination technology. Among them, PWM1 is the original PWM modulation signal in a digital controller, and this signal is a digital signal, where the numerical value 0 represents the output low level and the digital 1 represents the high level. PWM2 is the modulation signal obtained after delaying the original PWM signal by a narrow pulse time T by using a cache array Cache[N] in the digital controller. min PWM3 is the output PWM signal after eliminating narrow pulses calculated according to the PWM1 and PWM2 signals. The present invention proposes a narrow pulse elimination circuit for PWM modulation signals that does not require external circuits and does not depend on PWM modulation wave signals. Without changing the pulse width of the original PWM modulation signal, only by programming with a common digital signal processor, the elimination of narrow pulses in the PWM modulation signal can be achieved, and the width of the eliminated narrow pulses can be modified by programming, improving the flexibility of narrow pulse elimination.

Description

Technical Field

[0001] The present invention relates to the technical field of narrow pulse elimination technology, and specifically to a control method for eliminating narrow pulses in a PWM modulation signal. Background Art

[0002] PWM modulation signals are widely used in switch-mode converters to control the turn-on and turn-off of power switch transistors, thereby achieving shaping and modulation of the output voltage. Due to the existence of certain turn-on and turn-off times of power switch devices and the resulting switching losses, the narrow pulses in the PWM modulation signal cannot effectively turn on the power switch transistor, and thus cannot effectively modulate the output voltage. Instead, it increases the switching losses and heat dissipation pressure of the power switch transistor, thereby reducing the power density and efficiency of the switch-mode converter. Therefore, it is necessary to eliminate the narrow pulses in the PWM modulation signal to reduce the switching losses of the power switch transistor.

[0003] There are mainly two methods for existing narrow pulse elimination circuits:

[0004] The first method is achieved by adding an additional external resistor-capacitor delay circuit, a comparator circuit, and a logic circuit. This method requires designing precise delay resistor-capacitor values according to the width of the narrow pulse to be eliminated, and increases the difficulty and cost of hardware design. In addition, this method will cause the pulse width of the original PWM modulation signal to shrink by the width of a narrow pulse.

[0005] The second method mainly calculates the width of the PWM signal in advance according to the magnitude of the modulation wave signal that generates the PWM. When the calculated PWM modulation signal is less than the narrow pulse width, the modulation wave signal is modified to avoid outputting narrow pulses. However, this method is only applicable to the case where the sampling signal frequency is the same as the PWM carrier signal frequency. When the sampling signal frequency is greater than the PWM carrier signal, the modulation wave signal changes multiple times within a PWM carrier period, and multiple narrow pulses will appear, and these narrow pulses are difficult to accurately predict and eliminate.

[0006] In view of the above signals, a control method for eliminating narrow pulses in a PWM modulation signal is now provided. Summary of the Invention

[0007] The purpose of the present invention is to provide a control method for eliminating narrow pulses in a PWM modulation signal to solve the problems in the background art.

[0008] To achieve the above purpose, the present invention provides the following technical solutions:

[0009] A control method for eliminating narrow pulses in a PWM modulation signal. PWM1 is the original PWM modulation signal in a digital controller. This signal is a digital signal, where the value 0 represents the output low level and the digital 1 represents the high level. PWM2 is the modulation signal obtained by delaying the original PWM signal by a narrow pulse time T in the digital controller using a cache array Cache[N]. min The PWM3 is the output PWM signal after eliminating narrow pulses calculated based on the PWM1 and PWM2 signals. Its calculation method is shown in formula (1):

[0010]

[0011] In formula (1), when the PWM2 signal has a rising edge and at this time the PWM1 signal is equal to 1, the output signal PWM3 is equal to 1; at the falling edge of PWM2, the PWM3 signal is set to 0. When there is a pulse in PWM1 that is less than the narrow pulse time T min , it is eliminated in the output signal PWM3; while a pulse in PWM1 that is greater than or equal to the narrow pulse time T min is retained and output, achieving the purpose of narrow pulse elimination.

[0012] Based on the above technical solution, the present invention also provides the following optional technical solutions:

[0013] In an optional solution: The specific generation method of the delayed pulse PWM2 is as follows: In the digital controller, a timer is used to record the value of the original PWM signal PWM1 at a frequency fs and cyclically record it in the cache array Cache[N]. The timing period 1 / fs of the timer, etc., should be less than half of the minimum pulse width T min , where N is the number of elements in the cache array, and its calculation method is shown in formula (2):

[0014] N = T min ·f s +1 (2)

[0015] All the initial values of all elements in the cache array Cache are equal to 0. A cache array write index index is set, with an initial value equal to 0. A global variable DelayValue is set to save and record the value of the PWM2 signal for each timer interrupt. A global variable PWMOut is set to record the current value of the PWM3 signal, with an initial value set to 0.

[0016] In an alternative solution: a method for implementing the delayed modulation signal PWM2 and the output signal PWM3 after eliminating narrow pulses. First, store Cache[index] in the buffer array into the global variable DelayVaulue. This signal is obtained by delaying the PWM1 signal by a duration of Tmin, that is, the PWM2 signal. Then, increment the index variable by 1. After that, Cache[index] is equal to the next PWM2 signal of the timer interrupt. By judging the values of DelayValue and Cache[index], the rising edge and falling edge of the PWM2 signal can be determined.

[0017] When DelayValue < 1 and Cache[index] > 0, it is the rising edge of the PWM2 signal. If the PWM1 signal is high at this time, the buffer PWMOut corresponding to the PWM3 signal = 1, indicating that the PWM3 outputs a high level. Before changing the value of PWMOut, the output of the PWM3 signal remains high.

[0018] When DelayValue > 1 and Cache[index] < 0, it is the falling edge of the PWM2 signal. The buffer PWMOut corresponding to the PWM3 signal = 0, indicating that the PWM3 outputs a low level. Before changing the value of PWMOut, the output of the PWM3 signal remains low.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] The present invention provides a narrow pulse elimination circuit for PWM modulation signals that does not require an external circuit and does not depend on the PWM modulation wave signal. Without changing the pulse width of the original PWM modulation signal, only by programming with a common digital signal processor, the elimination of narrow pulses in the PWM modulation signal can be achieved, and the width of the eliminated narrow pulses can be modified by programming, improving the flexibility of narrow pulse elimination. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a control block diagram for eliminating narrow pulses in the PWM modulation signal in this application.

[0022] Figure 2 It is a flowchart of the method for generating the delayed signal PWM2 and the modulation signal PWM3 after eliminating narrow pulses in this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0024] In one embodiment, as Figure 1As shown, a control method for eliminating narrow pulses in a PWM modulation signal, where PWM1 is the original PWM modulation signal in a digital controller. This signal is a digital signal, with the numerical value 0 representing the output low level and the digital 1 representing the high level. PWM2 is the modulation signal obtained after delaying the original PWM signal by a narrow pulse time T using a cache array Cache[N] in the digital controller. min PWM3 is the output PWM signal after eliminating narrow pulses calculated based on the PWM1 and PWM2 signals, and its calculation method is as shown in formula (1):

[0025]

[0026] In formula (1), when the PWM2 signal has a rising edge and at this time the PWM1 signal is equal to 1, the output signal PWM3 is equal to 1; at the falling edge of PWM2, the PWM3 signal is set to 0. From Figure 1 it can be seen that when there is a pulse in PWM1 that is less than the narrow pulse time T min , it is eliminated in the output signal PWM3; while the pulses in PWM1 that are greater than or equal to the narrow pulse time T min are retained and output, achieving the purpose of narrow pulse elimination.

[0027] The specific generation method of the delayed pulse PWM2 in the present invention is as follows. In the digital controller, a timer is used to record the value of the original PWM signal PWM1 at a frequency fs and cyclically record it in the cache array Cache[N]. The timing period 1 / fs of the timer etc. should be less than half of the minimum pulse width T min . Where N is the number of elements in the cache array, and its calculation method is as shown in formula (2):

[0028] N = T min ·f s + 1 (2)

[0029] All the initial values of all elements in the cache array Cache are equal to 0. Set a cache array write index index, with an initial value equal to 0. Set a global variable DelayValue to save and record the value of the PWM2 signal for each timer interrupt. Set a global variable PWMOut to record the current value of the PWM3 signal, with an initial value set to 0.

[0030] In each timer interrupt, the implementation methods of the delayed modulation signal PWM2 and the output signal PWM3 after eliminating narrow pulses are as Figure 2 shown;

[0031] Figure 2Among them, first, Cache[index] in the cache array is stored in the global variable DelayVaulue. This signal is obtained after the PWM1 signal is delayed by the duration T min That is, the PWM2 signal. Then the index variable index is incremented by 1. After that, Cache[index] is equal to the PWM2 signal of the next timer interrupt. By judging the values of DelayValue and Cache[index], the rising edge and falling edge of the PWM2 signal can be judged.

[0032] When DelayValue < 1 and Cache[index] > 0, it is the rising edge of the PWM2 signal. If the PWM1 signal is high at this time, the buffer PWMOut corresponding to the PWM3 signal = 1, indicating that the PWM3 signal outputs a high level. Before changing the value of PWMOut, the output of the PWM3 signal remains high.

[0033] When DelayValue > 1 and Cache[index] < 0, it is the falling edge of the PWM2 signal. The buffer PWMOut corresponding to the PWM3 signal = 0, indicating that the PWM3 signal outputs a low level. Before changing the value of PWMOut, the output of the PWM3 signal remains low.

[0034] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A control method for eliminating narrow pulses in a PWM modulation signal, characterized in that: PWM1 is the original PWM modulation signal in the digital controller. This signal is a digital signal, where the value 0 represents the output low level and the digital 1 represents the high level. PWM2 is the modulation signal obtained by delaying the original PWM signal by a narrow pulse time T using the cache array Cache[N] in the digital controller. min The PWM3 is the output PWM signal after eliminating the narrow pulse calculated based on the PWM1 and PWM2 signals. Its calculation method is shown in formula (1): In formula (1), when a rising edge appears in the PWM2 signal and the PWM1 signal equals 1 at this time, the output signal PWM3 equals 1; at the falling edge of PWM2, the PWM3 signal is set to 0. When a pulse shorter than the narrow pulse time T min appears in PWM1, it is eliminated in the output signal PWM3; while a pulse longer than or equal to the narrow pulse time T min appearing in PWM1 is retained and output, achieving the purpose of narrow pulse elimination; Among them, the implementation methods of the delay modulation signal PWM2 and the output signal PWM3 after eliminating narrow pulses are as follows: Store Cache[index] in the buffer array into the global variable DelayVaulue. This signal is obtained by delaying the PWM1 signal by a duration of T min to obtain the PWM2 signal. Then, increment the index variable index by 1. After that, Cache[index] is equal to the PWM2 signal of the next timer interrupt. By judging the values of DelayValue and Cache[index], the rising edge and falling edge of the PWM2 signal can be determined; When DelayValue < 1 and Cache[index] > 0, at the rising edge of the PWM2 signal, if the PWM1 signal is high at this time, the buffer PWMOut corresponding to the PWM3 signal = 1, indicating that the PWM3 signal outputs a high level. Before changing the value of PWMOut, the output of the PWM3 signal remains high. When DelayValue > 1 and Cache[index] < 0, at the falling edge of the PWM2 signal, the buffer PWMOut corresponding to the PWM3 signal = 0, indicating that the PWM3 signal outputs a low level. Before changing the value of PWMOut, the output of the PWM3 signal remains low.

2. The control method for eliminating narrow pulses in a PWM modulation signal according to claim 1, wherein The specific generation method of the delayed pulse PWM2 is as follows: In the digital controller, a timer is used to record the value of the original PWM signal PWM1 at a frequency fs, and the recorded values are cyclically stored in the cache array Cache[N]. The timing period 1 / fs of the timer should be less than half of the minimum pulse width T min , where N is the number of elements in the cache array, and its calculation method is shown in formula (2): N = T min ·f s +1 (2) The initial values of all elements in the cache array Cache are all equal to 0. Set a cache array write index index with an initial value equal to 0. Set a global variable DelayValue to save and record the value of the PWM2 signal for each timer interrupt. Set a global variable PWMOut to record the current value of the PWM3 signal, with an initial value set to 0.

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