An amplifier with feedforward compensation

Abstract

The present invention belongs to the technical field of integrated circuits, and relates to an amplifier with feedforward compensation, including a differential signal main circuit, two feedforward circuits, two compensation circuits and two common-mode feedforward circuits; the differential signal main circuit includes a first-stage differential amplifier and two second-stage single-stage amplifiers; the input ends of the feedforward circuits and the input ends of the common-mode feedforward circuits are respectively connected to the first input end of the differential signal main circuit; the output ends of the feedforward circuits and the output ends of the common-mode feedforward circuits are electrically connected to the output end of the differential signal main circuit; compensation circuits are arranged in parallel at both ends of the second-stage single-stage amplifier. The present invention utilizes the first-stage differential amplifier and two second-stage single-stage amplifiers, and at the same time utilizes two sets of feedforward circuits as additional signal input paths, and utilizes two sets of common-mode feedforward circuits as additional signal inputs, which can effectively improve the gain-bandwidth product and loop relative margin of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular, to an amplifier with feedforward compensation. Background Art

[0002] An amplifier is an important component in the design of analog integrated circuits. In order to ensure the relative loop margin, a Miller compensation capacitor is added to the circuit in a traditional two-stage operational amplifier to ensure that the circuit has sufficient phase margin. However, the introduction of the Miller compensation capacitor will lead to a reduction in bandwidth, and further decline the gain-bandwidth product of the amplifier. Summary of the Invention

[0003] In order to solve the above technical problems, the present invention provides an amplifier with feedforward compensation, which includes a differential signal main circuit, two feedforward circuits, two compensation circuits, and two common-mode feedforward circuits;

[0004] The differential signal main circuit includes a first-stage differential amplifier and two second-stage single-stage amplifiers; the first input terminal of the differential signal main circuit is electrically connected to the first input terminal of the first-stage differential amplifier; the second input terminal of the differential signal main circuit is electrically connected to the second input terminal of the first-stage differential amplifier;

[0005] The first output terminal of the first-stage differential amplifier is electrically connected to the input terminal of one of the second-stage single-stage amplifiers; the second output terminal of the first-stage differential amplifier is electrically connected to the input terminal of the other second-stage single-stage amplifier; the output terminal of one of the second-stage single-stage amplifiers is electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other second-stage single-stage amplifier is electrically connected to the second output terminal of the differential signal main circuit; the first-stage differential amplifier is used to provide gain for the differential signal; the second-stage single-stage amplifier is used to provide voltage swing for the differential signal;

[0006] The input terminal of one of the feedforward circuits and the input terminal of one of the common-mode feedforward circuits are respectively electrically connected to the first input terminal of the differential signal main circuit; the input terminal of the other feedforward circuit and the input terminal of the other common-mode feedforward circuit are respectively electrically connected to the second input terminal of the differential signal main circuit; the output terminal of one of the feedforward circuits and the output terminal of one of the common-mode feedforward circuits are electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other feedforward circuit and the output terminal of the other common-mode feedforward circuit are electrically connected to the second output terminal of the differential signal main circuit; the feedforward circuit and the common-mode feedforward circuit are used to adjust the gain-bandwidth product of the amplifier;

[0007] One compensation circuit is connected in parallel to each of the two second-stage single-stage amplifiers; the output terminal of one compensation circuit is electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other compensation circuit is electrically connected to the second output terminal of the differential signal main circuit; the compensation circuit is used to adjust the phase margin of the frequency response of the feedforward circuit.

[0008] The beneficial effects of the present invention are as follows: By using the first-stage differential amplifier and the second-stage single-stage amplifier, and at the same time using the feedforward circuit as an additional signal input path and the common-mode feedforward circuit as an additional signal input, the gain-bandwidth product and the loop relative margin of the circuit can be effectively improved; by additionally introducing a feedforward path to generate a half-plane zero, and using the positive phase shift of the half-plane zero to cancel the negative phase shift of the poles in the circuit, an amplifier with a high gain-bandwidth product is realized. Brief Description of the Drawings

[0009] Figure 1 It is a schematic diagram of a system of an amplifier with feedforward compensation provided in Embodiment 1 of the present invention;

[0010] Figure 2 It is a circuit schematic diagram of an amplifier with feedforward compensation symmetrically provided with loads;

[0011] Figure 3 It is a circuit schematic diagram of an amplifier including a bias circuit;

[0012] Figure 4 It is a circuit schematic diagram of an amplifier with a current source as the load;

[0013] Figure 5 It is a circuit schematic diagram of an amplifier with a current source as the load and including a bias circuit;

[0014] Figure 6 It is a circuit schematic diagram of an amplifier with a P-type MOS transistor as the current source for the load.

[0015] Icons: N1 - First NMOS transistor; N2 - Second NMOS transistor; N3 - Third NMOS transistor; N4 - Fourth NMOS transistor; N5 - Fifth NMOS transistor; N6 - Sixth NMOS transistor; N7 - Seventh NMOS transistor; N8 - Eighth NMOS transistor; N9 - Ninth NMOS transistor; P1 - First PMOS transistor; P2 - Second PMOS transistor; P3 - Third PMOS transistor; P4 - Fourth PMOS transistor; P5 - Fifth PMOS transistor; P6 - Sixth PMOS transistor; R1 - First resistor; R2 - Second resistor; C1 - First polarized capacitor; C2 - Second polarized capacitor; VDD - Power signal input terminal; Z1 - First load; Z2 - Second load; VB, VB1 - Bias voltage; IB1 - First current source; IB2 - Second current source; P_IB1, P_IB2 - P-type MOS transistors. Detailed implementation manners

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0017] As an embodiment, as shown in the accompanying Figure 1 figures, to solve the above technical problems, this embodiment provides an amplifier with feedforward compensation, including a differential signal main circuit, two feedforward circuits, two compensation circuits, and two common-mode feedforward circuits;

[0018] The differential signal main circuit includes a first-stage differential amplifier and two second-stage single-stage amplifiers; the first input terminal of the differential signal main circuit is electrically connected to the first input terminal of the first-stage differential amplifier; the second input terminal of the differential signal main circuit is electrically connected to the second input terminal of the first-stage differential amplifier;

[0019] The first output terminal of the first-stage differential amplifier is electrically connected to the input terminal of one second-stage single-stage amplifier; the second output terminal of the first-stage differential amplifier is electrically connected to the input terminal of the other second-stage single-stage amplifier; the output terminal of one second-stage single-stage amplifier is electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other second-stage single-stage amplifier is electrically connected to the second output terminal of the differential signal main circuit; the first-stage differential amplifier is used to provide gain for the differential signal; the second-stage single-stage amplifier is used to provide voltage swing for the differential signal;

[0020] The input terminal of a feedforward circuit and the input terminal of a common-mode feedforward circuit are respectively electrically connected to the first input terminal of the differential signal main circuit; the input terminal of another feedforward circuit and the input terminal of another common-mode feedforward circuit are respectively electrically connected to the second input terminal of the differential signal main circuit; the output terminal of a feedforward circuit and the output terminal of a common-mode feedforward circuit are electrically connected to the first output terminal of the differential signal main circuit; the output terminal of another feedforward circuit and the output terminal of another common-mode feedforward circuit are electrically connected to the second output terminal of the differential signal main circuit; the feedforward circuit and the common-mode feedforward circuit are used to adjust the amplifier gain-bandwidth product;

[0021] A compensation circuit is provided in parallel with each of the two second-stage single-stage amplifiers; the output terminal of a compensation circuit is electrically connected to the first output terminal of the differential signal main circuit; the output terminal of another compensation circuit is electrically connected to the second output terminal of the differential signal main circuit; the compensation circuit is used to adjust the phase margin of the feedforward circuit frequency response.

[0022] The present invention utilizes the first-stage differential amplifier and the second-stage single-stage amplifier, and at the same time utilizes two sets of feedforward circuits as additional signal input paths and two sets of common-mode feedforward circuits as additional signal inputs, which can effectively improve the amplifier gain-bandwidth product and the loop relative margin of the circuit; through the additionally introduced feedforward circuit, a right-half-plane zero is generated, and the positive phase shift of the right-half-plane zero cancels the negative phase shift of the poles in the circuit, thereby realizing an amplifier with a high gain-bandwidth product.

[0023] Optionally, as shown in the attached Figure 2 figure, the first-stage differential amplifier includes a first NMOS transistor N1 and a second NMOS transistor N2; the first input terminal of the differential signal main circuit is electrically connected to the gate of the first NMOS transistor N1; the second input terminal of the differential signal main circuit is electrically connected to the gate of the second NMOS transistor N2; the drain of the first NMOS transistor N1 is electrically connected to the input terminal of a second-stage single-stage amplifier; the drain of the second NMOS transistor N2 is electrically connected to the input terminal of another second-stage single-stage amplifier; the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded.

[0024] In the actual application process, the first-stage differential amplifier is formed by the first NMOS transistor N1 and the second NMOS transistor N2, providing a sufficiently high gain for the amplifier circuit.

[0025] Optionally, as shown in the attached Figure 2As shown, the two second-stage single-stage amplifiers include a first PMOS transistor P1 and a second PMOS transistor P2; the gate of the first PMOS transistor P1 is electrically connected to the output terminal of a first-stage differential amplifier, and the gate of the second PMOS transistor P2 is electrically connected to the output terminal of another first-stage differential amplifier; the sources of the first PMOS transistor P1 and the second PMOS transistor P2 are respectively electrically connected to the power supply signal input terminal VDD of the differential signal main circuit; the drain of the first PMOS transistor P1 is electrically connected to the first output terminal of the differential signal main circuit; the drain of the second PMOS transistor P2 is electrically connected to the second output terminal of the differential signal main circuit.

[0026] In the actual application process, the second-stage single-stage amplifier is formed by the first PMOS transistor P1 and the second PMOS transistor P2, providing a sufficiently large swing for the amplifier circuit.

[0027] Optionally, as shown in the appendix Figure 2 As shown, the feedforward circuit includes a third NMOS transistor N3 and a fourth NMOS transistor N4; the gate of the third NMOS transistor N3 is electrically connected to the first input terminal of the differential signal main circuit; the gate of the fourth NMOS transistor N4 is electrically connected to the second input terminal of the differential signal main circuit; the drain of the third NMOS transistor N3 is electrically connected to the first output terminal of the differential signal main circuit; the drain of the fourth NMOS transistor N4 is electrically connected to the second output terminal of the differential signal main circuit; the sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 are grounded.

[0028] In the actual application process, the third NMOS transistor N3 and the fourth NMOS transistor N4 form a feedforward path for the differential signal.

[0029] Optionally, as shown in the appendix Figure 2As shown in the figure, the common-mode feedforward circuit includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a sixth PMOS transistor P6. The gate of the fifth NMOS transistor N5 is electrically connected to the first input terminal of the differential signal main circuit. The gate of the sixth NMOS transistor N6 is electrically connected to the second input terminal of the differential signal main circuit. The drain of the fifth NMOS transistor N5 is electrically connected to the drain of the fifth PMOS transistor P5, the gate of the fifth PMOS transistor P5, and the gate of the third PMOS transistor P3. The drain of the sixth NMOS transistor N6 is electrically connected to the drain of the sixth PMOS transistor P6, the gate of the sixth PMOS transistor P6, and the gate of the fourth PMOS transistor P4. The sources of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are grounded. The drain of the third PMOS transistor P3 is connected to the first output terminal of the differential signal main circuit. The drain of the fourth PMOS transistor P4 is connected to the second output terminal of the differential signal main circuit. The sources of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the power signal input terminal VDD of the differential signal main circuit.

[0030] In the actual application process, a common-mode feedforward path of the differential signal main circuit is formed by the fifth NMOS transistor N5, the sixth NMOS transistor N6, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6.

[0031] Optionally, as shown in the attached Figure 3 figure, the amplifier with feedforward compensation further includes a bias circuit. The bias circuit includes a bias voltage source VB, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor N9. The gates of the seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor N9 are respectively connected to the bias voltage source VB. The drain of the seventh NMOS transistor N7 is electrically connected to the ground terminal of the common-mode feedforward circuit. The drain of the eighth NMOS transistor N8 is electrically connected to the ground terminal of the feedforward circuit. The drain of the ninth NMOS transistor N9 is electrically connected to the ground terminal of the first-stage differential amplifier.

[0032] In the actual application process, a bias circuit of the amplifier circuit is formed by the seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor N9 to provide bias current for the common-mode feedforward circuit, the feedforward circuit, and the first-stage differential amplifier.

[0033] Optionally, as shown in the attached Figure 2 and attached Figure 3The circuit diagram of the shown embodiment. This amplifier with feedforward compensation further includes loads Z1 and Z2. The power signal input terminal VDD of the differential signal main circuit is electrically connected to the first ends of loads Z1 and Z2. The second ends of loads Z1 and Z2 are electrically connected to the output terminal of the first-stage differential amplifier and the input terminal of the second-stage single-stage amplifier.

[0034] Optionally, the load includes a first current source and a second current source. The first current source and the second current source are P-type MOS transistors. The source electrode of the P-type MOS transistor is electrically connected to the power signal input terminal VDD of the differential signal main circuit. The drain electrode of the P-type MOS transistor is electrically connected to the output terminal of the first-stage differential amplifier and the input terminal of the second-stage single-stage amplifier. The gate electrode of the P-type MOS transistor is connected to a bias voltage signal source.

[0035] In the actual application process, implementing a current source through a P-type MOS transistor can provide a constant current with low noise.

[0036] Specifically, this amplifier with feedforward compensation includes a differential signal main circuit, two feedforward circuits, and two common-mode feedforward circuits.

[0037] The differential signal main circuit, as the first signal path, includes a first-stage differential amplifier and a second-stage single-stage amplifier. The first-stage differential amplifier includes a first NMOS transistor N1 and a second NMOS transistor N2. The second-stage single-stage amplifier includes a first PMOS transistor P1 and a second PMOS transistor P2.

[0038] The third NMOS transistor N3 and the third NMOS transistor N3 form a feedforward circuit as the second signal path.

[0039] The fifth NMOS transistor N5, the sixth NMOS transistor N6, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the third PMOS transistor P3, and the fourth PMOS transistor P4 form a common-mode feedforward circuit as the third signal path.

[0040] The seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor N9 form a bias circuit of the amplifier circuit.

[0041] Among them, the positive input terminal of the differential signal main circuit is connected to the gate electrode of the first NMOS transistor N1, the gate electrode of the third NMOS transistor N3, and the gate electrode of the fifth NMOS transistor N5. The negative input terminal of the differential signal main circuit is connected to the gate electrode of the second NMOS transistor N2, the gate electrode of the fourth NMOS transistor N4, and the gate electrode of the sixth NMOS transistor N6.

[0042] Optionally, the compensation circuit includes a Miller compensation capacitor and a nulling resistor connected in series, which is used to adjust the phase margin of the frequency response of the feedforward circuit. One end of the nulling resistor is connected to the node between the output of the first-stage differential amplifier and the input of the second-stage single-stage amplifier; the other end of the nulling resistor is connected to the output of the differential signal main circuit through the Miller compensation capacitor. As shown in the appendix Figure 2 - 6 As shown, the first resistor R1 and the first Miller compensation capacitor form the first compensation circuit, and the second resistor R2 and the second Miller compensation capacitor form the second compensation circuit. One end of the first resistor R1 is connected to the gate of the first PMOS transistor P1 and the drain of the first NMOS transistor N1; one end of the second resistor R2 is connected to the gate of the second PMOS transistor P2 and the drain of the second NMOS transistor N2; the other end of the first resistor R1 is connected to the drain of the first PMOS transistor P1 and the positive output of the differential signal main circuit through the first Miller compensation capacitor C1, and the other end of the second resistor R2 is connected to the drain of the second PMOS transistor P2 and the negative output of the differential signal main circuit through the second Miller compensation capacitor C2.

[0043] In actual application, the first-stage differential amplifier, two second-stage single-stage amplifiers, differential signal main circuit, two feedforward circuits, two compensation circuits, and two common-mode feedforward circuits are powered by the DC power supply VDD.

[0044] As shown in the appendix Figure 2 and appendix Figure 3 As shown, the drain of the first NMOS transistor N1 is connected to the second end of the first load Z1, the gate of the first PMOS transistor P1, and the second end of the first resistor. The drain of the second NMOS transistor N2 is connected to the second end of the second load Z2, the gate of the second PMOS transistor P2, and the first end of the second resistor (assuming the upper part of the resistor in the figure is the first end, the lower part is the second end, the left part is the first end, and the right part is the second end).

[0045] The first end of the first resistor is connected to the drain of the third NMOS transistor N3, the positive output of the differential signal main circuit, and the drain of the third PMOS transistor P3 through the first polar capacitor; the second end of the second resistor is connected to the drain of the fourth NMOS transistor N4, the positive output of the differential signal main circuit, and the drain of the fourth PMOS transistor P4 through the second polar capacitor.

[0046] The drain of the fifth NMOS transistor N5 is connected to the drain of the fifth PMOS transistor P5, the gate of the fifth PMOS transistor P5, and the gate of the third PMOS transistor P3; the drain of the sixth NMOS transistor N6 is connected to the drain of the sixth PMOS transistor P6, the gate of the sixth PMOS transistor P6, and the gate of the fourth PMOS transistor P4.

[0047] The source electrodes of the first PMOS transistor P1, the fifth PMOS transistor P5, and the third PMOS transistor P3, the first ends of the first load and the second load, the source electrode of the second PMOS transistor P2, the source electrode of the fourth PMOS transistor P4, and the source electrode of the sixth PMOS transistor P6 are connected to the power signal input terminal VDD.

[0048] As shown in the appendix Figure 3 As shown, the source electrodes of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are connected to the drain electrode of the seventh NMOS transistor N7, the source electrodes of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the drain electrode of the eighth NMOS transistor N8, and the source electrodes of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the drain electrode of the ninth NMOS transistor N9. The source electrodes of the seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor N9 are grounded. The gate electrodes of the seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor N9 are connected to the bias voltage VB. The seventh NMOS transistor N7, the eighth NMOS transistor N8, and the ninth NMOS transistor N9 act as tail current sources. The seventh NMOS transistor N7 provides bias current for the first NMOS transistor N1 and the second NMOS transistor N2, the eighth NMOS transistor N8 provides bias current for the third NMOS transistor N3 and the fourth NMOS transistor N4, and the ninth NMOS transistor N9 provides bias current for the fifth NMOS transistor N5 and the sixth NMOS transistor N6.

[0049] Optionally, as shown in the appendix Figure 4 and the appendix Figure 5 The schematic diagram of the circuit implementation manner of the load using a current source as shown. The first load uses the first current source IB1, and the second load uses the second current source IB2.

[0050] Optionally, the first current source IB1 and the second current source IB2 are implemented using P-type MOS transistors. As shown in the appendix Figure 6 The circuit schematic diagram of the first current source IB1 and the second current source IB2 implemented using P-type MOS transistors as shown. The first current source IB1 is implemented using the P-type MOS transistor P_IB1, and the second current source IB2 is implemented using the P-type MOS transistor P_IB2. The gate electrodes of the P-type MOS transistors P_IB1 and P_IB2 are connected to the bias voltage VB1.

[0051] During the actual application process, by setting the parameters of the feedforward circuit and the compensation circuit as well as the parameters of the common-mode feedforward circuit, it is beneficial to improve the gain-bandwidth product and the loop relative margin of the circuit.

[0052] The parameters of the feedforward circuit and the compensation circuit, as well as the parameters of the common-mode feedforward circuit. For example, the parameters of the first NMOS transistor N1 and the second NMOS transistor N2 are: W = 3.6 μ, L = 200 n, m = 64; the parameters of the third NMOS transistor N3 and the fourth NMOS transistor N4 are: W = 3.6 μ, L = 100 n, m = 35; the parameters of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are: W = 3.6 μ, L = 100 n, m = 5; the parameters of the seventh NMOS transistor N7 are: W = 5.0 μ, L = 200 n, m = 20; the parameters of the eighth NMOS transistor N8 are: W = 5.0 μ, L = 200 n, m = 140; the parameters of the ninth NMOS transistor N9 are: W = 5.0 μ, L = 200 n, m = 190; the capacitance range values of the first polar capacitor C1 and the second polar capacitor C2 are 1 pF to 10 pF; the resistance values of R1 and R2 are: 1 Ω to 100 Ω; the parameters of the first PMOS transistor P1 and the second PMOS transistor P2 are: W = 4.0 μ, L = 100 n, m = 24; the parameters of the third PMOS transistor P3 and the fourth PMOS transistor P4 are: W = 4.0 μ, L = 200 n, m = 22; the parameters of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are: W = 4.0 μ, L = 200 n, m = 22; the parameters of P_IB1 and P_IB2 are: W = 4.0 μ, L = 200 n, m = 88.

[0053] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An amplifier with feedforward compensation, characterized in that, It includes a differential signal main circuit, two feedforward circuits, two compensation circuits, and two common-mode feedforward circuits; The differential signal main circuit includes a first-stage differential amplifier and two second-stage single-stage amplifiers; the first input terminal of the differential signal main circuit is electrically connected to the first input terminal of the first-stage differential amplifier; the second input terminal of the differential signal main circuit is electrically connected to the second input terminal of the first-stage differential amplifier; The first output terminal of the first-stage differential amplifier is electrically connected to the input terminal of one of the second-stage single-stage amplifiers; the second output terminal of the first-stage differential amplifier is electrically connected to the input terminal of the other second-stage single-stage amplifier; the output terminal of one of the second-stage single-stage amplifiers is electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other second-stage single-stage amplifier is electrically connected to the second output terminal of the differential signal main circuit; the first-stage differential amplifier is used to provide gain for the differential signal; the second-stage single-stage amplifier is used to provide voltage swing for the differential signal; The input terminal of one of the feedforward circuits and the input terminal of one of the common-mode feedforward circuits are respectively electrically connected to the first input terminal of the differential signal main circuit; the input terminal of the other feedforward circuit and the input terminal of the other common-mode feedforward circuit are respectively electrically connected to the second input terminal of the differential signal main circuit; the output terminal of one of the feedforward circuits and the output terminal of one of the common-mode feedforward circuits are electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other feedforward circuit and the output terminal of the other common-mode feedforward circuit are electrically connected to the second output terminal of the differential signal main circuit; the feedforward circuit and the common-mode feedforward circuit are used to adjust the amplifier gain-bandwidth product; One compensation circuit is connected in parallel with each of the two second-stage single-stage amplifiers; the output terminal of one compensation circuit is electrically connected to the first output terminal of the differential signal main circuit; the output terminal of the other compensation circuit is electrically connected to the second output terminal of the differential signal main circuit; the compensation circuit is used to adjust the phase margin of the frequency response of the feedforward circuit.

2. The amplifier with feedforward compensation according to claim 1, wherein The first-stage differential amplifier includes a first NMOS transistor and a second NMOS transistor; the first input terminal of the differential signal main circuit is electrically connected to the gate of the first NMOS transistor; the second input terminal of the differential signal main circuit is electrically connected to the gate of the second NMOS transistor; the drain of the first NMOS transistor is electrically connected to the input terminal of one of the second-stage single-stage amplifiers; the drain of the second NMOS transistor is electrically connected to the input terminal of the other second-stage single-stage amplifier; the source of the first NMOS transistor and the source of the second NMOS transistor are grounded.

3. The amplifier with feedforward compensation according to claim 1, wherein The two second-stage single-stage amplifiers include a first PMOS transistor and a second PMOS transistor; the gate of the first PMOS transistor is electrically connected to the output terminal of one of the first-stage differential amplifiers, and the gate of the second PMOS transistor is electrically connected to the output terminal of the other first-stage differential amplifier; the sources of the first PMOS transistor and the second PMOS transistor are respectively electrically connected to the power signal input terminal of the differential signal main circuit; the drain of the first PMOS transistor is electrically connected to the first output terminal of the differential signal main circuit; the drain of the second PMOS transistor is electrically connected to the second output terminal of the differential signal main circuit.

4. The amplifier with feedforward compensation according to claim 1, wherein The feedforward circuit includes a third NMOS transistor and a fourth NMOS transistor; the gate of the third NMOS transistor is electrically connected to the first input terminal of the differential signal main circuit; the gate of the fourth NMOS transistor is electrically connected to the second input terminal of the differential signal main circuit; the drain of the third NMOS transistor is electrically connected to the first output terminal of the differential signal main circuit; the drain of the fourth NMOS transistor is electrically connected to the second output terminal of the differential signal main circuit; the sources of the third NMOS transistor and the fourth NMOS transistor are grounded.

5. The amplifier with feedforward compensation according to claim 1, wherein The common-mode feedforward circuit includes a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; the gate of the fifth NMOS transistor is electrically connected to the first input terminal of the differential signal main circuit; the gate of the sixth NMOS transistor is electrically connected to the second input terminal of the differential signal main circuit; the drain of the fifth NMOS transistor is electrically connected to the drain of the fifth PMOS transistor, the gate of the fifth PMOS transistor, and the gate of the third PMOS transistor; the drain of the sixth NMOS transistor is electrically connected to the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor, and the gate of the fourth PMOS transistor; the sources of the fifth NMOS transistor and the sixth NMOS transistor are connected to the power signal input terminal of the differential signal main circuit; the drain of the third PMOS transistor is connected to the first output terminal of the differential signal main circuit; the drain of the fourth PMOS transistor is connected to the second output terminal of the differential signal main circuit; the sources of the third PMOS transistor and the fourth PMOS transistor are connected to the power signal input terminal of the differential signal main circuit.

6. The amplifier with feedforward compensation according to claim 1, wherein The compensation circuit includes a Miller compensation capacitor and a nulling resistor connected in series; one end of the nulling resistor is connected to the output terminal of the first-stage differential amplifier and the input terminal of the second-stage single-stage amplifier, and the other end of the nulling resistor is connected to the output terminal of the differential signal main circuit through the Miller compensation capacitor.

7. The amplifier with feedforward compensation according to any one of claims 1-6, characterized in that, It further includes a bias circuit; the bias circuit includes a bias voltage source, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the gates of the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are respectively connected to the bias voltage source; the drain of the seventh NMOS transistor is electrically connected to the ground terminal of the common-mode feedforward circuit; the drain of the eighth NMOS transistor is electrically connected to the ground terminal of the feedforward circuit; the drain of the ninth NMOS transistor is electrically connected to the ground terminal of the first-stage differential amplifier.

8. The amplifier with feedforward compensation according to claim 7, characterized in that, It further includes a load; the power signal input terminal of the differential signal main circuit is electrically connected to the first end of the load; the second end of the load is electrically connected to the output terminal of the first-stage differential amplifier and the input terminal of the second-stage single-stage amplifier.

9. The amplifier with feedforward compensation according to claim 8, wherein, The load includes a first current source and a second current source; the first current source and the second current source are P-type MOS transistors; the source of the P-type MOS transistor is electrically connected to the power signal input terminal of the differential signal main circuit; the drain of the P-type MOS transistor is electrically connected to the output terminal of the first-stage differential amplifier and the input terminal of the second-stage single-stage amplifier; the gate of the P-type MOS transistor is connected to a bias voltage signal source.

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