Data processing method and apparatus, and electronic device
By setting up first and second memory in the computer and dynamically allocating data reading paths, the problem of lag or crashes caused by insufficient memory is solved, a more stable data processing flow is achieved, and the user experience of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LENOVO (BEIJING) LTD
- Filing Date
- 2022-08-29
- Publication Date
- 2026-07-24
Smart Images
Figure CN115328405B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus and electronic device. Background Technology
[0002] With technological advancements, the applications configured on computers are becoming increasingly diverse. Some applications have high memory requirements. Once the memory required by an application exceeds the amount of memory configured on the computer, lag or even crashes may occur. Summary of the Invention
[0003] In view of the above, this application provides a data processing method, apparatus, and electronic device, as follows:
[0004] A data processing method, comprising:
[0005] A data read request is obtained from the processing unit, wherein the data read request contains at least a data identifier of the data to be read;
[0006] If the first memory meets the direct read condition, the target data corresponding to the data identifier is read from the second memory into the processing unit, so that the processing unit can process the target data according to the data read request;
[0007] The first memory is different from the second memory;
[0008] If the first memory does not meet the direct read condition, the target data is read from the second memory into the first memory, so that the processing unit can read the target data from the first memory into the processing unit according to the data read request and process the target data.
[0009] In the above method, preferably, the processing unit stores a data mapping table, which at least contains the data identifier and the storage address of the data;
[0010] The method further includes, after obtaining the data read request from the processing unit:
[0011] The storage address of the target data is obtained according to the data mapping table;
[0012] Wherein, if the storage address points to the first memory, the processing unit reads the target data from the first memory according to the storage address and processes the target data;
[0013] If the storage address points to the second memory, the following steps are performed: reading the target data corresponding to the data identifier from the second memory into the processing unit, or reading the target data from the second memory into the first memory.
[0014] Preferably, after reading the target data from the second memory into the first memory, the method further includes:
[0015] Update the data mapping table in the second memory according to the storage address of the target data in the first memory;
[0016] The data mapping table in the second memory is updated in the processing unit.
[0017] Preferably, after obtaining the data read request from the processing unit, the above method further includes:
[0018] Detect the processing task corresponding to the data identifier;
[0019] If the processing task satisfies the parallel reading condition, the first part of the data corresponding to the data identifier is read from the second memory into the processing unit, and the second part of the data corresponding to the data identifier is read from the second memory into the first memory, so that the processing unit can read the second part of the data from the first memory into the processing unit according to the data reading request, and the processing unit processes the first part of the data and the second part of the data.
[0020] The parallel reading conditions include: the processing task is a task with a data processing volume greater than or equal to a processing threshold, or the processing task is a target type task.
[0021] Preferably, in the above method, the processing unit processes the first portion of data and the second portion of data, including:
[0022] The processing unit merges the first part of data and the second part of data that correspond to the same data identifier to obtain the target data corresponding to the data identifier;
[0023] The processing unit processes the target data.
[0024] The above method, preferably, involves reading the target data corresponding to the data identifier from the second memory into the processing unit, including:
[0025] The task scheduler reads the target data corresponding to the data identifier from the second memory, so that the task scheduler writes the target data into the cache area in the processing unit.
[0026] In the above method, preferably, the task scheduler and the second memory are connected via a first bus interface;
[0027] The task scheduler and the processing unit are connected via a second bus interface, and the bus latency of the first bus interface and the second bus interface is lower than a preset latency threshold.
[0028] In the above method, preferably, the first memory satisfies the direct read condition as follows: the available storage area of the first memory is less than or equal to a preset storage threshold.
[0029] A data processing apparatus, comprising:
[0030] A request acquisition unit is used to acquire a data read request from the processing unit, wherein the data read request contains at least a data identifier of the data to be read;
[0031] The first reading unit is configured to read the target data corresponding to the data identifier from the second memory into the processing unit if the first memory meets the direct reading conditions, so that the processing unit can process the target data according to the data reading request;
[0032] The first memory is different from the second memory;
[0033] The second reading unit is configured to read the target data from the second memory into the first memory if the first memory does not meet the direct reading conditions, so that the processing unit can read the target data from the first memory into the processing unit according to the data reading request and process the target data.
[0034] An electronic device, comprising:
[0035] First memory;
[0036] Second memory;
[0037] Processing unit;
[0038] A task scheduler is configured to receive a data read request from the processing unit, the data read request containing at least a data identifier of the data to be read; if the first memory meets the direct read condition, the target data corresponding to the data identifier is read from the second memory into the processing unit, so that the processing unit can process the target data according to the data read request; wherein the first memory and the second memory are different; if the first memory does not meet the direct read condition, the target data is read from the second memory into the first memory, so that the processing unit can read the target data from the first memory into the processing unit according to the data read request and process the target data.
[0039] As can be seen from the above technical solutions, in the data processing method, apparatus, and electronic device disclosed in this application, after receiving a data read request from the processing unit, if the first memory meets the direct read condition, then the target data corresponding to the data identifier is read from the second memory and into the processing unit. The processing unit can then process the target data according to the data read request. However, if the first memory does not meet the direct read condition, then after reading the target data from the second memory into the first memory, the processing unit reads the target data from the first memory into itself, and then processes the target data. Therefore, this application prioritizes reading the target data from the second memory into the first memory, and then the processing unit reads the target data from the first memory into itself. When the first memory meets the direct read condition, the target data can be directly read from the second memory into the processing unit. This allows data to be read from the second memory regardless of whether the first memory is functioning properly, avoiding lag or even crashes caused by the first memory's inability to read data normally, thereby improving the user experience of the electronic device. Attached Figure Description
[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 A flowchart of a data processing method provided in Embodiment 1 of this application;
[0042] Figure 2 and Figure 3 These are another flowcharts of a data processing method provided in Embodiment 1 of this application;
[0043] Figure 4 This is a schematic diagram of the structure of a data processing device provided in Embodiment 2 of this application;
[0044] Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 3 of this application;
[0045] Figure 6 This is a hardware logic architecture diagram for the electronic device to which this application applies;
[0046] Figure 7 This is a partial hardware logic architecture diagram of the electronic device to which this application applies. Detailed Implementation
[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0048] refer to Figure 1 The diagram shown is a flowchart illustrating the implementation of a data processing method according to Embodiment 1 of this application. This method is applicable to electronic devices capable of data processing, such as mobile phones or computers. The technical solution in this embodiment is primarily used to improve the user experience of electronic devices.
[0049] Specifically, the method in this embodiment may include the following steps:
[0050] Step 101: Obtain a data read request from the processing unit.
[0051] The processing unit can be a processor in an electronic device, such as a central processing unit (CPU); or, the processing unit can be a program module loaded in an electronic device to implement the corresponding function.
[0052] Specifically, the data read request must contain at least a data identifier for the data to be read, such as the data name, to uniquely identify the target data that the processing unit needs to read.
[0053] Step 102: Determine whether the first memory meets the direct read conditions. If the first memory meets the direct read conditions, proceed to step 103. If the first memory does not meet the direct read conditions, proceed to step 104.
[0054] Specifically, in step 102, determining whether the first memory meets the direct read conditions can be done by: determining whether the available storage area of the first memory meets the direct read conditions.
[0055] Specifically, the direct read condition can be: the available storage area of the first memory is less than or equal to a preset storage threshold. For example, the first memory can be a memory device in an electronic device, such as Low Power Double Data Rate (LPDDRS) SDRAM, where SDRAM refers to Synchronous Dynamic Random-Access Memory. The electronic device may also contain other memory, such as a second memory. The second memory differs from the first memory in its data storage performance and / or its data storage function. For example, the second memory can be a memory storing the target data required by various processing units in the electronic device, such as a Solid State Drive (SSD), also known as an NVMe SSD (NVM Express, Non-Volatile Memory Host Controller Interface Specification) SSD. Based on this, the direct read condition can be: the remaining space of the memory in the electronic device is less than or equal to a preset storage threshold.
[0056] Step 103: Read the target data corresponding to the data identifier from the second memory into the processing unit so that the processing unit can process the target data according to the data read request.
[0057] For example, in this embodiment, when the remaining space of LPDDR is insufficient, the target data is directly read from the SSD into the CPU. Thus, the CPU can process the target data according to the data read request.
[0058] Step 104: Read the target data from the second memory into the first memory, so that the processing unit can read the target data from the first memory into the processing unit according to the data read request and process the target data.
[0059] For example, in this embodiment, when there is sufficient remaining space in the LPDDR, the target data is first read from the SSD into the LPDDR, and then the CPU reads the target data from the LPDDR into the CPU. Thus, the CPU can process the target data according to the data read request. Therefore, even if there is insufficient remaining space in the LPDDR, it does not affect the CPU's reading and processing of the target data.
[0060] As can be seen from the above technical solutions, in the data processing method provided in Embodiment 1 of this application, after receiving a data read request from the processing unit, if the first memory meets the direct read condition, then the target data corresponding to the data identifier is read from the second memory and into the processing unit. The processing unit can then process the target data according to the data read request. However, if the first memory does not meet the direct read condition, then after reading the target data from the second memory into the first memory, the processing unit reads the target data from the first memory into itself, and then processes the target data. Therefore, this application prioritizes reading the target data from the second memory into the first memory, and then the processing unit reads the target data from the first memory into itself. When the first memory meets the direct read condition, the target data can be directly read from the second memory into the processing unit. This allows for data reading from the second memory regardless of whether the first memory is functioning properly, avoiding lag or even system crashes caused by the first memory's inability to read data normally, thereby improving the user experience of the electronic device.
[0061] In one implementation, the processing unit stores a data mapping table, which at least contains the data identifier and the storage address of the data. The data mapping table stored in the processing unit can be obtained based on a data mapping table in a second memory. For example, the data mapping table stored in the second memory can be copied to the processing unit. The second memory can generate its own data mapping table based on the state in which the stored data is read. For example, the initial state of the data mapping table contains records of all data stored in the second memory, with each record containing the data identifier and the storage address of that data. As the electronic device operates, if any data is read into the first memory, the corresponding record in the data mapping table of the second memory is adjusted, and this record contains the data identifier of the data read into the first memory and its storage address in the first memory.
[0062] Based on this, this embodiment may further include the following steps after step 101, such as... Figure 2 As shown:
[0063] Step 105: Obtain the storage address of the target data based on the data mapping table.
[0064] In one implementation, this embodiment allows querying the storage address of the target data in a data mapping table stored in the processing unit, based on the data identifier in the data acquisition request. This storage address points to either a first memory or a second memory. It should be noted that the data mapping table in the second memory is updated and then updated in the processing unit each time data is read from the first memory.
[0065] In another implementation, this embodiment can first read the data mapping table from the second memory and update it in the processing unit, and then query the storage address of the target data in the data mapping table in the processing unit according to the data identifier. It should be noted that the data mapping table in the second memory is updated every time data is read into the first memory.
[0066] In another implementation, in this embodiment, the storage address of the target data can be directly queried from the data mapping table in the second memory based on the data identifier.
[0067] Step 106: Determine whether the storage address of the target data points to the first memory or the second memory. If the storage address of the target data points to the first memory, execute step 107. If the storage address of the target data points to the second memory, execute step 102. Then, if the first memory meets the direct read conditions, execute step 103. If the first memory does not meet the direct read conditions, execute step 104.
[0068] Step 107: The processing unit reads the target data from the first memory according to the storage address and processes the target data.
[0069] In other words, in this embodiment, after receiving a data read request, it first determines whether the target data read from the second memory is already stored in the first memory. If so, the processing unit can directly read the target data from the first memory according to the storage address. If the target data is not in the first memory, that is, the storage address of the target data points to the second memory, it first determines whether the first memory meets the direct read conditions, such as whether the available storage area of the first memory is less than or equal to the storage threshold. If the available storage area of the first memory is less than the storage threshold, the target data can be directly read from the second memory into the processing unit. If the available storage area of the first memory is greater than the storage threshold, the target data can be read from the second memory into the first memory first, so that the processing unit can read the target data from the first memory into the processing unit. Based on this, the processing unit can process the target data. As can be seen, in this embodiment, under the premise of prioritizing the use of the first memory to read the target data, it can be ensured that the target data can still be read even if the first memory is not working properly. At the same time, in this embodiment, after receiving the data acquisition request, it is first checked whether the target data is already stored in the first memory. Therefore, if the target data is stored in the first memory, the target data reading process can be reduced, thereby improving the efficiency of target data reading and processing.
[0070] Based on the above implementation scheme, in this embodiment, after reading the target data from the second memory into the first memory in step 104, the data mapping table in the second memory can be updated according to the storage address of the target data in the first memory. Then, the data mapping table in the second memory is updated in the processing unit to ensure that the data mapping table in the processing unit can more accurately represent the storage address of each data.
[0071] It should be noted that, in this embodiment, updating the data mapping table in the second memory specifically involves adding a data identifier for the target data and its storage address in the first memory to the data mapping table, indicating that the target data is stored at the corresponding storage address in the first memory. Based on this, after updating the data mapping table in the second memory to the processing unit, it is possible to determine whether the storage address of the target data points to the first memory through the data mapping table in the processing unit.
[0072] In one implementation, after step 101, this embodiment may further include the following steps, such as... Figure 3 As shown:
[0073] Step 108: Detect the processing task corresponding to the data identifier. If the processing task meets the parallel reading conditions, proceed to step 109. If the processing task does not meet the parallel reading conditions, proceed to step 102.
[0074] The conditions for parallel reading can be: the processing task is a task with a data processing volume greater than or equal to a processing threshold, and / or the processing task is a task with a specific target type. For example, the processing task is a large-scale 3D rendering task, where the amount of data to be read is greater than the processing threshold.
[0075] Based on this, in this embodiment, the processing task can be determined to meet the parallel reading condition by detecting the data processing volume or task type of the processing task corresponding to the data identifier. If the processing task meets the parallel reading condition, step 109 is executed. If the processing task does not meet the parallel reading condition, step 102 is executed.
[0076] Step 109: Read the first part of the data corresponding to the data identifier from the second memory into the processing unit, and read the second part of the data corresponding to the data identifier from the second memory into the first memory, so that the processing unit can read the second part of the data from the first memory into the processing unit according to the data read request, and the processing unit can process the first part of the data and the second part of the data.
[0077] The first part of the data and the second part of the data together form the target data corresponding to the data identifier.
[0078] In other words, in this embodiment, when the processing task corresponding to the data identifier is detected to meet the parallel reading conditions, the parallel reading scheme formed by executing steps 103 and 104 in parallel can be adopted. That is, while using the first memory to read a portion of data from the second memory into the processing unit, another portion of data is read from the second memory into the processing unit, thereby achieving parallel data reading. Based on this, the target data corresponding to the data identifier can be obtained in the processing unit, and data processing can then be achieved. It is evident that this embodiment flexibly implements data reading according to the processing task to ensure the normal execution of the processing task.
[0079] Based on the above implementation scheme, the processing unit can process the first part of the data and the second part of the data in the following ways:
[0080] First, the processing unit merges the first part of the data and the second part of the data that correspond to the same data identifier to obtain the target data corresponding to the data identifier; then, the processing unit can process the target data.
[0081] In other words, the processing unit may contain multiple data parts corresponding to multiple data identifiers. Before the processing unit processes the data, the data that originally corresponded to the same data identifier are merged, and then the merged data is processed.
[0082] In one implementation, step 103, when reading the target data corresponding to the data identifier from the second memory into the processing unit, can be achieved in the following way:
[0083] The task scheduler reads the target data corresponding to the data identifier from the second memory, so that the task scheduler writes the target data into the cache area in the processing unit.
[0084] For example, the target data is first read from the SSD by the access scheduler in the computer. Then, the access scheduler sends the read target data to the CPU's L4 cache so that the CPU can read and process the target data in the L4 cache.
[0085] In the specific implementation, the task scheduler is connected to the second memory via the first bus interface, and the task scheduler is connected to the processing unit via the second bus interface. The bus latency of the first bus interface and the second bus interface is lower than a preset latency threshold.
[0086] For example, the access scheduler in a computer can be connected to the SSD via a high-speed serial computer expansion bus standard PCI-E (PCI-Express (peripheral component interconnect express)) interface or CXL (Compute Express Link) interface, and the access scheduler in a computer can be connected to the CPU via CXL.
[0087] The task scheduler can be implemented by a control chip capable of performing the above functions, or it can be a program module in the processor that has the above functions.
[0088] refer to Figure 4 This is a schematic diagram of a data processing device provided in Embodiment 2 of this application. This device can be configured in electronic devices capable of data processing, such as mobile phones or computers. The technical solution in this embodiment is mainly used to improve the user experience of electronic devices.
[0089] Specifically, the device in this embodiment may include the following units:
[0090] The request acquisition unit 401 is used to obtain a data read request from the processing unit, wherein the data read request contains at least a data identifier of the data to be read;
[0091] The first reading unit 402 is configured to read the target data corresponding to the data identifier from the second memory into the processing unit if the first memory meets the direct reading conditions, so that the processing unit can process the target data according to the data reading request;
[0092] The first memory is different from the second memory;
[0093] The second reading unit 403 is used to read the target data from the second memory into the first memory if the first memory does not meet the direct reading conditions, so that the processing unit can read the target data from the first memory into the processing unit according to the data reading request and process the target data.
[0094] As can be seen from the above technical solutions, in the data processing device provided in Embodiment 2 of this application, after receiving a data read request from the processing unit, if the first memory meets the direct read condition, then the target data corresponding to the data identifier is read from the second memory and into the processing unit. The processing unit can then process the target data according to the data read request. However, if the first memory does not meet the direct read condition, then after reading the target data from the second memory into the first memory, the processing unit reads the target data from the first memory into the processing unit, and then processes the target data. It is evident that in this application, the target data is preferentially read from the second memory into the first memory, and then the processing unit reads the target data from the first memory into the processing unit. When the first memory meets the direct read condition, the target data can be directly read from the second memory into the processing unit. Therefore, data reading from the second memory can be achieved regardless of whether the first memory is functioning normally, avoiding lag or even system crashes caused by the first memory's inability to read data normally, thereby improving the user experience of the electronic device.
[0095] In one implementation, the processing unit stores a data mapping table, which at least contains the data identifier and the storage address of the data.
[0096] After the request obtaining unit 401 receives the data read request from the processing unit, it is further configured to: obtain the storage address of the target data according to the data mapping table; wherein, if the storage address points to the first memory, the processing unit reads the target data from the first memory according to the storage address and processes the target data; if the storage address points to the second memory, the first reading unit 402 is triggered to read the target data corresponding to the data identifier from the second memory into the processing unit, or the second reading unit 403 is triggered to read the target data from the second memory into the first memory.
[0097] Based on the above implementation, after the first reading unit 402 reads the target data from the second memory into the first memory, it is further configured to: update the data mapping table in the second memory according to the storage address of the target data in the first memory; and update the data mapping table in the second memory to the processing unit.
[0098] In one implementation, after the request obtaining unit 401 obtains the data read request from the processing unit, it is further configured to: detect the processing task corresponding to the data identifier; if the processing task satisfies the parallel read condition, trigger the first reading unit 402 to read the first part of the data corresponding to the data identifier from the second memory into the processing unit, and trigger the second reading unit 403 to read the second part of the data corresponding to the data identifier from the second memory into the first memory, so that the processing unit can read the second part of the data from the first memory into the processing unit according to the data read request, and enable the processing unit to process the first part of the data and the second part of the data.
[0099] Based on the above implementation scheme, when the processing unit processes the first part of data and the second part of data, it is specifically used to: merge the first part of data and the second part of data that correspond to the same data identifier to obtain the target data corresponding to the data identifier; and process the target data.
[0100] In one implementation, when the first reading unit 402 reads the target data corresponding to the data identifier from the second memory to the processing unit, it is specifically used to: use a task scheduler to read the target data corresponding to the data identifier from the second memory, so that the task scheduler writes the target data into the cache area in the processing unit.
[0101] Specifically, the task scheduler is connected to the second memory via a first bus interface; the task scheduler is connected to the processing unit via a second bus interface, and the bus latency of the first bus interface and the second bus interface is lower than a preset latency threshold.
[0102] In one implementation, the first memory satisfies the direct read condition by: the available storage area of the first memory is less than or equal to a preset storage threshold.
[0103] It should be noted that the specific implementation of each unit in this embodiment can be referred to the corresponding content above, and will not be described in detail here.
[0104] refer to Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 3 of this application. The electronic device may include the following structure:
[0105] First memory 501; First memory 501 can be a memory cluster composed of one or more memory chips;
[0106] Second memory 502; Second memory 502 can be a memory cluster composed of one or more memory chips;
[0107] Processing unit 503; Processing unit 503 may be a processor containing one or more cores, or processing unit 503 may be a program module with corresponding functions.
[0108] A task scheduler 504 is configured to receive a data read request from the processing unit 503, the data read request containing at least a data identifier of the data to be read; if the first memory 501 meets the direct read condition, the target data corresponding to the data identifier is read from the second memory 502 into the processing unit 503, so that the processing unit 503 can process the target data according to the data read request; wherein the first memory 501 and the second memory 502 are different; if the first memory 501 does not meet the direct read condition, the target data is read from the second memory 502 into the first memory 501, so that the processing unit 503 can read the target data from the first memory 501 into the processing unit 503 according to the data read request and process the target data.
[0109] The task scheduler 504 can be a control chip capable of performing the above functions, or the task scheduler can be a program module in the processor that has the above functions.
[0110] As can be seen from the above technical solutions, in the electronic device provided in Embodiment 3 of this application, after receiving a data read request from the processing unit, if the first memory meets the direct read condition, then the target data corresponding to the data identifier is read from the second memory and sent to the processing unit. The processing unit can then process the target data according to the data read request. However, if the first memory does not meet the direct read condition, then after reading the target data from the second memory to the first memory, the processing unit reads the target data from the first memory and sends it to the processing unit, whereby the processing unit processes the target data. It is evident that in this application, the target data is preferentially read from the second memory to the first memory, and then the processing unit reads the target data from the first memory to the processing unit. When the first memory meets the direct read condition, the target data can be directly read from the second memory to the processing unit. Therefore, data reading from the second memory can be achieved regardless of whether the first memory is functioning properly, avoiding lag or even system crashes caused by the first memory's inability to read data normally, thereby improving the user experience of the electronic device.
[0111] Taking a Creator laptop as an example, a designer's laptop, professional graphic design places very high demands on the computer. First and foremost, the CPU must be multi-core and multi-threaded, the more the better, and the CPU's clock speed should be as high as possible. Secondly, the memory capacity must be large, at least 32GB or more. Some programs, such as 3D Max, even require as much memory as possible, using as much as possible. Therefore, when the memory required by the designer's running programs exceeds the laptop's configured memory capacity, memory overflow will occur. Currently, the solution is to use virtual memory, but this method is very slow and causes program lag, affecting the designer's work efficiency. However, for laptop design, the mainstream configuration is generally 16GB, with a maximum of 32GB. Increasing the memory would significantly increase the cost of the laptop.
[0112] In view of this, the technical solution in this application mainly proposes a novel CPU design architecture, Infinity DRAM (Dynamic Random Access Memory), which uses a scheme of parallel access of NVME and LPDDR by the CPU. By utilizing NVME, the capacity of LPDDR is significantly expanded, thereby improving the speed of program execution for designers and thus improving efficiency. This allows creators to no longer be affected by memory capacity issues.
[0113] refer to Figure 6 The hardware logic diagram shown illustrates that the laptop includes an NVMe SSD, RAID, and LPDDR, as well as a System-on-Chip (SOC) containing a CPU, a memory controller, an access scheduler, and a corresponding PCIe controller. The CPU contains multiple cores and an iGPU (Integrated Graphics Processor Unit). Both the cores and iGPU have cache functionality. The implementation in the laptop is as follows:
[0114] First, this application improves NVMe access speed by combining Infinity DRAM Architecture, in-memory computing, RAID (Redundant Arrays of Independent Disks), and an accelerator with a composite transmission architecture. Furthermore, it addresses the issue of program memory / video memory exhaustion in the Creator through an LPDDR / SSD Parallel Access Architecture. Therefore, this application achieves Infinity DRAM by redefining the CPU memory access architecture and dynamically implementing parallel data access between NVMe and LPDDR. Specifically:
[0115] First, regarding latency, L1 (L1 D-cache and L1 I-cache) typically has 2 to 4 clock cycles, L2 cache has 11 to 13, L3 cache has 30 to 35, LPDDR has approximately 100, and PCIe has approximately 300. However, for CXL bus, connected to a Ring, PCIe latency can be reduced to below 200.
[0116] Secondly, this application defines a new CXL.io architecture that reuses NVME and PCIe controllers with PCIe, and places it alongside system memory on the CPU Ring bus.
[0117] In NVME or CXL.io devices, NVME-like in-memory compute storage is used, and DRAM and Accelerator are added to accelerate data access and reduce data access latency.
[0118] Based on this, this application performs real-time monitoring of the memory usage of the program (i.e., the processing unit mentioned above):
[0119] First, the SSD completely places the FTL mapping table (i.e., the data mapping table mentioned earlier) into the DRAM cache;
[0120] For programs where LPDDR capacity is sufficient, data access is achieved by reading (calling) data into LPDDR via Direct Memory Access (DMA), and then the CPU accesses the data from LPDDR.
[0121] For some memory-intensive programs, such as large-scale 3D rendering, enabling SSD / LPDDR parallel access mode allows the SSD to synchronously put the FTL mapping table into the L4 Cache / eSRAM / eDRAM, prioritizing data calls to LPDDR. The CPU accesses data from LPDDR. When data overflows the LPDDR capacity, the CPU directly calls data from the SSD to the CPU L3 or L4 cache via PCIe or CXL. This allows for unlimited memory capacity expansion, compensating for the insufficient capacity of LPDDR.
[0122] In addition, it is necessary to maintain the consistency of the last data. When the last data in LPDDR and the first data in SSD belong to the same data, the cache address needs to be exclusively occupied, and the two data need to be merged into one data in the cache.
[0123] When some LPDDR data is cleared, meaning the LPDDR5 capacity is sufficient, CPU data access reverts to solely reading data from the SSD via LPDDR, such as... Figure 7 As shown:
[0124] When the CPU needs to access data, the DMA first moves the data from the SSD to LPDDR, and then the CPU moves the data from LPDDR to the CPU Cache.
[0125] When the CPU detects that the memory capacity is about to overflow, it manages the data access mode and directly calls the SSD data from the SSD to the CPU cache via CXL.iobus or PCIE bus.
[0126] It should be noted that data transfer between the CPU and LPDDR can be achieved in several ways.
[0127] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0128] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0129] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0130] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A data processing method, comprising: A data read request is obtained from the processing unit, wherein the data read request contains at least a data identifier of the data to be read; If the first memory meets the direct read condition, the target data corresponding to the data identifier is read from the second memory into the processing unit, so that the processing unit can process the target data according to the data read request; The first memory is different from the second memory; If the first memory does not meet the direct read condition, the target data is read from the second memory into the first memory, so that the processing unit can read the target data from the first memory into the processing unit according to the data read request and process the target data; The first memory satisfies the direct read condition as follows: the available storage area of the first memory is less than or equal to a preset storage threshold.
2. The method according to claim 1, wherein the processing unit stores a data mapping table, the data mapping table containing at least the data identifier and the data storage address; in, After receiving the data read request from the processing unit, the method further includes: The storage address of the target data is obtained according to the data mapping table; Wherein, if the storage address points to the first memory, the processing unit reads the target data from the first memory according to the storage address and processes the target data; If the storage address points to the second memory, the following steps are performed: reading the target data corresponding to the data identifier from the second memory into the processing unit, or reading the target data from the second memory into the first memory.
3. The method according to claim 2, after reading the target data from the second memory into the first memory, the method further includes: Update the data mapping table in the second memory according to the storage address of the target data in the first memory; The data mapping table in the second memory is updated in the processing unit.
4. The method according to claim 1 or 2, after obtaining the data read request from the processing unit, the method further includes: Detect the processing task corresponding to the data identifier; If the processing task satisfies the parallel reading condition, the first part of the data corresponding to the data identifier is read from the second memory into the processing unit, and the second part of the data corresponding to the data identifier is read from the second memory into the first memory, so that the processing unit can read the second part of the data from the first memory into the processing unit according to the data reading request, and the processing unit processes the first part of the data and the second part of the data. The parallel reading conditions include: the processing task is a task with a data processing volume greater than or equal to a processing threshold, or the processing task is a target type task.
5. The method according to claim 4, wherein the processing unit processes the first portion of data and the second portion of data, comprising: The processing unit merges the first part of data and the second part of data that correspond to the same data identifier to obtain the target data corresponding to the data identifier; The processing unit processes the target data.
6. The method according to claim 1 or 2, wherein reading the target data corresponding to the data identifier from the second memory to the processing unit comprises: The task scheduler reads the target data corresponding to the data identifier from the second memory, so that the task scheduler writes the target data into the cache area in the processing unit.
7. The method according to claim 6, wherein the task scheduler and the second memory are connected via a first bus interface; The task scheduler and the processing unit are connected via a second bus interface, and the bus latency of the first bus interface and the second bus interface is lower than a preset latency threshold.
8. A data processing apparatus, comprising: A request acquisition unit is used to acquire a data read request from the processing unit, wherein the data read request contains at least a data identifier of the data to be read; The first reading unit is configured to read the target data corresponding to the data identifier from the second memory into the processing unit if the first memory meets the direct reading conditions, so that the processing unit can process the target data according to the data reading request; The first memory is different from the second memory; The second reading unit is configured to read the target data from the second memory into the first memory if the first memory does not meet the direct reading conditions, so that the processing unit can read the target data from the first memory into the processing unit according to the data reading request and process the target data. The first memory satisfies the direct read condition as follows: the available storage area of the first memory is less than or equal to a preset storage threshold.
9. An electronic device, comprising: First memory; Second memory; Processing unit; A task scheduler is used to obtain a data read request from the processing unit, wherein the data read request contains at least a data identifier of the data to be read. If the first memory meets the direct read condition, the target data corresponding to the data identifier is read from the second memory into the processing unit, so that the processing unit can process the target data according to the data read request; wherein, the first memory and the second memory are different; if the first memory does not meet the direct read condition, the target data is read from the second memory into the first memory, so that the processing unit can read the target data from the first memory into the processing unit according to the data read request and process the target data; wherein, the first memory meets the direct read condition including: the available storage area of the first memory is less than or equal to a preset storage threshold.