Compilation methods, electronic devices, and media for masked vector instructions

Abstract

This application relates to the field of computer technology, and in particular to a compilation method, electronic device, and medium for masked vector instructions. The method is applied to an electronic device equipped with a compiler; and the method includes: the compiler acquiring a program to be compiled; the compiler determining that the program to be compiled includes first program code, and that the code form of the first program code conforms to the form of a preset conditional operator expression; the compiler generating a first vector instruction based on a first mask and a vector operation expression of the first program code; and the compiler determining that the operation mode of the first program code is a zeroing mode, then generating a second vector instruction. The compilation method for masked vector instructions provided in this application eliminates the need for users to remember and call built-in interfaces related to operation modes during programming, improving the versatility of program code and ease of use, and increasing programming efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a compilation method, electronic device, and medium for masked vector instructions. Background Technology

[0002] The process of data processing in electronic devices, such as Figure 1 As shown: First, the user inputs the program code for data processing into the electronic device 10. The compiler 100 compiles the received program code to obtain executable instructions or executable files, and stores them in the memory 200. The operating system of the electronic device 10 allocates the compiled executable instructions or executable files that can be executed by the processor 300 to the processor 300 for data processing.

[0003] Currently, when compiler 100 compiles program code that includes masked vector instructions, it needs to implement the compilation of masked vector instructions through a series of compiler built-in interfaces. For example, for the addition instructions of masked vectors op1 and op2, the corresponding program code can be: op1 = add_m(op1, op2, mask), where mask is the mask, add_m is a function used to call the built-in interface of the corresponding merge mode. When compiling this code, the compiler determines the compiler intrinsic number corresponding to the add_m function in the software architecture in the compilation backend, and generates the corresponding assembly instructions or binary instructions according to the intrinsic number to complete the compilation of the program code.

[0004] Because compilers from different companies have different software architectures, and the functions corresponding to intrinsic numbers differ across these architectures, users need to remember the `add_m` functions corresponding to various built-in interfaces in different architectures to call those interfaces. This lack of generality in user-input code across different architectures leads to low programming efficiency. Furthermore, to support masked vector operations, compilers need to provide specific built-in interfaces, including merge-mode and zero-mode interfaces, requiring software developers to spend significant time maintaining them. Summary of the Invention

[0005] To address the issues of the aforementioned code's lack of versatility and low programming efficiency, embodiments of this application provide a compilation method, electronic device, and readable storage medium for masked vector instructions.

[0006] In a first aspect, embodiments of this application provide a method for compiling masked vector instructions, applied to an electronic device on which a compiler is installed;

[0007] The method includes:

[0008] The compiler obtains the program to be compiled;

[0009] The compiler determines that the program to be compiled includes first program code, and the code form of the first program code conforms to the form of a preset conditional operator expression. The first program code includes a first mask of a masked vector instruction, a vector operation expression, and an operation mode, and the operation mode is a merge mode or a zeroing mode.

[0010] The compiler generates a first vector instruction based on the first mask of the first program code and the vector operation expression. The first vector instruction is used to characterize the vector operation corresponding to the first program code.

[0011] If the compiler determines that the operation mode of the first program code is the zeroing mode, it generates a second vector instruction, which is used to characterize the operation mode corresponding to the first program code as the zeroing mode.

[0012] The compilation method for masked vector instructions provided in this application allows users to input program code into the compiler simply by entering the first program code in the form of a conditional expression. Users do not need to remember and call built-in interfaces related to the operation mode during programming. Users can program vector instructions like ordinary programming, improving the versatility and ease of use of the program code, and increasing programming efficiency. Furthermore, the compiler does not need to provide built-in interfaces for matching vector instructions, reducing the number of compiler interfaces and lowering the maintenance cost of built-in interfaces.

[0013] Furthermore, since this embodiment does not require a built-in interface for vector operations, the variable corresponding to the result of the vector operation is not limited to one of the input variables participating in the vector operation.

[0014] In one possible implementation of the first aspect above, the preset conditional operator expression includes a first expression, a second expression, and a third expression, wherein the second expression is located between the first expression and the third expression;

[0015] The first expression corresponds to the first mask in the first program code, the second expression corresponds to the vector operation expression in the first program code, and the third expression corresponds to the operation mode in the first program code.

[0016] In one possible implementation of the first aspect above, the preset conditional operator expression includes a first expression, a second expression, and a third expression, wherein the second expression is located between the first expression and the third expression;

[0017] The first expression corresponds to the first mask in the first program code, the second expression corresponds to the operation mode in the first program code, and the third expression corresponds to the vector operation expression in the first program code.

[0018] In one possible implementation of the first aspect above, the method further includes:

[0019] The compiler inverts the first mask bitwise to obtain the second mask;

[0020] The compiler generates second program code, which includes the second mask, the vector operation expression, and the operation mode.

[0021] The compiler generates a third vector instruction based on the second mask in the second program code and the vector operation expression.

[0022] In one possible implementation of the first aspect above, the method further includes:

[0023] If the first mask does not match a Boolean vector type, then the comparison result of the mask and the zero vector is determined to be the third mask corresponding to the first expression;

[0024] The method further includes:

[0025] The compiler generates a fourth vector instruction based on the third mask and the vector operation expression of the first program code.

[0026] In one possible implementation of the first aspect above, if the compiler determines that the operation mode of the first program code is a zero-setting mode, then it generates a second vector instruction, including:

[0027] The compiler determines that the operation mode of the first program code is the zeroing mode;

[0028] The compiler generates zeroing operation instructions.

[0029] In one possible implementation of the first aspect above, the method further includes:

[0030] The compiler determines that the execution order of the first vector instructions precedes the execution order of the second vector instructions.

[0031] In one possible implementation of the first aspect above, the method further includes:

[0032] The compiler determines that the operation mode of the first program code is merge mode;

[0033] The compiler determines that the return variable of the first program code is different from the variable corresponding to the operation mode, and the compiler generates a copy operation instruction.

[0034] In one possible implementation of the first aspect above, the method further includes:

[0035] The compiler determines that the execution order of the first vector instructions is after the execution order of the copy operation instructions.

[0036] In one possible implementation of the first aspect above, the method further includes:

[0037] The compiler determines that the program to be compiled includes third program code, and the third program code is either the code of a pre-copy instruction or the code of a post-copy instruction.

[0038] In one possible implementation of the first aspect above, if the compiler determines that the operation mode of the first program code is a zero-setting mode, then it generates a second vector instruction, including:

[0039] If the third program code is the code of the pre-copy instruction, and the operation mode is the zero-setting mode, then the second vector instruction is generated;

[0040] If the third program code is the code of the copy-after instruction, and the operation mode is the merge mode, then the second vector instruction is generated.

[0041] In one possible implementation of the first aspect above, the method further includes:

[0042] The compiler identifies the second vector instruction using instruction identifiers;

[0043] The compiler generates a first vector instruction package, which includes the first vector instruction and the second vector instruction, based on the instruction identifier.

[0044] Secondly, embodiments of this application provide a compilation apparatus for masked vector instructions, applied to an electronic device on which a compiler is installed; the apparatus includes:

[0045] The program acquisition module is used by the compiler to acquire the program to be compiled;

[0046] The code analysis module is used by the compiler to determine that the program to be compiled includes first program code, and the code form of the first program code conforms to the form of a preset conditional operator expression. The first program code includes a first mask of a masked vector instruction, a vector operation expression, and an operation mode, and the operation mode is a merge mode or a zeroing mode.

[0047] The first instruction generation module is used by the compiler to generate a first vector instruction based on the first mask of the first program code and the vector operation expression, wherein the first vector instruction is used to characterize the vector operation corresponding to the first program code;

[0048] The second instruction generation module is used by the compiler to generate a second vector instruction when the compiler determines that the operation mode of the first program code is the zeroing mode. The second vector instruction is used to characterize the operation mode corresponding to the first program code as the zeroing mode.

[0049] Thirdly, embodiments of this application provide an electronic device, including one or more processors; one or more memories; and one or more memories storing one or more programs, which, when executed by one or more processors, cause the electronic device to execute the above-described compilation method for masked vector instructions.

[0050] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the above-described compilation method for masked vector instructions.

[0051] Fifthly, embodiments of this application provide a computer program product including instructions that, when executed, cause a computer to perform the above-described compilation method for masked vector instructions. Attached Figure Description

[0052] Figure 1 The diagram shown is an application scenario illustration provided by an embodiment of this application;

[0053] Figure 2 The diagram shown is a schematic representation of the operation process for calculating a masked vector instruction provided in an embodiment of this application.

[0054] Figure 3 The diagram shown is a compilation flow diagram of a compiler 100 provided in an embodiment of this application;

[0055] Figure 4 The diagram shown is a flowchart of a compilation method for masked vector instructions provided in an embodiment of this application;

[0056] Figure 5The diagram shown is a flowchart of another compilation method for masked vector instructions provided in an embodiment of this application;

[0057] Figure 6 The diagram shown is a schematic block diagram of the system structure of an electronic device provided in an embodiment of this application;

[0058] Figure 7 The diagram shown is a structural schematic of a SOC provided in an embodiment of this application;

[0059] Figure 8 The diagram shown is a schematic of a program module for a compilation apparatus for masked vector instructions provided in an embodiment of this application. Detailed Implementation

[0060] The illustrative embodiments of this application include, but are not limited to, a data processing method, an electronic device, and a readable storage medium. The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0061] In the following description, numerous technical details are presented to enable the reader to better understand the present invention. However, those skilled in the art will understand that the technical solutions claimed in the claims of the present invention can be implemented even without these technical details and with various variations and modifications based on the following embodiments.

[0062] To better understand the solutions of the embodiments of this application, the relevant terms and concepts that may be involved in the embodiments of this application will be introduced below.

[0063] Compilation: Compilation is the process of converting user programs (usually written in a high-level source language, or source files) into intermediate representations (IR), and performing multiple transformations on the IR to finally generate the corresponding target language code (usually assembly code or binary executable code oriented towards the target architecture).

[0064] A compiler is software that translates computer code written in one programming language (source language) into another language (target language). It generally consists of three parts: front-end, middleware, and back-end.

[0065] Vector register: A register used to perform vector calculations and / or store vector data.

[0066] Mask register: Used to store mask data, and the multi-bit mask values ​​correspond to the data elements of the vector register. The values ​​of each mask bit in the mask data control whether the corresponding data element in the vector register participates in vector operations.

[0067] Merge mode: The corresponding position of the vector register that does not participate in vector operations retains the original value after the vector operation is completed.

[0068] Zero mode: The corresponding position of the vector register that does not participate in vector operations is set to zero after the vector operation is completed.

[0069] Built-in functions: Non-standard compiler functions provided by the compiler that can be predefined or user-defined.

[0070] Instruction descent (Lowering): Dispatching instruction IRs to the functions that actually process them. For example, in a Low-Level Virtual Machine (LLVM) architecture, instruction descent is the process of converting IRs into SelectionDAGs, where SelectionDAGs are used to describe the program flow of the input programming code. That is, before instruction descent, the input program code is represented by IRs, and after instruction descent, the program code is described by SelectionDAGs.

[0071] The following is combined with Figure 1 The data processing process will be further described in conjunction with the electronic device 10.

[0072] like Figure 1 As shown, the electronic device 10 may include a compiler 100, a memory 200, and a processor 300. The compiler 100 is the hardware structure of the electronic device 10, used to compile received programs. The memory 200 and processor 300 are the hardware structure of the electronic device 10; the memory 200 stores the program, the compiled executable instructions, etc., and the processor 300 performs data processing, such as vector operations.

[0073] It is understood that processor 300 may include application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU), etc.

[0074] It is understood that electronic device 10 may include, but is not limited to: laptop computers, desktop computers, tablet computers, mobile phones, servers, wearable devices, head-mounted displays, mobile email devices, portable game consoles, e-reader devices, televisions, etc.

[0075] Specifically, when a program is input into the electronic device 10, the compiler 100 compiles the received program to obtain executable instructions or an executable file, and stores it in the memory 200. The system of the electronic device 10 allocates the compiled executable instructions or executable file, which can be executed by the processor 300, to the processor 300 for data processing.

[0076] It is understood that the processor 300 may include an execution unit 301. The execution unit 301 is used to execute instructions, such as compiled masked vector instructions, and may include circuitry for executing instructions.

[0077] It is understood that the processor 300 may also include a register set 302. Register set 302 may include one or more sets of vector registers 311 and one or more sets of mask registers 312. Each vector register 311 may be 512-bit, 256-bit, or 128-bit wide, or may use different vector widths. Each mask register 312 may contain multiple mask bits, each mask bit corresponding to a data element in a vector register 311. For example, a 64-bit mask register may be used to mask 64 8-bit data elements of a 512-bit register. For vector registers with different widths (e.g., 256-bit or 128-bit) and data elements of different lengths (e.g., 16-bit, 32-bit, or 64-bit), vector operations can be combined to use different numbers of mask bits.

[0078] The processor 300 executes masked vector instructions. Specifically, the execution unit 301 can read the vector instruction from the memory 200 and obtain the corresponding mask and vector operands. The execution unit 301 can assign the read mask to the mask register 312 and the vector operands to the vector register 311. When the execution unit 301 executes the vector instruction, it can control the corresponding data elements in the vector register 311 to participate in the vector operations in the vector instruction through the mask in the mask register 312.

[0079] The following diagram, with reference to the accompanying figures, illustrates the computation process of masked vector instructions executed by processor 300. For ease of explanation, Figure 2Each vector register 311 is shown to have eight data elements. In other embodiments, the vector register 311 may have a different number of data elements. The vector register 311 may be 128-bit, 256-bit, or 512-bit wide, or different widths may be used. Since each vector register has eight data elements, only eight mask bits are used in combination for each vector register. Furthermore, the vector operation is described using addition as an example.

[0080] Figure 2 The diagram shown is a schematic representation of the operation process of calculating a masked vector instruction according to an embodiment of this application.

[0081] like Figure 2 As shown, vector register 311 may include vector register t1 and vector register t2. Vector register t1 stores vector data A and the result of adding vector data A and vector data B, vector register t2 stores vector data B and A. j B j The subscript j is used to indicate the number of the data element in the vector data. The mask register K is used to store the mask, and a mask bit value of 1 indicates that the data element corresponding to that mask bit participates in the addition operation, while a mask bit value of 0 indicates that the data element corresponding to that mask bit does not participate in the addition operation. Therefore, after executing A+B, the data in each data bit of vector register t1, vector register t2, and mask register K are as follows: Figure 2 As shown.

[0082] If the mask values ​​corresponding to mask bits 6, 2, and 1 of mask register K are 0, it means that data elements A6, A2, and A1 in vector register t1 do not participate in the addition operation. The value of the corresponding data bits in vector register t1 after the addition operation can be determined according to the corresponding operation mode, i.e., merge mode or zeroing mode.

[0083] When the operation mode is merge mode, after the addition operation is performed, the data elements C6, C2 and C1 in the vector register t1 retain their original values.

[0084] When the operation mode is set to zero, after the addition operation is performed, the data elements C6, C2, and C1 in the vector register t1 will be zero.

[0085] To facilitate understanding of the methods in the embodiments of this application, the following is combined with... Figure 3 The compilation process of compiler 100 will be introduced.

[0086] Figure 3 The diagram shown is a compilation process diagram of a compiler 100 provided in an embodiment of this application.

[0087] like Figure 3 As shown, the compilation process of compiler 100 includes three stages:

[0088] (1) Front end

[0089] The front end may include lexical analysis 321, syntax analysis 322 and semantic analysis 323.

[0090] Lexical analysis 321 may include: scanning the characters of the source program line by line using a lexical analyzer to identify each word in the source program, determining the type of each word, converting the identified words into a unified internal representation, that is, converting them into lexical unit (token) form, and obtaining the category code and attribute value of each word. For example, the category code of keyword words in the source program code is one code per word, and the attribute value is keyword. For example, the category code of constant words in the source program code is one code per type, and the attribute value is constant.

[0091] The syntax analysis 322 may include: identifying various phrases from the token sequence output by the lexical analyzer using a parser, and constructing a parse tree. The root node of the parse tree can be a "sentence", the child nodes can be various phrases and words that make up the "sentence", and the leaf nodes correspond to the grammatical type of each word in the "sentence", such as "preposition", "article", "noun", etc.

[0092] Semantic analysis 323 may include: performing type checking on the parsing tree, such as type binding, type inference, variable resolution and other semantic-related operations.

[0093] (2) Mid-range

[0094] The middle section can include intermediate representation 324, code optimization 325, etc.

[0095] The intermediate representation 324 can include the compiler's conversion of the front-end processing results into an internal representation, representing the semantics and syntactic structure of the source program. Each stage of the compiler performs analysis or optimization transformations on the intermediate representation. The intermediate representation can be an abstract syntax tree, reverse Polish notation, or 3-address code, etc. In some embodiments, conditional expressions in the intermediate representation can be represented using the (vselect) instruction.

[0096] Among them, code optimization 325 can include: optimizing and improving intermediate representation results in order to generate better target code, where "better" may be aimed at being faster, shorter, or less energy-consuming.

[0097] (3) Backend

[0098] The backend can include instruction selection 326, register allocation 327, instruction rearrangement 328, and then generate the final executable instruction file.

[0099] The instruction selection 326 may include: selecting an instruction that matches the mid-output from a set of multiple instructions executable by the processor 300, based on the result or optimization level of the code optimization.

[0100] Register allocation 327 can include: allocating variables, instructions, etc., that were allocated to virtual registers during the intermediate representation process to physical registers. Virtual registers are registers in an abstract sense, meaning they don't have corresponding hardware structures, while physical registers are the actual registers that exist on the processor 1300. This can be understood as... Figure 1 The vector register 311 and the mask register 312 on the register group 302 of the processor 300 are physical registers.

[0101] The instruction reordering 328 may include: analyzing multiple instructions selected in the instruction selection, the data dependencies between instructions, setting instructions without data dependencies as parallel instructions, and setting the instruction execution order of instructions with data dependencies according to their dependencies.

[0102] As mentioned earlier, in current solutions, for masked vector instructions, users generally need to be familiar with and call the corresponding built-in interfaces for vector operations. Furthermore, because different software architectures have different built-in interfaces, users need to remember various built-in interfaces for different software architectures to program vector operations, making programming cumbersome and resulting in low code versatility. Moreover, software architectures require specific built-in interfaces to implement corresponding vector operations, and maintaining these built-in interfaces consumes significant time and resources.

[0103] To address the aforementioned problems, this application provides a compilation method for masked vector instructions. Specifically, in this application embodiment, when the compiler 100 compiles the input program, for the vector instruction code portion of the program code, if it is confirmed that the vector instruction code portion satisfies the form of a conditional operation expression, the compiler 100 can generate a first vector instruction representing a masked vector operation based on the mask in the vector instruction code portion and the vector operation. Furthermore, when the operation mode in the conditional operation expression is a zero-based mode, a second vector instruction representing the operation mode can be generated. The conditional operation expression can include a mask, a vector operation, and a corresponding operation mode. For example, the form of the conditional operation expression is "mask?(op1+op2):a", where mask represents a mask, op1+op2 represents a vector operation, and a represents the operation mode.

[0104] The compilation method for masked vector instructions provided in this application allows users to input only the masked vector instruction code portion according to the conditional operation expression when inputting program code into the compiler 100. Users do not need to remember and call built-in interfaces related to the operation mode during programming. Users can program vector instructions like ordinary programming, improving the versatility and ease of use of the program code, and increasing programming efficiency. Furthermore, the compiler does not need to provide built-in interfaces for matching vector instructions, reducing the number of compiler interfaces and lowering the maintenance cost of built-in interfaces.

[0105] Furthermore, since this embodiment does not require a built-in interface for vector operations, the variable corresponding to the result of the vector operation is not limited to one of the input variables participating in the vector operation.

[0106] It can be understood that the mask indicates whether a corresponding position of the operand (i.e., the vector data mentioned above) participates in the vector operation. Each mask bit can correspond to one data element of the operand, meaning one mask bit can correspond to 1 bit of data in the operand, in which case the data element is 1 bit; it can also correspond to 8 bits of data, in which case the data element is 8 bits. This correspondence is related to the data type of the operand. In some embodiments, the mask can be a binary sequence, where 0 can indicate that the data element at the corresponding position in the operand does not participate in the vector operation, and 1 indicates that the data element at the corresponding position in the operand participates in the vector operation; alternatively, 0 can indicate that the data element at the corresponding position in the operand participates in the vector operation, and 1 indicates that the data element at the corresponding position in the operand does not participate in the vector operation. This application does not impose any restrictions on this.

[0107] It is understood that vector operations can be logical operations performed on input operands, such as addition, multiplication, shifting, multiply-accumulate, and accumulation. Vector operations can include a single type of operation or a mixture of multiple types of operations; this application does not impose any restrictions on this.

[0108] In some embodiments, vector operations can be operations supported by library files linked by the compiler, or operations supported by non-standard compilers, i.e., built-in functions. This application does not impose any restrictions on this.

[0109] It is understood that the conditional operation expression can be represented in the form of "expression 1 ? expression 2 : expression 3", where expression 1 can represent a mask, expression 2 can represent a vector operation, and expression 3 can represent an operation mode. In some other embodiments, expression 2 can represent an operation mode, expression 3 can represent a vector operation, and expression 1 can represent a mask. This application does not limit this.

[0110] It can be understood that the first vector instruction is an instruction generated based on the mask and vector operations. For example, for the program code "op3 = mask?(op1+op2): 0", the first vector instruction of the assembly language generated by the compiler can be "add.wt3, t1, t2, p0", where t3 corresponds to the vector register where the operand op3 is located, t1 corresponds to the vector register where the operand op2 is located, and p0 corresponds to the mask register where the mask is located.

[0111] It can be understood that the operation mode, namely the zeroing mode and the merge mode mentioned earlier, is used to indicate the value of data bits that do not participate in vector operations. Therefore, for the zeroing mode, the second vector instruction can be a zeroing operation instruction, used to assign the value of the data bits in the vector data that do not participate in the operation to zero, which is then used as the value of the corresponding data bit in the vector operation result.

[0112] For example, for the program code "op3=mask?(op1+op2):0", the generated second vector instruction can be a zero-assignment operation instruction. The corresponding assembly language code can be, for example, "movz.post t3", which is used to assign the data bits of the data elements in the result operand op3 that do not participate in the vector operation to 0 in the vector register t3 where the operand op3 is located.

[0113] In some embodiments, for the operation mode of merge mode, a copy operation instruction may or may not be generated, depending on the return value of the conditional operation expression and the parameters of the operation mode.

[0114] For example, the program code "op3 = mask?(op1+op2):op4" can generate a copy operation instruction. The corresponding assembly language code can be, for example, "mov.pre t3, t4", which is used to copy the value of the data bit in the vector register t4 where operand op4 is located to the corresponding data bit in the vector register t3 where operand op3 is located.

[0115] It is understood that the examples of program code and assembly language code in the above examples are merely examples of embodiments of this application. Those skilled in the art can make adaptive changes according to different high-level programming languages ​​and assembly languages, and this application does not impose any limitations on them.

[0116] The compiler generates a first vector instruction representing the masked vector operation based on the mask in the conditional operator and the vector operation. Furthermore, when the operation mode in the conditional expression is set to zero, it can generate a second vector instruction representing the operation mode. Specifically, this can include the compiler performing the following steps during compilation: Figure 3In the intermediate representation stage 324, the compiler can generate the vselect instruction of the intermediate representation of the conditional operation expression based on the conditional operation expression. This occurs during the instruction descent process in the compilation backend. Figure 3 In the instruction selection stage 326, the compiler can perform specific processing on the vselect instruction. Specifically, based on the vector operations and masks in the conditional expression, it generates a first vector instruction, and when the operation mode in the conditional expression is zeroed, it generates a second vector instruction. Specifically, for the zeroed operation mode, the first vector instruction precedes the second vector instruction. Therefore, when the processor 300 executes the executable program compiled by the compiler 100, when the operation mode is zeroed, the processor 300 can execute the first vector instruction first, and then execute the second vector instruction.

[0117] The following is combined with Figure 4 This application provides a detailed description of a compilation method for masked vector instructions in its embodiments.

[0118] It is understandable that, since the compilation of the conditional expression in this embodiment requires judging its truth value, i.e., the compiler 100 needs to support (bool) vectors, in order to better implement the method in this embodiment, programming languages ​​that do not support bool vectors need to be extended to support bool vectors. For example, the OpenCL compiler supports integer (int) vectors but not bool vectors, so the OpenCL compiler needs to be extended to support bool vectors.

[0119] Figure 4 The diagram shows a flowchart of a compilation method for masked vector instructions provided in an embodiment of this application.

[0120] like Figure 4 As shown, the compilation method for masked vector instructions in this application embodiment includes:

[0121] 401: Compiler 100 retrieves program code input from the user.

[0122] It is understood that the program code obtained by the compiler can be in a high-level programming language, such as C, C++, OpenCL, etc., and this application does not impose any restrictions on this.

[0123] 402: Compiler 100 has determined that the program code contains masked vector instructions that are represented as conditional operation expressions.

[0124] The conditional expression can be understood as "expression1 ? expression2 : expression3". Here, expression1 is a boolean value with two possible values: 0 (false) and 1 (true), used to determine whether a condition is true or false. If the condition is true, expression1 evaluates to 1; otherwise, it evaluates to 0. The conditional operator "expression1 ? expression2 : expression3" can be understood as follows: when expression1 evaluates to 1, the conditional expression returns the value of expression2; when expression1 evaluates to 0, the conditional expression returns the value of expression3.

[0125] It can be understood that the code for a masked vector instruction, represented as a conditional operation expression, can be "mask variable ? vector operation expression : operation mode variable". This masked vector instruction means that when the mask bit of the mask variable is 1, the data element corresponding to that mask bit in the operands participating in the vector operation expression participates in the vector operation; when the mask bit of the mask variable is 0, the data element corresponding to that mask bit in the operands participating in the vector operation expression does not participate in the vector operation. Furthermore, the value corresponding to that mask bit in the return value of the conditional operation expression can be determined based on the operation mode variable when the mask bit of the mask variable is 0. Specifically, when the operation mode variable represents the operation mode as the merge mode, then when the value of the mask bit of the mask variable is 0, the value corresponding to the mask bit in the return value of the conditional operation expression retains the value of the data element corresponding to the operand in the original vector operation expression; when the operation mode variable represents the operation mode as the zero-set mode, then when the value of the mask bit of the mask variable is 0, the value corresponding to the mask bit in the return value of the conditional operation expression is assigned to zero.

[0126] It is understandable that the data type of the mask variable is a Boolean vector type, the data type of the operands in the vector operation expression is a vector type, and the data type of the operation mode variable is a vector type.

[0127] It is understood that the vector operations corresponding to the vector operation expression can be logical operations performed on the input operands, such as addition, multiplication, shifting, multiply-accumulate, and accumulation. Vector operations can include a single operation type or a mixture of multiple operation types; this application does not impose any restrictions on this.

[0128] In some embodiments, vector operations can be operations supported by library files linked by the compiler, or operations supported by non-standard compilers, i.e., built-in functions. This application does not impose any restrictions on this.

[0129] It can be understood that the data corresponding to the variables involved in the vector operation in the vector operation expression is stored in the vector register 311, and the data corresponding to the mask variable is stored in the mask register 312.

[0130] In some embodiments, the code representing a masked vector instruction in the form of a conditional operation expression can be "mask variable?operation mode variable: vector operation expression". Before executing steps 403 and 404, compiler 100 can first invert the vector data of the mask variable corresponding to expression 1 and swap the contents of expressions 2 and 3. For example, for the program code "op3 = mask? 0: (op1 + op2)", compiler 100 determines that expression 2 corresponds to operation mode vector 0. Therefore, before executing steps 403 and 404 to generate the first and second vector instructions, compiler 100 will generate a bitwise inversion instruction for "mask", reversing the 0s and 1s in the mask vector. For example, ... Figure 2 The mask in the mask register K is obtained by inverting the bits of "10111001" to get the mask "01000110". Furthermore, compiler 100 swaps the 0 vector corresponding to expression 2 with the addition expression corresponding to expression 3, thus modifying the conditional operation expression to obtain the conditional operator expression "op3 = mask?(op1+op2) : 0". Here, mask is the bit-inverted mask vector.

[0131] In some embodiments, if the compiler 100 determines that the function corresponding to the vector operation expression in the conditional operation expression is a compiler intrinsic function, then the compiler 100 can determine the correspondence between intrinsic functions and intrinsic numbers in the software architecture, and determine the built-ins interface and generated instructions corresponding to the intrinsic function. The compiler can then execute steps 404 and 405 below.

[0132] In some embodiments, after executing step 402, compiler 100 can evaluate expression 1 in the conditional expression, i.e., the mask variable, to determine whether the mask variable is a bool vector. If it is a bool vector, steps 403 and 404 are executed; otherwise, the mask variable needs to be compared with a zero vector, and the return value of the comparison result is the bool vector corresponding to the mask variable. For example, if the mask variable in the conditional expression in the input program code is an integer vector, compiler 100 determines that the mask variable is not a bool vector. Then, compiler 100 can generate a comparison instruction to compare the integer vector with the zero vector, and use the return value of the comparison instruction as expression 1 in the conditional expression.

[0133] In some embodiments, before executing step 403, compiler 100 may perform intermediate representation and optimization of the program code through a compilation front-end and a compilation middle-end. Specifically, in the compilation middle-end, compiler 100 may, for example... Figure 3 The intermediate representation of stage 324 in the middle is the vselect instruction that generates the intermediate representation of the conditional operation expression based on the conditional operation expression.

[0134] It is understandable that the compiler 100 can perform an intermediate representation of the conditional operator expression to obtain the vselect instruction.

[0135] 403: Compiler 100 generates the first vector instruction based on the mask variables and vector operation expressions in the code of the masked vector instruction.

[0136] It can be understood that the first vector instruction is an instruction generated based on the mask and vector operations. This first vector instruction may include the vector register corresponding to the vector operation return value, the vector operation instruction, the vector register corresponding to the vector operation, and the mask register corresponding to the mask.

[0137] In some embodiments, step 403, generating the first vector instruction based on the mask variable and vector operation expression in the code of the masked vector instruction, specifically includes: the compiler performing this process at the compilation backend, i.e., during the instruction descent process at the compilation backend. Figure 3 In the instruction selection stage 326, the compiler can process the vselect instructions generated by the intermediate representation stage based on the conditional operation expression. That is, the compiler 100 can generate the first vector instruction, which includes the vector register corresponding to the vector operation return value, the vector operation instruction, the vector register corresponding to the vector operation, and the mask register corresponding to the mask, based on the vector operation and mask in the conditional operation expression.

[0138] For example, for the program code "op3 = mask?(op1 + op2): 0", the first vector instruction in the assembly language generated by the compiler can be "add.w t3, t1, t2, p0", where t3 corresponds to the vector register where operand op3 is located, t1 corresponds to the vector register where operand op2 is located, p0 corresponds to the mask register where the mask is located, and add.w means performing an addition operation on a 32-bit vector data.

[0139] 404: If compiler 100 determines that the operation mode in the code of the masked vector instruction is set to zero, then it generates a second vector instruction.

[0140] It can be understood that the operation mode, namely the zeroing mode and the merge mode mentioned earlier, is used to indicate the value of data bits that do not participate in vector operations. Therefore, for the zeroing mode, the second vector instruction can be a zeroing operation instruction, used to assign the value of the data bits in the vector data that do not participate in the operation to zero, which is then used as the value of the corresponding data bit in the vector operation result.

[0141] For example, for the program code "op3=mask?(op1+op2):0", the generated second vector instruction can be a zero-assignment operation instruction. The corresponding assembly language code can be, for example, "movz.post t3", which is used to assign the data bits of the data elements in the result operand op3 that do not participate in the vector operation to 0 in the vector register t3 where the operand op3 is located.

[0142] In some embodiments, for the operation mode of merge mode, a copy operation instruction may or may not be generated, depending on the return value of the conditional operation expression and the parameters of the operation mode.

[0143] For example, the program code "op3 = mask?(op1+op2):op4" can generate a copy operation instruction. The corresponding assembly language code could be, for example, "mov.pre t3, t4", which copies the values ​​of the data bits corresponding to the data elements in operand op1 that are not involved in vector operations from the vector register t4 where operand op4 is located to the corresponding data bits in the vector register t3 where operand op3 is located. Conversely, the program code "op3 = mask?(op1+op2):op3" can be used without generating a copy operation instruction.

[0144] In some embodiments, step 404 specifically includes: during the instruction descent process of the compilation backend, i.e. Figure 3 In the instruction selection stage 326, the compiler can perform specific processing on the vselect instruction, generating a second vector instruction when the operation mode in the conditional expression is determined to be zero-mode.

[0145] In some embodiments, the compiler 100 may sort the execution order of the first vector instruction and the second vector instruction during the instruction reordering stage. Specifically, for the operation mode of zeroing, the first vector instruction precedes the second vector instruction. Therefore, when the processor 300 executes the executable program compiled by the compiler 100, when the operation mode is zeroing, the processor 300 may execute the first vector instruction first, and then execute the second vector instruction.

[0146] In some embodiments, for copy operation instructions generated based on the merge operation mode, the first vector instruction follows the copy operation instruction. Therefore, when the processor 300 executes the executable program compiled by the compiler 100, the processor 300 may execute the second vector instruction first, and then execute the first vector instruction.

[0147] In some embodiments, the compiler 100 can package the first vector instruction and the second vector instruction. For example, for the program code "op3 = mask?(op1 + op2): 0", the following first vector instruction and second vector instruction can be generated:

[0148] {add.w t3, t1, t2, p0;

[0149] movz.post t3;}

[0150] The meaning of each parameter has been explained in the previous text and will not be repeated here.

[0151] For example, for the program code "op3 = mask?(op1 + op2): op3", the following first vector instruction can be generated, and the second vector instruction does not need to be generated:

[0152] {add.w t3, t1, t2, p0;}

[0153] The meaning of each parameter has been explained in the previous text and will not be repeated here.

[0154] For example, given the program code "op3 = mask?(op1 + op2): op4", the following first vector instruction and second vector instruction can be generated:

[0155] {mov.pre t3, t4;

[0156] add.w t3, t1, t2, p0;}

[0157] The meaning of each parameter has been explained in the previous text and will not be repeated here.

[0158] The compilation method for masked vector instructions provided in this application allows users to input only the masked vector instruction code portion according to the conditional operation expression when inputting program code into the compiler 100. Users do not need to remember and call built-in interfaces related to the operation mode during programming. Users can program vector instructions like ordinary programming, improving the versatility and ease of use of the program code, and increasing programming efficiency. Furthermore, the compiler does not need to provide built-in interfaces for matching vector instructions, reducing the number of compiler interfaces and lowering the maintenance cost of built-in interfaces.

[0159] Furthermore, since this embodiment does not require a built-in interface for vector operations, the variable corresponding to the result of the vector operation is not limited to one of the input variables participating in the vector operation.

[0160] The following is combined with Figure 5 Another compilation method for masked vector instructions provided in this application embodiment will be introduced. It will be understood that in this embodiment, the Very Long Instruction Word (VLIM) architecture corresponding to compiler 100 includes pre-move instructions and post-move instructions, and compiler 100 supports bool vector types.

[0161] Figure 5 The diagram shows a flowchart of another compilation method for masked vector instructions provided in an embodiment of this application.

[0162] like Figure 5 As shown, the compilation method for masked vector instructions in this application embodiment includes:

[0163] 501: Compiler 100 obtains the program code input by the user. Step 501 is the same as step 401, and will not be described again here.

[0164] 502: Compiler 100 has determined that the program code contains masked vector instructions that are represented as conditional operation expressions, as well as target copy code.

[0165] It is understood that the code for the masked vector instruction represented as a conditional operation expression is similar to that in step 402. The difference is that in this embodiment, the operation mode variable is fixed and can be a zero vector or a variable corresponding to the return value of the conditional operation expression. That is, in this embodiment, the compiler 100 has a default operation mode, which is either the zeroing mode or the merging mode, and the user does not need to change the setting of this expression.

[0166] It is understandable that the target copy code can be either the code for pre-copy instructions or the code for post-copy instructions. Users can modify the default operation mode of compiler 100 through the target instruction code. This will be explained in detail in step 504 below, and will not be elaborated upon here.

[0167] 503: Compiler 100 generates the first vector instruction based on the mask variable and vector operation expression in the code of the masked vector instruction. Step 503 is the same as step 403, and will not be described again here.

[0168] 504: Compiler 100 determines the target operation mode of the masked vector instruction based on the operation mode variables in the target copied code and the code of the masked vector instruction.

[0169] It can be understood that the second vector instruction can be a pre-copy instruction or a post-copy instruction. The pre-copy instruction is used to maintain the default operation mode, while the post-copy instruction is used to change the default operation mode.

[0170] For example, when the operation mode variable in the conditional operation expression indicates that the default operation mode of compiler 100 is merge mode, and the target copy code in the program code is the code of the pre-copy instruction, the target operation mode corresponding to the generated pre-copy instruction is merge mode; when the operation mode variable in the conditional operation expression indicates that the default operation mode of compiler 100 is merge mode, and the target copy code in the program code is the code of the post-copy instruction, the target operation mode corresponding to the generated post-copy instruction is zero-set mode.

[0171] 505: When compiler 100 determines that the target operation mode is zeroing mode, it generates a second vector instruction and marks the second vector instruction with an instruction identifier. The second vector instruction generated in steps 505 and 404 is generated using the same method, and will not be described in detail here.

[0172] It is understandable that the second vector instruction is marked by an instruction identifier, which may specifically include the compiler 100 marking the second vector instruction in the instruction description.

[0173] In some embodiments, for the operation mode of merge mode, a copy operation instruction may or may not be generated, depending on the return value variable of the conditional operation expression and the variable of the operation mode.

[0174] For example, the program code "op3 = mask?(op1+op2):op4" can generate a copy operation instruction. The corresponding assembly language code could be, for example, "mov.pre t3, t4", which copies the values ​​of the data bits corresponding to the data elements in operand op1 that are not involved in vector operations from the vector register t4 where operand op4 is located to the corresponding data bits in the vector register t3 where operand op3 is located. Conversely, the program code "op3 = mask?(op1+op2):op3" can be used without generating a copy operation instruction.

[0175] 506: Compiler 100 generates a vector instruction package that includes the first vector instruction and the second vector instruction based on the instruction identifier of the second vector instruction.

[0176] It can be understood that step 506 involves the compiler 100 packaging the first vector instruction and the second vector instruction according to the instruction identifier, for example, by enclosing the first vector instruction and the second vector instruction in a single instruction package using square brackets. The program code input in step 501 can correspond to multiple instruction packages. Each instruction package can include at least two instructions.

[0177] Figure 6 The diagram shown is a schematic block diagram of the system structure of an electronic device applied to the method in the embodiment of this application.

[0178] Electronic device 600 may include one or more processors 601 coupled to system control logic 603. In at least one embodiment, system control logic 603 communicates with processor 601 via a multi-branch bus such as a front-side bus (FSB), a point-to-point interface such as a Fast-Ahead Interconnect (QPI), or a similar connection. Processor 601 executes instructions that control general types of data processing operations. In some embodiments, system control logic 603 includes, but is not limited to, graphics memory system control logic (GMCH) (not shown) and an input / output hub (IOH) (which may be on a separate chip) (not shown), wherein the GMCH includes memory and a graphics controller and is coupled to the IOH.

[0179] Electronic device 600 may further include a coprocessor 602 and a memory 604 coupled to system control logic 603. Alternatively, one or both of the memory and GMCH may be integrated within the processor (as described in this application), with memory 604 and coprocessor 602 directly coupled to processor 601 and system control logic 603, which resides on a single chip with IOH. Memory 604 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of both. In one embodiment, coprocessor 602 is such as, for example, a high-throughput MIC processor, a network or communication processor, a graphics processor, a GPGPU, or an embedded processor, etc. Specifically, the compilation method for masked vector instructions in the embodiments of this application is applied to... Figure 6 The coprocessor 602 or processor 601 in the text can be understood as the coprocessor 602 or processor 601 being... Figure 1 The processor 300 in the middle.

[0180] In one embodiment, electronic device 600 may further include a network interface (NIC) 606. Network interface 606 may include a transceiver for providing a radio interface for electronic device 600 to communicate with any other suitable device, such as a front-end module, antenna, etc. In various embodiments, network interface 606 may be integrated with other components of electronic device 600. Network interface 606 can implement the functions of the communication unit in the above embodiments.

[0181] Electronic device 600 may further include input / output (I / O) devices 605. I / O 605 may include: a user interface designed to enable a user to interact with electronic device 600; a peripheral component interface designed to enable peripheral components to also interact with electronic device 600; and / or sensors designed to determine environmental conditions and / or location information related to electronic device 600.

[0182] It is worth noting that, Figure 6 This is merely an example. That is, although... Figure 6 The diagram shows that the electronic device 600 includes multiple devices such as a processor 601, system control logic 603, and memory 604. However, in practical applications, the system using the methods of this application may only include a portion of the devices in the electronic device 600. For example, it may only include the processor 601 and the NIC 606. Figure 6 The properties of the optional devices are shown by dashed lines.

[0183] Figure 7 The diagram shown is a structural schematic of a SOC provided in an embodiment of this application. Figure 7 In this designation, similar components share the same reference numerals. Additionally, the dashed box is an optional feature for more advanced SOCs. Figure 7 In this embodiment, the SOC 700 includes: an interconnect unit 705 coupled to a processor 701; a system proxy unit 707; a bus controller unit 708; an integrated memory control unit 704; a group or one or more coprocessors 702, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 703; and a direct memory access (DMA) unit 706. In one embodiment, the coprocessor 701 includes a dedicated processor, such as, for example, a network or communication processor, a GPGPU, a high-throughput MIC processor, or an embedded processor, etc. The processor 701 and the coprocessor 702 may correspond to... Figure 1 The processor 300 in the middle.

[0184] Figure 8The diagram shown is a program module schematic of a compilation apparatus 800 for masked vector instructions provided in an embodiment of this application. It can be used to execute the compilation method for masked vector instructions provided in this embodiment, for example, executing steps 401 to 404 as described above. This embodiment provides a compilation apparatus for masked vector instructions, applied to an electronic device, on which a compiler is installed; the apparatus includes:

[0185] The program acquisition module 801 is used by the compiler to acquire the program to be compiled.

[0186] The code analysis module 802 is used by the compiler to determine that the program to be compiled includes first program code, and the code form of the first program code conforms to the form of a preset conditional operator expression. The first program code includes a first mask of a masked vector instruction, a vector operation expression, and an operation mode, and the operation mode is either a merge mode or a zeroing mode.

[0187] The first instruction generation module 803 is used by the compiler to generate a first vector instruction based on the first mask and vector operation expression of the first program code. The first vector instruction is used to characterize the vector operation corresponding to the first program code.

[0188] The second instruction generation module 804 is used by the compiler to generate a second vector instruction when the compiler determines that the operation mode of the first program code is the zero-set mode. The second vector instruction is used to represent that the operation mode of the first program code is the zero-set mode.

[0189] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0190] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0191] The program code can be implemented using a high-level programming language or an object-oriented programming language to communicate with the processing system. This includes, but is not limited to, OpenCL, C, C++, and Java. However, for languages ​​like C++ and Java, due to the need for storage conversion, the application of the data processing method in the embodiments of this application may differ somewhat. Those skilled in the art can make modifications based on specific high-level languages, all without departing from the scope of the embodiments of this application.

[0192] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0193] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0194] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0195] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0196] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A compilation method for masked vector instructions, applied to electronic devices, characterized in that, The electronic device is equipped with a compiler; The method includes: The compiler obtains the program to be compiled; The compiler determines that the program to be compiled includes first program code, and the code form of the first program code conforms to the form of a preset conditional operator expression. The first program code includes a first mask of a masked vector instruction, a vector operation expression, and an operation mode, and the operation mode is a merge mode or a zeroing mode. The compiler generates a first vector instruction based on the first mask of the first program code and the vector operation expression. The first vector instruction is used to characterize the vector operation corresponding to the first program code. If the compiler determines that the operation mode of the first program code is the zeroing mode, it generates a second vector instruction, which is used to characterize the operation mode corresponding to the first program code as the zeroing mode.

2. The compilation method for masked vector instructions according to claim 1, characterized in that, The preset conditional operator expression includes a first expression, a second expression, and a third expression, with the second expression located between the first expression and the third expression; The first expression corresponds to the first mask in the first program code, the second expression corresponds to the vector operation expression in the first program code, and the third expression corresponds to the operation mode in the first program code.

3. The compilation method for masked vector instructions according to claim 1, characterized in that, The preset conditional operator expression includes a first expression, a second expression, and a third expression, with the second expression located between the first expression and the third expression; The first expression corresponds to the first mask in the first program code, the second expression corresponds to the operation mode in the first program code, and the third expression corresponds to the vector operation expression in the first program code.

4. The compilation method for masked vector instructions according to claim 3, characterized in that, Also includes: The compiler inverts the first mask bitwise to obtain the second mask; The compiler generates second program code, which includes the second mask, the vector operation expression, and the operation mode. The compiler generates a third vector instruction based on the second mask in the second program code and the vector operation expression.

5. The compilation method for masked vector instructions according to claim 2, characterized in that, Also includes: If the first mask does not match a Boolean vector type, then the comparison result of the mask and the zero vector is determined to be the third mask corresponding to the first expression; The method further includes: The compiler generates a fourth vector instruction based on the third mask and the vector operation expression of the first program code.

6. The compilation method for masked vector instructions according to claim 1, characterized in that, If the compiler determines that the operation mode of the first program code is zeroing mode, it generates a second vector instruction, including: The compiler determines that the operation mode of the first program code is the zeroing mode; The compiler generates zeroing operation instructions.

7. The compilation method for masked vector instructions according to claim 6, characterized in that, Also includes: The compiler determines that the execution order of the first vector instructions precedes the execution order of the second vector instructions.

8. The compilation method for masked vector instructions according to claim 1, characterized in that, Also includes: The compiler determines that the operation mode of the first program code is merge mode; The compiler determines that the return variable of the first program code is different from the variable corresponding to the operation mode, and the compiler generates a copy operation instruction.

9. The compilation method for masked vector instructions according to claim 8, characterized in that, Also includes: The compiler determines that the execution order of the first vector instructions is after the execution order of the copy operation instructions.

10. The compilation method for masked vector instructions according to claim 1, characterized in that, Also includes: The compiler determines that the program to be compiled includes third program code, and the third program code is either the code of a pre-copy instruction or the code of a post-copy instruction.

11. The compilation method for masked vector instructions according to claim 10, characterized in that, If the compiler determines that the operation mode of the first program code is zeroing mode, it generates a second vector instruction, including: If the third program code is the code of the pre-copy instruction, and the operation mode is the zero-setting mode, then the second vector instruction is generated; If the third program code is the code of the copy-after instruction, and the operation mode is the merge mode, then the second vector instruction is generated.

12. The compilation method for masked vector instructions according to claim 11, characterized in that, Also includes: The compiler identifies the second vector instruction using instruction identifiers; The compiler generates a first vector instruction package, which includes the first vector instruction and the second vector instruction, based on the instruction identifier.

13. An electronic device, characterized in that, include: Memory, used to store instructions executed by one or more processors of an electronic device, and A processor is one of the processors in an electronic device, used to control the compilation method for masked vector instructions as described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, The storage medium stores instructions that, when executed on a computer, cause the computer to perform the compilation method for masked vector instructions as described in any one of claims 1 to 12.

15. A computer program product, characterized in that, The computer program product includes instructions that, when executed, cause a computer to perform the compilation method for masked vector instructions as described in any one of claims 1 to 12.

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