Dag evaluation method, apparatus, device, and storage medium

Abstract

The disclosure provides a directed acyclic graph evaluation method and device, equipment and storage medium, relates to the technical field of artificial intelligence, specifically relates to the technical field of directed acyclic graph generation, concurrency evaluation and the like, and can be applied to the scene of directed acyclic graph design, risk judgment and quality evaluation of directed acyclic graph. The specific implementation scheme comprises the following steps: obtaining a directed acyclic graph; determining the target independent predecessor point set corresponding to each node in the directed acyclic graph according to the adjacency relationship between the nodes; determining the initial concurrency of the directed acyclic graph according to the node quantity of at least one target independent predecessor point set with the largest node quantity in the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph; and evaluating the directed acyclic graph according to the initial concurrency. The disclosure can evaluate the concurrency of the directed acyclic graph before the directed acyclic graph is applied.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of artificial intelligence, in particular to the technical field of directed acyclic graph generation, concurrency evaluation and the like, which can be applied to scenarios such as directed acyclic graph design, risk judgment and quality evaluation of directed acyclic graph, and particularly relates to a directed acyclic graph evaluation method and device, equipment and a storage medium. BACKGROUND

[0002] A directed acyclic graph (DAG) is a graph theory data structure, generally referring to a loop-free directed graph. The DAG structure has natural concurrency capability and is often used in services with parallel computing as a business process organization scheme, such as the SuperMario framework, a graph execution engine and the like.

[0003] In actual business policy access, the design of the DAG corresponding to the business process usually depends on the experience of engineers, and unreasonable concurrency setting of the DAG (such as too large or too small concurrency) may cause problems such as abnormal overall service function of the business process, resource waste, poor stability and the like.

[0004] At present, the concurrency of the DAG is usually set by a person according to historical experience values and obtained after repeated stress testing and debugging; or calculated according to dynamic performance data of each node in the DAG in the running process. SUMMARY

[0005] The present disclosure provides a directed acyclic graph evaluation method, device, equipment and storage medium, which can evaluate the concurrency of the directed acyclic graph before the directed acyclic graph is applied.

[0006] According to a first aspect of the present disclosure, a directed acyclic graph evaluation method is provided, the method comprising:

[0007] obtaining a directed acyclic graph, the directed acyclic graph comprising at least two nodes; determining a target independent predecessor point set corresponding to each node in the directed acyclic graph according to an adjacency relationship between the nodes in the directed acyclic graph; the target independent predecessor point set corresponding to the node being a set of nodes which do not have a predecessor relationship with each other in the directed acyclic graph and do not have a predecessor relationship with other nodes in the target independent predecessor point set; determining an initial concurrency of the directed acyclic graph according to the number of nodes in the largest target independent predecessor point set among the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph; and evaluating the directed acyclic graph according to the initial concurrency.

[0008] According to a second aspect of the present disclosure, a directed acyclic graph evaluation device is provided, the device comprising:

[0009] The acquisition unit is configured to acquire a directed acyclic graph, the directed acyclic graph comprising at least two nodes; the concurrency degree calculation unit is configured to determine, according to an adjacency relationship between the nodes in the directed acyclic graph, a target independent predecessor point set corresponding to each node in the directed acyclic graph; the target independent predecessor point set corresponding to the node is a set of nodes that do not have a predecessor relationship with each other between the nodes in the directed acyclic graph and do not have a predecessor relationship with each other between the nodes in the target independent predecessor point set; and the concurrency degree calculation unit is further configured to determine, according to the target independent predecessor point sets corresponding to all the nodes in the directed acyclic graph, a node quantity of at least one target independent predecessor point set with a maximum node quantity, an initial concurrency degree of the directed acyclic graph; and the evaluation unit is configured to evaluate the directed acyclic graph according to the initial concurrency degree.

[0010] According to a third aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to the first aspect.

[0011] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, the computer instructions being used to enable a computer to perform the method according to the first aspect.

[0012] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, the computer program being used to implement the method according to the first aspect when executed by a processor.

[0013] The present disclosure determines, by acquiring a directed acyclic graph, according to an adjacency relationship between nodes in the directed acyclic graph, a target independent predecessor point set corresponding to each node in the directed acyclic graph; according to the target independent predecessor point sets corresponding to all the nodes in the directed acyclic graph, a node quantity of at least one target independent predecessor point set with a maximum node quantity, an initial concurrency degree of the directed acyclic graph, and then evaluates the directed acyclic graph according to the initial concurrency degree, which realizes concurrency degree evaluation of the directed acyclic graph before application of the directed acyclic graph, can guide a designer to set a more optimal concurrency degree for the directed acyclic graph, and has a lower human cost. In addition, the present disclosure evaluates the concurrency degree of the directed acyclic graph before application of the directed acyclic graph, which realizes earlier risk evaluation of the directed acyclic graph, can improve algorithm access efficiency, and reduces invalid development and testing due to early unreasonable design of the directed acyclic graph.

[0014] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. Attached Figure Description

[0015] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0016] Figure 1 A schematic flowchart illustrating the directed acyclic graph evaluation method provided in this embodiment of the disclosure;

[0017] Figure 2 A schematic diagram of a directed acyclic graph provided in an embodiment of this disclosure;

[0018] Figure 3 Provided for the embodiments of this disclosure Figure 1 A schematic diagram of an implementation process for S102 in the middle;

[0019] Figure 4 Another schematic diagram of the directed acyclic graph evaluation method provided in the embodiments of this disclosure;

[0020] Figure 5 A schematic diagram of the composition of the directed acyclic graph evaluation device provided in the embodiments of this disclosure;

[0021] Figure 6 Another schematic diagram of a directed acyclic graph evaluation apparatus provided in an embodiment of this disclosure;

[0022] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0023] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0024] It should be understood that in the embodiments of this disclosure, the character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0025] A directed acyclic graph (DAG) is a graph theory data structure, generally referring to a directed graph without cycles. DAG structures possess inherent concurrency capabilities and are often used in services with parallel computation capabilities as a business process organization solution, such as the SuperMario framework and graph execution engines.

[0026] In actual business policy access, the design of the DAG corresponding to the business process usually depends on the experience of engineers, and unreasonable (such as too large or too small) concurrency of the DAG may cause problems such as abnormal service function of the overall business process, waste of resources, poor stability, and the like.

[0027] At present, the concurrency of the DAG is usually set by a person according to historical experience values and obtained after repeated stress testing and debugging; or calculated according to dynamic performance data of each node in the DAG in the running process.

[0028] Among them, the way of setting the concurrency of the DAG by a person according to historical experience values and obtaining it after repeated stress testing and debugging needs to consume a large amount of manpower, and it is difficult to adjust the concurrency of the DAG to the global optimum. If the concurrency of the DAG is set too high, it may cause excessive initialization of resources, waste of online resources of the business process, and low utilization rate; if the concurrency of the DAG is set too low, it may cause data calculation blocking of the business process, which will seriously affect the response time of online services.

[0029] The way of calculating the concurrency of the DAG according to dynamic performance data of each node in the DAG in the running process needs to be completed in the running process, and after the new concurrency of the DAG is calculated, the system of the business process needs to be reinitialized according to the new concurrency of the DAG, which affects the overall service level agreement (SLA) of the system of the business process to the outside, introduces additional risks, and is not suitable for actual production environment.

[0030] The present disclosure provides a directed acyclic graph evaluation method, which can evaluate the concurrency of a directed acyclic graph before the directed acyclic graph is applied.

[0031] The method can guide the designer to set a more optimal concurrency for the directed acyclic graph, and the cost of human resources is low. In addition, the method evaluates the concurrency of the directed acyclic graph before the directed acyclic graph is applied, realizes earlier risk evaluation of the directed acyclic graph, can improve the algorithm access efficiency, and reduce invalid development and testing caused by unreasonable early design of the directed acyclic graph.

[0032] The execution subject of the method can be a computer or a server, or can also be other devices with data processing capability. Herein, the execution subject of the method is not limited.

[0033] In some embodiments, the server can be a single server, or it can be a server cluster consisting of multiple servers. In some embodiments, the server cluster can also be a distributed cluster. This disclosure does not limit the specific implementation of the server.

[0034] The following provides an exemplary illustration of the method for evaluating directed acyclic graphs.

[0035] Figure 1 This is a schematic flowchart illustrating the directed acyclic graph evaluation method provided in this embodiment of the disclosure. Figure 1 As shown, the method may include:

[0036] S101. Obtain a directed acyclic graph, which includes at least two nodes.

[0037] In this context, a directed acyclic graph (DAG) refers to a DAG corresponding to a business process; that is, a DAG designed specifically for the business process. Business processes can be online or offline; there are no restrictions on the specific type of business process.

[0038] The nodes included in a directed acyclic graph are the nodes involved in the business process. For example, a directed acyclic graph can include the start node, calculation node, end node, and after-end node in the business process.

[0039] S102. Based on the adjacency relationships between nodes in the directed acyclic graph, determine the target-independent predecessor set corresponding to each node in the directed acyclic graph.

[0040] Here, the target-independent predecessor set corresponding to a node is the set of nodes in the directed acyclic graph that have no predecessor relationship with the node and have no predecessor relationship with other nodes in the target-independent predecessor set.

[0041] For example, Figure 2 This is a schematic diagram of a directed acyclic graph provided in an embodiment of this disclosure. For example... Figure 2 As shown in the example, the directed acyclic graph can include nodes A, B, C, D, E, F, and G. Node A is adjacent to node B via the directed edge "A-->B", node A is adjacent to node C via the directed edge "A-->C", and node A is adjacent to node D via the directed edge "A-->D". Node B is adjacent to node E via the directed edge "B-->E", and node E is adjacent to node G via the directed edge "E-->G". Node C is adjacent to node F via the directed edge "C-->F", and node F is adjacent to node G via the directed edge "F-->G". Node D is adjacent to node F via the directed edge "D-->F". These directed edges represent the adjacency relationships between nodes A, B, C, D, E, F, and G.

[0042] For example, taking node 1 and node 2 as an example, in the embodiment of the present disclosure, node 1 directly points to node 2 through a directed edge, and node 1 is a direct predecessor node of node 2; node 1 indirectly points to node 2 through a directed edge, and node 1 is an indirect predecessor node of node 2. When node 1 is a direct predecessor node or an indirect predecessor node of node 2, it indicates that there is a predecessor relationship between node 1 and node 2. Conversely, if there is no predecessor relationship between node 1 and node 2, it means that node 1 is neither a direct predecessor node nor an indirect predecessor node of node 2, and node 2 is neither a direct predecessor node nor an indirect predecessor node of node 1.

[0043] That is, for any two nodes, when neither of the two nodes is a predecessor node (including a direct predecessor or an indirect predecessor) of the other node, there is no predecessor relationship between the two nodes, and in the embodiment of the present disclosure, the two nodes can also be referred to as irrelevant nodes of each other.

[0044] For example, taking Figure 2 as an example, for each of nodes A, B, C, D, E, F, and G, a target irrelevant predecessor point set corresponding to each node can be determined according to the adjacency relationship between nodes in Figure 2 .

[0045] For example, in Figure 2 , for node A, node A is a direct predecessor node of nodes B, C, and D, and is an indirect predecessor node of nodes E, F, and G. The nodes that have no predecessor relationship with node A (i.e., the irrelevant nodes of node A) can include 0 nodes. The set of irrelevant nodes of node A can be referred to as the irrelevant point set of node A (which is empty at this time).

[0046] For node B, node A is a direct predecessor node of node B, and node B is a direct predecessor node of node E and an indirect predecessor node of node G. The nodes that have no predecessor relationship with node B (i.e., the irrelevant nodes of node B) can include nodes C, D, and F. That is, nodes C, D, and F form the irrelevant point set of node B.

[0047] For node C, node A is a direct predecessor node of node C, and node C is a direct predecessor node of node F and an indirect predecessor node of node G. The nodes that have no predecessor relationship with node C (i.e., the irrelevant nodes of node C) can include nodes B, D, and E. That is, nodes B, D, and E form the irrelevant point set of node C.

[0048] For node D, node A is a direct predecessor node of node D, node D is a direct predecessor node of node F, and is an indirect predecessor node of node G. Nodes that do not have a predecessor relationship with each other (i.e., irrelevant nodes of node D) can include: node B, node C, and node E. That is, node B, node C, and node E form an irrelevant node set of node D.

[0049] For node E, node A is an indirect predecessor node of node E, node B is a direct predecessor node of node E, and node E is a direct predecessor node of node G. Nodes that do not have a predecessor relationship with each other (i.e., irrelevant nodes of node E) can include: node C, node D, and node F. That is, node C, node D, and node F form an irrelevant node set of node E.

[0050] For node F, node A is an indirect predecessor node of node F, nodes C and D are direct predecessor nodes of node F, and node F is a direct predecessor node of node G. Nodes that do not have a predecessor relationship with each other (i.e., irrelevant nodes of node F) can include: node B and node E. That is, node B and node E form an irrelevant node set of node F.

[0051] For node G, nodes A, B, C, and D are indirect predecessor nodes of node G, nodes E and F are direct predecessor nodes of node G, and there can be 0 nodes that do not have a predecessor relationship with each other (i.e., irrelevant nodes of node G). That is, the irrelevant node set of node G is empty.

[0052] For the irrelevant node set of each of nodes A to G, only one node can be retained in the irrelevant node set if the nodes have a predecessor relationship with each other, i.e., a target irrelevant predecessor node set corresponding to the node can be obtained. That is, the target irrelevant predecessor node set corresponding to the node is a set of nodes that do not have a predecessor relationship with each other in the directed acyclic graph and do not have a predecessor relationship with other nodes in the target irrelevant predecessor node set.

[0053] For example, taking node B as an example, the irrelevant node set of node B can include: nodes C, D, and F. Among them, node C is a predecessor node of node F, so node F can be deleted from the irrelevant node set of node B, and only node C is retained between nodes C and F. At this time, the set composed of the remaining nodes C and D can be the target irrelevant predecessor node set corresponding to node B.

[0054] S103, according to the number of nodes in at least one target irrelevant predecessor node set with the largest number of nodes in the target irrelevant predecessor node sets corresponding to all nodes in the directed acyclic graph, determine the initial concurrency degree of the directed acyclic graph.

[0055] As described in S102, for each node in the directed acyclic graph, a target independent predecessor point set corresponding to the node can be determined. The number of nodes (i.e., the number of contained nodes) in the target independent predecessor point set corresponding to different nodes can be the same or different.

[0056] In S103, for the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph, at least one target independent predecessor point set with the largest number of nodes can be selected from the target independent predecessor point sets, and the initial concurrency degree of the directed acyclic graph can be determined according to the number of nodes of the at least one target independent predecessor point set with the largest number of nodes.

[0057] For example, the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph can be sorted from high to low according to the number of nodes, and then the first N target independent predecessor point sets (i.e., the N target independent predecessor point sets with the largest number of nodes) in the sorting result can be selected, and the initial concurrency degree of the directed acyclic graph can be determined according to the number of nodes of the N target independent predecessor point sets. N can be an integer greater than or equal to 1.

[0058] For example, when N is greater than 1, the average, median, or other value of the number of nodes of the N target independent predecessor point sets can be taken, or a value randomly selected from the number of nodes of the N target independent predecessor point sets can be taken, and 1 can be added to the value as the initial concurrency degree. The present disclosure does not limit the way of calculating the initial concurrency degree.

[0059] When N is equal to 1, the maximum number of nodes in all target independent predecessor point sets (i.e., the target independent predecessor point set containing the most nodes) is taken as the initial concurrency degree. The target independent predecessor point set with the maximum number of nodes can be referred to as the maximum predecessor point set.

[0060] The present disclosure does not limit the way of calculating the initial concurrency degree.

[0061] In S104, the directed acyclic graph is evaluated according to the initial concurrency degree.

[0062] In the embodiments of the present disclosure, when the directed acyclic graph is evaluated according to the initial concurrency degree, the size of the initial concurrency degree can be judged. When the initial concurrency degree is too large, it indicates that the directed acyclic graph is too bloated and may not meet the requirements of computing security and resource utilization. When the initial concurrency degree is too small, it indicates that the directed acyclic graph may cause insufficient concurrency and cause the problem of waiting for idling of operators (such as computing nodes).

[0063] That is, in the embodiments of the present disclosure, the quality of the directed acyclic graph, such as whether it is bloated, can be evaluated according to the size of the initial concurrency degree.

[0064] The method provided by the embodiments of the present disclosure comprises the following steps: determining a target independent predecessor point set corresponding to each node in the directed acyclic graph; determining an initial concurrency degree of the directed acyclic graph according to the number of nodes in at least one target independent predecessor point set with the largest number of nodes in the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph; and evaluating the concurrency degree of the directed acyclic graph based on the initial concurrency degree. The process can be completed after the design of the directed acyclic graph and before the application of the directed acyclic graph. Not only is a large amount of human cost saved, but also the time for evaluating the concurrency degree of the directed acyclic graph is greatly advanced. For example, in the embodiments of the present disclosure, the concurrency degree of the directed acyclic graph can be evaluated directly without completing the code writing and testing processes, and the directed acyclic graph can be used in the early stage of structure design, thereby improving the algorithm access efficiency and reducing the invalid development and testing caused by early unreasonable design.

[0065] That is, the present disclosure comprises the following steps: acquiring a directed acyclic graph; determining a target independent predecessor point set corresponding to each node in the directed acyclic graph according to the adjacency relationship between the nodes in the directed acyclic graph; determining an initial concurrency degree of the directed acyclic graph according to the number of nodes in at least one target independent predecessor point set with the largest number of nodes in the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph; and evaluating the directed acyclic graph according to the initial concurrency degree. The present disclosure realizes the evaluation of the concurrency degree of the directed acyclic graph before the application of the directed acyclic graph, can guide the designer to set a more optimal concurrency degree for the directed acyclic graph, and has a low human cost. In addition, the present disclosure realizes the earlier risk evaluation of the directed acyclic graph, can improve the algorithm access efficiency, and reduces the invalid development and testing caused by early unreasonable design of the directed acyclic graph.

[0066] Figure 3 For the embodiments of the present disclosure Figure 1 An implementation flowchart of S102 in the method is shown in FIG. 2. As shown in FIG. 2, in some embodiments, S102 can comprise the following steps: Figure 3 As shown in FIG. 2, in some embodiments, S102 can comprise the following steps:

[0067] For any first node in the directed acyclic graph, S301-S303 are performed.

[0068] S301: determining a second node that does not have a predecessor relationship with the first node according to the adjacency relationship between the first node and other nodes in the directed acyclic graph.

[0069] That is, in the embodiments of the present disclosure, for any first node in the directed acyclic graph, the node that does not have a predecessor relationship with the first node can be referred to as a second node. The second node is an independent node of the first node. The set composed of the second nodes is an independent point set of the first node.

[0070] For example, taking the first node as Figure 2 For example, taking the node B in the directed acyclic graph as an example, according to the adjacency relationship between the node B and other nodes in the directed acyclic graph, the second nodes (the irrelevant nodes of the node B) that do not have a predecessor relationship with the node B can include the node C, the node D, and the node F, as described in the foregoing embodiments.

[0071] S302, the second nodes are screened according to the rule that only one node with a predecessor relationship is retained, to obtain at least one irrelevant predecessor point set corresponding to the first node.

[0072] Similarly, taking the first node as Figure 2 For example, taking the node B in the directed acyclic graph as an example, according to the adjacency relationship between the node B and other nodes in the directed acyclic graph, the second nodes (the irrelevant nodes of the node B) that do not have a predecessor relationship with the node B can include the node C, the node D, and the node F, as described in the foregoing embodiments.

[0073] In S302, the irrelevant nodes of the node B can be screened according to the rule that only one node with a predecessor relationship is retained, to obtain at least one irrelevant predecessor point set corresponding to the node B.

[0074] For example, among the node C, the node D, and the node F, the node C and the node D are both predecessor nodes of the node F. When the node C, the node D, and the node F are screened according to the rule that only one node with a predecessor relationship is retained, in one implementation manner, the node C and the node D can be deleted, and only the node F is retained; in another implementation manner, the node F can be deleted, and only the node C and the node D are retained. For the node B, the two implementation manners can respectively obtain one irrelevant predecessor point set corresponding to the node B. That is, the irrelevant predecessor point set corresponding to the node B can include two, the first one is “the node F”, and the second one is “the node C, the node D”.

[0075] S303, a target irrelevant predecessor point set with the largest number of nodes is determined from the at least one irrelevant predecessor point set corresponding to the first node.

[0076] After the at least one irrelevant predecessor point set corresponding to the first node is obtained in S302, a target irrelevant predecessor point set with the largest number of nodes can be determined from the at least one irrelevant predecessor point set corresponding to the first node.

[0077] For example, similarly, taking the first node as Figure 2 For example, taking the node B in the directed acyclic graph as an example, according to the adjacency relationship between the node B and other nodes in the directed acyclic graph, the second nodes (the irrelevant nodes of the node B) that do not have a predecessor relationship with the node B can include the node C, the node D, and the node F, as described in the foregoing embodiments.

[0073] In S302, the irrelevant nodes of the node B can be screened according to the rule that only one node with a predecessor relationship is retained, to obtain at least one irrelevant predecessor point set corresponding to the node B.

[0074] For example, among the node C, the node D, and the node F, the node C and the node D are both predecessor nodes of the node F. When the node C, the node D, and the node F are screened according to the rule that only one node with a predecessor relationship is retained, in one implementation manner, the node C and the node D can be deleted, and only the node F is retained; in another implementation manner, the node F can be deleted, and only the node C and the node D are retained. For the node B, the two implementation manners can respectively obtain one irrelevant predecessor point set corresponding to the node B. That is, the irrelevant predecessor point set corresponding to the node B can include two, the first one is “the node F”, and the second one is “the node C, the node D”.

[0075] S303, a target irrelevant predecessor point set with the largest number of nodes is determined from the at least one irrelevant predecessor point set corresponding to the first node.

[0076] After the at least one irrelevant predecessor point set corresponding to the first node is obtained in S302, a target irrelevant predecessor point set with the largest number of nodes can be determined from the at least one irrelevant predecessor point set corresponding to the first node.

[0077] For example, similarly, taking the first node as Figure 2 For example, taking the node B in the directed acyclic graph as an example, according to the adjacency relationship between the node B and other nodes in the directed acyclic graph, the second nodes (the irrelevant nodes of the node B) that do not have a predecessor relationship with the node B can include the node C, the node D, and the node F, as described in the foregoing embodiments.

[0073] In S302, the irrelevant nodes of the node B can be screened according to the rule that only one node with a predecessor relationship is retained, to obtain at least one irrelevant predecessor point set corresponding to the node B.

[0074] For example, among the node C, the node D, and the node F, the node C and the node D are both predecessor nodes of the node F. When the node C, the node D, and the node F are screened according to the rule that only one node with a predecessor relationship is retained, in one implementation manner, the node C and the node D can be deleted, and only the node F is retained; in another implementation manner, the node F can be deleted, and only the node C and the node D are retained. For the node B, the two implementation manners can respectively obtain one irrelevant predecessor point set corresponding to the node B. That is, the irrelevant predecessor point set corresponding to the node B can include two, the first one is “the node F”, and the second one is “the node C, the node D”.

[0075] S303, a target irrelevant predecessor point set with the largest number of nodes is determined from the at least one irrelevant predecessor point set corresponding to the first node.

[0076] After the at least one irrelevant predecessor point set corresponding to the first node is obtained in S302, a target irrelevant predecessor point set with the largest number of nodes can be determined from the at least one irrelevant predecessor point set corresponding to the first node.

[0077] For example, similarly, taking the first node as Figure 2 For example, taking the node B in the directed acyclic graph as an example, according to the adjacency relationship between the node B and other nodes in the directed acyclic graph, the second nodes (the irrelevant nodes of the node B) that do not have a predecessor relationship with the node B can include the node C, the node D, and the node F, as described in the foregoing embodiments.

[0078] In the embodiments of the present disclosure, for each node in the directed acyclic graph, the target set of independent predecessors of the node is determined from the set of independent predecessors corresponding to the node, which has the largest number of nodes, so that the initial concurrency of the directed acyclic graph can be maximized when the initial concurrency of the directed acyclic graph is determined, and the designer can be guided to set a globally optimal concurrency for the directed acyclic graph.

[0079] In some other embodiments, the present disclosure can also determine a certain set of independent predecessors of the first node as the target set of independent predecessors from the at least one set of independent predecessors corresponding to the first node, which has a node number ranking second, third, or the like, or can also randomly select a set of independent predecessors as the target set of independent predecessors, which is not limited herein.

[0080] In some embodiments, the S104 can include: when the initial concurrency is greater than the preset concurrency threshold, determining that the concurrency evaluation result of the directed acyclic graph is inflation.

[0081] The concurrency threshold can be set according to experience by manually considering resource utilization and actual production environment for algorithms with high CPU / GPU resource requirements such as video and image. When the initial concurrency is greater than the concurrency threshold, the method can directly output the evaluation result of the concurrency of the directed acyclic graph as inflation. The evaluation result of the concurrency of the directed acyclic graph as inflation indicates that the graph structure of the directed acyclic graph is too inflated, and service splitting is needed, and remote calling is performed in the main service.

[0082] In the embodiments, by comparing the initial concurrency with the preset concurrency threshold, the evaluation result of the concurrency of the directed acyclic graph can be more intuitively given.

[0083] In some embodiments, the directed acyclic graph evaluation method can further include: evaluating redundant nodes in the directed acyclic graph according to input data and output data of each node in the directed acyclic graph.

[0084] Exemplarily, as described in the foregoing embodiments, the nodes included in the directed acyclic graph, i.e., the nodes involved in the business process, can include a start node, a calculation node, an end node, an after end node, and the like in the business process. Among them, the start node, the end node, and the after end node are three special types of nodes. The directed acyclic graph starts from the start node, which is generally for request resolution or parameter verification. Through the calculation of various operators, such as video download, frame cutting, feature calculation, and the like, the calculation results can be transmitted to the end node for packaging and return. The after end node can perform post-processing (i.e., environmental cleaning work) on the pictures and videos downloaded to the local, and then mark the start node, the end node, and the after end node.

[0085] In this embodiment, the redundant node refers to a node without data flowing in or out, which has no actual contribution to the function calculation. According to the input data and the output data of each node in the directed acyclic graph, it can be determined whether all output data of a certain calculation node in the directed acyclic graph does not form a connection with any operator (i.e., node) in the directed acyclic graph. If such a calculation node exists, the calculation node is a redundant node, which wastes the computing resources.

[0086] In this embodiment, by analyzing the input data and the output data of each node in the directed acyclic graph, it can be evaluated whether the nodes in the directed acyclic graph are redundant nodes, thereby guiding the designer to modify the directed acyclic graph to reduce the waste of computing resources by the redundant nodes.

[0087] In some embodiments, the directed acyclic graph evaluation method can further include: evaluating redundant output data in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0088] Exemplarily, for any node in the directed acyclic graph, when the node has multiple output data, if a certain data is not input into other operators (other nodes), the output data can be considered as redundant output, which wastes certain computing and storage resources. By analyzing the input data and the output data of each node in the directed acyclic graph, it can be evaluated whether there is redundant output data in the directed acyclic graph.

[0089] In this embodiment, by evaluating whether there is redundant output data in the directed acyclic graph, the designer can be guided to modify the directed acyclic graph to reduce the waste of computing and storage resources.

[0090] In some embodiments, the method for evaluating the directed acyclic graph further comprises: evaluating whether there is a loop in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0091] Generally, a loop structure should not appear in the structure (framework) of the directed acyclic graph. The loop structure will cause the nodes in the directed acyclic graph to be unable to execute or to execute abnormally. In this embodiment, whether there is a loop in which the output data is the input data of itself can be analyzed according to the input data and the output data of each node in the directed acyclic graph. When the loop appears, it indicates that there is an error in the implementation logic of the directed acyclic graph.

[0092] In this embodiment, by evaluating whether there is a loop in the directed acyclic graph, the designer can be guided to modify the directed acyclic graph, thereby reducing the implementation logic errors in the directed acyclic graph.

[0093] In some embodiments, the method for evaluating the directed acyclic graph further comprises: evaluating whether there is a post-processing in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0094] As described in the foregoing embodiments, the after end node can perform post-processing (i.e., environmental cleaning) on the pictures and videos downloaded to the local. In this embodiment, whether there is a post-processing in the directed acyclic graph can be analyzed and evaluated according to the input data and the output data of each node in the directed acyclic graph.

[0095] In this embodiment, by evaluating whether there is a post-processing in the directed acyclic graph, the designer can be guided to set an effective post-processing for the directed acyclic graph, thereby ensuring that the directed acyclic graph has a normal environmental cleaning in the application process.

[0096] In some other embodiments, the method for evaluating the directed acyclic graph further comprises: analyzing whether some common operator (node) of the write operation type such as “download” has a connection to the after end node according to the input data and the output data of each node in the directed acyclic graph; when the node of the write operation type has a connection to the after end node, it indicates that the production environment corresponding to the directed acyclic graph has a risk of being full of disk.

[0097] It should be understood that the evaluation of the directed acyclic graph described in the foregoing embodiments is performed before the directed acyclic graph is applied, and early risk evaluation of the directed acyclic graph before the directed acyclic graph is applied is achieved, which can guide the designer to design a better directed acyclic graph, has a lower human cost, improves the algorithm access efficiency, and reduces the invalid development and testing caused by the unreasonable early design of the directed acyclic graph.

[0098] Figure 4 Another flowchart of the method for evaluating a directed acyclic graph is provided for the embodiments of the present disclosure.

[0099] As shown in Figure 4 some embodiments, the method for evaluating a directed acyclic graph can include:

[0100] S401: Obtain time consumption data of each node in the directed acyclic graph at runtime.

[0101] The time consumption data of a node at runtime refers to the time length required for the node to complete a task.

[0102] S402: Determine path time consumption of each execution path in the directed acyclic graph according to the time consumption data of all nodes included in the execution path.

[0103] Determining the path time consumption of each execution path according to the time consumption data of all nodes included in the execution path in the directed acyclic graph can include: for each execution path, summing the time consumption data of all nodes in the execution path to obtain the path time consumption of the execution path.

[0104] For example, as shown in the directed acyclic graph in the above Figure 2 example, Figure 2 the directed acyclic graph can include the following execution paths: “A->B->E->G”, “A->C->F->G”, “A->D->F->G”, and the like.

[0105] For the execution path “A->B->E->G”, the time consumption data of node A, node B, node E, and node G can be summed, and the sum is the path time consumption of the execution path “A->B->E->G”.

[0106] For the execution path “A->C->F->G”, the time consumption data of node A, node C, node F, and node G can be summed, and the sum is the path time consumption of the execution path “A->C->F->G”.

[0107] For the execution path “A->D->F->G”, the time consumption data of node A, node D, node F, and node G can be summed, and the sum is the path time consumption of the execution path “A->D->F->G”.

[0108] S403: Determine the path time consumption variance of the directed acyclic graph according to the path time consumption of each execution path.

[0109] That is, in S403, the variance between the path time consumption of all execution paths in the directed acyclic graph can be calculated to obtain the path time consumption variance of the directed acyclic graph.

[0110] For example, the same as the above Figure 2 For example, Figure 2 The directed acyclic graph shown in FIG. 3 can include the following execution paths: "A->B->E->G", "A->C->F->G", "A->D->F->G", etc. The variance of the path time consumption of the execution path "A->B->E->G", the variance of the path time consumption of the execution path "A->C->F->G", and the variance of the path time consumption of the execution path "A->D->F->G" can be calculated in S403, and the calculated variance is the variance of the path time consumption of the directed acyclic graph shown in FIG. 3. Figure 2 The variance of the path time consumption of the directed acyclic graph shown in FIG. 3.

[0111] In S404, whether the directed acyclic graph needs to be optimized is evaluated according to the variance of the path time consumption.

[0112] In the embodiments of the present disclosure, the size of the variance of the path time consumption can be judged when the variance of the path time consumption is used to evaluate whether the directed acyclic graph needs to be optimized and in reverse. When the variance of the path time consumption is too large, it indicates that the calculation overhead of part of the paths in the directed acyclic graph is large, and the whole service is blocked, which can cause the idle waiting scenario of other nodes, and the directed acyclic graph needs to be optimized.

[0113] It can be understood that in the online service of the directed acyclic graph execution framework, the response time consumption of the service is determined by the longest time consumption path (i.e., the execution path). In the embodiments of the present disclosure, the time consumption data of each node can be input, the breadth-first search (BFS) algorithm can be used to traverse and obtain all the execution paths of the directed acyclic graph, the time consumption of each node on each path can be accumulated, and the variance of the path time consumption of the directed acyclic graph can be calculated. Then, whether the directed acyclic graph needs to be optimized is evaluated according to the variance of the path time consumption of the directed acyclic graph.

[0114] Optionally, when the variance of the path time consumption is too large, single-node time consumption optimization or path structure disassembly and independent deployment can be suggested.

[0115] In the directed acyclic graph evaluation method provided by the embodiments of the present disclosure, the time consumption data of each node in the directed acyclic graph in the running state is obtained, the path time consumption of each execution path is determined according to the time consumption data of all the nodes included in each execution path in the directed acyclic graph, the variance of the path time consumption of the directed acyclic graph is determined according to the path time consumption of each execution path, and whether the directed acyclic graph needs to be optimized is evaluated according to the variance of the path time consumption. The directed acyclic graph is further evaluated in the running state, the directed acyclic graph can be more comprehensively evaluated, the accuracy of the evaluation result of the directed acyclic graph is improved, and more comprehensive quality assurance for the directed acyclic graph is achieved.

[0116] In some embodiments, S404 can include determining that the path evaluation result of the directed acyclic graph is to be optimized when the variance of the path time consumption is greater than the preset variance threshold.

[0117] The variance threshold can be set according to experience by taking into account resource utilization and actual production environment by human. When the variance of the path time consumption is greater than the variance threshold, the method can directly output the path evaluation result of the directed acyclic graph as to be optimized or that the variance of the path time consumption is too large.

[0118] In this embodiment, by comparing the variance of the path time consumption and the preset variance threshold, the path evaluation result of the directed acyclic graph can be more intuitively given.

[0119] In some embodiments, S101 can include obtaining a static graph description of the directed acyclic graph.

[0120] The static graph description of the directed acyclic graph is mainly a description of nodes and edges in the directed acyclic graph. Taking the SuperMario framework as an example, the framework mainly solves the development and deployment problems often occurring in the content understanding strategy engineering process, implements a business process as a DAG structure, and configures a description through global assembly. The embodiment of the present disclosure can connect nodes-data-nodes by using input and output labels of each operator in the assemble to form a basic graph structure.

[0121] For example, the description configuration of each node in the static graph description can be as shown in Table 1, where the input and output labels can be configured multiple times.

[0122] Table 1

[0123]

[0124] In Table 1, “[.@op] name: node_name” indicates that the name of the node is node_name; “[..@input] type: content value: input_arg” indicates that the input label of the node, in which the type of the input data is content and the value is input_arg; “[..@output] type: content value: output_arg” indicates that the output label of the node, in which the type of the output data is content and the value is output_arg.

[0125] In the embodiments of the present disclosure, the adjacency relationship between nodes in the directed acyclic graph can be determined according to the static graph description of the directed acyclic graph, and the input data and output data of each node can be determined. For example, the adjacency relationship between nodes in the directed acyclic graph can be presented by an adjacency list, which is not limited herein.

[0126] In the embodiments, the static graph description can provide a data structure of the directed acyclic graph for the directed acyclic graph evaluation method, the running speed of the method can be faster, and the efficiency of evaluating the directed acyclic graph is improved.

[0127] In the exemplary embodiments, the embodiments of the present disclosure also provide a directed acyclic graph evaluation device, which can be used to implement the directed acyclic graph evaluation method as described in the foregoing embodiments. Figure 5 The composition of the directed acyclic graph evaluation device provided by the embodiments of the present disclosure is shown in the following. Figure 5 As shown in the figure, the device can include an acquisition unit 501, a concurrency degree calculation unit 502, and an evaluation unit 503.

[0128] The acquisition unit 501 is configured to acquire a directed acyclic graph, and the directed acyclic graph includes at least two nodes.

[0129] The concurrency degree calculation unit 502 is configured to determine a target independent predecessor point set corresponding to each node in the directed acyclic graph according to the adjacency relationship between nodes in the directed acyclic graph. The target independent predecessor point set corresponding to the node is a set of nodes that do not have a predecessor relationship with each other between the nodes and do not have a predecessor relationship with each other between other nodes in the target independent predecessor point set.

[0130] The concurrency degree calculation unit 502 is further configured to determine the initial concurrency degree of the directed acyclic graph according to the number of nodes in at least one target independent predecessor point set with the largest number of nodes in the target independent predecessor point sets corresponding to all nodes in the directed acyclic graph.

[0131] The evaluation unit 503 is configured to evaluate the directed acyclic graph according to the initial concurrency degree.

[0132] Optionally, the concurrency degree calculation unit 502 is specifically configured to: for any first node in the directed acyclic graph, determine second nodes that do not have a predecessor relationship with the first node according to the adjacency relationship between the first node and other nodes in the directed acyclic graph; filter the second nodes according to a rule that only one node with a predecessor relationship is retained, to obtain at least one independent predecessor point set corresponding to the first node; and determine a target independent predecessor point set with the largest number of nodes from the at least one independent predecessor point set corresponding to the first node.

[0133] Optionally, the evaluation unit 503 is specifically configured to determine that the concurrency evaluation result of the directed acyclic graph is bloated when the initial concurrency degree is greater than the preset concurrency degree threshold.

[0134] Optionally, the evaluation unit 503 is further configured to evaluate redundant nodes in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0135] Optionally, the evaluation unit 503 is further configured to evaluate redundant output data in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0136] Optionally, the evaluation unit 503 is further configured to evaluate whether there is a loop in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0137] Optionally, the evaluation unit 503 is further configured to evaluate whether there is post-processing in the directed acyclic graph according to the input data and the output data of each node in the directed acyclic graph.

[0138] Figure 6 Another constituent schematic diagram of the directed acyclic graph evaluation apparatus provided by the embodiments of the present disclosure is provided. Optionally, as shown in Figure 6 the apparatus can further include a path time consumption calculation unit 601.

[0139] The acquisition unit 501 is further configured to acquire time consumption data of each node in the directed acyclic graph at runtime.

[0140] The path time consumption calculation unit 601 is configured to determine path time consumption of each execution path according to the time consumption data of all nodes contained in the execution path in the directed acyclic graph.

[0141] The path time consumption calculation unit 601 is further configured to determine path time consumption variance of the directed acyclic graph according to the path time consumption of each execution path.

[0142] The evaluation unit 503 is further configured to evaluate whether the directed acyclic graph needs to be optimized according to the path time consumption variance.

[0143] Optionally, the evaluation unit 503 is specifically configured to determine that the path evaluation result of the directed acyclic graph is that optimization is needed when the path time consumption variance is greater than a preset variance threshold.

[0144] Optionally, the acquisition unit 501 is specifically configured to acquire a static graph description of the directed acyclic graph.

[0145] In the technical solutions of the present disclosure, the acquisition, storage and application of user personal information comply with relevant laws and regulations and do not violate public order and good customs.

[0146] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0147] In an exemplary embodiment, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described in the above embodiments. The electronic device may be the computer or server described above.

[0148] In an exemplary embodiment, the readable storage medium may be a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the above embodiments.

[0149] In an exemplary embodiment, the computer program product includes a computer program that, when executed by a processor, implements the method described in the above embodiments.

[0150] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0151] like Figure 7 As shown, the electronic device 700 includes a computing unit 701, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 708 into a random access memory (RAM) 703. The RAM 703 may also store various programs and data required for the operation of the device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0152] A plurality of components in the electronic device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the electronic device 700 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0153] The computing unit 701 can be various general and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 701 performs various methods and processes described above, such as the directed acyclic graph evaluation method. For example, in some embodiments, the directed acyclic graph evaluation method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the directed acyclic graph evaluation method described above can be performed. Alternatively, in other embodiments, the computing unit 701 can be configured to perform the directed acyclic graph evaluation method by other any appropriate means, such as by means of firmware.

[0154] The various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0155] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package, or entirely on a remote machine or server.

[0156] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0157] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0158] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0159] The computer system can include clients and servers. This relationship can be. The servers are typically remote from the clients with the interactions between them occurring over a communication network. The relationship between client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The servers can be cloud servers, servers of a distributed system, or servers incorporating blockchain.

[0160] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, without departing from the desired results of the technology disclosed in the present disclosure, and are not limited herein.

[0161] The specific embodiments described above are not intended to be limiting, and persons skilled in the art will appreciate that various modifications, combinations, sub-combinations and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Any further modifications, equivalents and / or alternatives thereof are also encompassed within the scope of the present disclosure.

Claims

1. A method for evaluating a directed acyclic graph, the method comprising: obtaining a directed acyclic graph, the directed acyclic graph comprising at least two nodes, the directed acyclic graph corresponding to a business process, the nodes included in the directed acyclic graph being nodes involved in the business process, the directed acyclic graph comprising a start node, a calculation node, an end node and a post-processing node in the business process, the post-processing node performing post-processing on a picture or a video downloaded to a local device; determining a target independent predecessor set corresponding to each node in the directed acyclic graph according to an adjacency relationship between the nodes in the directed acyclic graph, the target independent predecessor set corresponding to the node being a set of nodes that do not have a predecessor relationship with the node in the directed acyclic graph and do not have a predecessor relationship with other nodes in the target independent predecessor set; determining an initial concurrency degree of the directed acyclic graph according to a number of nodes in at least one target independent predecessor set with the largest number of nodes among the target independent predecessor sets corresponding to all nodes in the directed acyclic graph; when the initial concurrency degree is greater than a preset concurrency threshold, determining that a concurrency evaluation result of the directed acyclic graph is bloated; the determining of the target independent predecessor set corresponding to each node in the directed acyclic graph according to the adjacency relationship between the nodes in the directed acyclic graph comprises: for any first node in the directed acyclic graph: determining second nodes that do not have a predecessor relationship with the first node according to an adjacency relationship between the first node and other nodes in the directed acyclic graph; filtering the second nodes according to a rule that only one node with a predecessor relationship is kept, to obtain at least one independent predecessor set corresponding to the first node; determining a target independent predecessor set with the largest number of nodes from the at least one independent predecessor set corresponding to the first node. 2.The method of claim 1, further comprising: evaluating redundant nodes in the directed acyclic graph according to input data and output data of each node in the directed acyclic graph. 3.The method of claim 1 or 2, further comprising: evaluating redundant output data in the directed acyclic graph according to input data and output data of each node in the directed acyclic graph. 4.The method of claim 1 or 2, further comprising: evaluating whether there is a cyclic graph in the directed acyclic graph according to input data and output data of each node in the directed acyclic graph. 5.The method of claim 1 or 2, further comprising: evaluating whether there is post-processing in the directed acyclic graph according to input data and output data of each node in the directed acyclic graph. 6.The method of claim 1 or 2, further comprising: obtaining time consumption data of each node in the directed acyclic graph at runtime; determining a path time consumption of each execution path in the directed acyclic graph according to time consumption data of all nodes included in the execution path; determining a path time consumption variance of the directed acyclic graph according to the path time consumption of each execution path. According to the path time consumption variance, it is determined whether the directed acyclic graph needs to be optimized.

7. The method of claim 6, wherein according to the path time consumption variance, it is determined whether the directed acyclic graph needs to be optimized, comprising: when the path time consumption variance is greater than a preset variance threshold, it is determined that the path evaluation result of the directed acyclic graph is to be optimized.

8. The method of claim 1 or 2, wherein the obtaining of the directed acyclic graph comprises: obtaining a static graph description of the directed acyclic graph.

9. A directed acyclic graph evaluation device, comprising: an obtaining unit configured to obtain a directed acyclic graph, the directed acyclic graph comprising at least two nodes, the directed acyclic graph corresponding to a business process, the nodes comprised in the directed acyclic graph being nodes involved in the business process, the directed acyclic graph comprising a start node, a calculation node, an end node and a post-processing node in the business process, the post-processing node being configured to perform post-processing on a picture or a video downloaded to a local device; a concurrency degree calculation unit configured to, for any first node in the directed acyclic graph: determine, according to an adjacency relationship between the first node and other nodes in the directed acyclic graph, second nodes that do not have a predecessor relationship with the first node; filter the second nodes according to a rule that only one node having a predecessor relationship exists, to obtain at least one irrelevant predecessor point set corresponding to the first node; and determine, from the at least one irrelevant predecessor point set corresponding to the first node, a target irrelevant predecessor point set having a maximum number of nodes. The concurrency degree calculation unit is further configured to determine an initial concurrency degree of the directed acyclic graph according to the number of nodes in at least one target irrelevant predecessor point set having a maximum number of nodes from the target irrelevant predecessor point sets corresponding to all nodes in the directed acyclic graph. an evaluation unit configured to, when the initial concurrency degree is greater than a preset concurrency degree threshold, determine that a concurrency degree evaluation result of the directed acyclic graph is to be inflated.

10. An electronic device comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

11. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-8.

12. A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 1-8.

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