Operating voltage supply circuit

Abstract

The present invention provides an operating voltage supply circuit. The operating voltage supply circuit includes an operating circuit and a charge pump circuit. The operating circuit provides a plurality of boost clock signals in different multiple load states. The charge pump circuit receives the boost clock signals and provides an operating voltage based on the duty cycle of the boost clock signals. The multiple load states are alternately switched in a time interval. The duty cycles of the multiple boost clock signals are not exactly the same.

Description

Technical Field

[0001] The present invention relates to an operating voltage supply circuit, and more particularly to an operating voltage supply circuit with low power consumption. Background Art

[0002] Generally, an electronic device (such as, a touch device, a display device, or a touch display device) operates using an operating voltage. The operating voltage supply circuit provides the operating voltage through the pumping operation of a charge pump circuit. However, to maintain the high working efficiency of the charge pump circuit, the charge pump circuit is always in a fixed working state to provide the operating voltage. Therefore, the power consumption of the operating voltage supply circuit does not decrease. Summary of the Invention

[0003] The present invention provides an operating voltage supply circuit with low power consumption.

[0004] The operating voltage supply circuit of the present invention includes an operating circuit and a charge pump circuit. The operating circuit provides a plurality of pumping clock signals under different multiple load states. The charge pump circuit is coupled to the operating circuit. The charge pump circuit receives the pumping clock signals and provides the operating voltage based on the duty cycle of the pumping clock signals. The multiple load states are alternately switched in time intervals of different load states. In a specific mode, the duty cycles of the plurality of pumping clock signals provided under the multiple load states are not completely the same.

[0005] Based on the above, the operating circuit provides pumping clock signals under different multiple load states. The duty cycles of the plurality of pumping clock signals are not completely the same. In this way, in a single time interval, the power consumption of the operating voltage supply circuit can intermittently decrease.

[0006] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0007] Figure 1 is a schematic diagram of an operating voltage supply circuit according to a first embodiment of the present invention;

[0008] Figure 2 is a schematic diagram and a state diagram of a load state and a duty cycle of a pumping clock signal according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of an operating voltage supply circuit according to a second embodiment of the present invention;

[0010] Figures 4A to 4C are respectively schematic diagrams of a charge pump circuit according to an embodiment of the present invention;

[0011] Figure 5 is based on Figure 3 the state diagram shown;

[0012] Figure 6 is a schematic diagram of a charge pump circuit shown according to an embodiment of the present invention;

[0013] Figure 7 is based on Figure 6 the state diagram shown;

[0014] Figure 8 is a schematic diagram of an operation circuit shown according to an embodiment of the present invention;

[0015] Figure 9 is a schematic diagram of an operation circuit shown according to another embodiment of the present invention;

[0016] Figure 10 is a schematic diagram of an operation circuit shown according to still another embodiment of the present invention;

[0017] Figure 11 is an operation flowchart shown according to an embodiment of the present invention;

[0018] Figure 12 is an operation flowchart shown according to another embodiment of the present invention;

[0019] Figure 13 is a schematic diagram and a state diagram of the load state and the duty cycle of the pump-up clock signal shown according to another embodiment of the present invention.

[0020] Description of Reference Numerals

[0021] 100: Operation voltage supply circuit

[0022] 110, 210, 310, 410: Operation circuit

[0023] 120, 220-1, 220-2, 220-3, 220-4: Charge pump circuit

[0024] 211, 311, 411: Selection circuit

[0025] 212, 312, 412: Clock signal generation circuit

[0026] 221, 222-1, 222-2: Voltage regulation circuit

[0027] CC, CCA: Capacitor

[0028] CCK1, CCK2: Charge clock signal

[0029] DT: Time interval

[0030] DTC1, DTC2, DTC3: Duty Cycle

[0031] ED: Electronic Device

[0032] GND: Ground

[0033] MUX, MUX1, MUX2: Multiplexer

[0034] MUXC: Multiplexer Circuit

[0035] PCK1, PCK2, PCK3: Pump - up Clock Signal

[0036] PCKH, PCKL: Gate Voltage Pump - up Clock Signal

[0037] REG1, REG2, REG3: Register

[0038] S101 - S109, S201 - S212: Steps

[0039] SS, SS1, SS2: Selection Signal

[0040] ST1, ST2, ST2’, ST3: Load Status

[0041] STG1 - STG9, STG5’ - STG7’: Phases

[0042] SV1, SV2, SV3: Status Data

[0043] SW1 - SW11: Switches

[0044] VCI: Charging Voltage

[0045] VGH: Gate High Voltage

[0046] VGL: Gate Low Voltage

[0047] VR, VR1, VR2: Regulating Voltage

[0048] VRI: Reference Voltage

[0049] VSN, VSP: Operating Voltage Detailed Embodiments

[0050] Reference will now be made in detail to exemplary embodiments of the present invention. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and the description to denote the same or similar parts.

[0051] Please refer to Figure 1 , Figure 1FIG. 0 is a schematic diagram of an operating voltage supply circuit according to an embodiment of the present invention. In this embodiment, the operating voltage supply circuit 100 is used to provide an operating voltage VSP to an electronic device ED. The electronic device ED operates based on the operating voltage VSP. The electronic device ED can be a touch device, a display device, or a touch display device in a portable device or a wearable device. In this embodiment, the operating voltage supply circuit 100 includes an operating circuit 110 and a charge pump circuit 120. The operating circuit 110 provides a boost clock signal in different multiple load states. The multiple load states are alternately switched in a single time interval DT of a specific mode. In addition, the duty cycles of the multiple boost clock signals are not exactly the same. For example, taking this embodiment as an example, the operating circuit 110 provides a boost clock signal PCK1 in the load state ST1. The operating circuit 110 provides a boost clock signal PCK2 in the load state ST2. The load state ST1 is different from the load state ST2. The power consumption of the load state ST1 is different from that of ST2. The duty cycle of the boost clock signal PCK1 is different from the duty cycle of the boost clock signal PCK2. In addition, the load states ST1 and ST2 are alternately switched in the time interval DT of different load states. In other words, in the time interval DT, the operating circuit 110 is in a specific mode and alternately provides the boost clock signals PCK1 and PCK2. For example, the specific mode can be various types of standby modes. For example, the specific mode (or standby mode) includes at least one of a dark screen touch mode and an Always-on Display (AOD) mode.

[0052] In this embodiment, the charge pump circuit 120 is coupled to the operating circuit 110. The charge pump circuit 120 receives the boost clock signal provided by the operating circuit 110 and provides the operating voltage VSP based on the duty cycle of the received boost clock signal.

[0053] It is worth mentioning here that the duty cycles of the boost clock signals provided by the operating circuit 110 in different multiple load states are not exactly the same. The multiple load states are alternately switched in a single time interval DT. The multiple power consumptions of the multiple load states are different from each other. In this way, in a single time interval, the power consumption of the operating voltage supply circuit 100 can be intermittently reduced.

[0054] For ease of illustration, this embodiment exemplifies with two load states ST1 and ST2. The number of load states of the present invention can be multiple and is not limited to this embodiment.

[0055] Please refer to Figure 1 and Figure 2 at the same time. Figure 2It is a schematic diagram and a state diagram of the load state and the duty cycle of the pump-up clock signal shown according to an embodiment of the present invention. In this embodiment, in the time interval DT, the operation circuit 110 provides the pump-up clock signal PCK1 in the load state ST1. The pump-up clock signal PCK1 has a duty cycle DTC1. The operation circuit 110 provides the pump-up clock signal PCK2 in the load state ST2. The pump-up clock signal PCK2 has a duty cycle DTC2. The operation circuit 110 can alternately provide the pump-up clock signals PCK1 and PCK2 in a specific mode.

[0056] For example, the electronic device ED is a touch display device. The operation circuit 110 can alternately provide the pump-up clock signals PCK1 and PCK2 in the dark screen touch mode of the electronic device ED. The dark screen touch mode is the touch mode of the electronic device ED when the display panel stops displaying the picture. Therefore, the charge pump circuit 120 provides the operating voltage VSP according to the duty cycles DTC1 and DTC2. In this example, the load state ST1 is the touch sensing state of the electronic device ED. In the load state ST1, the operation circuit 110 provides the pump-up clock signal PCK1 with a duty cycle DTC1. The duty cycle DTC1 is, for example, 50% (the present invention is not limited thereto). Therefore, the charge pump circuit 120 provides the operating voltage VSP based on the duty cycle DTC1 in the load state ST1. The load state ST2 is the idle state of the electronic device ED. The operation circuit 110 provides the pump-up clock signal PCK2 with a duty cycle DTC2. The duty cycle DTC2 is less than the duty cycle DTC1. The duty cycle DTC2 is, for example, 12% (the present invention is not limited thereto). Therefore, the charge pump circuit 120 provides the operating voltage VSP based on the duty cycle DTC2 in the load state ST2. The operating voltage VSP is used to drive the touch sensing circuit of the electronic device ED.

[0057] It should be noted that the duty cycle DTC1 is greater than the duty cycle DTC2. The power consumption generated by the charge pump circuit 120 operating based on the duty cycle DTC2 is less than the power consumption generated by operating based on the duty cycle DTC1. Therefore, in the dark screen touch mode, the power consumption of the charge pump circuit 120 can be reduced.

[0058] In addition, in this embodiment, the time length of load state ST1 is shorter than that of load state ST2. For example, in time interval DT when the electronic device ED operates in the dark screen touch control mode, the alternation period of load states ST1 and ST2 is about 15 Hertz (Hz) (the present invention is not limited thereto). The running time length of load state ST1 is 2 milliseconds (the present invention is not limited thereto). The running time length of load state ST2 is 62 milliseconds (the present invention is not limited thereto). Moderately extending the running time length of load state ST2 can reduce the power consumption of the charge pump circuit 120.

[0059] Another example is that the electronic device ED is a display device. The operation circuit 110 can alternately provide the boost clock signals PCK1 and PCK2 in the Always-on Display (AOD) mode of the electronic device ED. The always-on display mode is the display mode of the electronic device ED when the display panel stops scanning the display screen. Therefore, the charge pump circuit 120 provides the operation voltage VSP according to the duty cycles DTC1 and DTC2. In this example, load state ST1 is the scanning state or data update state of the electronic device ED. In load state ST1, the operation circuit 110 provides the boost clock signal PCK1 with the duty cycle DTC1. The duty cycle DTC1 is, for example, 50% (the present invention is not limited thereto). Therefore, the charge pump circuit 120 provides the operation voltage VSP based on the duty cycle DTC1 in load state ST1. Load state ST2 is the idle state of the electronic device ED. The operation circuit 110 provides the boost clock signal PCK2 with the duty cycle DTC2. The duty cycle DTC2 is less than the duty cycle DTC1. The duty cycle DTC2 is, for example, 12% (the present invention is not limited thereto). Therefore, the charge pump circuit 120 provides the operation voltage VSP based on the duty cycle DTC2 in load state ST2. The operation voltage VSP is used to drive the display panel of the electronic device ED.

[0060] It should be noted that the duty cycle DTC1 is greater than the duty cycle DTC2. The power consumption generated when the charge pump circuit 120 operates based on the duty cycle DTC2 is less than that generated when it operates based on the duty cycle DTC1. Therefore, in the always-on display mode, the power consumption of the charge pump circuit 120 can be reduced.

[0061] In addition, in this embodiment, the time length of the load state ST1 is shorter than that of the load state ST2. For example, in the time interval DT when the electronic device ED operates in the dark screen touch mode, the alternation period of the load states ST1 and ST2 is about 15 Hertz (Hz) (the present invention is not limited thereto). The operating time length of the load state ST1 is 16 milliseconds (the present invention is not limited thereto). The operating time length of the load state ST2 is 48 milliseconds (the present invention is not limited thereto).

[0062] Please refer to Figure 3 , Figure 3 is a schematic diagram of an operating voltage supply circuit according to the second embodiment of the present invention. In this embodiment, the operating voltage supply circuit 200 includes an operating circuit 210 and a charge pump circuit 220. The operating circuit 210 provides a boost clock signal PCK1 and a charging clock signal CCK1 in the load state ST1. The operating circuit 210 provides a boost clock signal PCK2 and a charging clock signal CCK2 in the load state ST2. The power consumption of the load state ST1 is different from that of ST2. The duty cycle of the boost clock signal PCK1 is different from that of the boost clock signal PCK2. In addition, the load states ST1 and ST2 are alternately switched in the time interval DT. The charge pump circuit 220 is coupled to the operating circuit 210. The charge pump circuit 220 receives the boost clock signal provided by the operating circuit 210 and provides an operating voltage VSP based on the received boost clock signal and charging clock signal.

[0063] Next, the implementation details of the charge pump circuit 220 will be illustrated by way of example.

[0064] Figures 4A to 4C are schematic diagrams of a charge pump circuit according to an embodiment of the present invention. First, please refer to Figure 4A, in this embodiment, the charge pump circuit 220-1 includes a capacitor CC and switches SW1 to SW4. The first terminal of switch SW1 receives a charging voltage VCI. The second terminal of switch SW1 is coupled to the first terminal of capacitor CC. The control terminal of switch SW1 receives a charging clock signal CCK1 in a load state ST1 and receives a charging clock signal CCK2 in the load state ST2. The first terminal of switch SW2 receives a reference low voltage (such as ground GND). The second terminal of switch SW2 is coupled to the second terminal of capacitor CC. The control terminal of switch SW2 receives a charging clock signal CCK1 in a load state ST1 and receives a charging clock signal CCK2 in the load state ST2. The first terminal of switch SW3 is coupled to the first terminal of capacitor CC. The second terminal of switch SW3 is used to output an operating voltage VSP. The control terminal of switch SW3 receives a pumping clock signal PCK1 in a load state ST1 and receives a pumping clock signal PCK2 in the load state ST2. The first terminal of switch SW4 is coupled to the second terminal of capacitor CC. The second terminal of switch SW4 receives an adjustment voltage VR. The control terminal of switch SW4 receives a pumping clock signal PCK1 in a load state ST1 and receives a pumping clock signal PCK2 in the load state ST2.

[0065] In the charging stage of the load state ST1, switches SW1 and SW2 are turned on in response to the charging clock signal CCK1. Switches SW3 and SW4 are turned off in response to the pumping clock signal PCK1. Therefore, there will be a charging voltage difference between the first terminal and the second terminal of capacitor CC. In the pumping stage of the load state ST1, switches SW1 and SW2 are turned off in response to the charging clock signal CCK1. Switches SW3 and SW4 are turned on in response to the pumping clock signal PCK1. Therefore, the voltage value of the operating voltage VSP will be approximately equal to the sum of the voltage value of the adjustment voltage VR and the charging voltage difference.

[0066] For example, the voltage value of the charging voltage VCI is equal to 3.3 volts. The voltage value of the adjustment voltage VR is equal to 2.7 volts. Therefore, in the charging stage of the load state ST1, the charging voltage difference is approximately equal to 3.3 volts. In the pumping stage of the load state ST1, the voltage value of the operating voltage VSP will be approximately equal to 6 volts. Another example, the voltage value of the charging voltage VCI is equal to 6 volts. The voltage value of the adjustment voltage VR is equal to 1 volt. Therefore, in the charging stage of the load state ST1, the charging voltage difference is approximately equal to 6 volts. In the pumping stage of the load state ST1, the voltage value of the operating voltage VSP will be approximately equal to 7 volts. The operating voltage VSP can be used as a gate high voltage (VGH) for generating pixel scans and / or a power supply for touch sensing.

[0067] The operation of the charge pump circuit 220-1 in the charging stage of the load state ST2 is substantially similar to its operation in the charging stage of the load state ST1. The operation of the charge pump circuit 220-1 in the pumping-up stage of the load state ST2 is substantially similar to its operation in the pumping-up stage of the load state ST1. The difference in the operation of the charge pump circuit 220-1 in the load states ST1 and ST2 is mainly that the duty cycle of the pumping-up clock signal PCK1 is not the same as the duty cycle of the pumping-up clock signal PCK2.

[0068] Please refer to Figure 4B , in this embodiment, the charge pump circuit 220-2 includes a capacitor CC, switches SW1 to SW4, and a voltage regulation circuit 221. The configuration and operation of the capacitor CC and the switches SW1 to SW4 have been clearly described in the embodiment of Figure 4A and will not be repeated here. In this embodiment, the voltage regulation circuit 221 is coupled to the second end of the switch SW4. The voltage regulation circuit 221 provides a regulated voltage VR based on a reference voltage VRI. The voltage regulation circuit 221 can be operated to determine the voltage value of the regulated voltage VR using the reference voltage VRI.

[0069] Please refer to Figure 4C, in this embodiment, the charge pump circuit 220-3 includes a capacitor CC, switches SW1 to SW4, and a voltage regulation circuit 221. The first terminal of switch SW1 receives a charging voltage VCI. The second terminal of switch SW1 is coupled to the first terminal of capacitor CC. The control terminal of switch SW1 receives a charging clock signal CCK1 in a load state ST1 and receives a charging clock signal CCK2 in the load state ST2. The first terminal of switch SW2 receives a reference low voltage (such as ground). The second terminal of switch SW2 is coupled to the second terminal of capacitor CC. The control terminal of switch SW2 receives a charging clock signal CCK1 in a load state ST1 and receives a charging clock signal CCK2 in the load state ST2. The first terminal of switch SW3 is coupled to the first terminal of capacitor CC. The second terminal of switch SW3 receives a regulated voltage VR. The control terminal of switch SW3 receives a pumping clock signal PCK1 in a load state ST1 and receives a pumping clock signal PCK2 in the load state ST2. The first terminal of switch SW4 is coupled to the second terminal of capacitor CC. The first terminal of switch SW4 is used to output an operating voltage VSN. The control terminal of switch SW4 receives a pumping clock signal PCK1 in a load state ST1 and receives a pumping clock signal PCK2 in the load state ST2. In this embodiment, the voltage regulation circuit 221 is coupled to the second terminal of switch SW3. The voltage regulation circuit 221 provides the regulated voltage VR according to a reference voltage VRI. In the charging phase of the load state ST1, switches SW1 and SW2 are turned on in response to the charging clock signal CCK1. Switches SW3 and SW4 are turned off in response to the pumping clock signal PCK1. Therefore, there will be a charging voltage difference between the first terminal and the second terminal of capacitor CC. In the pumping phase of the load state ST1, switches SW1 and SW2 are turned off in response to the charging clock signal CCK1. Switches SW3 and SW4 are turned on in response to the pumping clock signal PCK1.

[0070] For example, the voltage value of the charging voltage VCI is equal to 3.3 volts. The voltage value of the regulated voltage VR is equal to 0 volts. Therefore, in the charging phase of the load state ST1, the charging voltage difference is approximately equal to 3.3 volts. In the pumping phase of the load state ST1, the voltage value of the operating voltage VSN will be approximately equal to -3.3 volts. Another example, the voltage value of the charging voltage VCI is equal to 3.3 volts. The voltage value of the regulated voltage VR is equal to -3.7 volts. Therefore, in the charging phase of the load state ST1, the charging voltage difference is approximately equal to 3.3 volts. In the pumping phase of the load state ST1, the voltage value of the operating voltage VSP will be approximately equal to -7 volts. The operating voltage VSP can be used as a gate low voltage (VGL) for pixel scanning and / or a reference low voltage for pixels.

[0071] In some embodiments, Figure 3The illustrated charge pump circuit 220 may be implemented by one of charge pump circuits 220-1, 220-2, and 220-3. In some embodiments, Figure 3 The illustrated charge pump circuit 220 may be implemented by the combination of charge pump circuits 220-2 and 220-3.

[0072] Please also refer to Figure 3 and Figure 5 , Figure 5 is based on Figure 3 the state diagram shown. In this embodiment, load states ST1 and ST2 are alternately switched in a single time interval DT. The charge pump circuit 220, for example, performs multiple stages STG1 to STG4 in sequence at least in load state ST1. In this embodiment, stage STG1 is a charging stage. Stage STG2 is a pumping-up stage. Stage STG3 is a charging stage. Stage STG4 is a pumping-up stage. In stages STG1 and STG3 (charging stages), the charge pump circuit 220 operates based on the charging clock signal CCK1. In stages STG2 and STG4 (pumping-up stages), the charge pump circuit 220 operates based on the pumping-up clock signal PCK1. In this embodiment, the charging stages STG1 and STG3 and the pumping-up stages STG2 and STG4 have the same duty cycle DTC1. Therefore, the time lengths of stages STG1 to STG4 are substantially the same. The duty cycle DTC1 is, for example, 50%.

[0073] In this embodiment, the charge pump circuit 220, for example, performs multiple stages STG5 to STG9 in sequence at least in load state ST2. Stage STG5 is a charging stage. Stage STG6 is a pumping-up stage. Stage STG7 is an additional stage. Stage STG8 is a charging stage STG8. Stage STG9 is a pumping-up stage. In stages STG5 and STG8, the charge pump circuit 220 operates based on the charging clock signal CCK2. In stages STG6 and STG9, the charge pump circuit 220 operates based on the pumping-up clock signal PCK2. In this embodiment, stages STG5 and STG8 have the duty cycle DTC1. Stages STG6 and STG9 have the duty cycle DTC2. For example, the duty cycles DTC1 and DTC2 are, for example, 50%. The operation of the charge pump circuit 220 in stage STG7 is substantially equal to the operation of a single stage STG5 or repeats stage STG5 at least twice. Therefore, the time interval between the pumping-up operations of the charge pump circuit 220 is lengthened. The power consumption of the charge pump circuit 220 can be reduced.

[0074] In this embodiment, stage STG7 can be ignored. The duty cycle DTC2 is designed to be less than the duty cycle DTC1. Therefore, the power consumption of the charge pump circuit 220 can be reduced.

[0075] Please refer to Figure 6 , Figure 6 which is a schematic diagram of a charge pump circuit shown in an embodiment of the present invention. In this embodiment, the charge pump circuit 220-4 includes a capacitor CCA and switches SW5 to SW11. The first terminal of switch SW5 receives the operating voltage VSP. The second terminal of switch SW5 is coupled to the first terminal of capacitor CCA. The control terminal of switch SW5 receives the charge clock signal CCK1 in the load state ST1 and receives the charge clock signal CCK2 in the load state ST2. The first terminal of switch SW6 receives the operating voltage VSN. The second terminal of switch SW2 is coupled to the second terminal of capacitor CC. The control terminal of switch SW2 receives the charge clock signal CCK1 in the load state ST1 and receives the charge clock signal CCK2 in the load state ST2.

[0076] The first terminal of switch SW7 is coupled to the first terminal of capacitor CCA. The second terminal of switch SW7 is used to output the gate high voltage VGH. The control terminal of switch SW7 receives the gate voltage boost clock signal PCKH with different duty cycles in different load states ST1 and ST2. The first terminal of switch SW8 is coupled to the second terminal of capacitor CCA. The second terminal of switch SW8 receives the regulation voltage VRP. The control terminal of switch SW8 receives the gate voltage boost clock signal PCKH with different duty cycles in different load states ST1 and ST2. The first terminal of switch SW9 is coupled to the first terminal of capacitor CCA. The second terminal of switch SW9 receives the regulation voltage VRN. The control terminal of switch SW9 receives the gate voltage boost clock signal PCKL with different duty cycles in different load states ST1 and ST2. The first terminal of switch SW10 is coupled to the second terminal of capacitor CC. The second terminal of switch SW10 is used to output the gate low voltage VGL. The control terminal of switch SW10 receives the gate voltage boost clock signal PCKL with different duty cycles in different load states ST1 and ST2.

[0077] In this embodiment, during the charging phase of load states ST1 and ST2, switches SW5 and SW6 are turned on. Switches SW7 to SW10 are turned off. Therefore, there will be a charging voltage difference between the first end and the second end of capacitor CCA. During the pumping-up phase of the gate high voltage VGH in load states ST1 and ST2, switches SW5, SW6, SW9, and SW10 are turned off. Switches SW7 and SW8 are turned on. Therefore, the voltage value of the gate high voltage VGH can be pumped up based on the regulation voltage VRP. During the pumping-up phase of the gate low voltage VGL in load states ST1 and ST2, switches SW5 to SW8 are turned off. Switches SW9 and SW10 are turned on. Therefore, the voltage value of the gate low voltage VGL can be pumped up based on the regulation voltage VRN. Based on the above, the charge pump circuit 220-4 can be used to provide the gate low voltage VGL and the gate high voltage VGH.

[0078] In this embodiment, the charge pump circuit 220-4 further includes voltage regulation circuits 222-1 and 222-2. The voltage regulation circuit 222-1 is coupled to the second end of switch SW8. The voltage regulation circuit 222-1 provides the regulation voltage VRP. The voltage regulation circuit 222-2 is coupled to the second end of switch SW9. The voltage regulation circuit 222-2 provides the regulation voltage VRN.

[0079] In this embodiment, the charge pump circuit 220-4 further includes a switch SW11. The first end of the switch SW11 is coupled to the second end of the capacitor CCA. The second end of the switch SW11 receives a reset voltage value VRST (e.g., 0 volts). When the switch SW11 is turned on, the voltage value at the second end of the capacitor CCA is reset.

[0080] In some embodiments, Figure 3 the illustrated charge pump circuit 220 can be implemented by the combination of charge pump circuits 220-2, 220-3, and 220-4.

[0081] Please also refer to Figure 6 and Figure 7 , Figure 7 is based on Figure 6The state diagram shown. In this embodiment, the charge pump circuit 220-4 operates based on the alternating switching of the load states ST1 and ST2. In the load state ST1, the charge pump circuit 220-4, for example, sequentially performs a plurality of stages STG1 to STG4. Stage STG1 is the charging stage STG1. Stage STG2 is the pumping-up stage of the gate high voltage VGH. Stage STG3 is the charging stage. Stage STG4 is the pumping-up stage of the gate low voltage VGL. In stage STG2, the charge pump circuit 220-4 operates based on the gate voltage pumping-up clock signal PCKH. In stage STG4, the charge pump circuit 220-4 operates based on the gate voltage pumping-up clock signal PCKL. The gate voltage pumping-up clock signal PCKH in stage STG2 has a duty cycle DTC1. The gate voltage pumping-up clock signal PCKL in stage STG4 has a duty cycle DTC1. For example, the duty cycle DTC1 is 25%.

[0082] In the load state ST2, the charge pump circuit 220-4, for example, sequentially performs a plurality of stages STG5 to STG8. Stage STG5 is the charging stage. Stage STG6 is the pumping-up stage of the gate high voltage VGH. Stage STG7 is the charging stage STG7. Stage STG8 is the pumping-up stage of the gate low voltage VGL STG8. In stage STG6, the charge pump circuit 220-4 operates based on the gate voltage pumping-up clock signal PCKH. In stage STG8, the charge pump circuit 220-4 operates based on the gate voltage pumping-up clock signal PCKL. The gate voltage pumping-up clock signal PCKH in stage STG6 has a duty cycle DTC2. The gate voltage pumping-up clock signal PCKL in stage STG8 has a duty cycle DTC2. For example, the duty cycle DTC1 is 12.5%.

[0083] It should be noted that the duty cycle DTC2 is less than the duty cycle DTC1. Therefore, the charge pump circuit 220-4 will have lower power consumption in the load state ST2.

[0084] The charge pump circuit 220-4 can also operate based on the alternating switching of the load states ST1 and ST2'. In the load state ST2', the charge pump circuit 220-4 sequentially performs multiple stages STG5' to STG7'. The stage STG5' is a charging stage. The stage STG6' is a boosting stage for the gate high voltage VGH. The stage STG7' is a boosting stage for the gate low voltage VGL. In the stage STG6', the charge pump circuit 220-4 operates based on the gate voltage boosting clock signal PCKH. In the stage STG7', the charge pump circuit 220-4 operates based on the gate voltage boosting clock signal PCKL. The gate voltage boosting clock signal PCKH in the stage STG6' has a duty cycle DTC2. The gate voltage boosting clock signal PCKL in the stage STG7' has a duty cycle DTC2. For example, the duty cycle DTC1 is 12.5%. In addition, the time length of the stage STG5' is approximately equal to the sum of the time lengths of the stages STG1 and STG3.

[0085] Please also refer to Figure 1 and Figure 8 , Figure 8 is a schematic diagram of an operation circuit shown according to an embodiment of the present invention. In this embodiment, the operation circuit 210 includes a selection circuit 211 and a clock signal generation circuit 212. The selection circuit 211 stores different state data SV1 and SV2 corresponding to the load states ST1 and ST2. The selection circuit 211 alternately selects one of the state data SV1 and SV2 as the selected state data and outputs the selected state data. The clock signal generation circuit 212 is coupled to the selection circuit 211 and the charge pump circuit 120. The clock signal generation circuit 212 provides a corresponding boosting clock signal corresponding to the selected state data in response to the selected state data. The duty cycle of the corresponding boosting clock signal corresponds to the selected state data. For example, when the selected state data is the state data SV1, the clock signal generation circuit 212 provides the boosting clock signal PCK1. When the selected state data is the state data SV2, the clock signal generation circuit 212 provides the boosting clock signal PCK2. The duty cycle of the boosting clock signal PCK1 is different from the duty cycle of the boosting clock signal PCK2.

[0086] In this embodiment, the state data SV1 includes generation parameters associated with the generation of the boosting clock signal PCK1. The generation parameters associated with the boosting clock signal PCK1 are, for example, at least one of the frequency, waveform, duration, and duty cycle of the boosting clock signal PCK1. The state data SV2 includes generation parameters associated with the generation of the boosting clock signal PCK2. The generation parameters associated with the boosting clock signal PCK2 are, for example, at least one of the frequency, waveform, duration, and duty cycle of the boosting clock signal PCK2.

[0087] For example, the status data SV1 corresponds to the load status ST1. The status data SV2 corresponds to the load status ST2. The load statuses ST1 and ST2 are alternately switched in a single time interval DT. Therefore, the selection circuit 211 preferentially outputs the status data SV1, for example. The clock signal generation circuit 212 provides the boost clock signal PCK1 in response to the status data SV1. Next, the selection circuit 211 outputs the status data SV2. The clock signal generation circuit 212 provides the boost clock signal PCK2 in response to the status data SV2.

[0088] In some embodiments, the operation circuit 210 can alternately provide the boost clock signals PCK1 and PCK2 in the dark screen touch mode of the electronic device ED. In some embodiments, the operation circuit 210 can alternately provide the boost clock signals PCK1 and PCK2 in the always-on display mode of the electronic device ED.

[0089] Please refer to Figure 9 , Figure 9 which is a schematic diagram of an operation circuit according to another embodiment of the present invention. In this embodiment, the operation circuit 310 includes a selection circuit 311 and a clock signal generation circuit 312. The selection circuit 311 includes registers REG1, REG2, and a multiplexer circuit MUXC. The register REG1 stores the status data SV1. The register REG2 stores the status data SV2. The multiplexer circuit MUXC is coupled to the registers REG1 and REG2. The multiplexer circuit MUXC receives the status data SV1, SV2, and a selection signal SS. The multiplexer circuit MUXC alternately selects one of the status data SV1 and SV2 as the selected status data in response to the selection signal SS. The selection circuit 311 provides the selected status data to the clock signal generation circuit 312. Therefore, the clock signal generation circuit 312 provides a corresponding boost clock signal corresponding to the selected status data in response to the selected status data.

[0090] In this embodiment, the multiplexer circuit MUXC includes a multiplexer MUX. The first input terminal of the multiplexer MUX is coupled to the register REG1 to receive the status data SV1. The second input terminal of the multiplexer MUX is coupled to the register REG2 to receive the status data SV2. The selection terminal of the multiplexer MUX receives the selection signal SS. The output terminal of the multiplexer MUX is coupled to the clock signal generation circuit 312. The output terminal of the multiplexer MUX is used to output the selected status data.

[0091] Please refer to Figure 10 , Figure 10It is a schematic diagram of an operation circuit shown in another embodiment of the present invention. In this embodiment, the operation circuit 410 includes a selection circuit 411 and a clock signal generation circuit 412. The selection circuit 411 includes registers REG1, REG2, REG3, and a multiplexer circuit MUXC. The register REG1 stores the status data SV1. The register REG2 stores the status data SV2. The register REG3 stores the status data SV3. The multiplexer circuit MUXC is coupled to the registers REG1, REG2, REG3. The multiplexer circuit MUXC receives the status data SV1, SV2, SV3 and the selection signals SS1, SS2. The multiplexer circuit MUXC responds to the selection signals SS1, SS2 to alternately select one of the status data SV1, SV2, SV3 as the selected status data. The selection circuit 411 provides the selected status data to the clock signal generation circuit 412. Therefore, the clock signal generation circuit 412 provides a corresponding pumped-up clock signal corresponding to the selected status data in response to the selected status data. For example, when the selected status data is the status data SV1, the clock signal generation circuit 412 provides the pumped-up clock signal PCK1. When the selected status data is the status data SV2, the clock signal generation circuit 412 provides the pumped-up clock signal PCK2. When the selected status data is the status data SV3, the clock signal generation circuit 412 provides the pumped-up clock signal PCK3. The duty cycles of the pumped-up clock signals PCK1, PCK2, PCK3 are not exactly the same.

[0092] In this embodiment, the multiplexer circuit MUXC includes multiplexers MUX1, MUX2. The first input terminal of the multiplexer MUX1 is coupled to the register REG1 to receive the status data SV1. The second input terminal of the multiplexer MUX1 is coupled to the register REG2 to receive the status data SV2. The selection terminal of the multiplexer MUX1 receives the selection signal SS1. The first input terminal of the multiplexer MUX2 is coupled to the output terminal of the multiplexer MUX1. The second input terminal of the multiplexer MUX2 is coupled to the register REG3 to receive the status data SV3. The selection terminal of the multiplexer MUX1 receives the selection signal SS2. The output terminal of the multiplexer MUX2 is coupled to the clock signal generation circuit 412. The output terminal of the multiplexer MUX2 is used to output the selected status data.

[0093] Please also refer to Figure 1 and Figure 11 . Figure 11It is an operation flowchart shown according to an embodiment of the present invention. In this embodiment, the electronic device ED enters a specific mode in step S101. The specific mode can be one of the dark screen touch mode and the always-on display mode. In step S102, in the specific mode, the operation voltage supply circuit 100 determines the rotation method of multiple load states. Further, based on the specific mode, the operation voltage supply circuit 100 selects at least two load states and schedules the rotation method of the load states. In step S103, the operation voltage supply circuit 100 determines the current load state. Taking this embodiment as an example, the operation circuit 110 selects the load states ST1 and ST2 and schedules the load state ST1 as the priority load state (the present invention is not limited thereto). Therefore, the operation circuit 110 provides the boost clock signal PCK1 with the first duty cycle in step S104. In step S105, the operation voltage supply circuit 100 operates based on the load state ST1. Further, the charge pump circuit 120 provides the operation voltage VSP based on the first duty cycle of the boost clock signal PCK1. In step S106, the operation voltage supply circuit 100 determines whether the load state ST1 ends. For example, the load state ST1 has an operating time length. When the operating time length of the load state ST1 has not reached the preset time length, the operation voltage supply circuit 100 determines that the load state ST1 has not ended. Therefore, the operation circuit 110 returns to the operation of step S104. On the other hand, when the operating time length of the load state ST1 reaches the preset time length, the operation voltage supply circuit 100 determines that the load state ST1 ends. Therefore, the operation circuit 110 returns to the operation of step S102.

[0094] After the load state ST1 ends, the operation circuit 110 determines in step S103 that the current load state is the load state ST2. Accordingly, the operation circuit 110 provides a boost clock signal PCK2 having a second duty cycle in step S107. In step S108, the operation voltage supply circuit 100 operates based on the load state ST2. Further, the charge pump circuit 120 provides an operation voltage VSP based on the second duty cycle of the boost clock signal PCK2. In step S109, the operation voltage supply circuit 100 determines whether the load state ST2 has ended. For example, the load state ST2 has a running time length. When the running time length of the load state ST2 has not reached a preset time length, the operation voltage supply circuit 100 determines that the load state ST2 has not ended. Accordingly, the operation circuit 110 returns to the operation of step S107. On the other hand, when the running time length of the load state ST2 reaches the preset time length, the operation voltage supply circuit 100 determines that the load state ST2 has ended. Accordingly, the operation circuit 110 returns to the operation of step S102. After the load state ST2 ends, the operation circuit 110 determines in step S103 that the current load state is the load state ST1.

[0095] Please also refer to Figure 1 and Figure 12 . Figure 12It is an operation flowchart shown according to another embodiment of the present invention. In this embodiment, the electronic device ED enters a specific mode in step S201. The specific mode can be at least one of a dark screen touch mode and a always-on display mode. In step S202, in the specific mode, the operation voltage supply circuit 100 will determine the rotation mode of multiple load states. Further, based on the specific mode, the operation voltage supply circuit 100 selects multiple load states and schedules the rotation mode of the load states. In step S203, the operation voltage supply circuit 100 will judge the current load state. Taking this embodiment as an example, the operation circuit 110 selects load states ST1, ST2, and ST3, and schedules load state ST1 as the preferred load state (the present invention is not limited thereto). Therefore, the operation circuit 110 will provide a boost clock signal PCK1 with a first duty cycle in step S204. In step S205, the operation voltage supply circuit 100 operates based on the load state ST1. The charge pump circuit 120 will provide an operation voltage VSP based on the first duty cycle of the boost clock signal PCK1. In step S206, the operation voltage supply circuit 100 will judge whether the load state ST1 ends. When the operation voltage supply circuit 100 judges that the load state ST1 has not ended, the operation circuit 110 will return to the operation of step S204. On the other hand, when the operation voltage supply circuit 100 judges that the load state ST1 ends, the operation circuit 110 will return to the operation of step S202. The judgment method of step S206 has been clearly described in the implementation content of step S106, so it will not be repeated here.

[0096] After the load state ST1 ends, the operation circuit 110 will judge that the current load state is the load state ST2 in step S203. Therefore, the operation circuit 110 will provide a boost clock signal PCK2 with a second duty cycle in step S207. In step S208, the operation voltage supply circuit 100 operates based on the load state ST2. The charge pump circuit 120 will provide an operation voltage VSP based on the second duty cycle of the boost clock signal PCK2. In step S209, the operation voltage supply circuit 100 will judge whether the load state ST2 ends. When the operation voltage supply circuit 100 judges that the load state ST2 has not ended, the operation circuit 110 will return to the operation of step S207. On the other hand, when the operation voltage supply circuit 100 judges that the load state ST2 ends, the operation circuit 110 will return to the operation of step S202.

[0097] After the load state ST2 ends, the operation circuit 110 determines in step S203 that the current load state is the load state ST3. Therefore, the operation circuit 110 provides a boost clock signal PCK3 with a third duty cycle in step S210. In step S211, the operation voltage supply circuit 100 operates based on the load state ST3. The charge pump circuit 120 provides an operation voltage VSP based on the third duty cycle of the boost clock signal PCK3. In step S212, the operation voltage supply circuit 100 determines whether the load state ST3 has ended. When the operation voltage supply circuit 100 determines that the load state ST3 has not ended, the operation circuit 110 returns to the operation of step S210. On the other hand, when the operation voltage supply circuit 100 determines that the load state ST3 has ended, the operation circuit 110 returns to the operation of step S202.

[0098] Please also refer to Figure 1 and Figure 13 , Figure 13 is a schematic diagram and a state diagram of the load state and the duty cycle of the boost clock signal shown in another embodiment of the present invention. In this embodiment, the specific mode may be a combined mode of the dark screen touch mode and the always-on display mode. In this embodiment, the always-on display mode includes a display scan state and a display idle state. The dark screen touch mode includes a touch idle state and a touch sensing state. Since the state cycle of the dark screen touch mode (e.g., 0.032 seconds) is different from the state cycle of the always-on display mode (e.g., 0.064 seconds), the combined mode includes three load states ST1, ST2, and ST3. In this embodiment, when the display scan state and the touch idle state occur, the operation voltage supply circuit 100 operates in the load state ST1. When the display scan state and the display idle state occur, the operation voltage supply circuit 100 operates in the load state ST2. In addition, when the touch idle state and the display idle state occur, the operation voltage supply circuit 100 operates in the load state ST3.

[0099] As Figure 13 shown, the state timing is sequentially carried out in the load state ST1, the load state ST2, the load state ST3, the load state ST1, the load state ST3, the load state ST2... Based on the change of the state timing of the dark screen touch mode and the always-on display mode, the order of the load states ST1 to ST3 will also change correspondingly. The order of the load states ST1 to ST3 of the present invention is not limited to this embodiment.

[0100] In this embodiment, the operation circuit 110 provides a boost clock signal PCK1 in the load state ST1. The boost clock signal PCK1 has a duty cycle DTC1. The operation circuit 110 provides a boost clock signal PCK2 in the load state ST2. The boost clock signal PCK2 has a duty cycle DTC2. The operation circuit 110 provides a boost clock signal PCK3 in the load state ST3. The boost clock signal PCK3 has a duty cycle DTC3. For example, the duty cycle DTC1 is 25%. The duty cycle DTC2 is 50%. The duty cycle DTC3 is 12.5%. Therefore, the power consumption of the charge pump circuit 120 can intermittently decrease in the load states ST1 and ST3. Another example, the duty cycle DTC1 is 50%. The duty cycle DTC2 is 50%. The duty cycle DTC3 is 12.5%. Therefore, the power consumption of the charge pump circuit 120 can intermittently decrease in the load state ST3. In this embodiment, the duty cycles DTC1, DTC2, and DTC3 are not exactly the same. The duty cycles DTC1, DTC2, and DTC3 can be different from each other. Any two of the duty cycles DTC1, DTC2, and DTC3 can be the same.

[0101] This embodiment is applicable to Figure 12 the operation flowchart shown.

[0102] In summary, the duty cycles of the boost clock signals provided by the operation circuit of the operation voltage supply circuit in different multiple load states are not exactly the same. The multiple load states are alternately switched in a single time interval. The multiple power consumptions of the multiple load states are different from each other. In this way, in a single time interval, the power consumption of the operation voltage supply circuit can intermittently decrease.

[0103] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An operating voltage supply circuit, characterized in that, the operating voltage supply circuit includes: an operating circuit configured to provide a plurality of boost clock signals in a plurality of different load states; and a charge pump circuit coupled to the operating circuit and configured to receive the plurality of boost clock signals and provide an operating voltage based on the duty cycles of the received boost clock signals, wherein the plurality of load states are alternately switched in time intervals of different load states, wherein in the standby mode, the duty cycles of the plurality of boost clock signals provided in the plurality of load states are not exactly the same, wherein the plurality of load states include a first load state and a second load state, wherein the operating circuit provides a first boost clock signal with a first duty cycle in the first load state and provides a second boost clock signal with a second duty cycle in the second load state, and wherein the first duty cycle is different from the second duty cycle, wherein the operating circuit provides a first charging clock signal in the first load state and provides a second charging clock signal in the second load state, wherein the charge pump circuit includes: a capacitor; a first switch, a first end of the first switch receives a charging voltage, a second end of the first switch is coupled to a first end of the capacitor, and a control end of the first switch receives the first charging clock signal in the first load state and receives the second charging clock signal in the second load state; a second switch, a first end of the second switch receives a reference low voltage, a second end of the second switch is coupled to a second end of the capacitor, and a control end of the second switch receives the first charging clock signal in the first load state and receives the second charging clock signal in the second load state; a third switch, a first end of the third switch is coupled to the first end of the capacitor; a fourth switch, a first end of the fourth switch is coupled to the second end of the capacitor; and a voltage regulation circuit coupled to one of a second end of the third switch and a second end of the fourth switch and configured to provide a first regulated voltage based on a reference voltage and provide the first regulated voltage to one of the second end of the third switch and the second end of the fourth switch.

2. The operating voltage supply circuit according to claim 1, characterized in that: the plurality of load states further include a third load state, and the operating circuit provides a third boost clock signal with a third duty cycle in the third load state.

3. The operating voltage supply circuit according to claim 1, characterized in that, the first duty cycle is equal to 50%.

4. The operating voltage supply circuit according to claim 1, characterized in that: the power consumption of the first load state is greater than the power consumption of the second load state, and the first duty cycle is greater than the second duty cycle.

5. The operating voltage supply circuit according to claim 4, characterized in that, The time length of the first load state is shorter than that of the second load state.

6. The operating voltage supply circuit according to claim 1, wherein: the second end of the third switch is used to output the operating voltage, and the control end of the third switch receives the first pumping clock signal in the first load state and receives the second pumping clock signal in the second load state; and the second end of the fourth switch receives the first regulated voltage, and the control end of the fourth switch receives the first pumping clock signal in the first load state and receives the second pumping clock signal in the second load state.

7. The operating voltage supply circuit according to claim 1, wherein: the second end of the third switch receives the first regulated voltage, and the control end of the third switch receives the first pumping clock signal in the first load state and receives the second pumping clock signal in the second load state; and the second end of the fourth switch is used to output the operating voltage, and the control end of the fourth switch receives the first pumping clock signal in the first load state and receives the second pumping clock signal in the second load state.

8. The operating voltage supply circuit according to claim 1, wherein, the operating circuit includes: a selection circuit configured to store a plurality of different state data corresponding to the plurality of load states, alternately take one of the plurality of state data as the selected state data, and output the selected state data; and a clock signal generation circuit coupled to the selection circuit and the charge pump circuit, configured to provide a corresponding pumping clock signal corresponding to the selected state data in response to the selected state data, wherein the duty cycle of the corresponding pumping clock signal corresponds to the selected state data.

9. The operating voltage supply circuit according to claim 8, wherein, the selection circuit includes: a plurality of registers respectively configured to store one of the plurality of state data; and a multiplexer circuit coupled to the plurality of registers and the clock signal generation circuit, configured to receive the plurality of state data and a selection signal, and alternately take one of the plurality of state data as the selected state data in response to the selection signal.

10. The operating voltage supply circuit according to claim 1, wherein, the standby mode includes at least one of a dark screen touch mode and a constant display mode.

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