Method of manufacturing a semiconductor device with an efficient edge structure

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device having a high-efficiency edge termination structure. A method of manufacturing an electronic device includes forming a drift layer of an N-type; forming a trench in the drift layer; forming an edge termination structure beside the trench by implanting a dopant species of a P-type; and forming a recessed region between the trench and the edge termination structure by digging the drift layer. The steps of forming the recessed region and the trench are performed simultaneously. The step of forming the recessed region includes patterning the drift layer to form a structural connection with the edge termination structure having a first slope, and the step of forming the trench includes etching the drift layer to define a sidewall of the trench having a second slope that is steeper than the first slope.

Description

[0001] This application is a divisional application of invention patent application No. 201811474637.9 (titled "Method for manufacturing a semiconductor device with a high-efficiency edge structure") filed on December 4, 2018. Technical Field

[0002] This disclosure relates to an electronic device (e.g., based on silicon carbide) having an edge structure. Background Technology

[0003] As is well known, it has a wide bandgap (specifically, the energy value of the bandgap Eg is greater than 1.1 eV) and a low on-state resistance (R). ON Semiconductor materials with high thermal conductivity, high operating frequency, and high carrier velocity saturation are ideal for manufacturing electronic components such as diodes or transistors, particularly for power applications. Silicon carbide (SiC) is a material possessing these properties and designed for manufacturing electronic components. Specifically, silicon carbide in its different polymorphs (e.g., 3C-SiC, 4H-SiC, 6H-SiC) is superior to silicon for the properties listed above.

[0004] Compared to similar devices mounted on silicon substrates, electronic devices mounted on silicon carbide substrates exhibit many advantageous characteristics, such as low output resistance during conduction, low leakage current, high operating temperature, and high operating frequency.

[0005] Figure 1 A Schottky diode 1 is shown in a cross-sectional view during an intermediate manufacturing step, including a drift layer 2 extending over a substrate 3 and having a first conductivity type (N). An active region 4 extends at the top surface 2a of the drift layer 2. An edge-terminating region 6 (specifically, an implantation region having a second conductivity type (P)) extends at the top surface 2a and completely or partially surrounds the active region 4. Extending between the active region 4 and the edge-terminating region 6 is an edge transition region 7 having a second conductivity type (P) and designed to be contacted by a metal layer (not shown) forming an anode contact. Conversely, a cathode contact (not shown) may be formed in the region corresponding to the substrate 3.

[0006] Multiple junction barrier (JB) elements 8 extend on the top surface 2a, each including a corresponding injection region having a second conductivity type. For each JB element 8, a corresponding recess 9 extends from the top surface 2a such that each recess 9 is completely surrounded by the corresponding JB element 8 and is not directly adjacent to a portion of the drift layer 2 having a first conductivity type. Instead, a region of the drift layer 2 having a first conductivity type extends between a JB element 8 and an adjacent JB element 8. Figure 1The metal layer (anodic metallization) formed in the subsequent manufacturing steps and not illustrated herein, on the top surface 2a and within the recess 9, specifically in direct contact with the drift layer 2 and the junction barrier element 8, provides a Schottky (metal-semiconductor) junction together with the portion of the drift layer 2 having a first conductivity type, and provides a different barrier junction together with the junction barrier element 8.

[0007] In use, when Schottky diode 1 is forward biased, the Schottky junction is turned on before the barrier junction. For low forward voltages, current drift is controlled by the majority carriers (electrons in this case) injected through the Schottky junction, and diode 1 operates in a conventional manner. When diode 1 is reverse biased, the depletion region formed adjacent to the barrier junction expands and blocks reverse current, thereby protecting the Schottky junction and limiting reverse leakage current. Under these conditions, diode 1 operates as a PIN diode. The presence of trench 9, relative to the absence of trench, enables the formation of the junction barrier element 8 at a greater depth in layer 2 (the injection to form the junction barrier element 8 is actually performed after etching trench 9). This technique proves particularly beneficial for SiC devices, improving the aforementioned effects of Schottky junction protection and reverse leakage current limitation. The step of forming trench 9 is envisioned by... Figure 1 Arrow 12 schematically represents chemical etching, such as directional dry etching. By selecting an anisotropic etching technique, generally vertical sidewalls can be provided to trench 9. Thus, a compact device is obtained, where the size of the active region is limited only by the photolithography technique used. However, this same type of etching results in the formation of a step 14 with a steep transition between edge transition region 7 and edge termination region 6 (approximately 90° XY relative to the flat plane of the top surface 2a). It is known that during use, the presence of the inner bottom edge 14a causes electric field concentration, leading to premature triggering of the avalanche multiplication process (low reverse bias value).

[0008] To overcome the aforementioned problems, the applicant's known solution envisions forming an edge transition region between the active region 4 and the edge termination region 6, the edge transition region having an inclined (relative to the plane of surface 2a) surface 24, and having a slope much lower than 90°, specifically less than 50° (an elevation angle measured within the drift layer 2, between the plane of surface 2a and the inclined surface of the edge termination region 6). This embodiment in... Figure 2 The image is shown in the middle. Figure 2 The cross-sectional view shows the relationship with Figure 1 The intermediate manufacturing step corresponds to the Schottky diode 20 in the intermediate manufacturing step. (And...) Figure 1 The corresponding components have similar functions Figure 2 The elements are designated by the same reference numerals and will not be described further herein.

[0009] In the following text, the step of forming trench 9 envisions a chemical etching schematically indicated by arrow 22, which considers the use of a process with a higher degree of isotropy. In this way, a transition region with a sloping surface 24 exhibiting a desired slope can be provided between the active region 4 and the edge region 6. Since trenches 9 are also formed during this etching step, these trenches 9 are defined by sidewalls having the same slope as the sloping surface 24. Although this characteristic does not adversely affect the electrical behavior in the active region 4, it does lead to an undesirable increase in the area occupied by the active region 4.

[0010] Figure 2 The solution to the drawbacks of the embodiment lies in performing two different steps of mask chemical etching: one step for forming a trench 9 with generally vertical walls, and the other step for forming a transition region of a sloping surface 24 with a desired slope (e.g., less than 55°). However, this solution also presents disadvantages because it requires providing at least two different etching masks and performing two different etching processes, which thus increases the cost and duration of the manufacturing process. Furthermore, misalignment may occur relative to the device envisioned at the design stage between the active and edge regions due to undesirable misalignment of the mask used during the aforementioned photolithography process. Under reverse bias conditions, potential misalignment may lead to a loss of device efficiency. Summary of the Invention

[0011] One or more embodiments of this disclosure provide a method of manufacturing an electronic device (specifically, a power diode having a Schottky junction) that does not exhibit the disadvantages of the prior art.

[0012] One or more embodiments of this disclosure relate to a method of manufacturing an electronic device, the method comprising: forming a drift layer having a top surface and a first conductivity; forming a trench in the drift layer by etching the drift layer starting from the top surface; laterally forming an edge-terminating structure relative to the trench by implanting a dopant species having a second conductivity different from the first conductivity; and forming a recessed region between the trench and the edge-terminating structure by etching the drift layer starting from the top surface. In one or more embodiments, forming the recessed region and forming the trench are performed simultaneously, forming the recessed region comprising patterning the drift layer to have a first slope, and forming the trench comprising etching the drift layer to define sidewalls of the trench having a second slope steeper than the first slope. Attached Figure Description

[0013] To better understand this disclosure, preferred embodiments thereof will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0014] Figure 1 A JBS (junction barrier Schottky) diode according to one embodiment that does not form the subject of this disclosure is shown;

[0015] Figure 2 A JBS diode according to another embodiment that does not form the subject of this disclosure is shown; and

[0016] Figures 3A to 3H The steps for manufacturing electronic devices, specifically power diodes, and more specifically JBS diodes, according to this disclosure are shown. Detailed Implementation

[0017] According to this disclosure, a method is provided for manufacturing an electronic device 50, specifically a diode, or even more specifically a power diode (JBS diode) having a Schottky junction.

[0018] Reference Figures 3A to 3H The manufacturing method is described. Figures 3A to 3H The steps of processing semiconductor material on wafer 100 are illustrated in a cross-sectional view. Figures 3A to 3H The wafer 100 is shown in a three-axis system with mutually orthogonal axes X, Y, and Z.

[0019] Reference Figure 3A The wafer 100 includes a substrate 30 of semiconductor material, specifically a silicon carbide (SiC) substrate 30 having a first conductivity type (N-type doped in this embodiment), the substrate 30 having a front side 30a and a rear side 30b opposite to each other. For example, the resistivity of the substrate 30 is included between 5 mΩ·cm and 40 mΩ·cm.

[0020] For example, a silicon carbide drift layer 32 is formed on the front side 30a of the substrate 30 by epitaxial growth. This silicon carbide has a first conductivity type (N) and a dopant concentration lower than that of the substrate 30 (e.g., included in 1.10). 14 With 5.10 16 atoms / cm 3 (between). The drift layer 32 is made of SiC, specifically 4H-SiC, but other polymorphs can be used, such as 2H, 6H, 3C and / or 15R.

[0021] Alternatively, the substrate 30 and the drift layer 32 can be made of other semiconductor materials, such as GaN, GaAs, Si, Ge, or some other semiconductor materials.

[0022] A drift layer 32 extends between a top side surface 32a and a bottom side surface 32b (the bottom side surface 32b is in direct contact with the front side surface 30a of the substrate 30). A hard mask 34 is formed on the top side surface 32a of the drift layer 32, for example, by depositing a mask layer and subsequently defining it using photolithography; the mask layer is made of, for example, tetraethyl orthosilicate (TEOS). The hard mask 34 has a thickness between 0.5 μm and 2 μm, or in any case, has features for shielding (referring to reference below). Figure 3D The thickness of the injection is described. Therefore, the hard mask 34 formed includes: a first portion 34a extending in region 33 of the wafer 100, at region 33, at the edge region of the diode 50 in subsequent steps (and...). Figure 1 and Figure 2 The edge region 6 (of the same type) will be formed; and a plurality of second portions 34b extending in region 35 of wafer 100, where the active region of diode 50 will be formed in a subsequent step.

[0023] For example, the etching of the mask layer 34 is performed via a dry etching process with a high anisotropic component, using an etching chemical composition selected for the drift layer 32, such as a RIE (Reactive Ion Etching) type or an ICP (Inductively Coupled Plasma) type. In this example, since layer 32 is made of SiC, under conditions where the pressure in the etching chamber is between 100 and 10 mTorr (depending on whether it is RIE or ICP etching), and with a power between 500 and 700 W, CHF3 / CF4 / Ar diluted in He can be used as the etching chemical composition. Thus, a second portion 34b can be obtained, which has sidewalls that are substantially orthogonal (between approximately 85° and 89°, for example, approximately 88°) to the planar plane (parallel to XY) of the top side surface 32a of the drift layer 32.

[0024] The material of the mask layer, like the etching chemistry, can be selected as a function of the angle desired between the sidewall of the second portion 34b and the flat plane of the top side surface 32a of the drift layer 32. Here, an angle close to 90° (or, typically greater than 85°) is desired to make the diode 50 compact in the X-axis direction.

[0025] then( Figure 3B The step of forming another mask 36 is to be formed on the wafer 100, and specifically, on the first portion 34a of the hard mask 34 and the drift layer 32, in the region of the drift layer 32 extending between the first portion 34a and the second portion 34b of the hard mask 34 (i.e., between region 33 and region 35).

[0026] Conversely, the mask 36 does not extend over or between the second portions 34b, or in any case, does not extend over the region 35 where the active region of the diode 50 of the wafer 100 will be formed.

[0027] If possible Figure 3B It is noted that the step of forming mask 36 after the deposition of the photoresist layer (e.g., by spin coating) envisions a step of removing selective portions of the photoresist layer to form a transition region 36a having a surface inclined relative to the top surface 32a; therefore, in the transition region 36a, the thickness of mask 36, measured along the Z-axis starting from the top surface 32a of the drift layer 32, decreases in the direction away from region 33 (or, similarly, in the direction toward region 35). Specifically, mask 36 has a maximum thickness d measured along the Z-axis. M Maximum thickness d M Included between 2μm and 6μm, and within the transition region 36a, the thickness of mask 36 decreases from d at a predetermined slope. M Reduced to zero thickness. The inclined surface of the mask 36 has a slope set between 10° and 60°, for example 45° (the magnitude of the interior angle α of the mask 36 formed by the intersection of the inclined surface and the top surface 32a of the drift layer 32).

[0028] exist Figure 3B In one embodiment, the reduction in the thickness of the mask 36 in the transition region 36a is approximately linear along the X-axis; in another embodiment (not shown), the reduction in the thickness of the mask 36 is performed along the X-axis in discrete steps, i.e., through small steps.

[0029] The desired shape of mask 36 (specifically, transition zone 36a) can be obtained using a process that employs a photoresist with a large thickness (specifically, equal to or greater than 2 μm), appropriate exposure steps, wherein the focusing conditions of this process can be varied relative to the best settings (autofocus) that the machine will automatically implement. Specifically, the defocusing conditions are included between 0 and -1.5 μm relative to the flat plane of mask 36 (or more precisely, the top side of mask 36 to reduce the effect of its thickness), followed by a development step, in which a single or double distribution of solvent (“double puddle”) can be performed to remove portions of the photoresist exposed to UV radiation during the exposure steps. At the end of the development step, transition zone 36a will exhibit an elevation angle (approximately 70° to 75°) within the plane defined by top side 32a. Figure 3BThe mask 36 is then subjected to appropriate heat treatment to improve its stability; this step causes a further change in angle α, which decreases to a value between approximately 60° and 70°. In one embodiment, the above-described heat treatment of the mask 36 is envisioned as a process of baking in an oven at a temperature between 120°C and 130°C for one hour, with or without an initial ramp; in another embodiment, the heat treatment is envisioned as a deep UV-type process, whereby baking is performed at a temperature between 200°C and 220°C (achieved via a temperature ramp lasting 3 to 5 minutes) in the presence of UV radiation. UV radiation facilitates and accelerates the crosslinking process of the photoresist.

[0030] During the aforementioned steps of the photoresist heat treatment, the photoresist releases the solvent trapped within it, while a crosslinking process is performed. This crosslinking process utilizes modifications to the double and triple bonds of the macromolecules constituting the photoresist: at the macroscopic level, this modification results in greater resistance to plasma (which is useful, especially in the subsequent etching of SiC) and a change in the contour of the photoresist layer itself. In this way, the contour of mask 36 (in a cross-sectional view in plane XZ) is generated, which forms an angle between 60° and 70° with the planar plane of side 32a (parallel to XY), as specified above.

[0031] Then, the next step is to etch the wafer 100. Figure 3C Specifically, dry etching is performed using an ICP etching tool with O2 / SF6 / HBr as the etching chemical composition. The pressure in the region is approximately 10 to 15 mTorr, and the power at the source (for generating plasma) is between 600 W and 800 W, with a bias power between 70 W and 150 W (for accelerating the etch species toward the chuck). Typically, the above parameters are selected to remove the mask 36 at a rate higher than the removal rate of the drift layer 32 (e.g., approximately three times the removal rate of the drift layer 32).

[0032] Etching continues, thereby removing portions of the drift layer 32 that are not protected by the mask 36 or mask 34, to form a trench 38 in the drift layer 32 in region 35 (the active region of the diode 50), the trench 38 having generally vertical walls.

[0033] Since the above etching process also removes a portion of the surface of mask 36, by performing Figure 3CThe etching step takes time as a function of the desired depth of penetration (where the upper limit is determined by the etching rate of the photoresist used for mask 36 and the thickness of mask 36), and also removes the surface portion of the drift layer 32 that is gradually exposed due to the removal of the gradually thinner portions of mask 36. In other words, the inclined surface of mask 36 in transition region 36a recedes in the direction of axis X (away from region 35) from the portion of the top surface 32a of the gradually exposed drift layer 32 that can therefore be etched and removed by ion beam.

[0034] In this way, a transition region 32c of the drift layer 32 is obtained between region 35 (the active region of diode 50) and region 33 (the edge termination region of diode 50). The transition region 32c has a slope as a transition region 36a of mask 36 and a slope as a function of the difference between the etching rate of the material of mask 36 and the etching rate of the material of drift layer 32.

[0035] Therefore, in Figure 3C At the end of the process, wafer 100 exhibits trench 38 and transition region 32c. Trench 38 is defined by walls having a slope between 80° and 90° relative to top surface 32a (here, parallel to the planar XY plane of wafer 100). Transition region 32c is defined by the surface of drift layer 32 having a slope between 10° and 60° relative to top surface 32a. Thus, in the same processing step, two different slopes are obtained for two different functional regions of the diode 50 being manufactured.

[0036] Then( Figure 3D Mask 36 is removed, and mask 34 remains on wafer 100. Now, using hard mask 34, the step of implanting a dopant species (e.g., boron or aluminum) having a second conductivity type (P) is performed (indicated by arrow 39 in the figures). Thus, multiple junction barrier (JB) elements 40 (P-type, here) are formed at each trench 38.

[0037] During the injection step described above, the injection anode region 41 is also formed between region 33 and region 35 (i.e., between mask portion 34a and multiple mask portions 34b).

[0038] In one embodiment, Figure 3D The steps involve one or more implantations of a dopant species having a second conductivity type, wherein the implantation energy is included between 30 keV and 400 keV, and wherein the dose is 1.10 12 atoms / cm 2 With 1.10 15 atoms / cm 2 Between, so as to form a value higher than 1.1018 atoms / cm 3 The dopant concentration of the junction barrier element 40 and the implanted anode region 41.

[0039] Then continue ( Figure 3E The edge region 42 is formed by implanting a dopant species having a second conductivity type. For this purpose, prior to the implantation step, mask 34 is removed, and then (e.g., TEOS) an implantation mask 43 is formed on wafer 100, patterned to expose only the surface portion where the edge region 42 is desired to form. Implantation (here, P-type, indicated by arrow 44 in the figures) is then performed by implanting dopant atoms (e.g., aluminum or boron), wherein the implantation energy is included between 20 keV and 300 keV, and the implantation dose is included in the range of 1.10 keV. 12 atoms / cm 2 With 1.10 13 atoms / cm 2 between.

[0040] According to one embodiment, the mask 43 is patterned such that the edge region 42 extends to partially overlap with the terminal portion of the injected anode region 41, so that the two regions will be in electrical contact, and the continuity of the P-type layer will be guaranteed even if there is any possible misalignment between the masks 34 and 43.

[0041] Next ( Figure 3F Mask 43 is removed, and a thermal annealing step is performed for use in Figure 3D and Figure 3E The diffusion and activation of the dopant species implanted in the process are described. For example, thermal annealing is performed at temperatures above 1600°C (e.g., between 1700 and 1900°C, and in some cases, even higher). After thermal annealing, the edge region 42 has a diameter of approximately 1.10 mm. 15 atoms / cm 3 With 1.10 17 atoms / cm 3 The concentration of dopant species between the junction barrier element 40 and the implanted anode region 41 is included in approximately 1.10. 17 atoms / cm 3 With 1.10 20 atoms / cm 3 The concentration of dopant species between them.

[0042] Next is the formation of insulating layer 46, which is designed to completely cover edge region 42 and expose transition region 32 and active region 35. Figure 3G For example, insulating layer 46 is deposited TEOS.

[0043] Then( Figure 3H Anode metallization is formed.

[0044] For this purpose, an interface layer 47 of metallic material, such as titanium, nickel, molybdenum, or other conductive materials, is deposited on wafer 100. These other conductive materials are selected based on the physical parameters of the metal used for interface layer 47 and the semiconductor used for drift layer 32 (typically, when a junction is positioned between a metal and a semiconductor, an energy barrier is formed for both electrons and holes). These parameters include the work function of the metal, the work function of the semiconductor, and the electron affinity of the semiconductor. A lower work function of the metal results in a lower voltage drop; however, a metal with a low work function corresponds to higher leakage in the finished device. Therefore, a metal can be selected based on a trade-off between acceptable leakage and acceptable voltage drop. Interface layer 47 is deposited via sputtering and has a thickness between approximately 10 nm and 500 nm. Interface layer 47 extends to contact the implanted anode region 41, to contact the region of drift layer 32 between a trench 38 and an adjacent trench, and similarly penetrates into trench 38. Specifically, the interface layer 47 forms a Schottky contact with the exposed area of ​​the drift layer 32, and forms an ohmic contact with the junction barrier element 40 and the injected anode region 41.

[0045] Next, another metal layer 48 is formed on top of the interface layer 47 and is in direct contact with the interface layer 47. For example, the metal layer 48 is aluminum or copper and has a thickness of a few micrometers, for example, between 1 and 10 μm.

[0046] The integral consisting of interface layer 47 and metal layer 48 forms an anodic metallization 49.

[0047] Therefore, multiple Schottky-type metal-semiconductor junctions are formed between the anode metallization 49 and the region of the drift layer 32 having a first conductivity type (N).

[0048] Conversely, an ohmic contact that functions to drive the PN junction is formed between the anode metallization 49 and the junction barrier element 40 (which has a second conductivity type, here P).

[0049] An ohmic contact with the function of driving the edge region is formed between the anode metallization 49 and the injected anode region 41 (having a second conductivity type, here P).

[0050] In different embodiments (not shown), the interface layer 47 may be omitted, such that the anodic metallization 49 is consistent with the metal layer 48, which extends to be in direct contact with the drift layer 32.

[0051] Finally, for example, a cathode contact is formed on the rear side 30b of the substrate 30 by depositing a layer 45 of metallic material designed to form an ohmic contact with the substrate 30.

[0052] The region of drift layer 32 extending along axis Z between the Schottky junction and the metal material layer 45 (cathode) is the active region 4 of diode 50 (i.e., the region where charge drift occurs). Edge region 42 completely (e.g., edge region 42 is a ring) or partially surrounds active region 4. The function of edge region 42 is to reduce or prevent congestion of electric field lines outside the Schottky junction.

[0053] Its advantages are obvious upon examination of the characteristics of the disclosure provided under this disclosure.

[0054] Specifically, this disclosure enables the formation of trenches and punch-holes in semiconductor devices using a low-cost process with fewer manufacturing steps compared to known types of processes. The trenches and punch-holes have different slopes in the walls defining them. Even more specifically, these trenches and punch-holes are formed simultaneously in the same processing step. This eliminates misalignment problems that may occur when using different masks to form trenches and punch-holes defined by walls with different slopes. Furthermore, due to the technical solution of this disclosure, and Figure 2 Compared to other solutions, the total area may be smaller, and at the same time, it avoids the concentration of undesirable field lines at the corners formed in the drift layer (as shown in the reference). Figure 1 (Discussion of existing technologies).

[0055] Finally, it is obvious that modifications and changes can be made to the content described and illustrated herein without departing from the scope of this disclosure.

[0056] For example, the previously described method for manufacturing an electronic device may be implemented, the electronic device having only one trench 38 and / or only one Schottky contact between the anodic metallization 48 and the drift layer 32.

[0057] Furthermore, the slope of region 32c can be increased to over 50°, while the performance of the receiving device decreases, in any case, keeping the slope less than the slope of the inner wall of trench 38. Similarly, the slope of the inner wall of trench 38 can be decreased to below 80°, in any case, keeping the slope greater than the slope of region 32c.

[0058] This disclosure can also be applied during the steps of generating the edge structure of a trench MOSFET device.

[0059] The various embodiments described above can be combined to provide other embodiments. In view of the above description, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be construed as including all possible embodiments, together with the full scope of equivalents to which such claims are given. Therefore, the claims are not limited to this disclosure.

Claims

1. A structure for a diode, comprising: Substrate with primary conductivity; A first conductive drift layer on a first side of the substrate, the drift layer having a first surface remote from the first side of the substrate; A first trench in the first surface of the drift layer, the first trench including sidewalls opposite each other in a first direction and a transition region, the sidewalls having a first slope that is steeper than a second slope of the transition region; as well as On the first surface of the drift layer and transverse to the trench, there is an edge termination structure having a second conductivity different from the first conductivity, and the transition region of the trench is close to the edge termination structure. The slope of the transition region is at least 20° smaller than the slope of the sidewall.

2. The structure according to claim 1, wherein the second slope is included between 10° and 60°, and the first slope is included between 80° and 90°.

3. The structure according to claim 1, wherein the drift layer has a dopant concentration of a first conductive dopant that is lower than the dopant concentration of the substrate.

4. The structure according to claim 1, wherein the drift layer is silicon carbide.

5. The structure of claim 1, comprising a second trench in the first surface of the drift layer, the second trench having two sidewalls opposite each other in the first direction, each of the two sidewalls having a slope in the range of 80° to 90°.

6. The structure according to claim 5, comprising a junction barrier element on the second trench, the junction barrier element having a second conductivity different from the first conductivity.

7. The structure according to claim 1, comprising an anode region on the first trench, the anode region having a second conductivity different from the first conductivity.

8. The structure of claim 7, wherein the edge termination structure includes an edge region of second conductivity, the edge region overlapping the anode region.

9. The structure according to claim 7, comprising an anode electrode on the anode region.

10. The structure of claim 9, comprising a metal interface layer between the anode electrode and the anode region.

11. The structure of claim 9, further comprising an insulating structure separating the anode electrode from the edge termination structure.

12. The structure of claim 9, comprising a cathode electrode on a second side of the substrate, the second side being opposite to the first side.

13. The structure according to claim 1, wherein the first conductivity is N-type and the second conductivity is P-type.

14. A power diode, comprising: Substrate; A first conductive drift layer on the substrate; A first conductive junction barrier element on a first trench of the drift layer, the first trench having two sidewalls opposite each other in a first direction, the two sidewalls having a slope in the range of 80° to 90°; as well as The second conductive anode region on the second trench of the drift layer, the second trench having a transition region and sidewalls opposite each other in the first direction, the slope of the transition region being at least 20° smaller than the slope of the sidewalls of the second trench.

15. The power diode of claim 14, wherein the anode region extends beyond the second trench.

16. The power diode of claim 15, comprising a termination region of the second conductivity on a first surface of the drift layer, wherein the second trench is located between the first trench and the termination region in the first direction. in, The anode region is in contact with the terminal region.

17. The power diode of claim 14, wherein the anode region and the junction barrier element are separated from each other by the drift layer.

18. The power diode of claim 14, comprising an anode electrode in contact with the anode region and the junction barrier element.

19. An apparatus for a diode, comprising: Substrate; A first conductive semiconductor layer on the substrate; A trench in one surface of the semiconductor layer, the trench having a transition region and sidewalls opposite each other in a first direction, the slope of the transition region being at least 20° smaller than the slope of the sidewalls; A first doped region with second conductivity in the trench, the first doped region including an extension beyond the surface of the semiconductor; as well as A second doped region on the surface of the semiconductor layer, the second doped region overlapping and contacting the extension portion of the first doped region.

20. The apparatus of claim 19, further comprising an insulating structure covering a portion of the second doped region and an extension of the first doped region.

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