Semiconductor device and manufacturing method thereof

Abstract

The present application provides a semiconductor device and a process method thereof. The process method of the semiconductor device includes: providing a semiconductor substrate, the semiconductor substrate includes a bottom semiconductor layer, a buried oxide layer and a top semiconductor layer stacked in sequence, the top semiconductor layer is divided into at least one active area; injecting a first ion into a portion of the active area corresponding to a channel area; performing an annealing treatment so that the first ion reacts with a portion of silicon in the active area, and an insulating dielectric layer is formed in a portion corresponding to the channel area to reduce the thickness of the channel area; forming a gate on the channel area, and forming a source area and a drain area in the active area on both sides of the gate. The process method of the semiconductor device can reduce the capacitance between the source area and the drain area, thereby reducing the influence of the parasitic capacitance of the manufactured semiconductor device on its radio frequency performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] RF technology is widely used in various aspects of life, such as semiconductor devices such as RF switches. However, as the frequency of semiconductor devices continues to increase, the parasitic capacitance of semiconductor devices is large, especially the large parasitic capacitance between the source and drain, which causes the RF performance of semiconductor devices to drop sharply. Summary of the invention

[0003] The semiconductor device and its manufacturing method provided in the present application are intended to solve the problem that the parasitic capacitance of the semiconductor device is large, especially the large parasitic capacitance between the source and the drain, which causes the RF performance of the semiconductor device to drop sharply.

[0004] In order to solve the above technical problems, a technical solution adopted by the present application is: to provide a process method for a semiconductor device. The process method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes a bottom semiconductor layer, a buried oxide layer and a top semiconductor layer stacked in sequence, and the top semiconductor layer is divided into at least one active area; implanting first ions into a portion of the active area corresponding to the channel area; performing annealing so that the first ions react with a portion of silicon in the active area, forming an insulating dielectric layer in the portion corresponding to the channel area, so as to reduce the thickness of the channel area; forming a gate on the channel area, and forming a source area and a drain area in the active area on both sides of the gate.

[0005] In one embodiment, the first ions include oxygen ions.

[0006] In a specific embodiment, the method further includes processing the active area to form a well area.

[0007] In a specific embodiment, the doping energy of the first ion is 30kev-65kev, so that the first ion is implanted into the portion of the active area corresponding to the channel area close to the buried oxide layer, so that the formed insulating dielectric layer is close to the side of the buried oxide layer away from the bottom semiconductor layer.

[0008] In a specific embodiment, the first ions are implanted into the portion of the active region corresponding to the channel region multiple times in batches.

[0009] In a specific embodiment, the doping dose of the first ion is 5E14-5E15 / cm 2 .

[0010] In a specific embodiment, the ratio of the thickness of the insulating dielectric layer to the thickness of the top semiconductor layer is in the range of 0.2-0.25, and the width of the insulating dielectric layer formed by injecting the first ions is greater than the width of the channel region; wherein the ratio of the distance between the first end of the insulating dielectric layer and the first end of the channel region to the width of the channel region is 5%-15%; and / or the ratio of the distance between the second end of the insulating dielectric layer and the second end of the channel region to the width of the channel region is 5%-15%.

[0011] In a specific embodiment, forming a gate on the channel region and forming a source region and a drain region in the active region on both sides of the gate includes: forming a gate oxide layer on the channel region; forming a gate on the gate oxide layer; forming side walls on both sides of the gate; lightly doping the well regions on both sides of the gate to form lightly doped regions; and doping the source and drain regions in the lightly doped regions to respectively form a source region and a drain region in the well regions on both sides of the gate.

[0012] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; wherein the semiconductor substrate includes a bottom semiconductor layer, a buried oxide layer and a top semiconductor layer stacked in sequence; wherein the top semiconductor layer includes a source region, a drain region, a channel region and an insulating dielectric layer, and the insulating dielectric layer corresponds to the channel region to reduce the thickness of the channel region between the source and drain regions.

[0013] In a specific embodiment, the insulating dielectric layer is located on a side of the buried oxide layer close to the top semiconductor layer; the ratio of the thickness of the insulating dielectric layer to the thickness of the top semiconductor layer is in the range of 0.2-0.25; and / or the width of the insulating dielectric layer is greater than the width of the channel region, and the ratio of the distance between the first end of the insulating dielectric layer and the first end of the channel region to the width of the channel region is 5%-15%; and / or the ratio of the distance between the second end of the insulating dielectric layer and the second end of the channel region to the width of the channel region is 5%-15%.

[0014] The beneficial effects of the present application are different from those of the prior art: the present application provides a semiconductor device and a process method thereof, wherein the process method of the semiconductor device injects a first ion into a portion of an active region corresponding to a channel region in a semiconductor substrate, and then performs an annealing treatment so that the first ion reacts with a portion of silicon in the active region, and forms an insulating dielectric layer in the portion corresponding to the channel region, so as to reduce the thickness of the channel region, thereby reducing the capacitance between the source region and the drain region, and thereby reducing the influence of the parasitic capacitance of the manufactured semiconductor device on its radio frequency performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown;

[0017] Figure 2 A schematic structural diagram of a semiconductor substrate provided by an embodiment of the present application is depicted;

[0018] Figure 3 A schematic diagram of a structure of implanting first ions on a semiconductor substrate according to an embodiment of the present application is depicted;

[0019] Figure 4 A schematic diagram of a structure for forming a well region on a semiconductor substrate according to an embodiment of the present application is depicted;

[0020] Figure 5 A schematic diagram of the structure of a semiconductor substrate after annealing treatment according to an embodiment of the present application is depicted;

[0021] Figure 6 A schematic diagram of a structure of forming a gate, a source region, and a drain region on a semiconductor substrate according to an embodiment of the present application is depicted;

[0022] Figure 7 A flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present application is shown;

[0023] Figure 8 A schematic structural diagram of forming a dielectric layer on a semiconductor substrate according to an embodiment of the present application is depicted.

[0024] Description of Reference Numerals

[0025] Semiconductor substrate 1; bottom semiconductor layer 11; buried oxide layer 12; top semiconductor layer 13; isolation structure 14; active area 15; first mask 2a; second mask 2b; first ion 3; gate oxide layer 4; insulating dielectric layer 5; gate 6; sidewall 7; source region 8a; drain region 8b; dielectric layer 9. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0028] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0030] See also Figure 1 , Figure 1 A flow chart of a process method for a semiconductor device provided by an embodiment of the present application is depicted; in this embodiment, the semiconductor device may be a radio frequency device, such as a radio frequency switch, a radio frequency power amplifier, etc. The process method for a semiconductor device of the present application can reduce the thickness of the channel region of the semiconductor device, thereby reducing the capacitance between the source region and the drain region, so as to reduce the influence of the parasitic capacitance of the manufactured semiconductor device on its radio frequency performance. The process method specifically includes:

[0031] Step S1: providing a semiconductor substrate.

[0032] In the specific implementation process, please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a semiconductor substrate provided in one embodiment of the present application is depicted. The semiconductor substrate 1 can be prepared by using separation by implanted oxygen (SIMOX) or bonding etch-back (BE). The semiconductor substrate 1 is a SOI (Semiconductor On Insulator) substrate, comprising a bottom semiconductor layer 11, a buried oxide layer 12, and a top semiconductor layer 13 stacked in sequence. The bottom semiconductor layer 11 and the top semiconductor layer 13 can be silicon, germanium, or other suitable materials in the art, and the buried oxide layer 12 can be silicon oxide or silicon oxynitride.

[0033] Afterwards, a shallow trench isolation (STI) process is used to form a plurality of isolation structures 14 on the top semiconductor layer 13 of the semiconductor substrate 1, so as to divide the top semiconductor layer 13 into at least one active region 15. The specific processes of the SIMOX technology, the BE technology and the STI process can be referred to in the prior art, and will not be described in detail here.

[0034] Step S2: implanting first ions into a portion of the active region corresponding to the channel region.

[0035] For details, see Figure 3 , Figure 3 A schematic diagram of a structure of implanting first ions on a semiconductor substrate according to an embodiment of the present application is shown; step S2 includes:

[0036] Step S21: a mask is disposed on the semiconductor substrate 1 to expose a portion of the active region 15 corresponding to the channel region.

[0037] Specifically, a first mask 2 a is disposed on the semiconductor substrate 1 , for example, a photoresist is coated, and a photolithography process is performed to expose a portion of the active region 15 corresponding to the channel region.

[0038] Step S22: implanting the first ions 3 into the portion of the exposed active region 15 corresponding to the channel region.

[0039] Among them, Figure 3 As shown, the first ions 3 may be oxygen ions. The doping dose of the first ions 3 may be 5E14-5E15 / cm 2 Under this doping dose, the insulating dielectric layer 5 formed later has better compactness, which can further reduce the capacitance between the source region 8a and the drain region 8b compared to the insulating dielectric layer with poor compactness.

[0040] During the specific implementation process, the doping energy of the first ion 3 is 30kev-65kev; so that the first ion 3 is injected into the portion of the active area 15 corresponding to the channel area close to the buried oxide layer 12, and then the subsequently formed insulating dielectric layer 5 is close to the surface of the side of the buried oxide layer 12 away from the bottom semiconductor layer 11.

[0041] Among them, the first ions 3 can be injected into the part corresponding to the channel area in the active area 15 in batches for multiple times; in this way, more first ions 3 can be injected according to actual needs, so as to form a thicker insulating dielectric layer 5 after subsequent annealing treatment, thereby reducing the capacitance between the source area 8a and the drain area 8b to a greater extent, and weakening the influence of the parasitic capacitance of the formed semiconductor device on its radio frequency performance.

[0042] According to actual needs, the first ions may also be implanted into the portion of the active region 15 corresponding to the channel region at one time.

[0043] Step S3: performing annealing treatment to make the first ions react with part of the silicon in the active area, forming an insulating dielectric layer in the portion corresponding to the channel area, so as to reduce the thickness of the channel area.

[0044] Wherein, step S3 specifically includes:

[0045] Step S31: Process the active region 15 to form a well region.

[0046] See also Figure 4 , Figure 4 A schematic diagram of a structure for forming a well region on a semiconductor substrate according to an embodiment of the present application is shown. Specifically, the first mask 2a is removed, and a second mask 2b is set on the semiconductor substrate 1, such as applying a photoresist and performing a photolithography process to expose a portion of the active region 15; then well doping is performed to form a well region. The specific process of performing well doping on the active region 15 to form a well region can refer to the existing process flow for performing well doping, which will not be repeated here.

[0047] Step S32: Annealing treatment to make the first ions 3 react with part of the silicon in the well region, and form an insulating dielectric layer 5 in the part of the well region corresponding to the channel region, so as to reduce the thickness of the channel region.

[0048] See also Figure 5 , Figure 5 The structure of the semiconductor substrate after annealing in one embodiment of the present application is shown. The second mask 2b is removed, and the active area 15 is annealed by using a rapid thermal processing (RTP) process, so that the first ions 3 react with part of the silicon in the well area to form an insulating dielectric layer 5. The product structure after this step can be seen in FIG. Figure 5The specific process of high temperature annealing treatment can refer to the existing high temperature annealing treatment process.

[0049] For details, see Figure 6 , Figure 6 A schematic diagram of the structure of forming a gate, a source region and a drain region on a semiconductor substrate according to an embodiment of the present application is depicted; the ratio of the thickness H1 of the insulating dielectric layer 5 to the thickness H2 of the top semiconductor layer 13 can be in the range of 0.2-0.25, so as to minimize the capacitance between the subsequently formed source region 8a and the drain region 8b, thereby reducing the impact on the radio frequency performance of the manufactured semiconductor device.

[0050] Specifically, Figure 6 As shown, the width W1 of the insulating dielectric layer 5 formed by injecting the first ions 3 is greater than the width W2 of the channel region to ensure that the bottom of the channel region is provided with an insulating dielectric layer 5, so that the capacitance between the source region 8a and the drain region 8b can be minimized through the insulating dielectric layer 5 under the same conditions of thickness, material, etc. of the insulating dielectric layer 5.

[0051] In a specific embodiment, the ratio of the distance L1 between the first end of the insulating dielectric layer 5 and the first end of the channel region to the width W2 of the channel region may be 5%-15%; and / or, the ratio of the distance between the second end of the insulating dielectric layer 5 and the second end L2 of the channel region to the width W2 of the channel region may be 5%-15%.

[0052] In the specific implementation process, the order of step S31 and step S32 is not limited. After step S2, step S31 can be performed first, and then step S32; in this way, an annealing process can be omitted. Of course, after step S2, step S32 can be performed first, and then step S31; in this case, an annealing process needs to be performed again after step S31. For details, please refer to the annealing process after the existing well doping.

[0053] Step S4: forming a gate on the channel region, and forming a source region and a drain region in the active region on both sides of the gate respectively.

[0054] In step S4, a source region 8a and a drain region 8b are formed in the well regions on both sides of the gate 6. Figure 6 As shown, step S4 specifically includes:

[0055] Step S41: forming a gate oxide layer 4 on the channel region.

[0056] Specifically, the gate oxide layer 4 may be silicon oxide or a hi-k dielectric layer.

[0057] Step S42 : forming a gate 6 on the gate oxide layer 4 .

[0058] Specifically, a gate material may be deposited on the surface of the semiconductor substrate 1 to form a gate material layer, wherein the gate material may be polysilicon or metal.

[0059] The gate material layer may be patterned through the steps of photoresist coating, exposure and development, etching, etc., so as to form the gate 6 on the gate oxide layer 4. In this embodiment, the gate material layer may be patterned by dry etching.

[0060] Step S43 : forming sidewall spacers 7 on both sides of the gate 6 .

[0061] Among them, Figure 6 As shown, a layer of silicon oxide can be deposited on the semiconductor substrate 1 by chemical deposition, and then the silicon oxide on the surface of the gate 6 facing away from the semiconductor substrate 1 is etched away, leaving the silicon oxide on both sides of the gate 6 to form a side wall 7; the specific implementation process can refer to the existing process for forming the dielectric side wall 7, which will not be repeated here.

[0062] Step S44: lightly doping is performed in the well regions on both sides of the gate 6 to form lightly doped regions.

[0063] The specific process of lightly doping the well regions on both sides of the gate 6 may refer to the existing lightly doping process, and the same or similar technical effects may be achieved, which will not be described in detail here.

[0064] Step S45: performing source and drain region doping in the lightly doped region to form a source region 8 a and a drain region 8 b in the well regions on both sides of the gate 6 , respectively.

[0065] Specifically, ion implantation is performed on the well region in the semiconductor substrate 1 using the gate 6 and the spacer 7 as masks to form a source region 8a and a drain region 8b. The specific process flow can refer to the source / drain region implantation of existing semiconductor devices, which will not be described in detail here.

[0066] In one embodiment, see Figure 7 , Figure 7 A flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present application is shown. The method for manufacturing a semiconductor device also includes:

[0067] Step S5: forming a dielectric layer on the semiconductor substrate.

[0068] Specifically, the dielectric layer 9 may be formed on the semiconductor substrate 1 by chemical deposition or other methods. Figure 8 , Figure 8A schematic diagram of a structure of a dielectric layer formed on a semiconductor substrate according to an embodiment of the present application is shown. The dielectric layer 9 is disposed on a surface of the top semiconductor layer 13 facing away from the buried oxide layer 12, and wraps around the gate 6 and the sidewall 7 to protect the gate 6, the source region 8a and the drain region 8b. The dielectric layer 9 is made of silicon oxide.

[0069] The process method of the semiconductor device provided in this embodiment is to implant the first ions 3 into the portion corresponding to the channel region in the active region 15 of the semiconductor substrate 1, and then perform annealing treatment so that the first ions 3 react with part of the silicon in the active region 15, and form an insulating dielectric layer 5 in the portion corresponding to the channel region in the active region 15, so as to reduce the thickness of the channel region between the source region 8a and the drain region 8b, thereby reducing the capacitance between the source region 8a and the drain region 8b, and further weakening the influence of the parasitic capacitance of the manufactured semiconductor device on its radio frequency performance.

[0070] In one embodiment, if Figure 8 As shown, a semiconductor device is also provided, which is manufactured by the manufacturing method of the semiconductor device. The parasitic capacitance of the semiconductor device is small and the radio frequency performance is good.

[0071] Specifically, Figure 8 As shown, the semiconductor device includes a semiconductor substrate 1. The semiconductor substrate 1 includes a bottom semiconductor layer 11, a buried oxide layer 12, and a top semiconductor layer 13 stacked in sequence. The bottom semiconductor layer 11 and the top semiconductor layer 13 may be silicon, germanium, or other suitable materials in the art, and the buried oxide layer 12 may be silicon oxide or silicon oxynitride.

[0072] Specifically, the top semiconductor layer 13 includes a source region 8a, a drain region 8b, a channel region and an insulating dielectric layer 5. The insulating dielectric layer 5 is disposed between the source region 8a and the drain region 8b and corresponds to the channel region to reduce the thickness of the channel region between the source region 8a and the drain region 8b, thereby reducing the capacitance between the source region 8a and the drain region 8b, and reducing the effect of the parasitic capacitance of the semiconductor device on its radio frequency performance, so that it has better radio frequency performance. The insulating dielectric layer 5 can be made of silicon dioxide.

[0073] In a specific embodiment, Figure 8 As shown, the insulating dielectric layer 5 is located on the side of the buried oxide layer 12 close to the top semiconductor layer 13. The ratio of the thickness H1 of the insulating dielectric layer 5 to the thickness H2 of the top semiconductor layer 13 can be in the range of 0.2-0.25, so as to reduce the capacitance between the source region 8a and the drain region 8b as much as possible, thereby reducing the parasitic capacitance of the semiconductor device.

[0074] The width W1 of the insulating dielectric layer 5 is greater than the width W2 of the channel region to ensure that the bottom of the channel region is provided with the insulating dielectric layer 5, so that the capacitance between the source region 8a and the drain region 8b can be reduced to the maximum extent through the insulating dielectric layer 5 under the same conditions of thickness, material, etc. of the insulating dielectric layer 5. Specifically, the ratio of the distance L1 between the first end of the insulating dielectric layer 5 and the first end of the channel region to the width W2 of the channel region can be 5%-15%; and / or, the ratio of the distance between the second end of the insulating dielectric layer 5 and the second end L2 of the channel region to the width W2 of the channel region can be 5%-15%.

[0075] In a specific embodiment, the semiconductor device further includes a gate oxide layer 4, a gate 6, a sidewall 7 and a dielectric layer 9. The gate oxide layer 4 corresponds to the channel region and is formed on the surface of the top semiconductor layer 13 facing away from the buried oxide layer 12; the gate oxide layer 4 can specifically be silicon oxide or a hi-k dielectric layer. The gate 6 and the sidewall 7 are arranged on the channel region and are located on the surface of the gate oxide layer 4 facing away from the semiconductor substrate 1. The sidewall 7 is located on both sides of the gate 6. The dielectric layer 9 is arranged on the surface of the top semiconductor layer 13 facing away from the buried oxide layer 12, and wraps the gate 6 and the sidewall 7 to protect the source region 8a and the drain region 8b of the gate 6. The material of the dielectric layer 9 can be silicon oxide.

[0076] The semiconductor device provided in this embodiment sets an insulating dielectric layer 5 between the source region 8a and the drain region 8b and at a position corresponding to the channel region to reduce the thickness of the channel region between the source region 8a and the drain region 8b, thereby reducing the capacitance between the source region 8a and the drain region 8b, thereby weakening the influence of the parasitic capacitance of the semiconductor device on its radio frequency performance, so that it has better radio frequency performance.

[0077] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate comprises a bottom semiconductor layer, a buried oxide layer and a top semiconductor layer stacked in sequence, and the top semiconductor layer is divided into at least one active area; Implanting first ions into a portion of the active region corresponding to the channel region; Performing an annealing process to allow the first ions to react with a portion of silicon in the active region to form an insulating dielectric layer in a portion corresponding to the channel region to reduce a thickness of the channel region; forming a gate on the channel region, and forming a source region and a drain region in the active region on both sides of the gate; The ratio of the thickness of the insulating dielectric layer to the thickness of the top semiconductor layer is in the range of 0.2-0.25; and / or The width of the insulating dielectric layer is greater than the width of the channel region, and the ratio of the distance between the first end of the insulating dielectric layer and the first end of the channel region to the width of the channel region is 5%-15%; and / or the ratio of the distance between the second end of the insulating dielectric layer and the second end of the channel region to the width of the channel region is 5%-15%.

2. The method according to claim 1, characterized in that The first ions include oxygen ions.

3. The method according to claim 1, characterized in that The method also includes processing the active area to form a well area.

4. The method according to claim 1, characterized in that The doping energy of the first ions is 30kev-65kev, so that the first ions are implanted into the portion of the active area corresponding to the channel area close to the buried oxide layer, so that the formed insulating dielectric layer is close to the side of the buried oxide layer away from the bottom semiconductor layer.

5. The method according to claim 1, characterized in that The first ions are implanted multiple times in batches into a portion of the active region corresponding to the channel region.

6. The method according to claim 1, characterized in that The doping dose of the first ion is 5E14~5E15 / cm 2 .

7. The method according to claim 3, characterized in that The step of forming a gate on the channel region and forming a source region and a drain region in the active region on both sides of the gate comprises: forming a gate oxide layer on the channel region; forming a gate on the gate oxide layer; Forming sidewalls on both sides of the gate; Lightly doping the well regions on both sides of the gate to form lightly doped regions; Doping of source and drain regions is performed in the lightly doped region to form a source region and a drain region in the well region on both sides of the gate, respectively.

8. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate comprises a bottom semiconductor layer, a buried oxide layer and a top semiconductor layer stacked in sequence; Wherein, the top semiconductor layer includes a source region, a drain region, a channel region and an insulating dielectric layer, and the insulating dielectric layer corresponds to the channel region to reduce the thickness of the channel region between the source region and the drain region; The insulating dielectric layer is located on a side of the buried oxide layer close to the top semiconductor layer; The ratio of the thickness of the insulating dielectric layer to the thickness of the top semiconductor layer is in the range of 0.2-0.25; and / or The width of the insulating dielectric layer is greater than the width of the channel region, and the ratio of the distance between the first end of the insulating dielectric layer and the first end of the channel region to the width of the channel region is 5%-15%; and / or the ratio of the distance between the second end of the insulating dielectric layer and the second end of the channel region to the width of the channel region is 5%-15%.

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