Array substrate and display device

Abstract

An array substrate according to one embodiment includes: a semiconductor layer; a signal line in contact with the semiconductor layer; a relay electrode separated from the signal line and in contact with the semiconductor layer; a first insulating layer covering the signal line and the relay electrode; and a gate electrode disposed above the first insulating layer and facing the semiconductor layer. The semiconductor layer has an opening located between the signal line and the relay electrode in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2021-074264, filed on April 26, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to an array substrate and a display device. Background Art

[0004] Display devices such as electrophoretic displays and liquid crystal displays include array substrates with thin-film transistors (TFTs). Multiple TFTs are sometimes arranged in close proximity within the array substrate. If the insulating layer between two conductive layers arranged above the semiconductor layer becomes locally thinner due to steps created by the semiconductor layers of each TFT, dielectric breakdown may occur. Summary of the Invention

[0005] An array substrate according to one embodiment includes: a semiconductor layer; a signal line in contact with the semiconductor layer; a relay electrode separated from the signal line and in contact with the semiconductor layer; a first insulating layer covering the signal line and the relay electrode; and a gate electrode disposed above the first insulating layer and facing the semiconductor layer. The semiconductor layer has an opening located between the signal line and the relay electrode in a plan view.

[0006] A display device according to one embodiment includes: the array substrate; an opposing substrate facing the array substrate; and a display function layer disposed between the array substrate and the opposing substrate.

[0007] According to these structures, it is possible to provide an array substrate with excellent reliability and a display device including the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a plan view showing the structure of the display device according to the first embodiment.

[0009] Figure 2 This is a schematic circuit diagram of the display device according to the first embodiment.

[0010] Figure 3 yes Figure 2 The equivalent circuit diagram applicable to the pixel shown.

[0011] Figure 4 It is a schematic cross-sectional view of a display panel included in the display device according to the first embodiment.

[0012] Figure 5This is a schematic plan view of main elements arranged on the array substrate according to the first embodiment.

[0013] Figure 6 It is an enlarged representation Figure 5 Schematic top view of the switching element in FIG.

[0014] Figure 7 yes Figure 6 Schematic top view of the semiconductor layer and scanning lines in FIG.

[0015] Figure 8 It is along Figure 7 A schematic cross-sectional view of the array substrate along line VIII-VIII in FIG.

[0016] Figure 9 It is along Figure 7 A schematic cross-sectional view of the array substrate along line IX-IX in FIG.

[0017] Figure 10 It is a schematic plan view of a switching element according to a comparative example.

[0018] Figure 11 is a schematic cross-sectional view of an array substrate according to a comparative example.

[0019] Figure 12 It is a schematic plan view of a switching element according to a second embodiment. DETAILED DESCRIPTION

[0020] Several embodiments will be described with reference to the accompanying drawings.

[0021] In addition, the disclosure is only an example, and for those skilled in the art, embodiments that can be easily conceived by appropriately changing the main idea of ​​the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings are sometimes schematically shown compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In each figure, for the same or similar elements arranged in a row, the figure marks are sometimes omitted. In addition, in this specification and each figure, the same reference figure marks are marked for the components that perform the same or similar functions as the components described in the figures that have appeared, and repeated detailed descriptions are sometimes omitted.

[0022] In each embodiment, an electrophoretic display device and an array substrate for the display device are disclosed as an example. However, each embodiment does not prevent the application of the various technical concepts disclosed in each embodiment to other types of display devices. Examples of other types of display devices include liquid crystal display devices with a liquid crystal layer, organic EL display devices with a light-emitting layer configured in each pixel, and LED display devices with a small LED configured in each pixel. In addition, the array substrate disclosed in each embodiment can also be applied to various electronic devices that do not have a display function.

[0023] When the structure disclosed in each embodiment is applied to a liquid crystal display device, the display device may also be a so-called polymer dispersed liquid crystal (PDLC) liquid crystal display device. This liquid crystal display device displays images by switching the liquid crystal layer of each pixel between a scattering state that scatters light and a transmissive state that transmits light. This polymer dispersed liquid crystal (PDLC) liquid crystal display device is used as a transparent display. When viewed from the image display surface (panel surface), the background on the back side of the panel is transparent, and similarly, when viewed from the back side of the panel, the background on the image display surface is transparent.

[0024] [First embodiment]

[0025] Figure 1 FIG. 1 is a top view showing the structure of the display device DSP according to the first embodiment. Figure 1 As shown, a first direction X, a second direction Y, and a third direction Z are defined. In this embodiment, the first direction X, the second direction Y, and the third direction Z are mutually orthogonal. However, the first direction X, the second direction Y, and the third direction Z may intersect at angles other than 90 degrees. The first direction X and the second direction Y are parallel to the main surfaces of each substrate included in the display device DSP. The third direction Z corresponds to the thickness direction of each element included in the display device DSP.

[0026] In the following description, when referring to "a second component above a first component" or "a second component below a first component," the second component may be in contact with or separated from the first component. In the latter case, another component may be sandwiched between the first and second components. Furthermore, viewing the display device DSP and its components parallel to the third direction Z is referred to as a top view.

[0027] The display device DSP includes an active matrix display panel PNL, a wiring substrate CB, and a controller CTL. The display panel PNL includes an array substrate AR and a counter substrate CT facing the array substrate AR in the third direction Z. Figure 1In the example, the array substrate AR and the counter substrate CT are rectangular in shape with short sides parallel to the first direction X and long sides parallel to the second direction Y. However, the shapes of the array substrate AR and the counter substrate CT are not limited to this example.

[0028] The display panel PNL includes a display area DA for displaying images and a peripheral area SA surrounding the display area DA. In this embodiment, the peripheral area SA has a frame shape. Furthermore, the display panel PNL includes gate drivers GD1 and GD2 and a source driver SD. The gate drivers GD1 and GD2 supply scanning signals to the scanning lines described below. The source driver SD supplies image signals to the signal lines described below.

[0029] The wiring substrate CB is connected to the array substrate AR. The controller CTL, for example, is an IC chip and is mounted on the wiring substrate CB. The controller CTL supplies drive signals to the gate drivers GD1 and GD2 and the source driver SD via the wiring substrate CB. The controller CTL can also be mounted elsewhere, such as on the array substrate AR.

[0030] Figure 2 This is a schematic circuit diagram of the display device DSP. Figure 3 yes Figure 2 The equivalent circuit diagram applicable to the pixel PX shown in FIG. Figure 2 and Figure 3 As shown, the display panel PNL includes a first substrate 1, a plurality of pixels PX, a plurality of scan lines G, a plurality of signal lines S, a plurality of capacitor lines CW, and a common electrode CE. The plurality of pixels PX are arranged in a matrix in the display area DA. The plurality of pixels PX, the plurality of scan lines G, the plurality of signal lines S, and the plurality of capacitor lines CW are disposed above the first substrate 1.

[0031] A plurality of scan lines G extend in a first direction X and are arranged in a second direction Y. Each scan line G is connected to one of gate drivers GD1 and GD2 and is connected to a plurality of pixels PX arranged in the first direction X. A plurality of signal lines S extend in a second direction Y and are arranged in the first direction X. Each signal line S is connected to a source driver SD and is connected to a plurality of pixels PX arranged in the second direction Y. A plurality of capacitor wires CW extend in the second direction Y and are arranged in the first direction X. Each capacitor wire CW is connected to a controller CTL and is connected to a plurality of pixels PX arranged in the second direction Y.

[0032] Gate drivers GD1 and GD2 supply scanning signals SG to scanning lines G. Controller CTL supplies image signals (or video signals) Vsig to source drivers SD. Source drivers SD then supply image signals Vsig to corresponding signal lines S. Controller CTL supplies voltage Vpc to capacitor lines CW. Furthermore, controller CTL supplies common voltage Vcom to common electrodes CE. For example, voltage Vpc and common voltage Vcom have the same potential.

[0033] like Figure 3 As shown, each pixel PX includes a switching element SW, a first capacitor C1, a second capacitor C2, and a pixel electrode PE. In this embodiment, the switching element SW includes a first transistor Tr1 and a second transistor Tr2.

[0034] The first transistor Tr1 and the second transistor Tr2 are composed of thin film transistors (TFTs) of the same conductivity type, for example, P-channel types. The semiconductor layers of the first transistor Tr1 and the second transistor Tr2 are each formed of an oxide semiconductor. In addition, as the semiconductor layer, a semiconductor other than an oxide semiconductor such as polycrystalline silicon or amorphous silicon, such as low-temperature polysilicon, may also be used. In addition, the first transistor Tr1 and the second transistor Tr2 may be composed of N-channel TFTs.

[0035] The first transistor Tr1 and the second transistor Tr2 are both thin-film transistors (TFTs) having a first electrode E1, a second electrode E2, and a gate electrode GE. One of the first electrode E1 and the second electrode E2 functions as a source electrode, and the other functions as a drain electrode. The first transistor Tr1 and the second transistor Tr2 are connected in parallel between a signal line S and a pixel electrode PE.

[0036] In each of the first transistor Tr1 and the second transistor Tr2, a first electrode E1 is connected to a signal line S, a second electrode E2 is connected to a pixel electrode PE, and a gate electrode GE is connected to a scan line G. Thus, the first transistor Tr1 and the second transistor Tr2 are each switched between a conductive state and a non-conductive state by a scan signal SG supplied to the scan line G. An image signal Vsig is supplied to the pixel electrode PE via the signal line S and the conductive transistors Tr1 and Tr2.

[0037] The first capacitor C1 is connected to the pixel electrode PE and the capacitor wiring CW, and the second capacitor C2 is connected to the pixel electrode PE and the common electrode CE.

[0038] Figure 4 FIG. 1 is a schematic cross-sectional view of the display panel PNL. Here, we focus on one pixel PX. Figure 4As shown, the array substrate AR includes a first substrate 1 and a pixel electrode PE disposed on the first substrate 1. The counter substrate CT includes a second substrate 2 and a common electrode CE opposing the pixel electrode PE. For example, the common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0039] The first substrate 1 and the second substrate 2 are formed of insulating materials such as plastic or glass. In this embodiment, the second substrate 2 is located on the screen side (observation side) and is light-transmissive. The first substrate 1 is located on the opposite side of the screen and can be opaque or transparent.

[0040] The display panel PNL includes a display function layer DL disposed between the array substrate AR and the counter substrate CT. A voltage applied between the pixel electrode PE and the common electrode CE acts on the display function layer DL. In this embodiment, the display function layer DL is an electrophoretic layer comprising a plurality of microcapsules 30 arranged almost seamlessly in the XY plane.

[0041] The microcapsules 30 are spherical particles with a particle size of, for example, approximately 20 μm to 70 μm. In the illustrated example, a plurality of microcapsules 30 are disposed between a single pixel electrode PE and a common electrode CE. However, the number of microcapsules 30 disposed between a single pixel electrode PE and a common electrode CE may be smaller than in the illustrated example.

[0042] Microcapsule 30 includes a dispersion medium 31, a plurality of black particles 32, a plurality of white particles 33, and a shell 34. Black particles 32 and white particles 33 are sometimes referred to as electrophoretic particles. Shell 34 is formed using a transparent resin such as acrylic resin. Dispersion medium 31 is a liquid that disperses black particles 32 and white particles 33 within microcapsule 30.

[0043] Black particles 32 are particles (polymers or colloids) composed of a black pigment such as aniline black, for example, and are positively charged in one example. White particles 33 are particles (polymers or colloids) composed of a white pigment such as titanium dioxide, for example, and are negatively charged in one example. Various additives may be added to these pigments as needed. Alternatively, pigments such as red, green, blue, yellow, cyan, and magenta may be used in place of black particles 32 and white particles 33.

[0044] In the display function layer DL of the above structure, when the pixel PX is displayed in black, the pixel electrode PE is maintained at a relatively higher potential than the common electrode CE. That is, when the potential of the common electrode CE is used as the reference potential, the pixel electrode PE is maintained at a positive polarity. As a result, the positively charged black particles 32 are attracted to the common electrode CE, while the negatively charged white particles 33 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed from the common electrode CE side, black is visually confirmed. On the other hand, when the pixel PX is displayed in white, when the potential of the common electrode CE is used as the reference potential, the pixel electrode PE is maintained at a negative polarity. As a result, the negatively charged white particles 33 are attracted to the common electrode CE side, while the positively charged black particles 32 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed, white is seen.

[0045] Figure 5 This is a schematic top view of the main elements configured on the array substrate AR. This figure shows a pixel PX and its surrounding structure. As described above, the scan line G extends in the first direction X. The signal line S extends in the second direction Y and intersects the scan line G.

[0046] The pixel electrode PE includes a first pixel electrode PE1 and a second pixel electrode PE2 that are electrically connected to each other. Figure 5 In the example shown in FIG, the second pixel electrode PE2 is disposed in a region surrounded by two scanning lines G and two signal lines S. Most of the first pixel electrode PE1 is also located in this region, but a portion thereof overlaps with the scanning line G at the bottom of the figure.

[0047] The switching element SW is disposed at the intersection of the scan line G and the signal line S. The switching element SW includes a semiconductor layer SC. A first electrode E1 and a second electrode E2 are in contact with the semiconductor layer SC. For example, the first electrode E1 may be referred to as a source electrode, and the second electrode E2 may be referred to as a drain electrode. In this embodiment, the first electrode E1 is part of the signal line S. The second electrode E2 is separated from the signal line S in the first direction X and extends in the second direction Y. A portion of the second electrode E2 overlaps with the second pixel electrode PE2.

[0048] The semiconductor layer SC overlaps with the first gate electrode GE1 and the second gate electrode GE2. The first gate electrode GE1 and the second gate electrode GE2 constitute Figure 3 The semiconductor layer SC is located between the first gate electrode GE1 and the second gate electrode GE2 in the third direction Z. In this embodiment, the first gate electrode GE1 is a part of the scanning line G.

[0049] The first relay electrode RE1 is arranged near the second gate electrode GE2. The first relay electrode RE1 is connected to the scanning line G through the contact hole CH1. The second gate electrode GE2 is connected to the first relay electrode RE1 through the contact hole CH2.

[0050] A capacitor electrode OE is disposed on the pixel PX. The capacitor electrode OE overlaps the first pixel electrode PE1 and the second pixel electrode PE2. In this embodiment, the entire capacitor electrode OE is located inside the outer contours of the first pixel electrode PE1 and the second pixel electrode PE2 in a plan view.

[0051] The capacitor electrodes OE arranged in adjacent pixels PX in the second direction Y are connected by a connection wiring NW. The connection wiring NW extends in a long strip along the second direction Y and intersects the scanning line G. The plurality of connection wirings NW and the plurality of capacitor electrodes OE arranged in the second direction Y form a Figure 3 Capacitor wiring CW is shown.

[0052] The second electrode E2 is connected to the second pixel electrode PE2 via a contact hole CH3. In the third direction Z, a second relay electrode RE2 is disposed between the second electrode E2 and the first pixel electrode PE1. The second relay electrode RE2 is connected to the second electrode E2 via a contact hole CH4. The second relay electrode RE2 is connected to the first pixel electrode PE1 via a contact hole CH5. Thus, the second electrode E2, the second relay electrode RE2, the first pixel electrode PE1, and the second pixel electrode PE2 are electrically connected.

[0053] The scan line G and the second pixel electrode PE2 are formed of the same material and in the same layer. The signal line S, the second electrode E2, the first relay electrode RE1, and the capacitor electrode OE are formed of the same material and in the same layer. The second gate electrode GE2, the second relay electrode RE2, and the connection wiring NW are formed of the same material and in the same layer.

[0054] For example, the scan line G, the second pixel electrode PE2, the signal line S, the second electrode E2, the first relay electrode RE1, the second relay electrode RE2, the capacitor electrode OE, the connection wiring NW, and the second gate electrode GE2 are formed of a metal material such as Al (aluminum), Ti (titanium), Ag (silver), Mo (molybdenum), W (tungsten), Cu (copper), Cr (chromium), or an alloy combining these metal materials. These elements such as the scan line G may have a single-layer structure of a metal material or alloy or a multi-layer structure.

[0055] The first pixel electrode PE1 is composed of, for example, a transparent conductive layer, a light reflecting layer, or a laminate of a transparent conductive layer and a light reflecting layer. Like the common electrode CE, the transparent conductive layer can be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0056] Figure 6 It will Figure 5 A schematic top view showing an enlarged view of the switching element SW in FIG. Figure 7 FIG is a schematic top view of the semiconductor layer SC and the scanning line G. Figure 6 In FIG, the second gate electrode GE2 is indicated by a dotted line.

[0057] exist Figure 6 and Figure 7 In the example shown, the semiconductor layer SC has a rectangular shape having a first side S1, a second side S2, a third side S3, and a fourth side S4. The first side S1 and the second side S2 are long sides parallel to the second direction Y, and the third side S3 and the fourth side S4 are short sides parallel to the first direction X. However, the shape of the semiconductor layer SC is not limited to a rectangle.

[0058] In this embodiment, the semiconductor layer SC has an opening AP at the center. The opening AP is located between the signal line S (first electrode E1) and the second electrode E2 in the first direction X. Figure 6 and Figure 7 In the example shown in FIG, the opening AP is in a rectangular shape that is long in the first direction X. However, the opening AP may also be in a circular or elliptical shape.

[0059] The scanning line G (first gate electrode GE1) has a protrusion PT protruding toward the third side S3 at a position overlapping with the semiconductor layer SC. Figure 6 In the example shown in FIG. 1 , the protrusion PT protrudes upward in the figure relative to the third side S3. By providing such a protrusion PT, most of the semiconductor layer SC overlaps with the scanning line G. The opening AP also overlaps with the scanning line G.

[0060] However, the scanning line G (first gate electrode GE1) only needs to overlap with the semiconductor layer SC, in particular the channel region (the first channel region CR1 and the second channel region CR2 described later), and the opening AP and the scanning line G (first gate electrode GE1) may be configured so as not to overlap. In the case of a configuration in which the opening AP and the scanning line G (first gate electrode GE1) do not overlap, for example, the scanning line G (first gate electrode GE1) may have an opening that overlaps with the opening AP.

[0061] The second gate electrode GE2 has a widened portion WP at a position overlapping with the semiconductor layer SC. The widened portion WP is, for example, Figure 6 It is shown as a rectangular shape, overlapping most of the semiconductor layer SC. Figure 6 In the example, the widened portion WP protrudes upward in the figure relative to the third side S3. Furthermore, the widened portion WP protrudes downward in the figure relative to the fourth side S4. The opening AP also overlaps with the widened portion WP.

[0062] However, the widened portion WP only needs to overlap with the semiconductor layer SC, particularly the channel region (the first channel region CR1 and the second channel region CR2 described later), and the opening AP and the widened portion WP may not overlap. In the case of a structure in which the opening AP and the widened portion WP do not overlap, for example, the widened portion WP may have an opening that overlaps with the opening AP.

[0063] As described above, the first gate electrode GE1 and the second gate electrode GE2 only need to overlap with the channel region of the semiconductor layer SC (the first channel region CR1 and the second channel region CR2 described later), and either or both of the first gate electrode GE1 and the second gate electrode GE2 may also have a structure having an opening in the region overlapping with the opening AP of the semiconductor layer SC.

[0064] The advantages of the structure in which the first gate electrode GE1 and the second gate electrode GE2 overlap with the opening AP of the semiconductor layer SC include: being able to suppress light leakage and shift of the threshold voltage Vth caused by light from an external light source entering the semiconductor layer SC, thereby further improving the display quality.

[0065] On the other hand, advantages of a structure in which the first gate electrode GE1 and the second gate electrode GE2 do not overlap with the opening AP of the semiconductor layer SC include the ability to reduce parasitic capacitance of the transistors Tr1 and Tr2, increase panel size, increase frame rate, and reduce power consumption. Furthermore, when the structure of this embodiment is applied to the aforementioned transparent display, by providing openings in the first gate electrode GE1 and the second gate electrode GE2 in regions that overlap with the opening AP of the semiconductor layer SC, the transparency of the transparent display can be further improved.

[0066] In at least one or both of the first gate electrode GE1 and the second gate electrode GE2 , whether or not an opening is provided in a region overlapping with the opening AP of the semiconductor layer SC can be determined according to the specifications of the display device.

[0067] Figure 7 1 shows the shapes of the first opening EAP1 and the second opening EAP2 of the insulating layer 12, described later. Both the first opening EAP1 and the second opening EAP2 have an elongated shape in the second direction Y. The first opening EAP1 overlaps with the end of the semiconductor layer SC including the first side S1. The second opening EAP2 overlaps with the end of the semiconductor layer SC including the second side S2. The opening AP is located between the first opening EAP1 and the second opening EAP2 in the first direction X.

[0068] The semiconductor layer SC has a first region R1 (source region) in contact with the signal line S and a second region R2 (drain region) in contact with the second electrode E2. Figure 7 In the embodiment, the first region R1 and the second region R2 are provided with oblique lines. For example, the first region R1 and the second region R2 have a stripe shape extending between the third side S3 and the fourth side S4.

[0069] The semiconductor layer SC further includes a first channel region CR1 and a second channel region CR2 arranged in the second direction Y. The first channel region CR1 is located between the first region R1 and the second region R2 in the first direction X, and between the opening AP and the third side S3 in the second direction Y. The second channel region CR2 is located between the first region R1 and the second region R2 in the first direction X, and between the opening AP and the fourth side S4 in the second direction Y. Both the first channel region CR1 and the second channel region CR2 entirely overlap with the scan line G and the second gate electrode GE2.

[0070] The first channel region CR1, the scan line G, the second gate electrode GE2, the signal line S and a portion of the second electrode E2 together form a first transistor Tr1. The second channel region CR2, the scan line G, the second gate electrode GE2, the signal line S and another portion of the second electrode E2 together form a second transistor Tr2.

[0071] The first channel region CR1 has a first channel width W1 in the second direction Y. The second channel region CR2 has a second channel width W2 in the second direction Y. The first channel width W1 and the second channel width W2 are, for example, the same.

[0072] The opening AP is located between the first region R1 and the second region R2 in the first direction X. In the second direction Y, the opening AP is located between the first channel region CR1 and the second channel region CR2.

[0073] The opening AP has a width Wx in the first direction X. Figure 7 In the example, the width Wx is greater than the distance D1 between the opening AP and the first region R1 in the first direction X (Wx>D1). In addition, the width Wx is greater than the distance D2 between the opening AP and the second region R2 in the first direction X (Wx>D2). The distances D1 and D2 are, for example, the same.

[0074] The opening AP has a width Wy in the second direction Y. Figure 7 In the example, the width Wy is sufficiently smaller than the first channel width W1 and the second channel width W2 (Wy <W1,W2)。

[0075] Figure 8 It is along Figure 7A schematic cross-sectional view of the array substrate AR taken along line VIII-VIII in FIG. Figure 9 It is along Figure 7 The array substrate AR is a schematic cross-sectional view of the array substrate AR along the line IX-IX. The array substrate AR includes the first base material 1, Figures 5 to 7 In addition to the elements shown, the present invention further includes insulating layers 11, 12, 13, and 14. In this embodiment, the insulating layer 13 is an example of a first insulating layer, and the insulating layer 12 is an example of a second insulating layer.

[0076] The scanning line G is disposed on the first substrate 1 . The insulating layer 11 covers the scanning line G. The semiconductor layer SC is disposed on the insulating layer 11 . The insulating layer 12 covers the semiconductor layer SC and the insulating layer 11 .

[0077] The signal line S and the second electrode E2 are disposed on the insulating layer 12. The insulating layer 12 has the first opening EAP1 and the second opening EAP2. The signal line S contacts the first region R1 of the semiconductor layer SC through the first opening EAP1. The second electrode E2 contacts the second region R2 of the semiconductor layer SC through the second opening EAP2.

[0078] The insulating layer 13 covers the signal line S, the second electrode E2, and the insulating layer 12. The second gate electrode GE2 is arranged on the insulating layer 13. The insulating layer 14 covers the second gate electrode GE2 and the insulating layer 13.

[0079] The first pixel electrode PE1 is disposed on the insulating layer 14. The first pixel electrode PE1 overlaps with the opening AP in the third direction Z. Figure 8 The first pixel electrode PE1 shown is not Figure 8 The electrodes of the pixels PX shown in FIG. 1 and FIG. 2 are not electrodes of the pixels PX including the semiconductor layer SC, but electrodes of the adjacent pixels PX (see FIG. 2 and FIG. 3 ). Figure 5 ).exist Figure 8 Although the layer above the first pixel electrode PE1 is not shown in the figure, the first pixel electrode PE1 may be covered by an insulating layer.

[0080] Insulating layers 11, 12, and 13 are formed from inorganic insulating materials such as silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Each of insulating layers 11, 12, and 13 can have a single-layer structure or a stacked structure. Insulating layer 14 is formed from an organic insulating material such as acrylic resin. Insulating layer 14 functions as a planarizing layer to smooth out unevenness caused by switching element SW and the like.

[0081] in addition, Figure 5 The contact holes CH1 and CH3 are provided in the insulating layers 11 and 12 , the contact holes CH2 and CH4 are provided in the insulating layer 13 , and the contact hole CH5 is provided in the insulating layer 14 .

[0082] The insulating layer 12 is formed in the area except the first opening EAP1 and the second opening EAP2. Figure 7 The first channel region CR1 and the second channel region CR2 are shown. Figure 8 In the example shown in FIG5 , the insulating layer 12 overlaps with the opening AP of the semiconductor layer SC in the third direction Z. Specifically, the insulating layer 12 fills the inside of the opening AP. Figure 9 The cross section of the array substrate AR in the second region R2 is equivalent to the first opening EAP1, so the cross section does not include the insulating layer 12. Figure 9 The cross-sectional structure in the first region R1 shown is the same.

[0083] When forming the semiconductor layer SC, the signal line S, and the second electrode E2, the semiconductor layer SC is first formed on the insulating layer 11. A conductive layer serving as the base of the signal line S and the second electrode E2 is then formed thereon. This conductive layer is then patterned, for example, by dry etching, to form the signal line S and the second electrode E2 in predetermined shapes.

[0084] During this patterning, the insulating layer 12 protects the channel regions CR1 and CR2 of the semiconductor layer SC. Specifically, if the insulating layer 12 were not present, the channel regions CR1 and CR2 would be damaged by etching during the formation of the signal line S and the second electrode E2, potentially adversely affecting the characteristics of the transistors Tr1 and Tr2. In contrast, if the insulating layer 12 having the first opening EAP1 and the second opening EAP2 is formed on the semiconductor layer SC, as in this embodiment, and the signal line S and the second electrode E2 are in contact with the semiconductor layer SC through these openings EAP1 and EAP2, the insulating layer 12 can protect the channel regions CR1 and CR2 from the etching.

[0085] Figure 8 and Figure 9 The thickness of each element shown is not particularly limited. As an example, the thickness of the first substrate 1 is 0.5 mm, the thickness of the scanning line G is 400 nm, the thickness of the insulating layer 11 is 500 nm, the thickness of the semiconductor layer SC is 70 nm, the thickness of the signal line S and the second electrode E2 is 600 nm, the thickness of the insulating layer 13 is 300 nm, the thickness of the second gate electrode GE2 is 150 nm, the thickness of the insulating layer 14 is 3000 nm, and the thickness of the first pixel electrode PE1 is 50 nm.

[0086] Next, an example of the effects achieved by this embodiment will be described.

[0087] Figure 101 is a schematic top view of a switching element SWex according to a comparative example. The switching element SWex includes two semiconductor layers SC1 and SC2 arranged in a second direction Y. A gap GP is formed between the semiconductor layers SC1 and SC2. The semiconductor layer SC1 forms a first transistor Tr1, and the semiconductor layer SC2 forms a second transistor Tr2.

[0088] Figure 11 It is along Figure 10 Schematic cross-sectional view of the array substrate ARex according to the comparative example taken along line XI-XI in FIG. In this comparative example, since a gap GP exists between the semiconductor layers SC1 and SC2 , the signal line S (first electrode E1 ), the insulating layer 13 , and the second gate electrode GE2 are recessed according to the shape of the gap GP.

[0089] When such a recess occurs, the thickness of insulating layer 13 becomes non-constant. Specifically, the thickness t2 of the portion of insulating layer 13 located above the end portions (tapered portions) of semiconductor layers SC1 and SC2 may be lower than the thickness t1 of the portion of insulating layer 13 located above the flat surfaces of semiconductor layers SC1 and SC2 (t1 > t2). In particular, above gap GP, where insulating layer 13 and other layers deform in complex patterns, the thicknesses t1 and t2 are likely to differ.

[0090] In areas where the thickness of the insulating layer 13 is reduced, the dielectric breakdown voltage between the signal line S and the second gate electrode GE2 is lower than in other areas, posing a risk of dielectric breakdown. If dielectric breakdown occurs, the signal line S and the second gate electrode GE2 become conductive, resulting in display failure. The risk of dielectric breakdown also arises between the second electrode E2 and the second gate electrode GE2.

[0091] In contrast, in this embodiment, Figure 9 As shown, below the signal line S and the second gate electrode GE2, the semiconductor layer SC does not have a structure equivalent to the gap GP. Similarly, below the second electrode E2 and the second gate electrode GE2, the semiconductor layer SC does not have a structure equivalent to the gap GP. That is, the semiconductor layer SC has Figure 10 The semiconductor layers SC1 and SC2 are shown in a shape where both ends in the first direction X are connected. With this structure, thin portions are unlikely to form in the insulating layer 13 between the signal line S and the second gate electrode GE2, and between the second electrode E2 and the second gate electrode GE2. As a result, the risk of insulation breakdown can be reduced, and the reliability of the array substrate AR and the display device DSP can be improved.

[0092] like Figure 7 As shown in FIG, the opening AP is located between the first region R1 and the second region R2. More specifically, as shown in FIG. Figure 6As shown, the aperture AP is located between the signal line S and the second electrode E2. In this structure, the signal line S and the second electrode E2 are not present in the portion of the insulating layer 13 where the aperture AP creates a step. Therefore, dielectric breakdown of the insulating layer 13 caused by the aperture AP can be suppressed.

[0093] Furthermore, it is assumed that a transistor with a large channel width is formed without providing an opening AP in the semiconductor layer SC. In this case, a large current easily flows through the semiconductor layer SC. If the current becomes too large, the semiconductor layer SC may be damaged. In contrast, when the opening AP is provided in the semiconductor layer SC as in the present embodiment, two channel regions CR1 and CR2 with a small channel width are formed in the semiconductor layer SC. With this structure, it is difficult for a large current to flow through the semiconductor layer SC, and as a result, damage to the semiconductor layer SC can be suppressed. Furthermore, from the perspective of promoting heat dissipation of the semiconductor layer SC, it is preferable to form two channel regions CR1 and CR2 with a small channel width in the semiconductor layer SC, compared to the case of using a single transistor with a large channel width.

[0094] In addition to the above, various preferable effects can be obtained according to this embodiment.

[0095] [Second embodiment]

[0096] The structures of the array substrate AR and the display device DSP not specifically mentioned in this embodiment are the same as those in the first embodiment.

[0097] Figure 12 This is a schematic plan view of a switching element SW according to the second embodiment. In the example shown in this figure, the semiconductor layer SC has two openings AP (AP1, AP2). These openings AP1, AP2 have, for example, the same shape and are arranged in the second direction Y at intervals.

[0098] exist Figure 12 In the example shown in FIG. 1 , the switch element SW includes a first transistor Tr1 including a first channel region CR1 between the third side S3 and the opening AP1; a second transistor Tr2 including a second channel region CR2 between the openings AP1 and AP2; and a third transistor Tr3 including a third channel region CR3 between the opening AP2 and the fourth side S4. These transistors Tr1, Tr2, and Tr3 are connected in parallel.

[0099] The number of openings AP included in the semiconductor layer SC is not limited to two, and may be three or more. Even when the semiconductor layer SC includes a plurality of openings AP as in this embodiment, the same effects as those of the first embodiment can be obtained.

[0100] Based on the display device and array substrate described above as embodiments of the present invention, all display devices and array substrates that can be implemented by those skilled in the art after appropriate design changes fall within the scope of the present invention as long as they include the gist of the present invention.

[0101] Within the scope of the present invention, those skilled in the art will be able to conceive of various variations, which should be interpreted as also falling within the scope of the present invention. For example, with respect to the above-mentioned embodiments, embodiments resulting from the addition, deletion, or design modification of structural elements, or embodiments resulting from the addition, omission, or condition modification of processes as appropriate by those skilled in the art are also within the scope of the present invention as long as they retain the gist of the present invention.

[0102] Furthermore, regarding other effects brought about by the methods described in the above embodiments, the contents that are clear from the description of this specification or the contents that can be appropriately imagined by those skilled in the art should naturally be interpreted as being brought about by the present invention.

Claims

1. An array substrate comprising: semiconductor layer; a first electrode in contact with the semiconductor layer; a second electrode, separated from the first electrode and in contact with the semiconductor layer; a first insulating layer, covering the first electrode and the second electrode; a gate electrode, disposed above the first insulating layer and facing the semiconductor layer; as well as a second insulating layer, which is disposed below the first insulating layer and covers the semiconductor layer; The semiconductor layer has an opening located between the first electrode and the second electrode in a plan view, The second insulating layer has a first opening overlapping with one end of the semiconductor layer and a second opening overlapping with the other end of the semiconductor layer. The first electrode contacts the semiconductor layer through the first opening and covers the upper surface and side surfaces of the one end portion of the semiconductor layer. The second electrode contacts the semiconductor layer through the second opening and covers the upper surface and side surfaces of the other end portion of the semiconductor layer.

2. The array substrate according to claim 1, It also includes a scanning line, which is located below the semiconductor layer and connected to the gate electrode. The semiconductor layer overlaps with the gate electrode and the scan line.

3. The array substrate according to claim 1, The gate electrode overlaps with the opening.

4. The array substrate according to claim 1, The first electrodes and the second electrodes are arranged in a first direction, The semiconductor layer includes: a first region in contact with the first electrode; a second region in contact with the second electrode; as well as a first channel region and a second channel region, located between the first region and the second region in the first direction and arranged in a second direction intersecting the first direction; The opening is located between the first channel region and the second channel region in the second direction.

5. The array substrate according to claim 4, A width of the opening in the first direction is greater than a distance between the opening and the first region in the first direction.

6. The array substrate according to claim 4, A width of the opening in the first direction is greater than a distance between the opening and the second region in the first direction.

7. The array substrate according to claim 4, A width of the opening in the second direction is smaller than a width of the first channel region or the second channel region in the second direction.

8. The array substrate according to claim 4, The semiconductor layer has a plurality of the openings arranged in the second direction.

9. The array substrate according to claim 1, The opening of the semiconductor layer overlaps with the second insulating layer.

10. The array substrate according to claim 1, The semiconductor layer has a first channel region and a second channel region covered by the second insulating layer, The opening of the semiconductor layer is located between the first channel region and the second channel region in a plan view.

11. The array substrate according to claim 1, The opening of the semiconductor layer is located between the first opening and the second opening in a plan view.

12. The array substrate according to claim 1, The first electrodes and the second electrodes are arranged in a first direction, The semiconductor layer has an elongated shape in a second direction intersecting the first direction.

13. The array substrate according to claim 12, The opening has an elongated shape in the first direction.

14. A display device comprising: The array substrate according to claim 1; an opposing substrate opposing the array substrate; and A display function layer is arranged between the array substrate and the counter substrate.

15. The display device according to claim 14, The array substrate includes a pixel electrode connected to the second electrode. The counter substrate includes a common electrode facing the pixel electrode.

16. The display device according to claim 14, The display function layer is an electrophoretic layer.

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