Phase selection circuit for multiphase control circuit and multiphase control circuit

Abstract

The application discloses a phase selection circuit of a multiphase control circuit and the multiphase control circuit, which comprises an amplifier circuit, a comparator circuit, a clamping state control circuit and a clamping signal control circuit. The amplifier circuit is configured to generate a comparison signal. The comparator circuit is configured to generate a phase switching signal according to the comparison signal and a second reference voltage signal. The clamping state control circuit is configured to generate a clamping state control signal and provide the clamping state control signal to the clamping signal control circuit. The clamping signal control circuit is configured to clamp the voltage value of a clamping signal at a clamping reference voltage. By setting the clamping state control circuit and the clamping signal control circuit for the multiphase control circuit, the inductance current peak value of the multiphase control circuit is clamped when the phase switching is performed during the load switching of the multiphase control circuit, so that the problem that the output voltage signal oscillates during the light and heavy load switching of the multiphase circuit in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular, to a phase selection circuit of a multiphase control circuit and a multiphase control circuit. BACKGROUND

[0002] In the design of a multiphase control circuit, the number of phases to be enabled is usually determined according to the load. In a full-phase application scheme, as long as the external load does not exceed the maximum value, the main phase or the main phase and all auxiliary phases can be turned on for loop regulation. When the external load is switched from light load to heavy load, the control system is switched from the main phase to the main phase and all auxiliary phases to maintain stable output voltage. At the same time, in the full-phase application scheme, the number of phases is directly written into the phase selection module of the chip by I2C. When the maximum external load is a heavy load, the number of phases written is large, which can reach 6 phases or more. Under this condition, the system will experience a sharp energy accumulation or loss during the process of turning on only the main phase to all phases or turning on all phases to only the main phase, which is easy to make the output voltage oscillate in a large signal.

[0003] Therefore, the output voltage signal of the multiphase circuit in the prior art has the problem of oscillation during light load and heavy load switching. SUMMARY

[0004] The main purpose of the present application is to provide a phase selection circuit of a multiphase control circuit and a multiphase control circuit to solve the problem of oscillation of the output voltage signal of the multiphase circuit in the prior art during light load and heavy load switching, and to achieve the technical effect of avoiding large signal oscillation of the output voltage.

[0005] To achieve the above purpose, the first aspect of the present application provides a phase selection circuit of a multiphase control circuit, comprising: an amplifier circuit, a comparator circuit, a clamping state control circuit and a clamping signal control circuit,

[0006] The amplifier circuit is configured to generate a comparison signal according to a feedback voltage of the multiphase control circuit and a first reference voltage from a first reference voltage terminal, and provide the comparison signal to the comparator circuit, wherein the comparison signal is used to represent the peak value of the inductor current of the multiphase control circuit.

[0007] The comparator circuit is configured to generate a phase switching signal according to the comparison signal and a second reference voltage signal from a second reference voltage terminal, and provide the phase switching signal to the multiphase control circuit through the output terminal of the comparator circuit, wherein the phase switching signal is used to control the multiphase control circuit to perform phase addition or phase subtraction operation.

[0008] The clamping state control circuit is configured to generate a clamping state control signal according to the phase switching signal, and provide the clamping state control signal to the clamping signal control circuit.

[0009] The clamping signal control circuit is configured to clamp the voltage value of the comparison signal at a clamping reference voltage when the clamping state control signal is at an active level.

[0010] In an optional embodiment of the present application, the amplifier circuit comprises an error amplifier,

[0011] The first input terminal of the error amplifier is coupled to the first reference voltage terminal, and the output terminal of the error amplifier is coupled to a first node. The feedback voltage is provided to the second input terminal of the error amplifier.

[0012] In an optional embodiment of the present application, the comparator circuit comprises a hysteretic voltage comparator, a delay circuit, a first inverter and a second inverter,

[0013] The first input terminal of the hysteretic voltage comparator is coupled to the first node to receive the comparison signal, and the second input terminal of the hysteretic voltage comparator is coupled to the second reference voltage terminal. The output terminal of the hysteretic voltage comparator is coupled to the input terminal of the delay circuit.

[0014] The output terminal of the delay circuit is coupled to the input terminal of the first inverter, and the output terminal of the second inverter is coupled to the input terminal of the second inverter.

[0015] The delay circuit is configured to delay the output signal of the hysteretic voltage comparator and output the phase switching signal through the output terminal of the second inverter.

[0016] In an optional embodiment of the present application,

[0017] The phase switching signal is provided to a phase switching circuit of the multiphase control circuit. When the phase switching signal is at a first level, the multiphase control circuit is in a full-phase-on control mode. When the phase switching signal is at a second level, the multiphase control circuit is in a main-phase-on and auxiliary-phase-screening control mode.

[0018] In an optional embodiment of the present application,

[0019] The input terminal of the clamping state control circuit is coupled to the output terminal of the comparator circuit through a second node, and the phase switching signal is received by the input terminal of the clamping state control circuit through the second node.

[0020] In an optional embodiment of the present application, the clamping state control circuit comprises a monostable trigger, a third inverter and a fourth inverter,

[0021] The input end of the monostable trigger is coupled to the output end of the comparator circuit to receive the phase switching signal.

[0022] The output end of the monostable trigger is coupled to the input end of the third inverter, the output end of the third inverter is coupled to the input end of the fourth inverter, and the input end of the fourth inverter outputs the clamping state signal.

[0023] In an optional embodiment of the present application, the clamping signal control circuit comprises a first voltage-controlled switch and an operational amplifier,

[0024] The controlled end of the first voltage-controlled switch is coupled to the output end of the clamping state control circuit, the first end of the first voltage-controlled switch is coupled to a first node to receive the comparison signal, and the second end of the first voltage-controlled switch is coupled to the first input end of the operational amplifier and the output end of the operational amplifier.

[0025] The second input end of the operational amplifier is provided with the clamping reference voltage.

[0026] In an optional embodiment of the present application, the second reference voltage end comprises a first value end and a second value end,

[0027] When the second reference voltage end is in a first state, the first value end is turned on, the second input end of the comparator circuit is turned on with the first value end, and the second input end of the comparator circuit is provided with the first value of the second reference voltage signal.

[0028] When the second reference voltage end is in a second state, the second value end is turned on, the second input end of the comparator circuit is turned on with the second value end, and the second input end of the comparator circuit is provided with the second value of the second reference voltage signal.

[0029] In an optional embodiment of the present application, the first value end comprises a second voltage-controlled switch, the controlled end of the second voltage-controlled switch is coupled to the output end of the comparator circuit, and whether the first value end is turned on with the second input end of the comparator circuit is controlled according to the phase switching signal;

[0030] The second value end comprises a third voltage-controlled switch, the controlled end of the third voltage-controlled switch is coupled to the comparator circuit to receive the inverted signal of the phase switching signal, and whether the second value end is turned on with the second output end of the comparator circuit is controlled according to the inverted signal of the phase switching signal.

[0031] In a second aspect of the present application, a multi-phase control circuit is provided, comprising the phase selection circuit of the multi-phase control circuit.

[0032] The technical solutions provided by the embodiments of the present application can have the following beneficial effects.

[0033] In the present application, a phase selection circuit of a multi-phase control circuit is provided, comprising an amplifier circuit, a comparator circuit, a clamping state control circuit and a clamping signal control circuit. The amplifier circuit is configured to generate a comparison signal according to a feedback voltage of the multi-phase control circuit and a first reference voltage from a first reference voltage terminal, and provide the comparison signal to the comparator circuit. The comparator circuit is configured to generate a phase switching signal according to the comparison signal and a second reference voltage signal from a second reference voltage terminal, and provide the phase switching signal to the multi-phase control circuit through an output terminal of the comparator circuit. The clamping state control circuit is configured to generate a clamping state control signal according to the comparison signal and the phase switching signal, and provide the clamping state control signal to the clamping signal control circuit. The clamping signal control circuit is configured to clamp a voltage value of a clamping signal at a clamping reference voltage when the clamping state control signal is at an active level. By setting the clamping state control circuit and the clamping signal control circuit for the multi-phase control circuit, the peak value of the inductance current of the multi-phase control circuit is clamped when the phase switching is performed during the load switching of the multi-phase control circuit, so as to avoid the output voltage from having a severe overshoot or undershoot when the phase switching is performed, and solve the problem of oscillation of the output voltage signal during the light and heavy load switching of the multi-phase circuit in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which form a part of the present application, are used to provide further understanding of the present application, and make the other features, purposes and advantages of the present application more apparent. The illustrative embodiments of the present application and their description serve the purpose of explaining the present application. They do not limit the present application unduly. In the drawings:

[0035] Figure 1 An exemplary circuit for a phase selection circuit of a multi-phase control circuit;

[0036] Figure 2 An exemplary circuit for a phase selection circuit of a multi-phase control circuit; Figure 1 An exemplary circuit for a phase selection circuit of a multi-phase control circuit;

[0037] Figure 3 An exemplary circuit for a phase selection circuit of a multi-phase control circuit;

[0038] Figure 4 An exemplary circuit for a phase selection circuit of a multi-phase control circuit;

[0039] Figure 5 An exemplary circuit for a phase selection circuit of a multi-phase control circuit; Figure 4Part of signal timing diagram of middle circuit. DETAILED DESCRIPTION

[0040] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0042] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current direction between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor is opposite, in the embodiments of the present disclosure, the controlled middle end of the transistor is referred to as the gate, and the remaining two ends of the transistor are referred to as the first pole and the second pole, respectively. The transistor used in the embodiments of the present disclosure is mainly a switching transistor. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0043] In the design of a multiphase control circuit, the number of phases to be enabled is usually determined according to the degree of the applied load. In a full-phase application scheme, as long as the applied load does not exceed the defined maximum value, the main phase or the main phase and all auxiliary phases can be turned on for loop regulation. When the applied load is switched from light load to heavy load, the control system is switched from only the main phase to the main phase and all auxiliary phases to maintain a stable output voltage. When the applied maximum load is a heavy load, the number of phases to be written is large. Under this condition, the system will experience a sharp energy accumulation or loss in the process of switching from only the main phase to all phases or from all phases to only the main phase, which is extremely easy to make the output voltage oscillate in a large signal and become unstable.

[0044] Figure 1An exemplary circuit of a phase selection circuit for a multiphase control circuit is shown. The phase selection circuit comprises a hysteresis comparator COMP, a first inverter NG1 and a second inverter NG2.

[0045] In Figure 1 In an example, a first input of the hysteresis comparator COMP is coupled with an EAO signal terminal to receive an EAO signal, which is a signal obtained by error amplification processing of an output feedback voltage VFB of the multiphase control circuit and a first reference voltage VREF1 (a reference voltage of the output voltage). In a multiphase control circuit with peak current mode control, the signal EAO can represent a sampling of the inductor current peak in the multiphase control circuit, and thus represent the level of the load applied to the multiphase control circuit at the moment.

[0046] A non-inverting input of the hysteresis comparator COMP is coupled with the EAO signal terminal, and an inverting input of the hysteresis comparator COMP is coupled with a second reference voltage terminal VREF2. The second reference voltage terminal VREF2 provides a second reference voltage through the inverting input of the hysteresis comparator COMP. The second reference voltage terminal includes a first value VH and a second value VL of the second reference voltage. An output of the hysteresis comparator COMP is coupled with an input of the first inverter NG1. An output of the first inverter NG1 is coupled with an input of the second inverter NG2. An output of the first inverter NG1 is coupled with an output of the second inverter NG2. The output of the first inverter NG1 and the output of the second inverter NG2 are coupled with the inverting input of the hysteresis comparator COMP to control the inverting input of the hysteresis comparator COMP to receive the first value VH of the second reference voltage or the second value VL of the second reference voltage. An output of the second inverter NG2 outputs a comparison signal PHASE_SEL, which is output to a phase selection circuit of the multiphase control circuit to control the selection of a full phase on mode or a main phase on and auxiliary phase off mode.

[0047] Figure 2 For Figure 1 A partial signal timing diagram of the exemplary circuit is shown. In the diagram, a high level and a low level of the signal PHASE_SEL represent the control mode of the full phase on mode and the auxiliary phase off mode, respectively. Signals i L1-i Li represent the inductor currents of the first phase to the i-th phase, respectively. A signal VOUT represents the output voltage of the system.

[0048] When the maximum load is extremely heavy, the phase number value written by I2C is large, which can reach 6 phases or more than 6 phases. Under this condition, the system will temporarily accumulate too much energy in the process from only the main phase being turned on to all phases being turned on, causing a sharp overshoot of the output voltage. In a short time, the system will adjust the phase selection to only turn on the main phase on the premise of the output voltage overshoot, thereby causing a large amount of energy loss, resulting in a sharp undershoot of the output voltage, and the system will adjust the phase selection to all phases being turned on on the premise of the output undershoot, and so on, so that the system will oscillate with a large signal.

[0049] In an optional embodiment of the present application, a phase selection circuit of a multiphase control circuit is provided, Figure 3 A schematic diagram of the phase selection circuit of the multiphase control circuit provided in the embodiments of the present application is shown in Figure 3 The phase selection circuit of the multiphase control circuit includes an amplifier circuit 100, a comparator circuit 200, a clamping state control circuit 300, and a clamping signal control circuit 400.

[0050] The amplifier circuit 100 is configured to generate a comparison signal EAO according to a feedback voltage VFB of the multiphase control circuit and a first reference voltage VREF1 from a first reference voltage terminal, and provide the comparison signal EAO to the comparator circuit 200, wherein the comparison signal EAO is used to represent a peak value of an inductor current of the multiphase control circuit;

[0051] The comparator circuit 200 is configured to generate a phase switching signal PHASE_SEL according to the comparison signal EAO and a second reference voltage signal VREF2 from a second reference voltage terminal, and provide the phase switching signal PHASE_SEL to the multiphase control circuit through an output terminal of the comparator circuit 200, wherein the phase switching signal PHASE_SEL is used to control the multiphase control circuit to perform a phase addition or phase subtraction operation;

[0052] The clamping state control circuit 300 is configured to generate a clamping state control signal according to the phase switching signal PHASE_SEL, and provide the clamping state control signal to the clamping signal control circuit 400;

[0053] The clamping signal control circuit 400 is configured to clamp the voltage value of the comparison signal EAO at a clamping reference voltage when the clamping state control signal is at an active level.

[0054] In the embodiment of the present application, by setting the clamping state control circuit and the clamping state control circuit in the phase selection circuit, the clamping state control circuit controls the clamping of the comparison signal according to the phase switching signal output by the comparator circuit, clamps the voltage of the comparison signal to the clamping reference voltage, so as to limit the peak value of the inductor current when the phase switching is performed in the multi-phase control circuit, suppress the instantaneous energy accumulation when the phase is turned on, avoid the sharp overshoot of the output voltage, and further avoid the large signal oscillation of the output voltage.

[0055] In another optional embodiment of the present application, a phase selection circuit of a multi-phase control circuit is provided, Figure 4 A circuit diagram of the phase selection circuit of the multi-phase control circuit provided in the present application is shown in Figure 4 The phase selection circuit includes an amplifier circuit 100, a comparator circuit 200, a clamping state control circuit 300 and a clamping signal control circuit 400.

[0056] The amplifier circuit 100 includes an error amplifier EA, a first input terminal of the error amplifier EA is coupled to a first reference voltage terminal VREF1, and an output terminal of the error amplifier EA is coupled to a first node N1, wherein a feedback voltage is provided to a second input terminal of the error amplifier EA.

[0057] The comparator circuit includes a hysteresis voltage comparator COMP, a delay circuit Delay_P_ADD, a first inverter NG1 and a second inverter NG2, wherein a first input terminal of the hysteresis voltage comparator COMP is coupled to the first node N1 to receive the comparison signal EAO, a second input terminal of the hysteresis voltage comparator COMP is coupled to a second reference voltage terminal VREF2, the second reference voltage terminal VREF2 provides a second reference voltage, the second reference voltage includes a first value VH and a second value VL, and an output terminal of the hysteresis voltage comparator COMP is coupled to an input terminal of the delay circuit Delay_P_ADD; an output terminal of the delay circuit Delay_P_ADD is coupled to an input terminal of the first inverter NG1, an output terminal of the second inverter NG2 is coupled to an input terminal of the second inverter NG2; the delay circuit Delay_P_ADD is configured to delay the output signal of the hysteresis voltage comparator COMP and output a phase switching signal PHASE_SEL through the output terminal of the second inverter.

[0058] The second reference voltage terminal comprises a first value terminal VH and a second value terminal VL. When the second reference voltage terminal VREF2 is in a first state, the first value terminal VH is turned on, the second input terminal of the comparator circuit 200 is turned on with the first value terminal, and the second input terminal of the comparator circuit 200 is provided with the first value VH of the second reference voltage signal. When the second reference voltage terminal VREF2 is in a second state, the second value terminal VL is turned on, the second input terminal of the comparator circuit 200 is turned on with the second value terminal VL, and the second input terminal of the comparator circuit 200 is provided with the second value VL of the second reference voltage signal.

[0059] The first value terminal VH and the second value terminal VL are respectively coupled to the second input terminal of the comparator circuit 200 through voltage-controlled switches. The controlled end of the voltage-controlled switch of the first value terminal VH is coupled to the output terminal of the comparator circuit 200 and is controlled by the phase switching signal PHASE_SEL. The voltage-controlled switch of the second value terminal VL is coupled to the output terminal of the first inverter NG1 in the comparator circuit 200 and is controlled by the signal PHASE_SELB output by the first inverter NG1. The signal PHASE_SEL and the signal PHASE_SELB are in a state that when the signal PHASE_SEL is high, the signal PHASE_SELB is low.

[0060] The first value terminal VH comprises a second voltage-controlled switch S2, and the controlled end of the second voltage-controlled switch S2 is coupled to the comparator circuit 200 to receive the phase switching signal PHASE_SEL and the inverted phase switching signal PHASE_SELB. The second voltage-controlled switch S2 controls whether the first value terminal VH is turned on with the second input terminal of the comparator 200 according to the received phase switching signal PHASE_SEL and the inverted phase switching signal PHASE_SELB. The second value terminal VL comprises a third voltage-controlled switch S3, and the controlled end of the third voltage-controlled switch S3 is coupled to the comparator circuit 200 to receive the inverted phase switching signal PHASE_SELB and the phase switching signal PHASE_SEL. The third voltage-controlled switch S3 controls whether the second value terminal VL is turned on with the second input terminal of the comparator 200 according to the received inverted phase switching signal PHASE_SELB and the phase switching signal PHASE_SEL.

[0061] The phase switching signal PHASE_SEL is provided to the phase switching circuit of the multiphase control circuit. When the phase switching signal PHASE_SEL is in a first level, the multiphase control circuit is in a control mode of full-phase opening. When the phase switching signal PHASE_SEL is in a second level, the multiphase control circuit is in a control mode of main-phase opening and auxiliary-phase shielding.

[0062] The input terminal of the clamping state control circuit 300 is coupled with the output terminal of the comparator circuit 200 via the second node N2, and the input terminal of the clamping state control circuit 300 receives the phase switching signal PHASE_SEL via the second node N2.

[0063] The clamping state control circuit 300 comprises a monostable trigger ONE SHOT, a third inverter NG3 and a fourth inverter NG4, wherein the input terminal of the monostable trigger ONE SHOT is coupled with the output terminal of the comparator circuit 200 to receive the phase switching signal PHASE_SEL; the output terminal of the monostable trigger ONE SHOT is coupled with the input terminal of the third inverter NG3, the output terminal of the third inverter NG3 is coupled with the input terminal of the fourth inverter NG4, and the input terminal of the fourth inverter NG4 outputs the clamping state signal.

[0064] The clamping signal control circuit 400 comprises a first voltage-controlled switch S1 and an operational amplifier AMP, the controlled terminal of the first voltage-controlled switch S1 is coupled with the output terminal of the clamping state control circuit 300, the first terminal of the first voltage-controlled switch S1 is coupled with the first node N1 to receive the comparison signal EAO, and the second terminal of the first voltage-controlled switch S1 is coupled with the first input terminal of the operational amplifier AMP and the output terminal of the operational amplifier AMP; the second input terminal of the operational amplifier AMP is provided with the clamping reference voltage REF_CLAMP.

[0065] In the embodiment of the present application, the clamping reference voltage REF_CLAMP is input to the operational amplifier AMP, so that the signal EAO is clamped to the clamping reference voltage when rising to the signal VH, the phase switching signal PHASE_SEL represents the full-phase opening, and the duration of clamping depends on the pulse width of the monostable trigger unit ONE SHOT. At the same time, the signal PHASE_SEL representing the full-phase opening instantaneously switches the input threshold voltage of the hysteresis comparator to the second value VL. The delay unit Delay_P_ADD is effective when the input signal PHASE_SEL of the hysteresis comparator at the front stage represents the sub-phase shielding, so as to give the loop sufficient adjustment time to avoid the sub-phase shielding action of the system in a short time after the full-phase opening. Within this delay, the multiphase control circuit adjusts the signal EAO to be above or below the signal VL according to the weight of the current external load. When the external load is relatively heavy, the signal EAO rises above the signal VL within the set delay, and then the system full-phase opening drives the current load adjustment output to a stable state; when the external load is relatively light, the signal EAO is still lower than the signal VL after the set delay, and then the system shields the sub-phase, and drives the current load adjustment output to a stable state through only the main phase opening. Similarly, after the delay, the signal PHASE_SEL representing the full-phase opening switches the input threshold voltage of the hysteresis comparator to the signal VH.

[0066] Figure 5 ForFigure 4 Part of signal timing diagram of middle circuit, Figure 5 The signal timing diagram represents the load switching from light load to heavy load. The clamping of signal REF_CLAMP limits the peak of inductor current in all phases, effectively suppressing the instantaneous energy accumulation of all phases, avoiding the sharp overshoot of output voltage. The delay unit Delay_P_ADD gives the system enough time to adjust the loop according to the current load, and determines the phase state after delay. In Figure 5 The system has adjusted to stable state by all phase on during the delay time, and will not enter single phase state again under the same load. The combination of signal REF_CLAMP and delay unit Delay_P_ADD makes the system unable to enter the cycle state of main / all phase switching under a certain load, thereby avoiding large signal oscillation of output voltage.

[0067] In another optional embodiment of the present application, a phase selection circuit of a multiphase control circuit is provided, comprising: an error amplifier EA, a hysteresis voltage comparator COMP, a delay circuit Delay_P_ADD, a monostable trigger ONE SHOT, an operational amplifier AMP, a first inverter NG1, a second inverter NG2, a third inverter NG3, a fourth inverter NG4, a first voltage-controlled switch S1, a second voltage-controlled switch S2, and a third voltage-controlled switch S3.

[0068] The first input terminal of the error amplifier EA is coupled to a first reference voltage terminal to receive a first reference voltage VREF1, a feedback voltage VFB of the multiphase control circuit is provided to the second input terminal of the error amplifier EA, and the output terminal of the error amplifier EA is coupled to a first node N1; the first input terminal of the hysteresis voltage comparator COMP is coupled to a second reference voltage terminal, the second input terminal of the hysteresis voltage comparator COMP is coupled to the first node N1, and the controlled terminal of the second voltage-controlled switch S2 is coupled to the output terminal of the second inverter NG2, the first terminal of the second voltage-controlled switch S2 is coupled to a first value terminal VH of the second reference voltage, the second terminal of the second voltage-controlled switch S2 is coupled to the first input terminal of the hysteresis voltage comparator COMP, the controlled terminal of the third voltage-controlled switch S3 is coupled to the output terminal of the first inverter NG1, the first terminal of the third voltage-controlled switch S3 is coupled to a second value terminal VL of the second reference voltage, the second terminal of the third voltage-controlled switch S3 is coupled to the first input terminal of the hysteresis voltage comparator COMP, and the output terminal of the hysteresis voltage comparator COMP is coupled to the input terminal of the delay circuit Delay_P_ADD; the output terminal of the delay circuit Delay_P_ADD is coupled to the input terminal of the first inverter NG1; the output terminal of the first inverter NG1 is coupled to the input terminal of the second inverter NG2; the output terminal of the second inverter NG2 is coupled to the input terminal of the monostable trigger ONE SHOT, the output terminal of the monostable trigger ONE SHOT is coupled to the input terminal of the third inverter NG3, the output terminal of the third inverter NG3 is coupled to the input terminal of the fourth inverter NG4, the output terminal of the third inverter NG3 is coupled to the controlled terminal of the first voltage-controlled switch S1, the first terminal of the first voltage-controlled switch S1 is coupled to the first node N1, and the second terminal of the first voltage-controlled switch S1 is coupled to the first input terminal of the operational amplifier AMP; the first input terminal of the operational amplifier AMP is coupled to the output terminal of the operational amplifier AMP, and the second input terminal of the operational amplifier AMP is coupled to a clamping reference voltage terminal, and the second input terminal of the operational amplifier AMP is provided with a clamping reference voltage REF_CLAMP.

[0069] In another optional embodiment of the present application, a multiphase control circuit is provided, comprising: a phase selection circuit, wherein the phase selection circuit comprises: an amplifier circuit 100, a comparator circuit 200, a clamping state control circuit 300 and a clamping signal control circuit 400. The amplifier circuit 100 is configured to generate a comparison signal EAO according to a feedback voltage VFB of the multiphase control circuit and a first reference voltage VREF1 from a first reference voltage terminal, and provide the comparison signal EAO to the comparator circuit 200, wherein the comparison signal EAO is used to represent a peak value of an inductor current of the multiphase control circuit; the comparator circuit 200 is configured to generate a phase switching signal PHASE SEL according to the comparison signal EAO and a second reference voltage signal VREF2 from a second reference voltage terminal, and provide the phase switching signal PHASE SEL to the multiphase control circuit through an output terminal of the comparator circuit 200, wherein the phase switching signal PHASE SEL is used to control the multiphase control circuit to perform a phase addition or a phase subtraction operation; the clamping state control circuit 300 is configured to generate a clamping state control signal according to the phase switching signal PHASE SEL, and provide the clamping state control signal to the clamping signal control circuit 400; and the clamping signal control circuit 400 is configured to clamp a voltage value of the comparison signal EAO at a clamping reference voltage when the clamping state control signal is at an effective level.

[0070] In the embodiments of the present application, by setting the phase selection circuit in the multiphase control circuit, setting the clamping state control circuit and the clamping signal control circuit, when the load is switched from light load to heavy load, the peak value of the full-phase inductor current is limited by clamping in the process of full-phase opening, the instantaneous energy accumulation of full-phase opening is suppressed, the sharp overshoot of the output voltage is avoided, and the oscillation of the output voltage signal is avoided, thereby improving the stability of the circuit output signal.

[0071] The specific manners of performing operations of the units in the above embodiments have been described in detail in the embodiments related to the method, and will not be described in detail here.

[0072] To sum up, in the present application, a phase selection circuit of a multiphase control circuit is provided, comprising an amplifier circuit, a comparator circuit, a clamping state control circuit and a clamping signal control circuit. The amplifier circuit is configured to generate a comparison signal according to a feedback voltage of the multiphase control circuit and a first reference voltage from a first reference voltage terminal, and provide the comparison signal to the comparator circuit. The comparator circuit is configured to generate a phase switching signal according to the comparison signal and a second reference voltage signal from a second reference voltage terminal, and provide the phase switching signal to the multiphase control circuit through an output terminal of the comparator circuit. The clamping state control circuit is configured to generate a clamping state control signal according to the comparison signal and the phase switching signal, and provide the clamping state control signal to the clamping signal control circuit. The clamping signal control circuit is configured to clamp a voltage value of a clamping signal at a clamping reference voltage when the clamping state control signal is at an effective level. By setting the clamping state control circuit and the clamping signal control circuit for the multiphase control circuit, the inductance current peak of the multiphase control circuit is clamped when the phase switching is performed during the load switching of the multiphase control circuit, so as to avoid the output voltage from performing severe overshoot or undershoot when the phase switching is performed, and solve the problem of oscillation of the output voltage signal during the light and heavy load switching of the multiphase circuit in the prior art.

[0073] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0074] Obviously, those skilled in the art should understand that the units or steps of the present application described above can be realized by general computing devices, and they can be centralized on a single computing device or distributed on a network composed of multiple computing devices, and alternatively, they can be realized by program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, or they can be respectively manufactured into each integrated circuit module, or multiple modules or steps among them can be manufactured into a single integrated circuit module to realize. Thus, the present application is not limited to any particular combination of hardware and software.

[0075] The above only describes preferred embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A phase selection circuit for a multi-phase control circuit, characterized in that: include: amplifier circuit, comparator circuit, clamp state control circuit and clamp signal control circuit, The amplifier circuit is configured to generate a comparison signal based on a feedback voltage of the multi-phase control circuit and a first reference voltage from a first reference voltage terminal, and provide the comparison signal to the comparator circuit, wherein the comparison signal is used to represent a peak value of the inductor current of the multi-phase control circuit; The comparator circuit is configured to generate a phase switching signal according to the comparison signal and a second reference voltage signal from a second reference voltage terminal, and provide the phase switching signal to the multi-phase control circuit via an output terminal of the comparator circuit, wherein the phase switching signal is used to control the multi-phase control circuit to perform a phase addition or subtraction operation; The clamp state control circuit is configured to generate a clamp state control signal according to the phase switching signal and provide the clamp state control signal to the clamp signal control circuit; The clamp signal control circuit is configured to clamp the voltage value of the comparison signal to a clamp reference voltage when the clamp state control signal is at an active level; The clamping state control circuit includes: a monostable trigger, a third inverter and a fourth inverter. Wherein, the input terminal of the monostable trigger is coupled to the output terminal of the comparator circuit to receive the phase switching signal; The output terminal of the monostable trigger is coupled to the input terminal of the third inverter, the output terminal of the third inverter is coupled to the input terminal of the fourth inverter, and the input terminal of the fourth inverter outputs the clamping state control signal.

2. The phase selection circuit according to claim 1, wherein: The amplifier circuit includes: an error amplifier, The first input terminal of the error amplifier is coupled to the first reference voltage terminal, the output terminal of the error amplifier is coupled to a first node, and the feedback voltage is provided to the second input terminal of the error amplifier.

3. The phase selection circuit according to claim 1, wherein: The comparator circuit includes: a hysteresis voltage comparator, a delay circuit, a first inverter and a second inverter. The first input terminal of the hysteresis voltage comparator is coupled to the first node to receive the comparison signal, the second input terminal of the hysteresis voltage comparator is coupled to the second reference voltage terminal, and the output terminal of the hysteresis voltage comparator is coupled to the input terminal of the delay circuit; The output end of the delay circuit is coupled to the input end of the first inverter, and the output end of the second inverter is coupled to the input end of the second inverter; The delay circuit is configured to perform delay processing on the output signal of the hysteresis voltage comparator and output the phase switching signal via the output terminal of the second inverter.

4. The phase selection circuit according to claim 3, wherein: The phase switching signal is provided to the phase switching circuit of the multi-phase control circuit; when the phase switching signal is at a first level, the multi-phase control circuit is in a control mode in which all phases are turned on; When the phase switching signal is at the second level, the multi-phase control circuit is in a control mode in which the main phase is turned on and the auxiliary phase is shielded.

5. The phase selection circuit according to claim 1, wherein: An input terminal of the clamp state control circuit is coupled to an output terminal of the comparator circuit via a second node, and an input terminal of the clamp state control circuit receives the phase switching signal via the second node.

6. The phase selection circuit according to claim 1, wherein: The clamping signal control circuit includes: a first voltage-controlled switch and an operational amplifier, A controlled terminal of the first voltage-controlled switch is coupled to the output terminal of the clamp state control circuit, a first terminal of the first voltage-controlled switch is coupled to a first node to receive the comparison signal, and a second terminal of the first voltage-controlled switch is coupled to the first input terminal of the operational amplifier and the output terminal of the operational amplifier; The clamped reference voltage is provided to the second input terminal of the operational amplifier.

7. The phase selection circuit according to claim 1, wherein: The second reference voltage terminal includes a first value terminal and a second value terminal, Wherein, when the second reference voltage terminal is in the first state, the first value terminal is turned on, the second input terminal of the comparator circuit is turned on and the first value terminal is turned on, and the second input terminal of the comparator circuit is provided with the first value of the second reference voltage signal; When the second reference voltage terminal is in the second state, the second value terminal is turned on, the second input terminal of the comparator circuit is turned on and the second value terminal is turned on, and the second input terminal of the comparator circuit is provided with the second value of the second reference voltage signal.

8. The phase selection circuit according to claim 7, wherein: The first value terminal includes a second voltage-controlled switch, a controlled terminal of the second voltage-controlled switch is coupled to the output terminal of the comparator circuit, and controls whether the first value terminal and the second input terminal of the comparator circuit are connected according to the phase switching signal; The second value end includes a third voltage-controlled switch, and the controlled end of the third voltage-controlled switch is coupled to the comparator circuit to receive the inverted signal of the phase switching signal, and controls whether the second value end and the second output end of the comparator circuit are turned on according to the inverted signal of the phase switching signal.

9. A multi-phase control circuit, characterized in that: include: The phase selection circuit according to any one of claims 1 to 8.

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