A Turbo code encoding circuit

Abstract

The present invention application discloses a Turbo code encoding circuit, including a component encoder, an interleaver module and a multiplexer, wherein the component encoder adopts a component encoder with a code rate of 1 / 2. The Turbo code encoding circuit of the present invention reduces the generation of calculation units in the circuit structure of the Turbo code encoding circuit of the embodiment of the present invention by multiplexing the component encoder with a code rate of 1 / 2, thereby reducing the power consumption of the Turbo code encoding circuit; by selecting the first interleaver or the second interleaver to process the input bit according to the bit width of the input bit based on the preset bit width to obtain the output bit, the circuit structure is improved, and the power consumption of the Turbo code encoding circuit is further reduced, thereby meeting the low power consumption requirements of the NB‑IoT application scenario. The present invention can be widely used in the field of integrated circuits.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, in particular to a Turbo code encoding circuit. Background Art

[0002] In the digital baseband processing of NB-IoT, Turbo code is often used for wireless data transmission. It is an error correction coding scheme close to the Shannon limit (the theoretical maximum information transmission rate for a channel with a specific noise level). Therefore, Turbo code has attracted a lot of attention. The 1 / 3 code rate Turbo code encoder circuit is mainly composed of an interleaver, a component encoder, and a multiplexer. In the NB-IoT application scenario, since the NB-IoT scenario has extremely strict requirements on power consumption, the power consumption of the current Turbo code encoder circuit is still relatively high. Summary of the invention

[0003] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an embodiment of the present invention provides a Turbo code encoding circuit, which reduces the power consumption of the Turbo code encoding circuit.

[0005] The technical solutions adopted in the embodiments of the present invention include:

[0006] A turbo code encoding circuit includes a component encoder, an interleaver module and a multiplexer;

[0007] The component encoder adopts a component encoder with a code rate of 1 / 2;

[0008] The interleaver module includes a first interleaver and a second interleaver, and when the bit width of the input data is less than the preset bit width, the first interleaver is used to process the input bits to generate output bits; when the bit width of the input data is greater than or equal to the preset bit width, the second interleaver is used to process the input bits to generate the output bits;

[0009] The multiplexer is used for multiplexing the system information sequence and the check information sequence after passing through the component encoder.

[0010] As an optional implementation, the component encoder adopts a cyclic recursive convolutional code, and the component code of the component encoder is generated by a (2, 1, 4) system feedback encoder.

[0011] As an optional implementation, the component encoder includes a first register, a second register, a third register, a first adder, a second adder, a third adder and a fourth adder;

[0012] The first adder receives and sums the original information sequence and the bits output by the third adder, and outputs a first state, wherein the original information sequence includes the input bits and the output bits, and the component encoder outputs the original information sequence as a first component code information sequence according to the first state;

[0013] The first register obtains a second state according to the first state;

[0014] The second adder receives the first state and the second state, adds them together, and outputs a first bit;

[0015] The second register obtains a third state according to the second state, and the third register obtains a fourth state according to the third state;

[0016] The third adder receives the third state and the fourth state, adds them together, and outputs a second bit to the first adder;

[0017] The fourth adder receives and sums the first bit and the fourth state, and outputs a second component code information sequence.

[0018] As an optional implementation, the first register, the second register and the third register are shift registers.

[0019] As an optional implementation, the first interleaver processes the input bits by matrix interleaving to generate the output bits.

[0020] As an optional implementation, the second interleaver adopts a quadratic permutation polynomial interleaver, and the second interleaver includes an address calculation module and a multiplexer;

[0021] The address calculation module calculates the interleaving address corresponding to the input bit, and the multiplexer processes the input bit according to the interleaving address to generate the output bit.

[0022] As an optional implementation, the multiplexer includes a first IP core and a second IP core, the first IP core receives the interleaving address and forwards the interleaving address to the second IP core, and the second IP core processes the input bits according to the interleaving address to generate the output bits.

[0023] The advantages and benefits of the present invention will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0024] The Turbo code encoding circuit of the embodiment of the present invention reduces the generation of calculation units in the circuit structure of the Turbo code encoding circuit of the embodiment of the present invention by multiplexing a component encoder with a 1 / 2 code rate, thereby reducing the power consumption of the Turbo code encoding circuit; by selecting the first interleaver or the second interleaver to process the input bits according to the bit width of the input bits based on a preset bit width to obtain output bits, the circuit structure is improved, the power consumption of the Turbo code encoding circuit is further reduced, thereby meeting the low power consumption requirements of NB-IoT application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of circuit connection of a Turbo code encoding circuit according to an embodiment of the present invention;

[0026] Figure 2 Schematic diagram of circuit connection of component encoder of Turbo code encoding circuit according to an embodiment of the present invention;

[0027] Figure 3 It is a schematic diagram of the principle and structure of the first interleaver of the Turbo code encoding circuit according to an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the structure of the second interleaver of the Turbo code encoding circuit according to an embodiment of the present invention;

[0029] Figure 5 It is a module schematic diagram of a multiplexer of a Turbo code encoding circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0031] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0032] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] Flyback transformer switching power supply circuit: refers to a transformer switching power supply in which when the primary coil of the transformer is excited by a DC pulse voltage, the secondary coil of the transformer does not provide output power to the load, and only provides power output to the load after the excitation voltage of the primary coil of the transformer is turned off.

[0034] In the digital baseband processing of NB-IoT, Turbo code is usually used for wireless data transmission. It is an error correction coding scheme close to the Shannon limit (the theoretical maximum information transmission rate for a channel with a specific noise level). Therefore, Turbo code has attracted a lot of attention. The 1 / 3 code rate Turbo code encoder circuit is mainly composed of an interleaver, a component encoder and a multiplexer. In the NB-IoT application scenario, since the NB-IoT scenario has extremely strict requirements on power consumption, the power consumption of the current Turbo code encoder circuit is still relatively high. To this end, an embodiment of the present invention proposes a Turbo code encoding circuit, which reduces the generation of calculation units in the circuit structure of the Turbo code encoding circuit of the embodiment of the present invention by multiplexing a component encoder with a code rate of 1 / 2, thereby reducing the power consumption of the Turbo code encoding circuit; by selecting the first interleaver or the second interleaver based on the preset bit width according to the bit width of the input bit to process the input bit to obtain the output bit, the circuit structure is improved, and the power consumption of the Turbo code encoding circuit is further reduced, thereby meeting the low power consumption requirements of the NB-IoT application scenario.

[0035] like Figure 1 As shown, an embodiment of the present invention provides a Turbo code encoding circuit, including a component encoder, an interleaver module and a multiplexer;

[0036] The component encoder adopts a component encoder with a code rate of 1 / 2;

[0037] The interleaver module includes a first interleaver and a second interleaver, and when the bit width of the input bit is less than the preset bit width, the first interleaver is used to process the input bit to generate the output bit; when the bit width of the input data is greater than or equal to the preset bit width, the second interleaver is used to process the input bit to generate the output bit;

[0038] The multiplexer is used for multiplexing the system information sequence and the check information sequence after passing through the component encoder.

[0039] Among them, the interleaver module receives the data blocks as a bit stream, stores the bits and transmits the bits again.

[0040] Optionally, in one embodiment of the present invention, the preset bit width is 40 bits.

[0041] Reference Figure 2 As an optional implementation, the component encoder adopts a cyclic recursive convolutional code (RSC), and the component code of the component encoder is generated by a (2,1,4) system feedback encoder.

[0042] Specifically, the generator matrix of the component encoder in the embodiment of the present invention is:

[0043]

[0044] Wherein, D represents a register.

[0045] Continue to refer to Figure 2 , as an optional implementation, the component encoder includes a first register, a second register, a third register, a first adder, a second adder, a third adder and a fourth adder;

[0046] The first adder receives the original information sequence x n and the bits output by the third adder are summed to output the first state, the original information sequence x n Including the input bits and the output bits, the component encoder converts the original information sequence x n The output is the first component code information sequence y n ;

[0047] The first register is configured to determine the first state a n Get the second state b n ;

[0048] The second adder receives the first state a n and the second state b n And sum them up, output the first bit;

[0049] The second register is configured to generate a plurality of registers according to the second state b. n Get the third state c n , the third register is based on the third state c n Get the fourth state d n ;

[0050] The third adder receives the third state c n and the fourth state d nand sum them, and output a second bit to the first adder;

[0051] The fourth adder receives the first bit and the fourth state and sums them, outputting a second component code information sequence z n .

[0052] As an optional implementation, the first register, the second register and the third register are shift registers.

[0053] It can be seen that the component encoder of the embodiment of the present invention has a recursive property, and the relationship between the output data of each part is as follows:

[0054] a n =x n ⊕c n ⊕d n

[0055] b n =a n-1

[0056] c n =b n-1 =a n-2

[0057] d n =c n-1 =b n-2 =a n-3

[0058] y n =x n

[0059] z n =a n ⊕b n ⊕d n

[0060] Among them, x n is the original information sequence input at time n, a n , b n 、c n and d n is the state of the register at time n, y n is the first component code information sequence output at time n, z n is the second component code information sequence output at time n.

[0061] It can be understood that the component code output at time n is not only related to the original information sequence input at the current time, but also to the original information sequence input at the previous three times. In the embodiment of the present invention, the initial values ​​of the first register, the second register and the third register are set to 0 as the initial state, and the recursive data path is obtained according to the structure of the component encoder as follows:

[0062] R=X i ^D2^D3

[0063] Then the output encoding information path is X i ^R i ^D1^D3.

[0064] Wherein, D1 represents the first register, D2 represents the second register, and D3 represents the third register.

[0065] As an optional implementation, the first interleaver processes the input bits by matrix interleaving to generate the output bits.

[0066] Specifically, refer to Figure 3 In an embodiment of the present invention, when the data bit width of the input bits is less than the preset bit width, the input bits are processed by the first interleaver in a matrix interleaving manner to generate output bits. Figure 3 (b) shows the structure of the first interleaver and the corresponding deinterleaver structure of an embodiment of the present invention, by writing the input bits into the first interleaver by columns and reading them out from the first interleaver by rows.

[0067] Optionally, refer to Figure 3 The matrix interleaving principle of the first interleaver shown in (a) divides a frame of input bits into 4 bits on average and forms three groups, takes out the first bits of the three groups respectively and forms a new 3-bit group as the first frame, takes out the second bits of the three groups respectively and forms a new 3-bit group as the second frame, takes out the third bits of the three groups respectively and forms a new 3-bit group as the third frame, takes out the fourth bits of the three groups respectively and forms a new 3-bit group as the fourth frame; transmits the first frame, the second frame, the third frame and the fourth frame at a time to form output bits.

[0068] Reference Figure 4 As an optional implementation, the second interleaver adopts a quadratic permutation polynomial interleaver (QuadraticPermutationPolynomial, QPP), and the second interleaver includes an address calculation module and a multiplexer;

[0069] The address calculation module calculates the interleaving address corresponding to the input bit, and the multiplexer outputs the input bit according to the interleaving address to generate the output bit.

[0070] Optionally, the second interleaver is a QPP with a length of K, and the relationship between the input bits and the output bits is as follows:

[0071] c′ i =cπ(i) ,i=0,1,2,...,(K-1)

[0072] in:

[0073] π(i)=(f1i+f2i)modK

[0074] Wherein, i is the address of the input bit (the address of the sequence before interleaving); f1 is the first-order coefficient, which is an odd number; f2 is the second-order coefficient, which is an even number. The QPP used in the embodiment of the present invention supports 188 different K values ​​(40 to 6144).

[0075] f1 and f2 can be obtained by querying the interleaver module parameter table of the Turbo code encoding circuit in the embodiment of the present invention, as shown in Table 1.

[0076] Table 1

[0077]

[0078] Continue to refer to Figure 4 As an optional implementation, the multiplexer includes a first IP core and a second IP core, the first IP core receives the interleaving address and forwards the interleaving address to the second IP core, and the second IP core outputs the input bits according to the interleaving address to generate the output bits.

[0079] The first IP core is a Block ROM IP core, and the second IP core is a Block RAM IP core.

[0080] Specifically, in an embodiment of the present invention, based on the interleaving rules of NB-IoT, the idea of ​​controlling the reading and writing of input and output by RAM is utilized, the input bits are written into the second IP core in sequence, and the input bits in the second IP core are read out according to the interleaving address calculated by the address calculation module to generate output bits.

[0081] Figure 5 The multiplexer circuit diagram of the embodiment of the present invention is shown, wherein x k is the system information sequence after the component encoder, z k and z′ k is the check information sequence after the component encoder, d k The output of the multiplexer is:

[0082]

[0083] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A Turbo code encoding circuit, characterized in that: including a component encoder, an interleaver module and a multiplexer; The component encoder adopts a component encoder with a code rate of 1 / 2; The interleaver module comprises a first interleaver and a second interleaver, and when the bit width of the input bit is less than the preset bit width, the first interleaver is used to process the input bit to generate the output bit; when the bit width of the input bit is greater than or equal to the preset bit width, the second interleaver is used to process the input bit to generate the output bit; The multiplexer is used to multiplex the system information sequence and the check information sequence after passing through the component encoder; The component encoder adopts a cyclic recursive convolutional code, and the component code of the component encoder is generated by a (2, 1, 4) system feedback encoder; The component encoder includes a first register, a second register, a third register, a first adder, a second adder, a third adder and a fourth adder; The first adder receives and sums the original information sequence and the bits output by the third adder, and outputs a first state, wherein the original information sequence includes the input bits and the output bits, and the component encoder outputs the original information sequence as a first component code information sequence according to the first state; The first register obtains a second state according to the first state; The second adder receives the first state and the second state, adds them together, and outputs a first bit; The second register obtains a third state according to the second state, and the third register obtains a fourth state according to the third state; The third adder receives the third state and the fourth state, adds them together, and outputs a second bit to the first adder; The fourth adder receives and sums the first bit and the fourth state, and outputs a second component code information sequence.

2. A Turbo code encoding circuit according to claim 1, characterized in that: The first register, the second register and the third register are shift registers.

3. A Turbo code encoding circuit according to claim 1, characterized in that: The first interleaver processes the input bits in a matrix interleaving manner to generate the output bits.

4. A Turbo code encoding circuit according to claim 1, characterized in that: The second interleaver adopts a quadratic permutation polynomial interleaver, and the second interleaver includes an address calculation module and a multiplexer; The address calculation module calculates the interleaving address corresponding to the input bit, and the multiplexer outputs the input bit according to the interleaving address to generate the output bit.

5. A Turbo code encoding circuit according to claim 4, characterized in that: The multiplexer includes a first IP core and a second IP core, the first IP core receives the interleaving address and forwards the interleaving address to the second IP core, and the second IP core outputs the input bits according to the interleaving address to generate the output bits.

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