Multilayer capacitors

Abstract

A stacked capacitor comprises: a stacked body having a first side surface and a second side surface; a first side surface covering portion covering the first side surface; and a second side surface covering portion covering the second side surface. The stacked body is stacked in the z direction with a plurality of first conductor layers, a plurality of second conductor layers, a plurality of dielectric layers, and a plurality of insulating layers. The plurality of first conductor layers are respectively connected to the first side surface covering portion and separated from the second side surface covering portion. The plurality of second conductor layers are respectively connected to the second side surface covering portion and separated from the first side surface covering portion. The plurality of insulating layers have lower insulation resistance than each of the plurality of dielectric layers. Each of the plurality of dielectric layers is sandwiched by each of the first conductor layers of the plurality of first conductor layers and each of the second conductor layers of the second conductor layers (3). Among the plurality of insulating layers, there is an insulating layer sandwiched by two first conductor layers (2) and an insulating layer sandwiched by two second conductor layers (3).

Description

Technical Field

[0001] The present disclosure relates to a stacked capacitor. Background Art

[0002] In the past, there are known electronic circuits assembled in power conversion devices (inverters, etc.) for vehicles, industrial machinery, etc. In such electronic circuits, capacitors are used for the purpose of, for example, smoothing voltage. Patent document 1 discloses a conventional stacked capacitor. The stacked capacitor described in patent document 1 includes a plurality of first internal electrodes, a plurality of second internal electrodes, a plurality of dielectric films, a plurality of insulating materials, and a pair of external electrodes. Each first internal electrode and each second internal electrode is a metal film. The plurality of first internal electrodes are connected through one of a pair of external electrodes, and the plurality of second internal electrodes are connected through the other of a pair of external electrodes. The plurality of first internal electrodes and the plurality of second internal electrodes have opposite polarities to each other when the stacked capacitor is energized. Each insulating film is, for example, a plastic polymer film such as trifluoroethylene chloroethylene resin. In the stacked capacitor, each insulating film, each first internal electrode, each dielectric film, and each second internal electrode are stacked in order, and the stack is composed of a plurality of overlapping layers. Therefore, each insulating film is sandwiched by each first internal electrode and each second internal electrode to insulate them.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 08-97078 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In the multilayer capacitor described in Patent Document 1, when a potential difference is generated between the first internal electrode and the second internal electrode, a voltage is applied not only to the dielectric layer but also to the insulating film. Therefore, the insulation resistance of the multilayer capacitor is limited to the lower one of the insulation resistance of the dielectric layer or the insulation resistance of the insulating film. In particular, when the insulation resistance of the insulating film is lower than the insulation resistance of the dielectric layer, the insulation resistance of the multilayer capacitor is reduced.

[0008] The present disclosure has been made in view of the above circumstances, and one object of the present disclosure is to provide a multilayer capacitor capable of suppressing a decrease in dielectric strength.

[0009] Solutions to Solve Problems

[0010] The stacked capacitor provided by the present disclosure comprises: a stacked body having a main surface and a back surface facing opposite sides in a first direction, and having a first side surface and a second side surface facing opposite sides in a second direction orthogonal to the first direction; a first side surface electrode covering the first side surface; and a second side surface electrode covering the second side surface. The stacked body is stacked with a plurality of conductor layers, a plurality of dielectric layers, and a plurality of insulating layers in the first direction. The plurality of conductor layers include a plurality of first conductor layers and a plurality of second conductor layers separated from each other in the first direction, the plurality of first conductor layers being connected to the first side surface electrodes, respectively, and being separated from the second side surface electrodes. The plurality of second conductor layers are connected to the second side surface electrodes, respectively, and being separated from the first side surface electrodes. The insulation resistance of each of the plurality of insulating layers is lower than the insulation resistance of each of the plurality of dielectric layers. Each of the plurality of dielectric layers is sandwiched by each of the first conductor layers of the plurality of first conductor layers and each of the second conductor layers of the plurality of second conductor layers. The plurality of insulating layers include: an insulating layer sandwiched between two of the dielectric layers adjacent to each other in the first direction and two of the first conductor layers; and an insulating layer sandwiched between two of the dielectric layers adjacent to each other in the first direction and two of the second conductor layers.

[0011] Preferably, the plurality of dielectric layers are in contact with both the first side electrode and the second side electrode respectively.

[0012] Preferably, the plurality of dielectric layers are connected from an end edge on one side to an end edge on the other side of the stacked body in a third direction perpendicular to the first direction and the second direction.

[0013] Preferably, in the second direction, an insulator made of the same material as that of the plurality of insulating layers is arranged between each of the plurality of first conductive layers and the second side electrode.

[0014] Preferably, in the second direction, an insulator made of the same material as that of the plurality of insulating layers is arranged between each of the plurality of second conductive layers and the first side electrode.

[0015] Effects of the Invention

[0016] According to the multilayer capacitor of the present disclosure, it is possible to suppress a decrease in dielectric strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a perspective view showing the multilayer capacitor according to the first embodiment.

[0018] Figure 2 It is a plan view showing the multilayer capacitor according to the first embodiment.

[0019] Figure 3 It is a bottom view showing the multilayer capacitor according to the first embodiment.

[0020] Figure 4 It is a front view showing the multilayer capacitor according to the first embodiment.

[0021] Figure 5 It is a rear view showing the multilayer capacitor according to the first embodiment.

[0022] Figure 6 It is a left side view showing the multilayer capacitor according to the first embodiment.

[0023] Figure 7 It is a right side view showing the multilayer capacitor according to the first embodiment.

[0024] Figure 8 It is along Figure 2 A cross-sectional view taken along line VIII-VIII.

[0025] Fig. 9 It is a plan view showing the first conductor layer according to the first embodiment.

[0026] Fig.10 It is a plan view showing the dielectric layer according to the first embodiment.

[0027] Fig.11 It is a plan view showing the second conductor layer according to the first embodiment.

[0028] Fig.12 It is a plan view showing the insulating layer according to the first embodiment.

[0029] Fig.13 It is a perspective view showing a multilayer capacitor according to a second embodiment.

[0030] Fig.14 It is a plan view showing a multilayer capacitor according to a second embodiment.

[0031] Fig.15 It is a bottom view showing the multilayer capacitor according to the second embodiment.

[0032] Fig.16 It is a front view showing a multilayer capacitor according to a second embodiment.

[0033] Fig.17 It is a rear view showing the multilayer capacitor according to the second embodiment.

[0034] Fig.18It is a left side view showing the multilayer capacitor according to the second embodiment.

[0035] Fig.19 It is a right side view showing the multilayer capacitor according to the second embodiment.

[0036] Fig. 20 It is along Fig.14 Cross-sectional view of line XX-XX.

[0037] Fig.21 It is a plan view showing a first conductive layer according to the second embodiment.

[0038] Fig. 22 It is a plan view showing a dielectric layer according to the second embodiment.

[0039] Fig.23 It is a plan view showing a second conductor layer according to the second embodiment.

[0040] Fig.24 It is a plan view showing an insulating layer according to the second embodiment. DETAILED DESCRIPTION

[0041] Hereinafter, preferred embodiments of the multilayer capacitor disclosed in the present disclosure will be described with reference to the accompanying drawings. In the following description, the same or similar components are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0042] <First Embodiment>

[0043] Figures 1 to 12 The multilayer capacitor A1 of the first embodiment is shown. The multilayer capacitor A1 includes a multilayer body 1 and a pair of external electrodes 61 and 62. The multilayer body 1 includes a plurality of first conductive layers 2, a plurality of second conductive layers 3, a plurality of dielectric layers 4, and a plurality of insulating layers 5.

[0044] Figure 1 It is a perspective view showing the multilayer capacitor A1. Figure 2 1 is a plan view showing the multilayer capacitor A1. Figure 3 FIG. 1 is a bottom view showing the multilayer capacitor A1. Figure 4 1 is a front view showing the multilayer capacitor A1. Figure 5 FIG. 1 is a rear view showing the multilayer capacitor A1. Figure 6 It is a left side view showing the multilayer capacitor A1. Figure 7 It is a right side view showing the multilayer capacitor A1. Figure 8 It is along Figure 2 A cross-sectional view taken along line VIII-VIII. Fig. 9 It is a plan view showing each first conductor layer 2 . Fig.10It is a plan view showing each dielectric layer 4 . Fig.11 It is a plan view showing each second conductor layer 3 . Fig.12 It is a plan view showing each insulating layer 5 .

[0045] For the sake of convenience, three mutually orthogonal directions are defined as the x-direction, the y-direction, and the z-direction. The z-direction is the thickness direction of the multilayer capacitor A1. The x-direction is the top view of the multilayer capacitor A1 (see Figure 2 ) in the left-right direction. The y direction is the top view of the multilayer capacitor A1 (refer to Figure 2 ). One side of the x direction is set to the x1 direction, and the other side of the x direction is set to the x2 direction. Similarly, one side of the y direction is set to the y1 direction, and the other side of the y direction is set to the y2 direction, one side of the z direction is set to the z1 direction, and the other side of the z direction is set to the z2 direction. In the following description, "looking down" means observing in the z direction. The z direction is an example of a "first direction", the x direction is an example of a "second direction", and the y direction is an example of a "third direction".

[0046] The laminate 1 is, for example, a substantially rectangular parallelepiped. Figure 2 As shown, the laminate 1 has a rectangular shape with the x direction as the short side direction and the y direction as the long side direction in a plan view. The laminate 1 has a main surface 101 , a rear surface 102 , and a plurality of side surfaces 103 to 106 .

[0047] like Figures 4 to 8 As shown, the main surface 101 and the back surface 102 are separated in the z direction. The main surface 101 faces the z2 direction, and the back surface 102 faces the z1 direction. Figures 4 to 8 As shown, the plurality of side surfaces 103 to 106 are respectively located between the main surface 101 and the back surface 102 in the z direction, and are respectively connected to the main surface 101 and the back surface 102. Figure 2 as well as Figure 3 As shown, the side surface 103 and the side surface 104 are separated in the x direction. The side surface 103 faces the x2 direction, and the side surface 104 faces the x1 direction. Figure 2 as well as Figure 3 As shown, the side surface 105 and the side surface 106 are separated in the y direction. The side surface 105 faces the y2 direction, and the side surface 106 faces the y1 direction. The side surface 103 is an example of a "first side surface", and the side surface 104 is an example of a "second side surface".

[0048] As described above, the laminate 1 includes a plurality of first conductor layers 2, a plurality of second conductor layers 3, a plurality of dielectric layers 4, and a plurality of insulating layers 5. In this embodiment, Figure 8As shown, the laminate 1 includes three first conductor layers 2a to 2c, three second conductor layers 3a to 3c, three dielectric layers 4a to 4c, and four insulating layers 5a to 5d. The plurality of first conductor layers 2, the plurality of second conductor layers 3, the plurality of dielectric layers 4, and the plurality of insulating layers 5 are stacked in the z direction by a structure described in detail later. The combination of the plurality of first conductor layers 2 and the plurality of second conductor layers 3 is an example of "a plurality of conductor layers".

[0049] Each of the plurality of first conductor layers 2 is made of, for example, Cu. The thickness of each first conductor layer 2 is, for example, not less than 30 μm and not more than 70 μm. Figure 8 As shown in FIG. 1 , the end edge of each first conductor layer 2 on the x2 direction side is exposed from the side surface 103. The plurality of first conductor layers 2 overlap each other in a plan view. Fig. 9 As shown in FIG. 1 , each first conductive layer 2 extends from the edge of the laminate 1 on the x2 direction side toward the x1 direction in a plan view. Fig. 9 As shown in FIG. 1 , the end edge of each first conductor layer 2 on the x2 direction side is exposed from the side surface 103, and the end edge on the x1 direction side is not exposed from the side surface 104. Therefore, in a plan view, the end edge of each first conductor layer 2 on the x1 direction side is located on the inner side of the stacked body 1 than the side surface 104. Fig. 9 As shown, each first conductor layer 2 is not exposed from either the side surface 105 or the side surface 106 when viewed from above. Therefore, when viewed from above, the end edge of each first conductor layer 2 on the y1 direction side is located inside the laminate 1 than the side surface 106, and the end edge on the y2 direction side is located inside the laminate 1 than the side surface 105.

[0050] like Fig. 9 As shown in FIG. 1 , in a plan view, an insulator 29 is formed around each first conductor layer 2 (except for the end edge on the x2 direction side). Specifically, the insulator 29 is located between each first conductor layer 2 and the side surface 104, between each first conductor layer 2 and the side surface 105, and between each first conductor layer 2 and the side surface 106. The insulator 29 is made of the same material as the insulating layer 5 described later.

[0051] Each of the plurality of second conductor layers 3 is made of, for example, Cu. The thickness of each second conductor layer 3 is, for example, not less than 30 μm and not more than 70 μm. Figure 8 As shown in FIG. 1 , the end edge of each second conductor layer 3 on the x1 direction side is exposed from the side surface 104. The plurality of second conductor layers 3 overlap each other in a plan view. Fig.11 As shown in FIG. 1 , each second conductive layer 3 extends from the edge of the laminate 1 on the x1 direction side toward the x2 direction in a plan view. Fig.11 As shown in FIG. 1 , the end edge of each second conductor layer 3 on the x1 direction side is exposed from the side surface 104, and the end edge on the x2 direction side is not exposed from the side surface 103. Therefore, in a plan view, the end edge of each second conductor layer 3 on the x2 direction side is located on the inner side of the stacked body 1 than the side surface 103. Fig.11 As shown, each second conductor layer 3 is not exposed from either the side surface 105 or the side surface 106 when viewed from above. Therefore, when viewed from above, the end edge of each second conductor layer 3 on the y1 direction side is located inside the laminate 1 than the side surface 106, and the end edge on the y2 direction side is located inside the laminate 1 than the side surface 105.

[0052] like Fig.11 As shown in FIG. 1 , in a plan view, an insulator 39 is formed around each second conductor layer 3 (except for the end edge on the x1 direction side). Specifically, the insulator 39 is located between each second conductor layer 3 and the side surface 103, between each second conductor layer 3 and the side surface 105, and between each second conductor layer 3 and the side surface 106. The insulator 39 is made of the same material as the insulator 29. That is, the insulator 39 is made of the same material as the insulating layer 5 described later.

[0053] The plurality of first conductor layers 2 and the plurality of second conductor layers 3 partially overlap each other in a plan view. In addition, the plurality of first conductor layers 2 and the plurality of second conductor layers 3 have opposite polarities when current is supplied to the multilayer capacitor A1.

[0054] Each dielectric layer 4 is sandwiched between each first conductor layer 2 and each second conductor layer 3. Figure 8 In the example shown, the dielectric layer 4a is sandwiched between the first conductor layer 2a and the second conductor layer 3a. The dielectric layer 4b is sandwiched between the second conductor layer 3b and the first conductor layer 2b. The dielectric layer 4c is sandwiched between the first conductor layer 2c and the second conductor layer 3c. Fig.10 As shown, each dielectric layer 4 is connected from the end edge of the stack 1 in the x1 direction to the end edge of the x2 direction, and from the end edge of the stack 1 in the y1 direction to the end edge of the y2 direction when viewed from above. Each dielectric layer 4 is composed of a film-like resin material such as a polymer film. The constituent material of each dielectric layer 4 is not limited to a film-like resin material, and can be, for example, a material having a relative dielectric constant greater than 1. As such a material, ceramics having a metal oxide perovskite compound as a main component can be cited. The thickness of each dielectric layer 4 is, for example, not less than 8 μm and not more than 25 μm.

[0055] The plurality of insulating layers 5 are each made of, for example, prepreg. Each insulating layer 5 insulates the two first conductor layers 2 and the two second conductor layers 3 respectively in contact with the two surfaces in the z direction. The insulation resistance of each insulating layer 5 is lower than that of each dielectric layer 4. In addition, each insulating layer 5 also functions as an adhesive layer for the two first conductor layers 2 and the two second conductor layers 3 respectively in contact with the two surfaces in the z direction. The thickness of each insulating layer 5 is, for example, not less than 40 μm and not more than 100 μm.

[0056] like Figure 8As shown, the plurality of insulating layers 5 include an insulating layer sandwiched between two first conductor layers 2 between two dielectric layers 4 adjacent in the z direction and an insulating layer sandwiched between two second conductor layers 3 between two dielectric layers 4 adjacent in the z direction. Figure 8 As shown, the plurality of insulating layers 5 also include: an insulating layer sandwiched between a pair of external electrodes 61, 62 (main surface covering portions 612, 622 described later) formed on the main surface 101 of the stack 1 and the first conductor layer 2; and an insulating layer sandwiched between a pair of external electrodes 61, 62 (back surface covering portions 613, 623 described later) formed on the back surface 102 of the stack 1 and the second conductor layer 3. Figure 8 In the example shown, the insulating layer 5a is a surface layer on the z2 direction side of the laminate 1, and is sandwiched between the main surface covering portions 612, 622 described later and the first conductor layer 2a. The insulating layer 5b is sandwiched between the two dielectric layers 4a, 4b by the second conductor layer 3a and the second conductor layer 3b. The insulating layer 5c is sandwiched between the two dielectric layers 4b, 4c by the first conductor layer 2b and the first conductor layer 2c. The insulating layer 5d is a surface layer on the z1 direction side of the laminate 1, and is sandwiched between the back surface covering portions 613, 623 described later and the second conductor layer 3c.

[0057] In the laminate 1, the first unit stacked in the order of the first conductor layer 2, the dielectric layer 4, and the second conductor layer 3 in the z direction and the second unit stacked in the order of the second conductor layer 3, the dielectric layer 4, and the first conductor layer 2 from the z2 direction toward the z1 direction are alternately overlapped with the insulating layer 5. The number of the first unit and the second unit is not particularly limited, and the number of the first unit and the second unit may be different. Figure 8 In the example shown, the insulating layer 5, the first unit, the insulating layer 5, the second unit, the insulating layer 5, the first unit, and the insulating layer 5 are stacked in this order. Figure 8 In the example shown, two first units and one second unit are alternately stacked with the insulating layer 5 interposed therebetween. The stacked structure of the stacked body 1 is not limited to the above example, and the surface layers on both sides in the z direction may be configured as the dielectric layer 4.

[0058] In the laminate 1, the x-direction dimension, y-direction dimension, and z-direction dimension (thickness) of each layer (each first conductor layer 2, each second conductor layer 3, dielectric layer 4, and insulating layer 5), the constituent material of each layer, the number of layers stacked, etc. are not particularly limited and can be appropriately changed based on the specifications (e.g., electrostatic capacitance, size, etc.) of the laminated capacitor A1. The electrostatic capacitance C of the laminated capacitor A1 is C=ε0·ε r ·(S / d)·N[F]. In this formula, ε0 represents the dielectric constant of vacuum, ε rrepresents the relative dielectric constant of the dielectric (each dielectric layer 4), S represents the area of ​​the internal electrode (the area where each first conductor layer 2 and each second conductor layer 3 overlap when viewed from above), d represents the distance between the electrodes (between each first conductor layer 2 and each second conductor layer 3), and N represents the number of stacked dielectric layers 4. For example, according to the above formula, the larger the separation distance in the z direction between each first conductor layer 2 and each second conductor layer 3 (the thickness of the dielectric layer 4), the smaller the electrostatic capacitance. In addition, the larger the relative dielectric constant of the dielectric layer 4, the larger the electrostatic capacitance. In addition, the larger the top-view area of ​​each first conductor layer 2 and each second conductor layer 3, the larger the electrostatic capacitance. In addition, the more the number of stacked layers of each layer (the number of the above-mentioned units), the larger the electrostatic capacitance.

[0059] The pair of external electrodes 61, 62 is formed so as to cover a part of the main surface 101, a part of the back surface 102, and each side surface 103, 104 of the laminate 1. The pair of external electrodes 61, 62 is a terminal of the laminated capacitor A1. The pair of external electrodes 61, 62 are separated from each other and insulated from each other. The pair of external electrodes 61, 62 is composed of Cu, for example, but not limited to this. The pair of external electrodes 61, 62 is formed by plating, for example, but not limited to this.

[0060] The external electrode 61 is one terminal of the multilayer capacitor A1. The external electrode 61 includes a side cover 611, a main surface cover 612, and a back surface cover 613. Figure 1 to Figure 5 , Figure 7 as well as Figure 8 As shown, the side cover 611 covers the side 103. Figure 1 , Figure 2 , Figure 4 , Figure 5 as well as Figure 8 As shown, the main surface covering portion 612 covers a portion of the main surface 101. Figure 2 As shown in FIG. 1 , the main surface covering portion 612 is formed on the x2-direction side portion of the main surface 101. The main surface covering portion 612 is connected to the side covering portion 611. Figure 3 to Figure 5 as well as Figure 8 As shown, the back cover 613 covers a portion of the back surface 102. Figure 3 As shown in FIG. 1 , the back cover 613 is formed on the x2-direction side of the back surface 102. The back cover 613 is connected to the side cover 611. Figure 8 In the example shown, the main surface covering portion 612 and the back surface covering portion 613 do not overlap with each second conductive layer 3 in a plan view. In addition, the external electrode 61 may also include a portion that is connected to the side surface covering portion 611, the main surface covering portion 612, and the back surface covering portion 613 and covers a portion of the two side surfaces 105 and 106. In addition, the external electrode 61 may not include the main surface covering portion 612 and the back surface covering portion 613.

[0061] As described above, since the insulator 39 is disposed between the side surface 103 and each second conductive layer 3, Fig.11 As shown in FIG. 1 , in the x direction, each insulator 39 is disposed between the side cover 611 and each second conductor layer 3. Therefore, the side cover 611 is insulated from each second conductor layer 3 by each insulator 39. Figure 8 as well as Fig. 9 As shown, the side cover 611 contacts the edge of each first conductor layer 2 on the x2 direction side, so the side cover 611 electrically connects the plurality of first conductor layers 2 separated and arranged in the z direction. Therefore, the plurality of first conductor layers 2 have the same potential via the side cover 611. The side cover 611 is an example of a "first side electrode".

[0062] The external electrode 62 is another terminal of the multilayer capacitor A1. The external electrode 62 includes a side cover 621, a main surface cover 622, and a back surface cover 623. Figure 2 to Figure 6 as well as Figure 8 As shown, the side cover 621 covers the side 104. Figure 2 , Figure 4 , Figure 5 as well as Figure 8 As shown, the main surface covering portion 622 covers a portion of the main surface 101. Figure 2 As shown, the main surface covering portion 622 is formed on the x1 direction side of the main surface 101 and is separated from the main surface covering portion 612 (external electrode 61). The main surface covering portion 622 is connected to the side covering portion 621. Figure 3 to Figure 5 as well as Figure 8 As shown, the back cover 623 covers a portion of the back surface 102. The back cover 623 is formed on the x1 side of the back surface 102 and is separated from the back cover 613 (external electrode 61). The back cover 623 is connected to the side cover 621. Figure 8 In the example shown, the main surface covering portion 622 and the back surface covering portion 623 do not overlap with each first conductor layer 2 in a plan view. In addition, the external electrode 62 may also include a portion that is connected to the side surface covering portion 621, the main surface covering portion 622, and the back surface covering portion 623 and covers a portion of the two side surfaces 105 and 106. In addition, the external electrode 62 may not include the main surface covering portion 622 and the back surface covering portion 623.

[0063] As described above, since the insulator 29 is disposed between the side surface 104 and each first conductive layer 2, Fig. 9As shown in FIG. 1 , in the x direction, each insulator 29 is disposed between the side cover 621 and each first conductor layer 2. Therefore, the side cover 621 is insulated from each first conductor layer 2 by each insulator 29. Figure 8 as well as Fig.11 As shown, the side cover 621 contacts the edge of each second conductor layer 3 on the x1 direction side, so the side cover 621 electrically connects the plurality of second conductor layers 3 separated and arranged in the z direction. Therefore, the plurality of second conductor layers 3 are at the same potential via the side cover 621. The side cover 621 is an example of a "second side electrode".

[0064] The operation and effect of the multilayer capacitor A1 are as follows.

[0065] In the multilayer capacitor A1, a plurality of dielectric layers 4 are sandwiched by each first conductor layer 2 and each second conductor layer 3 in the z direction. A plurality of insulating layers 5 include: an insulating layer sandwiched by two first conductor layers 2 (e.g., first conductor layers 2b, 2c) between two dielectric layers 4 adjacent in the z direction (e.g., dielectric layers 4b, 4c); and an insulating layer sandwiched by two second conductor layers 3 (e.g., second conductor layers 3a, 3b) between two dielectric layers 4 adjacent in the z direction (e.g., dielectric layers 4a, 4b). The insulation resistance of each insulating layer 5 is lower than that of each dielectric layer 4. According to this structure, the dielectric layer 4 is sandwiched by two conductor layers (the first conductor layer 2 and the second conductor layer 3) with different potentials, and the insulating layer 5 is sandwiched by two conductor layers (the two first conductor layers 2 or the two second conductor layers 3) with the same potential. Therefore, when the multilayer capacitor A1 is energized, when a potential difference is generated between the plurality of first conductor layers 2 and the plurality of second conductor layers 3, a voltage is applied in the thickness direction (z direction) of the dielectric layer 4, but no voltage is applied in the thickness direction (z direction) of the insulating layer 5. Therefore, the withstand voltage (insulation resistance) of the insulating layer 5 may not be guaranteed. That is, the multilayer capacitor A1 can suppress a decrease in insulation resistance.

[0066] In the multilayer capacitor A1, for example, the dielectric layer 4 is a resin material, and the insulating layer 5 is a prepreg. Among the existing multilayer capacitors, there are ceramic capacitors in which the dielectric layer 4 is composed of ceramics. Ceramics are easily broken by stresses such as thermal stress due to their physical properties. Therefore, ceramic capacitors may cause cracks and other damage in the dielectric layer 4 due to the heat generated when they are energized. Due to this damage, the insulation resistance of the dielectric layer 4 is reduced. On the other hand, in the multilayer capacitor A1 disclosed in the present invention, the dielectric layer 4 is not ceramic, so the generation of cracks and the like caused by thermal stress can be suppressed. Therefore, the multilayer capacitor A1 can suppress the reduction of insulation resistance.

[0067] In the multilayer capacitor A1, the end edge on the y1 direction side and the end edge on the y2 direction side of each first conductor layer 2 are covered by the insulator 29. In addition, the end edge on the y1 direction side and the end edge on the y2 direction side of each second conductor layer 3 are covered by the insulator 39. According to this structure, each first conductor layer 2 and each second conductor layer 3 are not exposed on each side surface 105, 106 of the multilayer body 1. Therefore, it is possible to suppress the occurrence of an unintentional short circuit between each first conductor layer 2 and each second conductor layer 3 on each side surface 105, 106.

[0068] <Second Embodiment>

[0069] Figure 13 to Figure 24 A multilayer capacitor A2 according to a second embodiment is shown.

[0070] Fig.13 FIG. 1 is a perspective view showing a multilayer capacitor A2. Fig.14 FIG. 1 is a plan view showing the multilayer capacitor A2. Fig.15 FIG. 1 is a bottom view showing the multilayer capacitor A2. Fig.16 FIG. 1 is a front view showing the multilayer capacitor A2. Fig.17 FIG. 1 is a rear view showing the multilayer capacitor A2. Fig.18 It is a left side view showing the multilayer capacitor A2. Fig.19 It is a right side view showing the multilayer capacitor A2. Fig. 20 It is along Fig.14 Cross-sectional view of line XX-XX. Fig.21 It is a plan view showing each first conductive layer 2 according to the second embodiment. Fig. 22 It is a plan view showing each dielectric layer 4 according to the second embodiment. Fig.23 It is a plan view showing each second conductor layer 3 according to the second embodiment. Fig.24 It is a plan view showing each insulating layer 5 according to the second embodiment.

[0071] like Fig.13 As shown in FIG. 1 , the multilayer capacitor A2 is a substantially rectangular parallelepiped similar to the multilayer capacitor A1. Figure 13 to Figure 24 As shown, the multilayer capacitor A2 is different from the multilayer capacitor A1 in that it is a rectangular shape with the x direction as the long side direction and the y direction as the short side direction when viewed from above. Except for this point, the multilayer body 1 (a plurality of first conductor layers 2, a plurality of second conductor layers 3, a plurality of dielectric layers 4, and a plurality of insulating layers 5) and a pair of external electrodes 61, 62 as the components of the multilayer capacitor A2 are constructed in the same manner as the multilayer capacitor A1.

[0072] In the stacked capacitor A2, similarly to the stacked capacitor A1, the plurality of dielectric layers 4 are sandwiched by the first conductor layers 2 and the second conductor layers in the z direction, respectively. The plurality of insulating layers 5 include an insulating layer sandwiched by two first conductor layers 2 (e.g., the first conductor layers 2b and 2c) and an insulating layer sandwiched by two second conductor layers 3 (e.g., the second conductor layers 3a and 3b). Therefore, when a potential difference is generated between the plurality of first conductor layers 2 and the plurality of second conductor layers 3, a voltage is applied in the thickness direction (z direction) of the dielectric layer 4, but no voltage is applied in the thickness direction (z direction) of the insulating layer 5, so the withstand voltage (insulation resistance) of the insulating layer 5 may not be guaranteed. That is, the stacked capacitor A2 can suppress the reduction of insulation resistance. In addition, the stacked capacitor A2 can achieve the same effect as the above-mentioned stacked capacitor A1.

[0073] The multilayer capacitor according to the present invention is not limited to the above-described embodiment. The specific structure of each part of the multilayer capacitor disclosed in the present invention can be freely modified in various designs.

[0074] Explanation of symbols

[0075] A1, A2—stacked capacitor; 1—stacked body; 101—main surface; 102—back surface; 103, 104, 105, 106—side surface; 2, 2a, 2b, 2c—first conductor layer; 3, 3a, 3b, 3c—second conductor layer; 29, 39—insulator; 4, 4a, 4b, 4c—dielectric layer; 5, 5a, 5b, 5c, 5d—insulating layer; 61, 62—external electrode; 611, 621—side surface covering portion; 612, 622—main surface covering portion; 613, 623—back surface covering portion.

Claims

1. A multilayer capacitor, characterized in that: have: A laminate having a main surface and a back surface facing opposite sides to each other in a first direction, and having a first side surface and a second side surface facing opposite sides to each other in a second direction orthogonal to the first direction; A first side electrode covering the first side; as well as a second side electrode covering the second side, The laminate includes a plurality of conductor layers, a plurality of dielectric layers, and a plurality of insulating layers laminated in the first direction. The plurality of conductor layers include a plurality of first conductor layers and a plurality of second conductor layers separated from each other in the first direction, The plurality of first conductor layers are respectively connected to the first side electrodes and separated from the second side electrodes. The plurality of second conductor layers are respectively connected to the second side electrodes and separated from the first side electrodes. The insulation resistance of each of the plurality of insulating layers is lower than the insulation resistance of each of the plurality of dielectric layers. Each of the plurality of dielectric layers is sandwiched by each of the plurality of first conductor layers and each of the plurality of second conductor layers. Among the plurality of insulating layers, there is: an insulating layer sandwiched between two of the dielectric layers adjacent to each other in the first direction and by two of the first conductor layers; and an insulating layer sandwiched by two second conductor layers between two adjacent dielectric layers in the first direction, The plurality of dielectric layers are in direct contact with both the first side electrode and the second side electrode, respectively. The plurality of dielectric layers are arranged to be separated from each other in the first direction and are formed to be separate from each other.

2. The multilayer capacitor according to claim 1, wherein: The plurality of dielectric layers are connected from an end edge on one side to an end edge on the other side of the stacked body in a third direction perpendicular to the first direction and the second direction.

3. The multilayer capacitor according to claim 1, wherein: In the second direction, an insulator made of the same material as that of the plurality of insulating layers is arranged between each of the plurality of first conductive layers and the second side electrode.

4. The multilayer capacitor according to any one of claims 1 to 3, characterized in that: In the second direction, an insulator made of the same material as that of the plurality of insulating layers is arranged between each of the plurality of second conductive layers and the first side electrode.

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