Solid-state imaging device and imaging apparatus

Abstract

The present invention aims to improve the image quality of a solid-state imaging device that performs exposure for all pixels at the same time. A pre-stage circuit block generates a specified reset level and each of a plurality of signal levels corresponding to an exposure amount, and holds the reset level and the signal levels in different capacitive elements. A selection unit sequentially performs: control to connect the capacitive element holding the reset level among a specified number of the capacitive elements to a specified post-stage node; control to disconnect the specified number of the capacitive elements from the post-stage node; and control to connect the capacitive elements holding the plurality of signal levels among the specified number of the capacitive elements to the post-stage node. A post-stage reset transistor initializes the post-stage node when the specified number of the capacitive elements have been disconnected from the post-stage node. A post-stage circuit sequentially reads each of the reset level and the plurality of signal levels through the post-stage node.

Description

TECHNICAL FIELD

[0001] The present technology relates to a solid-state imaging device. Specifically, the present technology relates to a solid-state imaging device that performs analog-digital (AD) conversion for each column and an imaging apparatus. BACKGROUND

[0002] Conventionally, for the purpose of miniaturizing pixels, a column analog-digital converter (ADC) system has been used in a solid-state imaging device in which an ADC is arranged for each column outside a pixel array section and pixel signals are read sequentially in rows. In this column ADC system, when exposure is performed by a rolling shutter system in which exposure is started in rows, there is a possibility that rolling shutter distortion occurs. Therefore, a solid-state imaging device has been proposed in which a pair of capacitors is provided for each pixel to hold a reset level and a signal level in the capacitors to realize a global shutter system in which exposure is started at the same time in all pixels (for example, refer to Non-Patent Literature 1). The pair of capacitors is connected in series with a source follower circuit via a node, and the reset level and the signal level are read sequentially by the source follower circuit.

[0003] LIST OF CITATIONS

[0004] NON-PATENT LITERATURE

[0005] Non-Patent Literature 1: Jae-kyu Lee et al., A 2.1e-Temporal Noise and-105dB Parasitic Light Sensitivity Backside-Illuminated 2.3μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020. SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In the above-described conventional technology, the global shutter system of the column ADC system is realized by holding a reset level and a signal level in a pair of capacitors for each pixel. However, when a transistor pair of a source follower circuit initializes a node connected to the capacitors, there is a problem that kTC noise (in other words, reset noise) is generated at a level corresponding to the capacitors, so that image quality of image data is reduced due to the noise.

[0008] The present technology is made in view of this situation, and aims to improve the image quality of a solid-state imaging device that performs exposure on all pixels at the same time.

[0009] Solution to the technical problem

[0010] The present technology is made to solve the above problems, and a first aspect thereof relates to a solid-state imaging device including: a predetermined number of capacitive elements; an upstream circuit block that generates a predetermined reset level and each of a plurality of signal levels that respectively correspond to an exposure amount, and causes capacitive elements that are different from each other to hold the reset level and the plurality of signal levels; a selection section that sequentially performs control to connect a capacitive element that holds the reset level among the predetermined number of capacitive elements to a predetermined downstream node, control to disconnect the predetermined number of capacitive elements from the predetermined downstream node, and control to connect a capacitive element that holds any one of the plurality of signal levels among the predetermined number of capacitive elements to the downstream node; a downstream reset transistor that initializes a level of the downstream node in a case where the predetermined number of capacitive elements are disconnected from the downstream node; and a downstream circuit that sequentially reads each of the reset level and the plurality of signal levels via the downstream node. This produces an effect of reducing kTC noise.

[0011] Further, in the first aspect, the predetermined number of capacitive elements can include first and second capacitive elements and third and fourth capacitive elements; the upstream circuit block can include: a first upstream circuit that sequentially generates a first reset level and a first signal level, and causes the first and second capacitive elements to hold the first reset level and the first signal level; and a second upstream circuit that sequentially generates a second reset level and a second signal level, and causes third and fourth capacitive elements to hold the second reset level and the second signal level; and the selection section can include: a first selection circuit that connects any one of the first and second capacitive elements to the downstream node; and a second selection circuit that connects any one of the third and fourth capacitive elements to the downstream node. This produces an effect of holding the reset level and the signal level of each of two pixels.

[0012] Further, in the first aspect, the first upstream circuit can include a first photoelectric conversion element, a first upstream transfer transistor that transfers charge from the first photoelectric conversion element to a first floating diffusion layer, a first reset transistor that initializes the first floating diffusion layer, and a first upstream amplification transistor that amplifies a voltage of the first floating diffusion layer, and the second upstream circuit can include a second photoelectric conversion element, a second upstream transfer transistor that transfers charge from the second photoelectric conversion element to a second floating diffusion layer, a second reset transistor that initializes the second floating diffusion layer, and a second upstream amplification transistor that amplifies a voltage of the second floating diffusion layer. This produces an effect of holding a level corresponding to the voltage of the floating diffusion layer.

[0013] Further, in the first aspect, the first upstream circuit can further include a first current source transistor connected to a first upstream node, the second upstream circuit can further include a second current source transistor connected to a second upstream node, the first upstream amplification transistor can amplify the voltage of the first floating diffusion layer and output the amplified voltage to the first upstream node, the second upstream amplification transistor can amplify the voltage of the second floating diffusion layer and output the amplified voltage to the second upstream node, the first and second capacitive elements can have first ends commonly connected to the first upstream node and second ends connected to the first selection circuit, respectively, and the third and fourth capacitive elements can have first ends commonly connected to the second upstream node and second ends connected to the second selection circuit, respectively. This produces an effect of providing a constant current for each pixel.

[0014] Further, in the first aspect, the first and second upstream transfer transistors can transfer charge to the first and second floating diffusion layers, and at a predetermined exposure start time, the first and second reset transistors can initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers, and at a predetermined exposure end time, the first and second upstream transfer transistors can transfer charge to the first and second floating diffusion layers. This produces an effect of simultaneously exposing all pixels.

[0015] Further, in the first aspect, the selection section can sequentially perform control to connect one of the first and second capacitive elements to the downstream node, control to connect the other of the first and second capacitive elements to the downstream node, control to connect one of the third and fourth capacitive elements to the downstream node, and control to connect the other of the third and fourth capacitive elements to the downstream node. This produces the effect of sequentially reading the reset level and the signal level of each of the two pixels.

[0016] Further, in the first aspect, in a predetermined addition mode, the selection section can sequentially perform control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the downstream node, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the downstream node. This produces the effect of reading a signal obtained by pixel addition.

[0017] Further, in the first aspect, the first upstream circuit can further include a first upstream selection transistor that outputs a voltage amplified by the first upstream amplification transistor to a predetermined upstream node in accordance with a predetermined first selection signal, the second upstream circuit can further include a second upstream selection transistor that outputs a voltage amplified by the second upstream amplification transistor to the upstream node in accordance with a predetermined second selection signal, and a current source transistor connected to the upstream node, the first and second capacitive elements can each have a first terminal commonly connected to the upstream node and a second terminal connected to the first selection circuit, and the third and fourth capacitive elements can each have a first terminal commonly connected to the upstream node and a second terminal connected to the second selection circuit. This produces the effect of the current source transistor being shared by the two pixels.

[0018] Further, in the first aspect, the first upstream selection transistor and the second upstream selection transistor can be sequentially turned to the closed state immediately before a predetermined exposure end time and after the exposure end time, the first reset transistor can initialize the first floating diffusion layer when the first upstream selection transistor is in the closed state, the second reset transistor can initialize the second floating diffusion layer when the second upstream selection transistor is in the closed state, the first upstream selection transistor and the second upstream selection transistor can be sequentially turned to the closed state immediately after the exposure end time, and the first upstream transfer transistor and the second upstream transfer transistor can transfer the charge at the predetermined exposure end time. This generates the effect of simultaneously exposing all the pixels in a configuration in which the current source transistor is shared by two pixels.

[0019] Further, in the first aspect, a short-circuit transistor that opens and closes a path between the first downstream node and the second downstream node can be provided, the predetermined number of capacitive elements can include a first capacitive element, a second capacitive element, a third capacitive element, a fourth capacitive element, a fifth capacitive element, a sixth capacitive element, a seventh capacitive element, and an eighth capacitive element, and the selection section can include a first selection circuit that connects either of the first capacitive element and the second capacitive element to the first downstream node, a second selection circuit that connects either of the third capacitive element and the fourth capacitive element to the first downstream node, a third selection circuit that connects either of the fifth capacitive element and the sixth capacitive element to the second downstream node, and a fourth selection circuit that connects either of the seventh capacitive element and the eighth capacitive element to the second downstream node. This generates the effect of short-circuiting the first downstream node and the second downstream node.

[0020] Further, in the first aspect, the short-circuit transistor can be in the open state in a predetermined non-adding mode, and in the non-adding mode, the selection section can perform control to sequentially connect each of the first capacitive element and the second capacitive element to the first downstream node, control to sequentially connect each of the third capacitive element and the fourth capacitive element to the first downstream node, control to sequentially connect each of the fifth capacitive element and the sixth capacitive element to the second downstream node, and control to sequentially connect each of the seventh capacitive element and the eighth capacitive element to the second downstream node in a predetermined order. This generates the effect of sequentially reading the reset level and the signal level of each of the four pixels in the non-adding mode.

[0021] Further, in the first aspect, the short-circuit transistor can be in a closed state in a predetermined adding mode, and in the adding mode, the selection section can sequentially perform control of connecting one of the fifth and sixth capacitive elements and one of the seventh and eighth capacitive elements to the second downstream node and simultaneously connecting one of the first and second capacitive elements and one of the third and fourth capacitive elements to the first downstream node; and control of connecting the other of the fifth and sixth capacitive elements and the other of the seventh and eighth capacitive elements to the second downstream node and simultaneously connecting the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the first downstream node. This results in an effect of adding four pixels in a pixel adding mode.

[0022] Further, in the first aspect, the predetermined number of capacitive elements can include first and second capacitive elements and a third capacitive element; the upstream circuit block can include a first photoelectric conversion element; a first upstream transfer transistor that transfers charge from the first photoelectric conversion element to a predetermined floating diffusion layer; a second photoelectric conversion element; a second upstream transfer transistor that transfers charge from the second photoelectric conversion element to the predetermined floating diffusion layer; a reset transistor that initializes the floating diffusion layer; and an upstream amplification transistor that amplifies a voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node; and the first and second capacitive elements and the third capacitive element can have first ends commonly connected to the upstream node and second ends connected to the selection section, respectively. This results in an effect of holding the reset level and the plurality of signal levels.

[0023] Further, in the first aspect, the first and second upstream transfer transistors can transfer charge to the floating diffusion layer at a predetermined exposure start timing, and the reset transistor can initialize the first and second photoelectric conversion elements together with the floating diffusion layer; and the first and second upstream transfer transistors can sequentially transfer charge to the floating diffusion layer at a predetermined exposure end timing. This results in an effect of exposing all pixels.

[0024] Further, in the first aspect, the selection section can sequentially perform control to connect one of the first and second capacitor elements to the downstream node, control to connect the other of the first and second capacitor elements to the downstream node, and control to connect the third capacitor element to the downstream node. This results in the effect of sequentially reading the reset level and the plurality of signal levels.

[0025] Further, in the first aspect, the upstream circuit block can be provided on a first chip, and the predetermined number of capacitor elements, the selection section, the downstream reset transistor, and the downstream circuit can be provided on a second chip. This results in the effect of facilitating pixel miniaturization.

[0026] Further, in the first aspect, an analog-digital converter that sequentially converts the output reset level and the output plurality of signal levels into digital signals can also be provided, and the analog-digital converter can be provided on the second chip. This results in the effect of facilitating pixel miniaturization.

[0027] Further, in the first aspect, an analog-digital converter that sequentially converts the output reset level and the output plurality of signal levels into digital signals can also be provided, and the analog-digital converter can be provided on the third chip. This results in the effect of facilitating pixel miniaturization.

[0028] Further, a second aspect of the present technology relates to an imaging device including: a predetermined number of capacitor elements; an upstream circuit block that generates a predetermined reset level and each of a plurality of signal levels that respectively correspond to exposure amounts, and causes capacitor elements that are different from each other to hold the reset level and the plurality of signal levels; a selection section that sequentially performs control to connect a capacitor element that holds the reset level among the predetermined number of capacitor elements to a predetermined downstream node, control to disconnect the predetermined number of capacitor elements from the predetermined downstream node, and control to connect a capacitor element that holds any one of the plurality of signal levels among the predetermined number of capacitor elements to the downstream node; a downstream reset transistor that initializes a level of the downstream node in a case where the predetermined number of capacitor elements are disconnected from the downstream node; a downstream circuit that sequentially reads each of the reset level and the plurality of signal levels via the downstream node; and a signal processing circuit that sequentially converts the reset level and the plurality of signal levels into digital signals and processes the digital signals. This results in the effect of generating image data with reduced kTC noise.

[0029] Further, the third aspect of the present technology relates to a solid-state imaging device including: a first photoelectric conversion element that converts incident light into electric charges; a second photoelectric conversion element that converts incident light into electric charges; an upstream amplification transistor that converts the electric charges into a voltage; a predetermined number of capacitance elements each having a first end connected to an upstream node that is a destination of an output of the upstream amplification transistor; a predetermined number of selection transistors inserted in each path between a second end of each of the predetermined number of capacitance elements and a predetermined downstream node; a reset transistor having a source or a drain connected to the downstream node; and a downstream amplification transistor having a gate connected to the downstream node and outputting a pixel signal. This produces an effect of reducing kTC noise. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a block diagram illustrating a configuration example of an imaging device of the first embodiment of the present technology.

[0031] Figure 2 is a block diagram illustrating a configuration example of a solid-state imaging device of the first embodiment of the present technology.

[0032] Figure 3 is a circuit diagram illustrating a configuration example of a pixel block of the first embodiment of the present technology.

[0033] Figure 4 is a circuit diagram illustrating a configuration example of an upstream circuit and a selection circuit of the first embodiment of the present technology.

[0034] Figure 5 is a block diagram illustrating a configuration example of a column signal processing circuit of the first embodiment of the present technology.

[0035] Figure 6 is a timing chart illustrating an example of a global shutter operation of the first embodiment of the present technology.

[0036] Figure 7 is a timing chart illustrating an example of a read operation of a first pixel of a pixel block of the first embodiment of the present technology.

[0037] Figure 8 is a timing chart illustrating an example of a read operation of a second pixel of a pixel block of the first embodiment of the present technology.

[0038] Figure 9 is a circuit diagram illustrating a configuration example of a pixel of a comparative example.

[0039] Figure 10 is a diagram illustrating an example of a state of a pixel block of the first embodiment of the present technology when reading a reset level and initializing a downstream node.

[0040] Figure 11 is a diagram showing a state example of a pixel block of the first embodiment of the present technology at the time of reading a signal level.

[0041] Figure 12 is a flowchart showing an operation example of the solid-state imaging device of the first embodiment of the present technology.

[0042] Figure 13 is a timing chart showing an operation example of reading a reset level operation and a signal level in the first modified example of the first embodiment of the present technology.

[0043] Figure 14 is a diagram showing an example of a stacked structure of the solid-state imaging device of the second modified example of the first embodiment of the present technology.

[0044] Figure 15 is a circuit diagram showing a configuration example of a pixel block of the second modified example of the first embodiment of the present technology.

[0045] Figure 16 is a diagram showing an example of a stacked structure of the solid-state imaging device of the third modified example of the first embodiment of the present technology.

[0046] Figure 17 is a plan view showing a configuration example of a pixel array section of the second embodiment of the present technology.

[0047] Figure 18 is a circuit diagram showing a configuration example of a pixel block of the second embodiment of the present technology.

[0048] Figure 19 is a circuit diagram showing a configuration example of an upstream circuit and a selection circuit of the second embodiment of the present technology.

[0049] Figure 20 is a timing chart showing an example of a read operation of a first pixel and a second pixel of a pixel block of the second embodiment of the present technology.

[0050] Figure 21 is a timing chart showing an example of a read operation of a third pixel and a fourth pixel of a pixel block of the second embodiment of the present technology.

[0051] Figure 22 is a timing chart showing an example of a read operation in an addition mode of the second embodiment of the present technology.

[0052] Figure 23 is a circuit diagram showing a configuration example of a pixel block of the third embodiment of the present technology.

[0053] Figure 24 is a timing chart showing an example of a global shutter operation of the third embodiment of the present technology.

[0054] Figure 25 is a timing chart showing a control example immediately after exposure just ends, of the third embodiment of the present technology.

[0055] Figure 26 is a circuit diagram showing a configuration example of a pixel block of the fourth embodiment of the present technology.

[0056] Figure 27 is a timing chart showing an example of a global shutter operation of the fourth embodiment of the present technology.

[0057] Figure 28 is a timing chart showing an example of an operation of reading a reset level and a signal level of the fourth embodiment of the present technology.

[0058] Figure 29 is a block diagram showing a schematic configuration example of a vehicle control system.

[0059] Figure 30 is an explanatory diagram showing an example of a mounting position of an imaging section. DETAILED DESCRIPTION

[0060] Hereinafter, a mode for implementing the present technology (hereinafter, referred to as an embodiment) will be explained. The mode will be shown in the following order.

[0061] 1. First embodiment (example of holding a reset level and a signal level in multiple capacitors)

[0062] 2. Second embodiment (example of holding a reset level and a signal level in multiple capacitors and downstream nodes being short-circuited)

[0063] 3. Third embodiment (example of holding a reset level and a signal level in multiple capacitors and sharing a current source)

[0064] 4. Fourth embodiment (example of holding a reset level in one capacitor and holding a signal level in multiple capacitors)

[0065] 5. Application example applied to a mobile body

[0066] <1. First embodiment>

[0067] [Configuration example of imaging device]

[0068] Figure 1is a block diagram showing a configuration example of an imaging device 100 of the first embodiment of the present technology. The imaging device 100 is a device that images image data, and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control section 130. As the imaging device 100, a digital camera or an electronic device (a smartphone, a personal computer, or the like) having an imaging function is assumed.

[0069] The solid-state imaging element 200 images the image data under the control of the imaging control section 130. The solid-state imaging element 200 supplies the image data to the recording unit 120 via a signal line 209.

[0070] The imaging lens 110 collects light and guides the light to the solid-state imaging element 200. The imaging control section 130 controls the solid-state imaging element 200 to image the image data. The imaging control section 130 supplies an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139, for example. The recording unit 120 records the image data.

[0071] Here, the vertical synchronization signal VSYNC is a signal indicating an imaging timing, and as the vertical synchronization signal VSYNC, a period signal of a constant frequency (such as 60 Hz or the like) is used.

[0072] Incidentally, the imaging device 100 records the image data, and can transmit the image data to the outside of the imaging device 100. In this case, an external interface configured to transmit the image data is also provided. Alternatively, the imaging device 100 can also display the image data. In this case, a display section is also provided.

[0073] [Configuration Example of Solid-State Imaging Element]

[0074] Figure 2 is a block diagram showing a configuration example of the solid-state imaging element 200 of the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array section 220, a plurality of pixel blocks 300 are arranged in a two-dimensional grid pattern. In each of the pixel blocks 300, a plurality of pixels (for example, two pixels) are arranged. Further, each of the circuits in the solid-state imaging element 200 is provided on, for example, a single semiconductor chip.

[0075] Hereinafter, the pixel block 300 or the pixel group arranged along the horizontal direction will be referred to as a "row", and the pixel block 300 or the pixel group arranged along a direction perpendicular to the row will be referred to as a "column".

[0076] The timing control circuit 212 controls the operation timing of each of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control section 130.

[0077] The DAC 213 generates a ramp signal in a sawtooth waveform shape through digital-analog (DA) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0078] The vertical scanning circuit 211 selects and drives the rows in turn and outputs an analog pixel signal. The pixel photoelectrically converts incident light to generate the analog pixel signal. The pixel supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0079] In the load MOS circuit block 250, a MOS transistor that supplies a constant current is provided for each column.

[0080] The column signal processing circuit 260 performs signal processing such as AD conversion processing and correlated double sampling (CDS) processing on the pixel signal of each column. The column signal processing circuit 260 supplies image data including the processed signal to the recording unit 120. Incidentally, the column signal processing circuit 260 is an example of the signal processing circuit described in the claims.

[0081] [Configuration Example of Pixel Block]

[0082] Figure 3 is a circuit diagram that shows a configuration example of a pixel block 300 of the first embodiment of the present technology. In the pixel block 300, an upstream circuit block 305, a capacitor element 331, a capacitor element 332, a capacitor element 336, and a capacitor element 337, a selection section 340, a downstream reset transistor 361, and a downstream circuit 370 are arranged. As the capacitor element 331, the capacitor element 332, the capacitor element 336, and the capacitor element 337, for example, a capacitor having a metal-insulator-metal (MIM) structure is used.

[0083] Incidentally, the capacitor element 331 and the capacitor element 332 are examples of the first capacitor element and the second capacitor element described in the claims, and the capacitor element 336 and the capacitor element 337 are examples of the third capacitor element and the fourth capacitor element described in the claims.

[0084] Further, in the upstream circuit block 305, an upstream circuit 310 and an upstream circuit 320 are arranged. In the selection section 340, a selection circuit 350 and a selection circuit 355 are arranged. The downstream circuit 370 includes a downstream amplification transistor 371 and a downstream selection transistor 372.

[0085] The upstream circuit 310 generates a reset level and a signal level in turn, and holds the reset level and the signal level to the capacitor element 331 and the capacitor element 332. The upstream circuit 320 generates a reset level and a signal level in turn, and holds the reset level and the signal level to the capacitor element 336 and the capacitor element 337. Incidentally, the upstream circuit 310 is an example of the first upstream circuit according to the claim, and the upstream circuit 320 is an example of the second upstream circuit according to the claim.

[0086] The selection circuit 350 connects one of the capacitor element 331 and the capacitor element 332 to the downstream node 360. The selection circuit 355 connects one of the capacitor element 336 and the capacitor element 337 to the downstream node 360. Incidentally, the selection circuit 350 is an example of the first selection circuit according to the claim, and the selection circuit 355 is an example of the second selection circuit according to the claim.

[0087] Figure 4 is a circuit diagram showing a configuration example of the upstream circuit 310 and the upstream circuit 320 and the selection circuit 350 and the selection circuit 355 of the first embodiment of the present technology.

[0088] The upstream circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a floating diffusion (FD) reset transistor 313, an FD 314, an upstream amplification transistor 315, and a current source transistor 316.

[0089] Further, the upstream circuit 320 includes a photoelectric conversion element 321, a transfer transistor 322, an FD reset transistor 323, an FD 324, an upstream amplification transistor 325, and a current source transistor 326.

[0090] The photoelectric conversion element 311 and the photoelectric conversion element 321 generate charges by photoelectric conversion. The transfer transistor 312 transfers the charges from the photoelectric conversion element 311 to the FD 314 according to a transfer signal trg1 from the vertical scanning circuit 211. The transfer transistor 322 transfers the charges from the photoelectric conversion element 321 to the FD 324 according to a transfer signal trg2 from the vertical scanning circuit 211.

[0091] Incidentally, the photoelectric conversion element 311 and the photoelectric conversion element 321 are examples of the first photoelectric conversion element and the second photoelectric conversion element according to the claim. The transfer transistor 312 and the transfer transistor 322 are examples of the first transfer transistor and the second transfer transistor according to the claim.

[0092] The FD reset transistor 313 extracts and initializes the charge from the FD 314 according to an FD reset signal rstl from the vertical scanning circuit 211. The FD reset transistor 323 extracts and initializes the charge from the FD 324 according to an FD reset signal rst2 from the vertical scanning circuit 211. The FD 314 and the FD 324 accumulate the charges and generate voltages corresponding to the amounts of the charges, respectively.

[0093] Incidentally, the FD reset transistor 313 and the FD reset transistor 323 are examples of the first reset transistor and the second reset transistor according to the claim. The FD 314 and the FD 324 are examples of the first floating diffusion layer and the second floating diffusion layer according to the claim.

[0094] The upstream amplification transistor 315 amplifies the voltage level of the FD 314 and outputs the amplified voltage to an upstream node 330. The upstream amplification transistor 325 amplifies the voltage level of the FD 324 and outputs the amplified voltage to an upstream node 335. Incidentally, the upstream amplification transistor 315 and the upstream amplification transistor 325 are examples of the first upstream amplification transistor and the second upstream amplification transistor according to the claim.

[0095] The drains of the FD reset transistor 313 and the FD reset transistor 323 and the upstream amplification transistor 315 and the upstream amplification transistor 325 are connected to a power supply voltage VDD. A current source transistor 316 is connected to the source of the upstream amplification transistor 315. The current source transistor 316 supplies a current idl 1 under the control of the vertical scanning circuit 211. A current source transistor 326 is connected to the source of the upstream amplification transistor 325. The current source transistor 326 supplies a current idl 2 under the control of the vertical scanning circuit 211.

[0096] Incidentally, the current source transistor 316 and the current source transistor 326 are examples of the first current source transistor and the second current source transistor according to the claim.

[0097] The capacitor element 331 and the capacitor element 332 have one ends commonly connected to the upstream node 330 and the other ends connected to a selection circuit 350. The capacitor element 336 and the capacitor element 337 have one ends commonly connected to the upstream node 335 and the other ends connected to a selection circuit 355.

[0098] The selection circuit 350 includes a selection transistor 351 and a selection transistor 352. The selection transistor 351 turns on and off a path between the capacitor element 331 and a downstream node 360 according to a selection signal Φrl from the vertical scanning circuit 211. The selection transistor 352 turns on and off a path between the capacitor element 332 and the downstream node 360 according to a selection signal Φsl from the vertical scanning circuit 211.

[0099] The selection circuit 355 includes a selection transistor 356 and a selection transistor 357. The selection transistor 356 turns on and off a path between the capacitive element 336 and the downstream node 360 in accordance with a selection signal Φr2 from the vertical scanning circuit 211. The selection transistor 357 turns on and off a path between the capacitive element 337 and the downstream node 360 in accordance with a selection signal Φs2 from the vertical scanning circuit 211.

[0100] The downstream reset transistor 361 initializes the level of the downstream node 360 to a predetermined potential Vreg in accordance with a downstream reset signal rstb from the vertical scanning circuit 211. As the potential Vreg, a potential different from the power supply potential VDD (for example, a potential lower than VDD) is set.

[0101] In the downstream circuit 370, a downstream amplification transistor 371 amplifies the level of the downstream node 360. A downstream selection transistor 372 outputs a signal of the level amplified by the downstream amplification transistor 371 as a pixel signal to the vertical signal line 309 in accordance with a downstream selection signal selb from the vertical scanning circuit 211.

[0102] Incidentally, for example, in the pixel block 300, n-channel metal oxide semiconductor (nMOS) transistors are used as various transistors (the transfer transistor 312 and the like).

[0103] The above-described circuit including the upstream circuit 310, the capacitive element 331 and the capacitive element 332, the selection circuit 350, the downstream reset transistor 361, and the downstream circuit 370 functions as one pixel. Further, the circuit including the upstream circuit 320, the capacitive element 336 and the capacitive element 337, the selection circuit 355, the downstream reset transistor 361, and the downstream circuit 370 also functions as one pixel. These two pixels share the downstream reset transistor 361 and the downstream circuit 370.

[0104] Further, for example, two pixels of the pixel block 300 are arranged in the column direction. In other words, these two pixels are arranged in odd-numbered rows and even-numbered rows. Incidentally, the positional relationship between the two pixels of the pixel block 300 is not limited to odd-numbered rows and even-numbered rows. For example, the two pixels can also be arranged in odd-numbered columns and even-numbered columns. Alternatively, one of the two pixels can be arranged obliquely above the other.

[0105] When exposure is started, the vertical scanning circuit 211 supplies the high-level FD reset signal (rst1 or rst2) and the high-level transfer signal (trg1 or trg2) to all rows. Thus, the photoelectric conversion element (311 or 321) is initialized. Hereinafter, this control is referred to as "PD reset".

[0106] Then, the vertical scanning circuit 211 supplies the high-level FD reset signals rst1 and rst2 for all the rows in a pulse period while setting the downstream reset signal rstb and the selection signals Φr1 and Φr2 to high levels just before the end of exposure. Thus, the FDs 314 and 324 are initialized, and at this time, levels corresponding to the levels of the FDs 314 and 324 are held in the capacitance elements 331 and 336. Hereinafter, this control is referred to as "FD reset".

[0107] The levels of the FDs 314 and 324 at the time of the FD reset and the levels corresponding to these levels (the levels held in the capacitance elements 331 and 336 and the level of the vertical signal line 309) are collectively referred to as "P-phase" or "reset level" hereinafter.

[0108] When the exposure ends, the vertical scanning circuit 211 supplies the high-level transfer signals trg1 and trg2 for all the rows in a pulse period while setting the downstream reset signal rstb and the selection signals Φs1 and Φs2 to high levels. Thus, the signal charges corresponding to the exposure amounts are transferred to the FDs 314 and 324, and at this time, levels corresponding to the levels of the FDs 314 and 324 are held in the capacitance elements 332 and 337, respectively.

[0109] The levels of the FDs 314 and 324 at the time of the transfer of the signal charges and the levels corresponding to these levels (the levels held in the capacitance elements 332 and 337 and the level of the vertical signal line 309) are collectively referred to as "D-phase" or "signal level" hereinafter.

[0110] This exposure control that starts and ends exposure of all the pixels at the same time is referred to as a global shutter system. This exposure control causes the upstream circuit 310 of all the pixels to generate the reset level and the signal level in turn. The reset level is held in the capacitance elements 331 and 336, and the signal level is held in the capacitance elements 332 and 337.

[0111] After the end of exposure, the vertical scanning circuit 211 selects the rows in turn and outputs the reset level and the signal level of the row in turn. When the reset level is to be output, the vertical scanning circuit 211 supplies the high-level selection signal Φr1 or the high-level selection signal Φr2 for a predetermined period while setting the FD reset signal rst1 or the FD reset signal rst2 of the selected row and the downstream selection signal selb to high levels. Thus, the capacitance element 331 or the capacitance element 336 is connected to the downstream node 360, and thereby the reset level is read.

[0112] After reading the reset level, the vertical scanning circuit 211 supplies a high-level downstream reset signal rstb during a pulse period while making the FD reset signal rstl or the FD reset signal rst2 and the downstream selection signal selb of the selected row high. Thus, the level of the downstream node 360 is initialized. At this time, the selection transistor 351, the selection transistor 352, the selection transistor 356, and the selection transistor 357 are in an open state, and the capacitor element 331, the capacitor element 332, the capacitor element 336, and the capacitor element 337 are disconnected from the downstream node 360.

[0113] After the downstream node 360 is initialized, the vertical scanning circuit 211 supplies a high-level selection signal Φsl or a high-level selection signal Φs2 during a predetermined period while keeping the FD reset signal (rstl or rst2) and the downstream selection signal selb of the selected row high. Thus, the capacitor element 332 or the capacitor element 337 is connected to the downstream node 360, and a signal level is read.

[0114] Under the above read control, the selection circuit 350 of the selected row sequentially performs the control to connect the capacitor element 331 to the downstream node 360, the control to disconnect the capacitor element 331 and the capacitor element 332 from the downstream node 360, and the control to connect the capacitor element 332 to the downstream node 360.

[0115] Further, the selection circuit 355 of the selected row sequentially performs the control to connect the capacitor element 336 to the downstream node 360, the control to disconnect the capacitor element 336 and the capacitor element 337 from the downstream node 360, and the control to connect the capacitor element 337 to the downstream node 360.

[0116] Further, when the capacitor element 331, the capacitor element 332, the capacitor element 336, and the capacitor element 337 are disconnected from the downstream node 360, the downstream reset transistor 361 of the selected row initializes the level of the downstream node 360. Further, the downstream circuit 370 of the selected row sequentially reads the reset level and the signal level from the capacitor element 331 and the capacitor element 332 (or the capacitor element 336 and the capacitor element 337) via the downstream node 360 and outputs the read reset level and signal level to the vertical signal line 309.

[0117] [Configuration example of column signal processing circuit]

[0118] Figure 5 is a block diagram illustrating a configuration example of the column signal processing circuit 260 of the first embodiment of the present technology.

[0119] In the load MOS circuit block 250, a vertical signal line 309 is wired for each column of the pixel block 300. When the number of columns is I (I is an integer), I vertical signal lines 309 are wired. Further, a load MOS transistor 251 that supplies a constant current id2 is connected to each vertical signal line 309.

[0120] In the column signal processing circuit 260, a plurality of ADCs 261 and a digital signal processing section 262 are arranged. The ADC 261 is arranged for each column. When the number of columns is I, I ADCs 261 are arranged.

[0121] The ADC 261 converts an analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing section 262. For example, a single slope ADC including a comparator and a counter is arranged as the ADC 261.

[0122] The digital signal processing section 262 performs predetermined signal processing such as CDS processing on each digital signal of each column. The digital signal processing section 262 supplies image data including the processed digital signal to the recording unit 120.

[0123] [Operation Example of Solid-state Imaging Device]

[0124] Figure 6 is a timing chart showing an example of a global shutter operation of the first embodiment of the present technology. From a time T0 immediately before the start of exposure to a time T1 after the passage of a pulse period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst1 and the high-level FD reset signal rst2 and the high-level transfer signal trg1 and the high-level transfer signal trg2 to all rows (in other words, all pixels). Therefore, all pixels undergo PD reset, and exposure starts at the same time in all rows.

[0125] Here, rst1_[n], rst2_[n], trg1_[n], and trg2_[n] in the figure represent signals with respect to the nth row of pixels in N rows. N is an integer representing the total number of rows in which the pixel block 300 is arranged, and n is an integer from 1 to N. In a case where two pixels of the pixel block 300 are pixels of an even row and a pixel of an odd row, the nth row of the pixel block 300 includes two rows, that is, an odd row and an even row.

[0126] At a time T2 immediately before the end of the exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signals rst1 and rst2 for the pulse period in all the rows, while setting the downstream reset signal rstb and the selection signals Φr1 and Φr2 to the high level. Thus, all the pixels are subjected to the FD reset, and the reset level is sampled and held. Here, rstb_[n], Φr1_[n], and Φr2_[n] in the figure represent signals with respect to the nth row of pixels.

[0127] At a time T3 after the time T2, the vertical scanning circuit 211 returns the selection signals Φr1 and Φr2 to the low level.

[0128] At an exposure end time T4, the vertical scanning circuit 211 supplies the high-level transfer signals trg1 and trg2 for the pulse period, while setting the downstream reset signal rstb and the selection signals Φs1 and Φs2 to the high level in all the rows. Thus, the signal level is sampled and held. Further, Φs1_[n] and Φs2_[n] in the figure represent signals with respect to the nth row of pixels.

[0129] At a time T5 after the time T4, the vertical scanning circuit 211 returns the selection signals Φs1 and Φs2 to the low level.

[0130] Figure 7 Fig. 14 is a timing chart showing an example of a read operation of the first pixel of the pixel block 300 of the first embodiment of the present technology. The vertical scanning circuit 211 sets the FD reset signals rst1 and rst2 and the downstream selection signal selb of the nth row to the high level in the read period of the nth row from a time T10. Further, the downstream reset signal rstb of all the rows is controlled to the low level at the time T10. Here, selb_[n] in the figure represents a signal with respect to the nth row of pixels.

[0131] The vertical scanning circuit 211 supplies the high-level selection signal Φr1 to the nth row for a period from a time T11 immediately after the time T10 to a time T12. The potential of the downstream node 360 becomes the reset level Vrst1. The ADC 261 performs AD conversion on the reset level.

[0132] The vertical scanning circuit 211 supplies the high-level downstream reset signal rstb to the nth row for a pulse period from a time T13 immediately after the time T12. Thus, when there is a parasitic capacitance in the downstream node 360, it is possible to erase the history of the previous signal held in the parasitic capacitance.

[0133] The vertical scanning circuit 211 supplies a high-level selection signal Φs1 to the n-th row during a period from a time T14 immediately after the initialization of the downstream node 360 to a time T15. The potential of the downstream node 360 becomes a signal level Vsig1. The ADC 261 performs AD conversion on this signal level. The difference between the reset level Vrst1 and the signal level Vsig1 corresponds to a net signal level from which the reset noise and the offset noise of the FD have been removed.

[0134] Figure 8 is a timing chart showing an example of a read operation of the second pixel of the pixel block 300 of the first embodiment of the present technology.

[0135] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb to the n-th row during a pulse period from a time T16 immediately after the time T15.

[0136] The vertical scanning circuit 211 supplies a high-level selection signal Φr2 to the n-th row during a period from a time T17 immediately after the initialization of the downstream node 360 to a time T18. The potential of the downstream node 360 becomes a reset level Vrst2. The ADC 261 performs AD conversion on this reset level.

[0137] The vertical scanning circuit 211 supplies a high-level downstream reset signal rstb to the n-th row during a pulse period from a time T19 immediately after the time T18.

[0138] The vertical scanning circuit 211 supplies a high-level selection signal Φs2 to the n-th row during a period from a time T20 immediately after the initialization of the downstream node 360 to a time T21. The potential of the downstream node 360 becomes a signal level Vsig2. The ADC 261 performs AD conversion on this signal level.

[0139] Further, at the time T21, the vertical scanning circuit 211 returns the FD reset signal rst1 and the FD reset signal rst2 and the downstream selection signal selb of the n-th row to the low level.

[0140] As shown in Figure 7 and Figure 8 , the high-level selection signal Φr1, the high-level selection signal Φs1, the high-level selection signal Φr2, and the high-level selection signal Φs2 are supplied in order. According to these selection signals, the selection section 340 connects the capacitive element 331, the capacitive element 332, the capacitive element 336, and the capacitive element 337 to the downstream node 360 in order. Then, the reset level Vrst1 and the signal level Vsig1 of the first pixel and the reset level Vrst2 and the signal level Vsig2 of the second pixel of the pixel block 300 are read in order.

[0141] Incidentally, the solid-state imaging device 200 reads the signal level after reading the reset level, but is not limited to this order. The solid-state imaging device 200 can also read the reset level after reading the signal level. In this case, the vertical scanning circuit 211 supplies the high-level selection signal Φr after supplying the high-level selection signal Φs. Further, in this case, it is necessary to reverse the inclination of the slope of the ramp signal.

[0142] Figure 9 is a circuit diagram showing a configuration example of a pixel of a comparative example. In the comparative example, the selection circuit 350 is not provided, and a transfer transistor is inserted between the upstream node 330 and the upstream circuit. Further, instead of the capacitor element 331 and the capacitor element 332, a capacitor Cl and a capacitor C2 are inserted. The capacitor Cl is inserted between the upstream node 330 and a ground terminal, and the capacitor C2 is inserted between the upstream node 330 and the downstream node 360.

[0143] For example, exposure control and read control of the pixel of the comparative example are explained in Non-Patent Literature 1 Figure 5 .5.2. In the comparative example, it is assumed that the capacitance value of each of the capacitor Cl, the capacitor C2 is C, then the level Vn of the kTC noise at the time of exposure and read is represented by the following formula.

[0144] Vn = (3 * kT / C) 1 / 2 ... Formula 1

[0145] In the above formula, k is the Boltzmann constant, and the unit is, for example, Joule / Kelvin (J / K). T is the absolute temperature, and the unit is, for example, Kelvin (K). Further, the unit of Vn is, for example, Volt (V), and the unit of C is, for example, Farad (F).

[0146] Figure 10 is a diagram showing a state example of the pixel block in the first embodiment of the present technology when reading the reset level and initializing the downstream node. In the diagram, a indicates the state of the pixel block 300 when reading the reset level, and b in the diagram indicates the state of the pixel block 300 when initializing the downstream node 360. Further, in the diagram, for convenience of explanation, the selection transistor 351, the selection transistor 352, and the downstream reset transistor 361 are represented by the graphical symbol of a switch.

[0147] As shown in a of the diagram, the vertical scanning circuit 211 sets the selection transistor 351 to the closed state, and sets the selection transistor 352 and the downstream reset transistor 361 to the open state. Therefore, the reset level of the first pixel is read via the downstream circuit 370.

[0148] As shown in b of the drawing, after reading the reset level, the vertical scanning circuit 211 sets the selection transistor 351 and the selection transistor 352 to the open state, and sets the downstream reset transistor 361 to the closed state. Thus, the capacitor elements 331 and 332 are disconnected from the downstream node 360, and the level of the downstream node 360 is initialized.

[0149] In this way, the capacitance value of the parasitic capacitance Cp of the downstream node 360 in the disconnected state with the capacitor elements 331 and 332 is set to be much smaller than the capacitance values of the capacitor elements 331 and 332. For example, assuming that the parasitic capacitance Cp is several femtofarad (fF), the capacitor elements 331 and 332 are approximately the level of several tens of femtofarad.

[0150] Figure 11 is a drawing illustrating an example of the state of the pixel block 300 at the read signal level of the first embodiment of the present technology.

[0151] After the initialization of the downstream node 360, the vertical scanning circuit 211 sets the selection transistor 352 to the closed state, and sets the selection transistor 351 and the downstream reset transistor 361 to the open state. Thus, the signal level of the first pixel is read via the downstream circuit 370.

[0152] Here, the kTC noise at the time of pixel exposure is considered. At the time of exposure, the kTC noise occurs in each of the sampling of the reset level and the sampling of the signal level immediately before the end of exposure. Assuming that the capacitance value of each of the capacitor elements 331 and 332 is C, the level Vn of the kTC noise at the time of exposure is represented by the following equation.

[0153] Vn = (2 * kT / C) 1 / 2 ... Equation 2

[0154] Further, at the time of reading as shown in Figure 10 and Figure 11 The downstream reset transistor 361 is driven, and thus the kTC noise occurs at this time. However, the capacitor elements 331 and 332 are disconnected at the time of driving the downstream reset transistor 361, and the parasitic capacitance Cp at this time is small. Thus, the kTC noise at the time of reading can be ignored in comparison with the kTC noise at the time of exposure. Thus, the kTC noises at the time of exposure and the time of reading are represented by Equation 2.

[0155] According to Equations 1 and 2, the kTC noise in the pixel block 300 in which the capacitor is disconnected at the time of reading is smaller than the kTC noise of the comparative example in which the capacitor is not disconnected at the time of reading. Thus, it is possible to improve the image quality of the image data.

[0156] Further, since two pixels of the pixel block 300 share the downstream reset transistor 361 and the downstream circuit 370, the circuit scale of the pixel array unit 220 can be reduced as compared with a case where the downstream reset transistor 361 and the downstream circuit 370 are not shared. Incidentally, the number of pixels to be shared is not limited to two pixels. Three or more pixels can also share the downstream reset transistor 361 and the downstream circuit 370.

[0157] Figure 12 FIG. 10 is a flowchart illustrating an example of an operation of the solid-state imaging device 200 of the first embodiment of the present technology. This operation is started, for example, when a predetermined application for imaging image data is executed.

[0158] The vertical scanning circuit 211 exposes all pixels (step S901). Then, the vertical scanning circuit 211 selects a row of the pixel block 300 to be read (step S902). The column signal processing circuit 260 reads the reset level of the first pixel of the pixel block 300 of the row (step S903), and then reads the signal level of the pixel (step S904). Next, the column signal processing circuit 260 reads the reset level of the second pixel (step S905), and then reads the signal level of the pixel (step S906).

[0159] The solid-state imaging device 200 determines whether the reading of all rows has been completed (step S907). In a case where the reading of all rows has not been completed (step S907: No), the solid-state imaging device 200 repeats step S902 and subsequent steps. On the other hand, in a case where the reading of all rows has been completed (step S907: Yes), the solid-state imaging device 200 performs a CDS process and the like, and ends the imaging operation. In a case where a plurality of image data is continuously shot, steps S901 to S907 are repeatedly performed in synchronization with a vertical synchronization signal.

[0160] In this way, in the first embodiment of the present technology, the downstream reset transistor 361 initializes the downstream node 360 when the selection circuit 350 disconnects the capacitance element 331 and the capacitance element 332 from the downstream node 360. Since the capacitance element 331 and the capacitance element 332 are disconnected, the level of the reset noise caused by the driving of the downstream reset transistor 361 becomes a level corresponding to a parasitic capacitance smaller than its own capacitance. This noise reduction can improve the image quality of the image data.

[0161] Further, since two pixels share the downstream reset transistor 361 and the downstream circuit 370, the circuit scale of the pixel array unit 220 can be reduced as compared with a case where the downstream reset transistor 361 and the downstream circuit 370 are not shared.

[0162] [First Modification Example]

[0163] Although the solid-state imaging device 200 sequentially reads the respective pixel signals of the two pixels of the pixel block 300 in the above-described first embodiment, there is a possibility that the reading speed is insufficient in this configuration. The solid-state imaging device 200 of the first modification of the first embodiment differs from the first embodiment in that pixel addition is performed.

[0164] Figure 13 is a timing chart illustrating an operation example of reading the reset level and the signal level in the first modification of the first embodiment of the present technology. In the solid-state imaging device 200 of the first modification of the first embodiment, either of a plurality of modes including a non-addition mode in which pixel addition is not performed and an addition mode in which pixel addition is performed is set. The global shutter operation and the reading operation in the non-addition mode are similar to those of the first embodiment. The global shutter operation in the addition mode is similar to that in the non-addition mode.

[0165] As illustrated, in a case where reading is performed in the addition mode, the vertical scanning circuit 211 supplies the high-level FD reset signal rst1 and the high-level FD reset signal rst2 in a pulse period at a time T10 at which reading of the nth row is started. Further, the vertical scanning circuit 211 sets the downstream selection signal selb to the high level during a reading period from the time T10 to a time T15.

[0166] The vertical scanning circuit 211 supplies the high-level selection signal Φr1 and the high-level selection signal Φr2 to the nth row during a period from a time T11 immediately after the time T10 to a time T12. Accordingly, the potential of the downstream node 360 becomes the reset level Vrst. The reset level Vrst is a value obtained by adding the reset levels of the two pixels of the pixel block 300.

[0167] The vertical scanning circuit 211 supplies the high-level downstream reset signal rstb to the nth row in a pulse period from a time T13 immediately after the time T12.

[0168] The vertical scanning circuit 211 supplies the high-level selection signal Φs1 and the high-level selection signal Φs2 to the nth row during a period from the time T14 immediately after the initialization of the downstream node 360 to the time T15. Accordingly, the potential of the downstream node 360 becomes the signal level Vsig. The signal level Vsig is a value obtained by adding the signal levels of the two pixels of the pixel block 300.

[0169] As illustrated, the high-level selection signal Φr1 and the high-level selection signal Φr2 are supplied, and the selection section 340 connects the capacitance element 331 and the capacitance element 336 to the downstream node 360 in accordance with these selection signals. In other words, the capacitance element 331 and the capacitance element 336 are short-circuited. Thus, the reset levels of the two pixels are added. Further, the high-level selection signal Φs1 and the high-level selection signal Φs2 are supplied, and the selection section 340 connects the capacitance element 332 and the capacitance element 337 to the downstream node 360 in accordance with these selection signals. In other words, the capacitance element 332 and the capacitance element 337 are short-circuited. Thus, the signal levels of the two pixels are added. By this pixel addition, the sensitivity and the reading speed can be improved compared to the case where no addition is performed. Further, the number of rows to be read is reduced by the pixel addition, and thus the power consumption can be reduced.

[0170] Incidentally, the solid-state imaging device 200 reads the signal level after reading the reset level, but is not limited to this order, and can also read the reset level after reading the signal level.

[0171] In this way, according to the first modification of the first embodiment of the present technology, since the selection section 340 connects the capacitance element 331 and the capacitance element 336 to the downstream node 360, and connects the capacitance element 332 and the capacitance element 337 to the downstream node 360, it is possible to add the pixel signals of the two pixels respectively. Thus, the sensitivity and the reading speed can be improved compared to the case where no addition is performed, and the power consumption can be reduced.

[0172] [Second Modification]

[0173] Although the circuit of the solid-state imaging device 200 in the above-described first embodiment is provided on a single semiconductor chip, when miniaturizing the pixel in this configuration, there is a possibility that the element does not fit on the semiconductor chip. The solid-state imaging device 200 of the second modification of the first embodiment is different from the first embodiment in that the circuit of the solid-state imaging device 200 is arranged dispersedly on two semiconductor chips.

[0174] Figure 14 is a drawing illustrating an example of the stacked structure of the solid-state imaging device 200 of the second modification of the first embodiment of the present technology. The solid-state imaging device 200 of the second modification of the first embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Incidentally, in addition to Cu-Cu bonding, connection can also be made by a via or a bump.

[0175] The upper pixel array section 221 is arranged on the upper pixel chip 201. The lower pixel array section 222 and the column signal processing circuit 260 are arranged on the lower pixel chip 202. As for each pixel in the pixel array section 220, a part thereof is arranged in the upper pixel array section 221, and the remaining part thereof is arranged in the lower pixel array section 222.

[0176] Further, the vertical scanning circuit 211, the timing control circuit 212, the DAC 213, and the load MOS circuit block 250 are also arranged on the lower pixel chip 202. These circuits are not shown in the figure.

[0177] Further, the upper pixel chip 201 is manufactured, for example, by a pixel-specific process, and the lower pixel chip 202 is manufactured, for example, by a complementary MOS (CMOS) process. Incidentally, the upper pixel chip 201 is an example of the first chip recited in the claims, and the lower pixel chip 202 is an example of the second chip recited in the claims.

[0178] Figure 15 is a circuit diagram showing a configuration example of the pixel block 300 of the second modification example of the first embodiment of the present technology. In the pixel block 300, the upstream circuit block 305 is configured on the upper pixel chip 201, and other circuits and elements such as the capacitor element 331 and the capacitor element 332 are configured on the lower pixel chip 202. Incidentally, the current source transistor 316 and the current source transistor 326 can also be arranged on the lower pixel chip 202. Since the elements of the pixel block 300 are arranged in a scattered manner on the stacked upper pixel chip 201 and lower pixel chip 202 as shown in the figure, it is possible to reduce the area of the pixel, and facilitate pixel miniaturization.

[0179] In this way, since the circuits and elements of the pixel block 300 are arranged in a scattered manner on the two semiconductor chips according to the second modification example of the first embodiment of the present technology, it is possible to facilitate pixel miniaturization.

[0180] [Third Modification Example]

[0181] In the second modification example of the above-described first embodiment, a part of the pixel block 300 and the peripheral circuit such as the column signal processing circuit 260 are provided on the lower lower pixel chip 202. However, in this configuration, the arrangement area of the circuits and elements on the lower pixel chip 202 side is larger than that of the upper pixel chip 201 by the peripheral circuit, and thus there is a possibility that unnecessary space not containing the circuits and elements is generated in the upper pixel chip 201. The solid-state imaging device 200 of the third modification example of the first embodiment differs from the solid-state imaging device 200 of the second modification example of the first embodiment in that the circuits of the solid-state imaging device 200 are arranged in a scattered manner on three semiconductor chips.

[0182] Figure 16 FIG. 20 is a diagram showing an example of a stack structure of a solid-state imaging device 200 of a third modification of the first embodiment of the present technology. The solid-state imaging device 200 of the third modification of the first embodiment includes an upper pixel chip 201, a lower pixel chip 202, and a circuit chip 203. These chips are stacked and electrically connected, for example, by Cu-Cu bonding. Incidentally, in addition to Cu-Cu bonding, connection can be made by a via or a bump.

[0183] An upper pixel array section 221 is arranged on the upper pixel chip 201. A lower pixel array section 222 is arranged on the lower pixel chip 202. As for each pixel of the pixel array section 220, a part thereof is arranged in the upper pixel array section 221, and the remaining part thereof is arranged in the lower pixel array section 222.

[0184] Further, a column signal processing circuit 260, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are arranged on the circuit chip 203. The circuits other than the column signal processing circuit 260 are not illustrated in the figure.

[0185] Incidentally, the upper pixel chip 201 is an example of the first chip according to the claim, and the lower pixel chip 202 is an example of the second chip according to the claim. The circuit chip 203 is an example of the third chip according to the claim.

[0186] Since a three-layer configuration as shown in the figure is adopted, compared with a two-layer configuration, it is possible to reduce unnecessary space and further miniaturize the pixel. Further, the lower pixel chip 204 of the second layer can be manufactured by a dedicated process for a capacitor or a switch.

[0187] In this way, since the circuits of the solid-state imaging device 200 are dispersedly arranged on the three semiconductor chips of the third modification of the first embodiment of the present technology, compared with a case where the circuits are dispersedly arranged on two semiconductor chips, it is possible to further miniaturize the pixel.

[0188] <2. Second Embodiment>

[0189] Although in the above-described first embodiment the solid-state imaging device 200 sequentially reads each pixel signal of two pixels of the pixel block 300, in this configuration there is a possibility that the reading speed is insufficient. The solid-state imaging device 200 of the second embodiment differs from the solid-state imaging device 200 of the first embodiment in that pixel addition is performed.

[0190] Figure 17is a plan view showing a configuration example of the pixel array section 220 of the second embodiment of the present technology. In this drawing, a is a plan view showing an example of the pixel array section 220 in a Bayer array. In this drawing, b is a plan view showing an example of the pixel array section 220 in a Quadra-Bayer array.

[0191] As shown in a of this drawing, red (R), green (G), and blue (B) pixels are arranged in a Bayer array of the pixel array section 220 of the second embodiment. The solid-state imaging device 200 can add pixel signals of the R pixel 301 and R pixels 302 to 304 in the vicinity thereof among these pixels. Similarly, for G pixels and B pixels, the solid-state imaging device 200 can add respective pixel signals of four adjacent pixels.

[0192] Incidentally, instead of the Bayer array, the pixels can be arranged in a Quadra-Bayer array as shown in b of this drawing. In the Quadra-Bayer array, four pixels of the same color are arranged adjacent to each other in 2 rows x 2 columns. Then, with four R pixels in view, four B pixels are arranged to the right and below the R pixels, and four G pixels are arranged to the right and below the R pixels. The solid-state imaging device 200 can add pixel signals of the adjacent four pixels of the same color (pixel 301 to pixel 304, and so on) among these pixels.

[0193] Incidentally, the array of the pixels is not limited to the Bayer array or the Quadra-Bayer array. For example, R, G, B, and W (white) pixels can also be arranged.

[0194] Figure 18 is a circuit diagram showing a configuration example of the pixel block 300 of the second embodiment of the present technology. In the pixel block 300 of the second embodiment, four pixels to be added when performing pixel addition are arranged. For example, Figure 17 The pixels 301 to 304 of are arranged in the pixel block 300.

[0195] The pixel block 300 of the second embodiment is further provided with the capacitance element 431, the capacitance element 432, the capacitance element 436, and the capacitance element 437, the short-circuit transistor 480, the downstream reset transistor 461, and the downstream circuit 470. Further, in the second embodiment, the upstream circuit 410 and the upstream circuit 420 are further arranged in the upstream circuit block 305, and the selection circuit 450 and the selection circuit 455 are further arranged in the selection section 340. The vertical scanning circuit 211 supplies the downstream reset signal rstbl to the downstream reset transistor 361, and supplies the downstream reset signal rstb2 to the downstream reset transistor 461.

[0196] In the downstream circuit 470, a downstream amplification transistor 471 and a downstream selection transistor 472 are arranged. For example, nMOS transistors are used as these transistors. In addition, the circuit configuration of the downstream reset transistor 461 and the downstream circuit 470 is similar to that of the downstream reset transistor 361 and the downstream circuit 370. The downstream circuit 370 and the downstream circuit 470 are connected to the same vertical signal line 309. The vertical scanning circuit 211 supplies a downstream selection signal selb1 to the downstream selection transistor 372 and a downstream selection signal selb2 to the downstream selection transistor 472.

[0197] The upstream circuit 410 generates a reset level and a signal level in turn, and causes the capacitor element 431 and the capacitor element 432 to hold the reset level and the signal level. The upstream circuit 420 generates a reset level and a signal level in turn, and causes the capacitor element 436 and the capacitor element 437 to hold the reset level and the signal level. Incidentally, the capacitor element 431 and the capacitor element 432 are examples of the fifth capacitor element and the sixth capacitor element described in the claims, and the capacitor element 436 and the capacitor element 437 are examples of the seventh capacitor element and the eighth capacitor element described in the claims.

[0198] In addition, the selection circuit 450 connects either of the capacitor element 431 and the capacitor element 432 to the downstream node 460, and the selection circuit 455 connects either of the capacitor element 436 and the capacitor element 437 to the downstream node 460. Incidentally, the selection circuit 450 is an example of the third selection circuit described in the claims, and the selection circuit 455 is an example of the fourth selection circuit described in the claims. In addition, the downstream node 360 is an example of the first downstream node described in the claims, and the downstream node 460 is an example of the second downstream node described in the claims.

[0199] The short-circuit transistor 480 opens and closes a path between the downstream node 360 and the downstream node 460 in accordance with a short-circuit signal sht from the vertical scanning circuit 211. For example, an nMOS transistor is used as the short-circuit transistor 480.

[0200] Figure 19 is a circuit diagram showing a configuration example of the upstream circuit 410 and the upstream circuit 420 and the selection circuit 450 and the selection circuit 455 of the second embodiment of the present technology.

[0201] The upstream circuit 410 includes a photoelectric conversion element 411, a transfer transistor 412, an FD reset transistor 413, an FD 414, an upstream amplification transistor 415, and a current source transistor 416. The vertical scanning circuit 211 supplies a transfer signal trg3 and an FD reset signal rst3 to the transfer transistor 412 and the FD reset transistor 413.

[0202] Further, the upstream circuit 420 includes a photoelectric conversion element 421, a transfer transistor 422, an FD reset transistor 423, an FD 424, an upstream amplification transistor 425, and a current source transistor 426. The vertical scanning circuit 211 supplies a transfer signal trg4 and an FD reset signal rst4 to the transfer transistor 422 and the FD reset transistor 423.

[0203] The selection circuit 450 includes a selection transistor 451 and a selection transistor 452, and the selection circuit 455 includes a selection transistor 456 and a selection transistor 457. The vertical scanning circuit 211 supplies a selection signal Φr3 and a selection signal Φs3 to the selection transistor 451 and the selection transistor 452, and supplies a selection signal Φr4 and a selection signal Φs4 to the selection transistor 456 and the selection transistor 457.

[0204] The circuit configurations of the upstream circuit 410 and the upstream circuit 420 are similar to those of the upstream circuit 310 and the upstream circuit 320. Further, the circuit configurations of the selection circuit 450 and the selection circuit 455 are similar to those of the selection circuit 350 and the selection circuit 355.

[0205] Figure 20 is a timing chart showing an example of a read operation of the first pixel and the second pixel of the pixel block 300 of the second embodiment of the present technology. In the solid-state imaging device 200 of the second embodiment, any one of a plurality of modes including a non-addition mode in which pixel addition is not performed and an addition mode in which pixel addition is performed is set. The global shutter operation and the read operation in the non-addition mode are similar to those of the first embodiment. The global shutter operation in the addition mode is similar to that in the non-addition mode.

[0206] In the non-addition mode, the vertical scanning circuit 211 sets the short-circuit signal sht to a low level. Further, at a time T10 at which reading of the nth row of the pixel block 300 is started, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 to a high level. Further, during a period from the time T10 to a time T18, the vertical scanning circuit 211 sets the downstream selection signal selb1 to a high level and sets the downstream selection signal selb2 to a low level.

[0207] Further, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstb1 in a pulse period from the time T10 to a time T11, and supplies the high-level selection signal Φr1 during a period from the time T11 to a time T12. During this period, the reset level Vrst1 of the first pixel is read via the vertical signal line 309.

[0208] In the pulse period from time T12 to time T13, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstbl, and supplies the high-level selection signal Φsl during the period from time T13 to time T14. During this period, the signal level Vsigl of the first pixel is read via the vertical signal line 309.

[0209] Next, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstbl in the pulse period from time T14 to time T15, and supplies the high-level selection signal Φr2 during the period from time T15 to time T16. During this period, the reset level Vrst2 of the second pixel is read via the vertical signal line 309.

[0210] The vertical scanning circuit 211 supplies the high-level downstream reset signal rstbl in the pulse period from time T16 to time T17, and supplies the high-level selection signal Φs2 during the period from time T17 to time T18. During this period, the signal level Vsig2 of the second pixel is read via the vertical signal line 309.

[0211] Figure 21 is a timing chart showing an example of a read operation of the third pixel and the fourth pixel of the pixel block 300 of the second embodiment of the present technology.

[0212] The vertical scanning circuit 211 sets the downstream selection signal selbl to the low level and sets the downstream selection signal selb2 to the high level during the period from time T18 to time T26.

[0213] Further, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstb2 in the pulse period from time T18 to time T19, and supplies the high-level selection signal Φr3 during the period from time T19 to time T20. During this period, the reset level Vrst3 of the third pixel is read via the vertical signal line 309.

[0214] The vertical scanning circuit 211 supplies the high-level downstream reset signal rstb2 in the pulse period from time T20 to time T21, and supplies the high-level selection signal Φs3 during the period from time T21 to time T22. During this period, the signal level Vsig3 of the third pixel is read via the vertical signal line 309.

[0215] Next, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstb2 in the pulse period from time T22 to time T23, and supplies the high-level selection signal Φr4 during the period from time T23 to time T24. During this period, the reset level Vrst4 of the fourth pixel is read via the vertical signal line 309.

[0216] The vertical scanning circuit 211 supplies the high-level downstream reset signal rstb2 for the pulse period from the time T24 to the time T25, and supplies the high-level selection signal Φs4 for the period from the time T25 to the time T26. During this period, the signal level Vsig4 of the fourth pixel is read via the vertical signal line 309.

[0217] Further, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 to the low level at the time T26 when the reading of the nth row is completed.

[0218] As shown in FIG. 17, the short-circuit transistor 480 is controlled to the open-circuit state in the non-addition mode. Further, the capacitor elements 331 and 332 are connected to the downstream node 360 in turn, and the reset level and the signal level of the first pixel are read out in turn. The capacitor elements 336 and 337 are connected to the downstream node 360 in turn, and the reset level and the signal level of the second pixel are read out in turn. Next, the capacitor elements 431 and 432 are connected to the downstream node 460 in turn, and the reset and signal levels of the third pixel are read in turn. The capacitor elements 436 and 437 are connected to the downstream node 460 in turn, and the reset level and the signal level of the fourth pixel are read in turn. In this way, the reset level and the signal level of each of the four pixels of the pixel block 300 are read in turn. Figure 20 Figure 21 As shown in FIG. 17, the short-circuit transistor 480 is controlled to the open-circuit state in the non-addition mode. Further, the capacitor elements 331 and 332 are connected to the downstream node 360 in turn, and the reset level and the signal level of the first pixel are read out in turn. The capacitor elements 336 and 337 are connected to the downstream node 360 in turn, and the reset level and the signal level of the second pixel are read out in turn. Next, the capacitor elements 431 and 432 are connected to the downstream node 460 in turn, and the reset and signal levels of the third pixel are read in turn. The capacitor elements 436 and 437 are connected to the downstream node 460 in turn, and the reset level and the signal level of the fourth pixel are read in turn. In this way, the reset level and the signal level of each of the four pixels of the pixel block 300 are read in turn.

[0219] Figure 22 is a timing chart showing an example of the read operation in the addition mode of the second embodiment of the present technology. In the addition mode, the vertical scanning circuit 211 sets the short-circuit signal sht to the high level. During the period from the time T10 to the time T14 at which the nth row of the pixel block 300 is read, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 and the downstream selection signals selb1 and selb2 to the high level.

[0220] Further, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstb1 and the high-level downstream reset signal rstb2 for the pulse period from the time T10 to the time T11, and supplies the high-level selection signals Φr1 to Φr4 for the period from the time T11 to the time T12. During this period, the reset level Vrst is read via the vertical signal line 309. The reset level Vrst is a value obtained by adding the reset levels of the four pixels of the pixel block 300.

[0221] ​Next, in the pulse period from time T12 to time T13, the vertical scanning circuit 211 supplies the high-level downstream reset signal rstbl and the high-level downstream reset signal rstb2, and supplies the high-level selection signal Φsl to the high-level selection signal Φs4 during the period from time T13 to time T14. During this period, the signal level Vsig is read via the vertical signal line 309. The signal level Vsig is a value obtained by adding the signal levels of the four pixels of the pixel block 300.

[0222] Here, by increasing the number of pixels sharing the downstream circuit 370 to four in the pixel block 300 of the first embodiment, it is possible to add four pixels. However, an increase in the number of pixels sharing the downstream circuit 370 can cause adverse effects. When the number of pixels sharing the downstream circuit 370 is four, the wiring of the downstream node 360 extends across four pixels, and the parasitic capacitance of the downstream node 360 is increased. Due to the increase in the parasitic capacitance, the signal gain in the case where pixel addition is not performed is reduced. This is because the parasitic capacitance reduces the voltage held in the capacitor element 331 and the capacitor element 332 when connected to the downstream node 360. This reduction in the gain causes a reduction in the signal-to-noise (SN) ratio.

[0223] On the other hand, in the second embodiment provided with the short-circuit transistor 480, by placing the short-circuit transistor 480 in an open state in the non-addition mode, it is possible to set the number of pixels of each of the shared downstream circuit 370 and the downstream circuit 470 to two pixels. Therefore, compared to the case where the downstream circuit 370 is shared by four pixels, it is possible to suppress an increase in the parasitic capacitance of the downstream node. With this configuration, it is possible to realize pixel addition of two or more pixels while suppressing a reduction in the SN ratio in the non-addition mode.

[0224] Incidentally, Figure 18 The downstream circuit 370 and the downstream circuit 470 of the illustrated pixel block 300 share a single vertical signal line 309, but the present application is not limited to this configuration. It is also possible to arrange a vertical signal line 309-1 and a vertical signal line 309-2, connect the downstream circuit 370 to the vertical signal line 309-1, and connect the downstream circuit 470 to the vertical signal line 309-2. In this case, it is necessary to double the number of load MOS transistors 251 and the number of ADCs 261 of the downstream stage according to the number of wirings of the vertical signal lines. In place of this, it is possible to simultaneously read one of the two pixels sharing the downstream circuit 370 and one of the two pixels sharing the downstream circuit 470 in the non-addition mode, and thus it is possible to improve the reading speed. Furthermore, in the addition mode, only one of the vertical signal line 309-1 and the vertical signal line 309-2 is used, and the load MOS transistor 251 corresponding to the other is controlled to be in an off state.

[0225] Incidentally, the first to third modifications of the first embodiment can also be applied to the second embodiment.

[0226] In this way, since the short-circuit transistor 480 short-circuits the downstream node 360 and the downstream node 460 according to the second embodiment of the present technology, the pixel block 300 is able to add the respective pixel signals of the four pixels. Therefore, compared to the case where addition is not performed, it is possible to improve the sensitivity and the reading speed, and to reduce the power consumption.

[0227] <3. Third Embodiment>

[0228] Although a current source transistor (316 and 326) is arranged for each pixel in the above-described first embodiment, there is a possibility that the miniaturization of the pixel becomes difficult in this configuration. The solid-state imaging device 200 of the third embodiment differs from the first embodiment in that a plurality of pixels share a current source transistor.

[0229] Figure 23 is a circuit diagram showing a configuration example of the pixel block 300 of the third embodiment of the present technology. The pixel block 300 of the third embodiment differs from the first embodiment in that an upstream selection transistor 317 and an upstream selection transistor 327 are further provided, and a current source transistor 316 is not provided.

[0230] The upstream selection transistor 317 outputs the voltage amplified by the upstream amplification transistor 315 to the upstream node 338 according to an upstream selection signal sel1 from the vertical scanning circuit 211. The upstream selection transistor 327 outputs the voltage amplified by the upstream amplification transistor 325 to the upstream node 338 according to an upstream selection signal sel2 from the vertical scanning circuit 211. Further, the current source transistor 326 is connected to the upstream node 338.

[0231] Further, the capacitance element 331, the capacitance element 332, the capacitance element 336, and the capacitance element 337 have one end commonly connected to the upstream node 339 and the other end connected to the selection circuit 350 and the selection circuit 355. The upstream node 339 is connected to the upstream node 338.

[0232] Further, the circuits and elements of the solid-state imaging device 200 are arranged on the upper pixel chip 201 and the lower pixel chip 202 in a scattered manner. For example, the upstream circuit 310 and the upstream circuit 320 are arranged on the upper pixel chip 201, and the circuits at the downstream stage thereof are arranged on the lower pixel chip 202. Further, the upstream node 338 and the upstream node 339 are connected by Cu-Cu connection or the like.

[0233] In the first embodiment in which a current source transistor is arranged for each pixel, when a stacked structure is formed, it is necessary to, for example,Figure 15 Cu-Cu connection is performed for each pixel. In particular, in a case where the capacitor element 331 having an MIM structure or the like is arranged on the lower pixel chip 202, the thickness of the chip increases, and the surfaces connecting the upper and lower chips become difficult to planarize, and thus the pitch of the Cu-Cu connection is limited. For example, the pitch of the Cu-Cu connection is several micrometers (μm), whereas the size of a fine pixel of a mobile image sensor is less than one micrometer (μm). Therefore, in a configuration where the current source transistor is arranged for each pixel, miniaturization becomes difficult.

[0234] On the other hand, in a configuration where the current source transistor 326 is shared by two pixels, the number of Cu-Cu connections can be reduced. Therefore, pixel miniaturization is facilitated. Further, the current during a global shutter operation can be reduced. Further, the current source transistor 326 is typically adopted in a cascade configuration to suppress a current variation due to a channel length modulation effect of the transistor. Since the current source transistor 326 having a large size is shared, the area of the transistor can be reduced.

[0235] Incidentally, the current source transistor 326 is shared by two pixels, but the number of pixels to be shared is not limited to two pixels and can be three or more pixels.

[0236] Figure 24 is a timing chart showing an example of a global shutter operation of the third embodiment of the present technology. From a time T0 immediately before the start of exposure to a time T1 at which the pulse period ends, the vertical scanning circuit 211 supplies the high-level FD reset signal rst1 and the high-level FD reset signal rst2 and the high-level transfer signal trg1 and the high-level transfer signal trg2 to all rows. Therefore, all pixels undergo PD reset, and exposure starts simultaneously in all rows.

[0237] During a period from a time T2 immediately before the end of exposure to a time T5, the vertical scanning circuit 211 sets the upstream selection signal sel1 of all rows to the high level. At a time T3 within the period, in all rows, the vertical scanning circuit 211 supplies the high-level FD reset signal rst1 within the pulse period while setting the downstream reset signal rstb and the selection signal Φr1 to the high level. Therefore, the first pixel of the pixel block 300 undergoes FD reset, and the reset level is sampled and held.

[0238] At time T4, the vertical scanning circuit 211 returns the selection signal Φr1 to the low level. Further, during a period from time T5 to time T8, the vertical scanning circuit 211 sets the upstream selection signal sel1 of all the rows to the low level and sets the upstream selection signal sel2 to the high level. At time T6 during the period, the vertical scanning circuit 211 supplies the FD reset signal rst2 of the high level within the pulse period while setting the downstream reset signal rstb and the selection signal Φr2 of all the rows to the high level. Thus, the second pixel of the pixel block 300 is subjected to the FD reset, and the reset level is sampled and held.

[0239] Then, the vertical scanning circuit 211 returns the selection signal Φr2 of all the rows to the low level at time T7, sets the upstream selection signal sel2 to the low level, and sets the upstream selection signal sel1 to the high level at time T8.

[0240] Here, sel1_[n] and sel2_[n] in the drawing indicate signals to the nth row pixel.

[0241] As shown in the drawing, immediately before the end of exposure, the vertical scanning circuit 211 sequentially sets the upstream selection transistor 317 and the upstream selection transistor 327 to the closed state. Then, the FD reset transistor 313 performs the FD reset while the upstream selection transistor 317 is in the closed state, and the FD reset transistor 323 performs the FD reset while the upstream selection transistor 327 is in the closed state.

[0242] Figure 25 is a timing chart showing a control example immediately after the end of exposure of the third embodiment of the present technology. At the end of exposure time T9, the vertical scanning circuit 211 supplies the high level transfer signal trg1 and the high level transfer signal trg2 of the pulse period in all the rows.

[0243] Then, during a period from time T10 to time T11, the vertical scanning circuit 211 sets the selection signal Φs1 to the high level in all the rows. Thus, the signal level of the first pixel of the pixel block 300 is sampled and held.

[0244] At time T12, the vertical scanning circuit 211 sets the upstream selection signal sel1 of all the rows to the low level and sets the upstream selection signal sel2 to the high level.

[0245] Then, during a period from time T13 to time T14, the vertical scanning circuit 211 sets the selection signal Φs2 to the high level in all the rows. Thus, the signal level of the second pixel of the pixel block 300 is sampled and held.

[0246] The vertical scanning circuit 211 returns the upstream selection signal sel2 of all the rows to the low level at time T15.

[0247] As shown in the drawing, the vertical scanning circuit 211 sequentially sets the upstream selection transistor 317 and the upstream selection transistor 327 to the closed state at the end of exposure. Then, the vertical scanning circuit 211 causes the transfer transistor 312 and the transfer transistor 322 to transfer the charge at the end of exposure, and then sequentially sets the upstream selection transistor 317 and the upstream selection transistor 327 to the closed state.

[0248] Incidentally, the first modification and the third modification of the first embodiment and the second embodiment can be applied to the third embodiment.

[0249] In this way, since two pixels share the current source transistor 326 according to the third embodiment of the present technology, it is possible to reduce the number of Cu-Cu connections between chips. Thus, it is easy to downsize the pixels.

[0250] <4. Fourth Embodiment>

[0251] Although one pair of capacitors is arranged for each pixel in the above-described first embodiment, downsizing of the pixels is difficult in this configuration. The solid-state imaging device 200 of the fourth embodiment differs from the first embodiment in that the number of capacitors is reduced.

[0252] Figure 26 is a circuit diagram showing a configuration example of a pixel block 300 of the fourth embodiment of the present technology. In the pixel block 300 of the fourth embodiment, an upstream circuit block 305, a capacitor element 331 and a capacitor element 332, a capacitor element 531, a capacitor element 532, and a capacitor element 533, a selection section 340, a downstream reset transistor 361, and a downstream circuit 370 are arranged. In the pixel block 300 of the fourth embodiment, four pixels are arranged. For example, the pixels 301 to 304 are arranged in the pixel block 300. Figure 17

[0253] The upstream circuit block 305 includes the photoelectric conversion element 311, the photoelectric conversion element 511, the photoelectric conversion element 512, and the photoelectric conversion element 513, the transfer transistor 312, and the transfer transistor 514, the transfer transistor 515, and the transfer transistor 516. Further, the upstream circuit block 305 includes the FD reset transistor 313, the FD 314, the upstream amplification transistor 315, and the current source transistor 316. For example, nMOS transistors are used as the transfer transistor 312, the transfer transistor 514, the transfer transistor 515, and the transfer transistor 516.

[0254] ​Further, the selection portion 340 includes the selection transistor 351 and the selection transistor 352, and the selection transistor 551, the selection transistor 552, and the selection transistor 553. For example, nMOS transistors are used as the selection transistor 551, the selection transistor 552, and the selection transistor 553.

[0255] The connection configuration of the photoelectric conversion element 311, the transfer transistor 312, the FD reset transistor 313, the FD 314, the upstream amplification transistor 315, and the current source transistor 316 of the fourth embodiment is similar to those of the first embodiment. However, the FD reset signal rst from the vertical scanning circuit 211 is input to the FD reset transistor 313.

[0256] The photoelectric conversion elements 511 to 513 generate charges by photoelectric conversion. The transfer transistor 514 transfers the charges from the photoelectric conversion element 511 to the FD 314 in accordance with the transfer signal trg2 from the vertical scanning circuit 211. The transfer transistor 515 transfers the charges from the photoelectric conversion element 512 to the FD 314 in accordance with the transfer signal trg3 from the vertical scanning circuit 211. The transfer transistor 516 transfers the charges from the photoelectric conversion element 513 to the FD 314 in accordance with the transfer signal trg4 from the vertical scanning circuit 211.

[0257] The connection configuration between the capacitive elements 331 and 332 and the selection transistors 351 and 352 of the fourth embodiment is similar to those of the first embodiment. However, the selection signal Φr from the vertical scanning circuit 211 is input to the selection transistor 351.

[0258] The capacitive elements 531, 532, and 533 have one end commonly connected to the upstream node 330 and the other end connected to the selection portion 340.

[0259] The selection transistor 551 opens and breaks the path between the capacitive element 531 and the downstream node 360 in accordance with the selection signal Φs2 from the vertical scanning circuit 211. The selection transistor 552 opens and breaks the path between the capacitive element 532 and the downstream node 360 in accordance with the selection signal Φs3 from the vertical scanning circuit 211. The selection transistor 553 opens and breaks the path between the capacitive element 533 and the downstream node 360 in accordance with the selection signal Φs4 from the vertical scanning circuit 211.

[0260] The circuit configuration of the downstream reset transistor 361 and the downstream circuit 370 of the fourth embodiment is similar to those of the first embodiment.

[0261] Furthermore, the circuitry and components of the solid-state imaging element 200 are distributed across the upper pixel chip 201 and the lower pixel chip 202. For example, the upstream circuit block 305 is disposed on the upper pixel chip 201, and its downstream circuitry is disposed on the lower pixel chip 202.

[0262] like Figure 26 As shown, the four pixels share a single FD 314, downstream reset transistor 361, and downstream circuit 370. Furthermore, the reset level of the four pixels is maintained in capacitor element 331, and the signal levels of the four pixels are maintained in capacitor elements 332, 531, 532, and 533, respectively. Although in the first embodiment, capacitors configured to maintain the reset level need to be arranged for each pixel, in the fourth embodiment, since the capacitors are shared by the four pixels, the number of capacitors can be reduced. Therefore, pixel miniaturization is facilitated compared to the case where capacitors are not shared.

[0263] Incidentally, FD 314, etc., is shared by four pixels, but the number of shared pixels is not limited to four. Furthermore, capacitor elements 331 and 332 are examples of the first and second capacitor elements described in the claims. Capacitor elements 531, 532, and 533 are examples of the third capacitor element described in the claims.

[0264] Figure 27 This is a timing diagram illustrating an example of global shutter operation according to the fourth embodiment of the present technology. During the period from exposure start time T0 to time T4, the vertical scan circuit 211 supplies a high-level FD reset signal rst to all rows. At times T0, T1, T2, and T3 within this period, the vertical scan circuit 211 supplies transmission signals trg1, trg2, trg3, and trg4 to all rows within a pulse period. Therefore, all pixels undergo PD reset.

[0265] Then, during the period from the end of exposure T5 to T15, the vertical scan circuit 211 supplies a high-level downstream reset signal rstb to all rows. Furthermore, at time T5, the vertical scan circuit 211 supplies an FD reset signal rst to all rows within a pulse period. Immediately following time T5, at time T6, the vertical scan circuit 211 supplies a selection signal Φr to all rows within a pulse period. Therefore, all rows are FD reset.

[0266] Further, at time T7, the vertical scanning circuit 211 supplies the transfer signal trg1 to all the rows for the pulse period. At time T8 immediately after time T7, the vertical scanning circuit 211 supplies the selection signal Φs1 to all the rows for the pulse period. Thus, the signal level of the first pixel of the pixel block 300 is sampled and held.

[0267] Further, at time T9, the vertical scanning circuit 211 supplies the transfer signal trg2 to all the rows for the pulse period. At time T10 immediately after time T9, the vertical scanning circuit 211 supplies the selection signal Φs2 to all the rows for the pulse period. Thus, the sum of the signal levels of the first and second pixels of the pixel block 300 is sampled and held.

[0268] Further, at time T11, the vertical scanning circuit 211 supplies the transfer signal trg3 to all the rows for the pulse period. At time T12 immediately after time T11, the vertical scanning circuit 211 supplies the selection signal Φs3 to all the rows for the pulse period. Thus, the sum of the signal levels of the first to third pixels of the pixel block 300 is sampled and held.

[0269] Further, at time T13, the vertical scanning circuit 211 supplies the transfer signal trg4 to all the rows for the pulse period. At time T14 immediately after time T13, the vertical scanning circuit 211 supplies the selection signal Φs4 to all the rows for the pulse period. Thus, the sum of the signal levels of the first to fourth pixels of the pixel block 300 is sampled and held.

[0270] Here, rst_[n] and Φr_[n] represent signals with respect to the nth row pixel among the N rows.

[0271] Since the FD 314 is shared by four pixels in the fourth embodiment, it is not possible to perform charge transfer of each of the four pixels at the same time as illustrated. However, the four capacitors (capacitive elements 332, 531, 532, and 533) as the charge transfer destinations can be sampled on the order of several microseconds (μs), and the exposure time difference between the pixels does not become too large.

[0272] Figure 28 is a timing chart illustrating an operation example of reading a reset level and a signal level of the fourth embodiment of the present technology.

[0273] During a period from time T20 to time T26 at which the nth row is read, the vertical scanning circuit 211 sets the FD reset signal rst to the high level.

[0274] Furthermore, at time T20, the vertical scan circuit 211 supplies a high-level downstream reset signal rstb to the nth row within a pulse period. Then, at time T21, immediately following time T20, the vertical scan circuit 211 supplies a high-level selection signal Φr to the nth row within a pulse period. Immediately following this control, the reset level shared by the four pixels is read via the vertical signal line 309.

[0275] Then, at time T22 after reading the reset level, the vertical scan circuit 211 supplies a high-level selection signal Φs1 to the nth row within a pulse period. Immediately following this control, the signal level Vsig1 of the first pixel is read via the vertical signal line 309. The column signal processing circuit 260 obtains the difference between the reset level Vrst and the signal level Vsig1 as the net signal level of the first pixel after CDS processing.

[0276] Then, at time T23 after reading signal level Vsig1, the vertical scan circuit 211 supplies a high-level selection signal Φs2 to the nth row within a pulse period. Immediately following this control, Vsig2 is read via vertical signal line 309. This Vsig2 corresponds to the sum of the signal levels of the first and second pixels. The column signal processing circuit 260 obtains the difference between Vsig1 and Vsig2 as the signal level of the second pixel after CDS processing.

[0277] Then, at time T24 after reading Vsig2, the vertical scan circuit 211 supplies a high-level selection signal Φs3 to the nth row within a pulse period. Immediately following this control, Vsig3 is read via the vertical signal line 309. This Vsig3 corresponds to the sum of the signal levels of the first to the third pixel. The column signal processing circuit 260 obtains the difference between Vsig2 and Vsig3 as the signal level of the third pixel after CDS processing.

[0278] Then, at time T25 after reading Vsig3, the vertical scan circuit 211 supplies a high-level selection signal Φs4 to the nth row within a pulse period. Immediately following this control, Vsig4 is read via the vertical signal line 309. This Vsig4 corresponds to the sum of the signal levels of the first to fourth pixels. The column signal processing circuit 260 obtains the difference between Vsig3 and Vsig4 as the signal level of the fourth pixel after CDS processing.

[0279] Incidentally, the third variation of the first implementation scheme can also be applied to the fourth implementation scheme.

[0280] In this way, since the capacitor element 331 that maintains the reset level in the fourth embodiment of this technology is shared by four pixels, it is easier to miniaturize pixels compared to the case where the capacitor element is not shared.

[0281] <5. Application Examples for Moving Bodies>

[0282] The technology according to the present invention (the technology) can be applied to various products. For example, the technology according to embodiments of the present invention can be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, robots, etc.

[0283] Figure 29 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present invention can be applied.

[0284] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 29 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / visual output unit 12052, and an in-vehicle network interface (I / F) 12053, which are functional components of the integrated control unit 12050, are shown.

[0285] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for devices such as internal combustion engines, drive motors, etc., which generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate vehicle braking force.

[0286] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various switches sent from a keyless entry device can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signal inputs and controls the vehicle's door locks, power windows, or lights, etc.

[0287] The vehicle exterior information detection unit 12030 detects information about the outside of the vehicle that includes the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging section 12031. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to image an image of the outside of the vehicle, and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing of detecting an object such as a person, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance to the above-described object.

[0288] The imaging section 12031 is an optical sensor that receives light and outputs an electric signal corresponding to the amount of light received. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light, or can be invisible light such as infrared rays.

[0289] The vehicle interior information detection unit 12040 detects information about the inside of the vehicle. The vehicle interior information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects a state of a driver. The driver state detection section 12041 includes, for example, a camera that captures the driver. Based on detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate a degree of fatigue of the driver or a degree of concentration of the driver, or can determine whether the driver is dozing off.

[0290] The microcomputer 12051 can calculate a control target value of a driving force generation device, a steering mechanism, or a braking device based on information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing functions of an advanced driver assistance system (ADAS) including collision avoidance or impact mitigation for the vehicle, following driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, and the like.

[0291] Furthermore, by controlling the driving force generation device, the steering mechanism, the braking device, and the like based on information about the outside or inside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform cooperative control aimed at realizing automatic driving and the like that enables the vehicle to travel autonomously without relying on an operation of a driver.

[0292] Further, based on information about the outside of the vehicle acquired by the outside information detecting unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control intended to prevent glare by controlling the headlamp to change from high beam to low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside information detecting unit 12030.

[0293] The sound image output section 12052 transmits an output signal of at least one of sound or an image to an output device capable of notifying a passenger of the vehicle or the outside of the vehicle visually or aurally. In Figure 29 Examples of the output device include an audio speaker 12061, a display section 12062, and an instrument panel 12063. The display section 12062 can include at least one of a vehicle-mounted display and a head-up display, for example.

[0294] Figure 30 FIG. 12 is a diagram showing an example of a mounting position of the imaging section 12031.

[0295] In Figure 30 The imaging section 12031 includes an imaging section 12101, an imaging section 12102, an imaging section 12103, an imaging section 12104, and an imaging section 12105, for example.

[0296] The imaging section 12101, the imaging section 12102, the imaging section 12103, the imaging section 12104, and the imaging section 12105 are provided at positions on the front nose, the side mirror, the rear bumper, and the rear door of the vehicle 12100, and a position on the upper portion of the windshield in the vehicle, for example. The imaging section 12101 provided on the front nose and the imaging section 12105 provided on the upper portion of the windshield in the vehicle mainly acquire images of the front of the vehicle 12100. The imaging section 12102 and the imaging section 12103 provided on the side mirror mainly acquire images of both sides of the vehicle 12100. The imaging section 12104 provided on the rear bumper or the rear door mainly acquires images of the rear of the vehicle 12100. The imaging section 12105 provided on the upper portion of the windshield in the vehicle is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, and the like.

[0297] Incidentally, Figure 30Examples of imaging ranges of the imaging sections 12101 to 12104 are shown. The imaging range 12111 represents an imaging range of the imaging section 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively represent imaging ranges of the imaging section 12102 and the imaging section 12103 provided at the side mirrors. The imaging range 12114 represents an imaging range of the imaging section 12104 provided on the rear bumper or the rear cover. A bird's-eye image of the vehicle 12100 viewed from above is obtained, for example, by superimposing image data imaged by the imaging sections 12101 to 12104.

[0298] At least one of the imaging sections 12101 to 12104 can have a function of acquiring distance information. For example, at least one of the imaging sections 12101 to 12104 can be a stereo camera composed of a plurality of imaging elements, or can be an imaging element having pixels for phase difference detection.

[0299] For example, based on the distance information acquired from the imaging sections 12101 to 12104, the microcomputer 12051 can determine distances of respective three-dimensional objects within the imaging ranges 12111 to 12114 and time changes of the distances (relative speeds with respect to the vehicle 12100), and thereby extract, as a preceding vehicle, the closest three-dimensional object that is particularly on a travel path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). Further, the microcomputer 12051 can set a following distance to be maintained from the preceding vehicle in advance, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control aimed at automatic driving and the like of the vehicle not depending on an operation of the driver can be performed.

[0300] For example, based on distance information acquired from the imaging sections 12101 to 12104, the microcomputer 12501 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of obstacles. For example, the microcomputer 12051 classifies obstacles around the vehicle 12100 into obstacles that can be visually recognized by a driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a case where the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or evasive steering by the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collision.

[0301] At least one of the imaging sections 12101 to 12104 can be an infrared camera that detects infrared rays. The microcomputer 12051 can recognize a pedestrian, for example, by determining whether a pedestrian is present in an image imaged by the imaging sections 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a step of extracting feature points in an image imaged by the imaging sections 12101 to 12104 as infrared cameras and a step of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. If the microcomputer 12051 determines that a pedestrian is present in an image imaged by the imaging sections 12101 to 12104 and thus recognizes a pedestrian, the sound image output section 12052 controls the display section 12062 so that a square outline for emphasis is displayed superimposed on the recognized pedestrian. The sound image output section 12052 can also control the display section 12062 so as to display an icon or the like representing a pedestrian at a desired position.

[0302] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging section 12031 in the above-described configuration. Specifically, for example, Figure 1 The imaging device 100 of Patent Literature 1 can be applied to the imaging section 12031. When the technology according to the present disclosure is applied to the imaging section 12031, kTC noise can be reduced, and an imaged image that is easier to view can be obtained, so that fatigue of a driver can be reduced.

[0303] By the way, the above-described embodiments show examples for implementing the present technology, and the content of the embodiments respectively has a correspondence with the content of the present invention specified in the claims. Similarly, the content of the present invention specified in the claims respectively has a correspondence with the content having the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and is implemented by various modifications to the embodiments within the scope of the gist thereof.

[0304] By the way, the effects described in this specification are only examples and are not limiting, and there can be other effects.

[0305] By the way, the present technology can also have the following configuration.

[0306] (1) A solid-state imaging device comprising:

[0307] a predetermined number of capacitive elements;

[0308] an upstream circuit block that generates a predetermined reset level and each of a plurality of signal levels respectively corresponding to an exposure amount, and causes the capacitive elements different from each other to hold the reset level and the plurality of signal levels;

[0309] a selection section that sequentially performs control to connect a capacitive element holding the reset level among the predetermined number of capacitive elements to a predetermined downstream node, control to disconnect the predetermined number of capacitive elements from the downstream node, and control to connect a capacitive element holding any of the plurality of signal levels among the predetermined number of capacitive elements to the downstream node;

[0310] a downstream reset transistor that initializes a level of the downstream node in a case where the predetermined number of capacitive elements are disconnected from the downstream node; and

[0311] a downstream circuit that sequentially reads each of the reset level and the plurality of signal levels via the downstream node.

[0312] (2) The solid-state imaging device according to the preceding (1), wherein,

[0313] the predetermined number of capacitive elements include a first capacitive element and a second capacitive element and a third capacitive element and a fourth capacitive element;

[0314] the upstream circuit block includes:

[0315] a first upstream circuit that sequentially generates a first reset level and a first signal level, and causes the first capacitive element and the second capacitive element to hold the first reset level and the first signal level; and

[0316] a second upstream circuit that generates a second reset level and a second signal level in sequence, and causes the third capacitive element and the fourth capacitive element to hold the second reset level and the second signal level; and

[0317] The selection section includes:

[0318] a first selection circuit that connects either of the first capacitive element and the second capacitive element to the downstream node; and

[0319] a second selection circuit that connects either of the third capacitive element and the fourth capacitive element to the downstream node.

[0320] (3) The solid-state imaging device according to the preceding (2), wherein

[0321] The first upstream circuit includes:

[0322] a first photoelectric conversion element;

[0323] a first upstream transfer transistor that transfers charge from the first photoelectric conversion element to a first floating diffusion layer;

[0324] a first reset transistor that initializes the first floating diffusion layer; and

[0325] a first upstream amplification transistor that amplifies a voltage of the first floating diffusion layer; and

[0326] The second upstream circuit includes:

[0327] a second photoelectric conversion element;

[0328] a second upstream transfer transistor that transfers charge from the second photoelectric conversion element to a second floating diffusion layer;

[0329] a second reset transistor that initializes the second floating diffusion layer; and

[0330] a second upstream amplification transistor that amplifies a voltage of the second floating diffusion layer.

[0331] (4) The solid-state imaging device according to the preceding (3), wherein

[0332] The first upstream circuit further includes a first current source transistor connected to a first upstream node;

[0333] The second upstream circuit further includes a second current source transistor connected to a second upstream node;

[0334] The first upstream amplification transistor amplifies a voltage of the first floating diffusion layer, and outputs the amplified voltage to the first upstream node.

[0335] the second upstream amplification transistor amplifies a voltage of the second floating diffusion layer and outputs the amplified voltage to the second upstream node;

[0336] the first and second capacitive elements each have a first end and a second end connected to the first selection circuit, the first ends of the first and second capacitive elements being commonly connected to the first upstream node; and

[0337] the third and fourth capacitive elements each have a first end and a second end connected to the second selection circuit, the first ends of the third and fourth capacitive elements being commonly connected to the second upstream node.

[0338] (5) The solid-state imaging device according to any one of (3) to (4) above, wherein

[0339] the first and second upstream transfer transistors transfer the electric charges to the first and second floating diffusion layers at a predetermined start-of-exposure timing, and the first and second reset transistors initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers; and

[0340] the first and second upstream transfer transistors transfer the electric charges to the first and second floating diffusion layers at a predetermined end-of-exposure timing.

[0341] (6) The solid-state imaging device according to any one of (3) to (5) above, wherein

[0342] the selection section sequentially performs: control to connect one of the first and second capacitive elements to the downstream node, control to connect the other of the first and second capacitive elements to the downstream node, control to connect one of the third and fourth capacitive elements to the downstream node, and control to connect the other of the third and fourth capacitive elements to the downstream node.

[0343] (7) The solid-state imaging device according to any one of (3) to (6) above, wherein

[0344] The selection section sequentially performs, in a predetermined addition mode, control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the downstream node, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the downstream node.

[0345] (8) The solid-state imaging device according to (3) above, wherein

[0346] The first upstream circuit further includes a first upstream selection transistor that outputs the voltage amplified by the first upstream amplification transistor to a predetermined upstream node according to a predetermined first selection signal.

[0347] The second upstream circuit includes:

[0348] a second upstream selection transistor that outputs the voltage amplified by the second upstream amplification transistor to the upstream node according to a predetermined second selection signal, and

[0349] a current source transistor connected to the upstream node.

[0350] The first and second capacitive elements each have a first terminal commonly connected to the upstream node and a second terminal connected to the first selection circuit; and

[0351] The third and fourth capacitive elements each have a first terminal commonly connected to the upstream node and a second terminal connected to the second selection circuit.

[0352] (9) The solid-state imaging device according to (8) above, wherein

[0353] The first and second upstream selection transistors sequentially transition to a closed state immediately before a predetermined end-of-exposure timing and after the end-of-exposure timing,

[0354] The first reset transistor initializes the first floating diffusion layer when the first upstream selection transistor is in the closed state.

[0355] The second reset transistor initializes the second floating diffusion layer when the second upstream selection transistor is in the closed state.

[0356] The first and second upstream selection transistors sequentially transition to a closed state immediately after the end-of-exposure timing; and

[0357] The first upstream transfer transistor and the second upstream transfer transistor transfer the electric charges at a predetermined end-of-exposure timing.

[0358] (10) The solid-state imaging device according to (1) above, further comprising:

[0359] a short-circuit transistor that opens and closes a path between the first downstream node and the second downstream node,

[0360] wherein the predetermined number of capacitive elements includes a first capacitive element, a second capacitive element, a third capacitive element, a fourth capacitive element, a fifth capacitive element, a sixth capacitive element, a seventh capacitive element, and an eighth capacitive element; and

[0361] the selection section includes:

[0362] a first selection circuit that connects either of the first capacitive element and the second capacitive element to the first downstream node;

[0363] a second selection circuit that connects either of the third capacitive element and the fourth capacitive element to the first downstream node;

[0364] a third selection circuit that connects either of the fifth capacitive element and the sixth capacitive element to the second downstream node; and

[0365] a fourth selection circuit that connects either of the seventh capacitive element and the eighth capacitive element to the second downstream node.

[0366] (11) The solid-state imaging device according to (10) above, wherein

[0367] the short-circuit transistor is in an open-circuit state in a predetermined non-addition mode, and

[0368] in the non-addition mode, the selection section performs, in a predetermined order, control to sequentially connect each of the first capacitive element and the second capacitive element to the first downstream node, control to sequentially connect each of the third capacitive element and the fourth capacitive element to the first downstream node, control to sequentially connect each of the fifth capacitive element and the sixth capacitive element to the second downstream node, and control to sequentially connect each of the seventh capacitive element and the eighth capacitive element to the second downstream node.

[0369] (12) The solid-state imaging device according to (10) or (11) above, wherein

[0370] the short-circuit transistor is in a closed-circuit state in a predetermined addition mode, and

[0371] In the addition mode, the selection section sequentially performs: control of connecting one of the fifth and sixth capacitive elements and one of the seventh and eighth capacitive elements to the second downstream node and simultaneously connecting one of the first and second capacitive elements and one of the third and fourth capacitive elements to the first downstream node; and control of connecting the other of the fifth and sixth capacitive elements and the other of the seventh and eighth capacitive elements to the second downstream node and simultaneously connecting the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the first downstream node.

[0372] (13) The solid-state imaging device according to the foregoing (1), wherein

[0373] the predetermined number of capacitive elements includes a first capacitive element and a second capacitive element and a third capacitive element;

[0374] the upstream circuit block includes:

[0375] a first photoelectric conversion element;

[0376] a first upstream transfer transistor that transfers charge from the first photoelectric conversion element to a predetermined floating diffusion layer;

[0377] a second photoelectric conversion element;

[0378] a second upstream transfer transistor that transfers charge from the second photoelectric conversion element to the predetermined floating diffusion layer;

[0379] a reset transistor that initializes the floating diffusion layer; and

[0380] an upstream amplification transistor that amplifies a voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node; and

[0381] the first capacitive element and the second capacitive element and the third capacitive element each have a first end commonly connected to the upstream node and a second end connected to the selection section.

[0382] (14) The solid-state imaging device according to the foregoing (13), wherein

[0383] the first upstream transfer transistor and the second upstream transfer transistor transfer the charge to the floating diffusion layer at a predetermined exposure start timing, and the reset transistor initializes the first photoelectric conversion element and the second photoelectric conversion element together with the floating diffusion layer; and

[0384] The first upstream transfer transistor and the second upstream transfer transistor sequentially transfer the electric charges to the floating diffusion layer at a predetermined end-of-exposure timing.

[0385] (15) The solid-state imaging device according to any one of the preceding (13) or (14), wherein

[0386] The selection section sequentially performs control to connect one of the first and second capacitor elements to the downstream node, control to connect the other of the first and second capacitor elements to the downstream node, and control to connect the third capacitor element to the downstream node.

[0387] (16) The solid-state imaging device according to any one of the preceding (1) to (15), wherein

[0388] The upstream circuit block is provided on a first chip, and

[0389] The predetermined number of capacitor elements, the selection section, the downstream reset transistor, and the downstream circuit are provided on a second chip.

[0390] (17) The solid-state imaging device according to the preceding (16), further comprising

[0391] an analog-to-digital converter that sequentially converts the output reset level and the output plurality of signal levels to digital signals,

[0392] wherein the analog-to-digital converter is provided on the second chip.

[0393] (18) The solid-state imaging device according to the preceding (16) or (17), further comprising

[0394] an analog-to-digital converter that sequentially converts the output reset level and the output plurality of signal levels to digital signals,

[0395] wherein the analog-to-digital converter is provided on a third chip.

[0396] (19) An imaging apparatus comprising:

[0397] a predetermined number of capacitor elements;

[0398] an upstream circuit block that generates a predetermined reset level and each of a plurality of signal levels respectively corresponding to exposure amounts, and causes capacitor elements different from each other to hold the reset level and the plurality of signal levels;

[0399] a selection section that sequentially performs control to connect a capacitor element that holds the reset level among the predetermined number of capacitor elements to a predetermined downstream node, control to disconnect the predetermined number of capacitor elements from the downstream node, and control to connect a capacitor element that holds any one of the plurality of signal levels among the predetermined number of capacitor elements to the downstream node;

[0400] a downstream reset transistor that initializes a level of the downstream node in a case where the predetermined number of capacitor elements are disconnected from the downstream node;

[0401] a downstream circuit that sequentially reads the reset level and each of the plurality of signal levels via the downstream node; and

[0402] a signal processing circuit that sequentially converts the reset level and the plurality of signal levels into digital signals and processes the digital signals.

[0403] (20) A solid-state imaging device, comprising:

[0404] a first photoelectric conversion element that converts incident light into electric charges;

[0405] a second photoelectric conversion element that converts incident light into electric charges;

[0406] an upstream amplification transistor that converts the electric charges into a voltage;

[0407] a predetermined number of capacitor elements each having a first terminal connected to an upstream node that is an output destination of the upstream amplification transistor;

[0408] a predetermined number of selection transistors inserted in each path between a second terminal of each of the predetermined number of capacitor elements and a predetermined downstream node;

[0409] a reset transistor having a source or a drain connected to the downstream node; and

[0410] a downstream amplification transistor having a gate connected to the downstream node and outputting a pixel signal.

[0411] BIBLIOGRAPHIC REFERENCES

[0412] 100 imaging device

[0413] 110 imaging lens

[0414] 120 recording unit

[0415] 130 imaging control section

[0416] 200 solid-state imaging device

[0417] 201 upper pixel chip

[0418] 202 lower pixel chip

[0419] 203 circuit chip

[0420] 211 vertical scanning circuit

[0421] 212 timing control circuit

[0422] 213 DAC

[0423] 220 pixel array section

[0424] 221 upper pixel array section

[0425] 222 lower pixel array section

[0426] 250 load MOS circuit block

[0427] 251 load MOS transistor

[0428] 260 column signal processing circuit

[0429] 261 ADC

[0430] 262 digital signal processing section

[0431] 300 pixel block

[0432] 301 to 304 pixels

[0433] 305 upstream circuit block

[0434] 310, 320, 410, 420 upstream circuit

[0435] 311, 321, 411, 421, 511 to 513 photoelectric conversion element

[0436] 312, 322, 412, 422, 514 to 516 transfer transistor

[0437] 313, 323, 413, 423 FD reset transistor

[0438] 314, 324, 414, 424 FD

[0439] 315, 325, 415, 425 upstream amplification transistor

[0440] 316, 326, 416, 426 current source transistor

[0441] 317, 327 upstream selection transistor

[0442] 331, 332, 336, 337, 431, 432, 436, 437, 531 to 533 Capacitive elements

[0443] 340 Selection unit

[0444] 350, 355, 450, 455 Selection circuit

[0445] 351, 352, 356, 357, 451, 452, 456, 457, 551 to 553 Selection transistors

[0446] 361, 461 Downstream reset transistor

[0447] 370, 470 Downstream circuit

[0448] 371, 471 Downstream amplification transistor

[0449] 372, 472 Downstream selection transistor

[0450] 480 Short-circuit transistor

[0451] 12031 Imaging unit

Claims

1. A solid-state imaging element, comprising: A predetermined number of capacitor components; An upstream circuit block generates a predetermined reset level and each of a plurality of signal levels corresponding to the exposure amount, and maintains the reset level and the plurality of signal levels by the different capacitive elements; The selection unit sequentially executes: control to connect the capacitor element that maintains the reset level among the predetermined number of capacitor elements to a predetermined downstream node, control to disconnect the predetermined number of capacitor elements from the downstream node, and control to connect the capacitor element that maintains any of the plurality of signal levels among the predetermined number of capacitor elements to the downstream node. The downstream reset transistor initializes the level of the downstream node when the predetermined number of capacitor elements are disconnected from the downstream node; as well as The downstream circuit sequentially reads the reset level and each of the plurality of signal levels via the downstream node.

2. The solid-state imaging element according to claim 1, wherein, The predetermined number of capacitor elements includes a first capacitor element, a second capacitor element, a third capacitor element, and a fourth capacitor element; The upstream circuit block includes: A first upstream circuit sequentially generates a first reset level and a first signal level, and maintains the first capacitor element and the second capacitor element at the first reset level and the first signal level, respectively; and The second upstream circuit sequentially generates a second reset level and a second signal level, and maintains the second reset level and the second signal level by the third capacitor element and the fourth capacitor element; and The selection unit includes: A first selection circuit connects either the first capacitor element or the second capacitor element to the downstream node; and A second selection circuit connects either the third or fourth capacitor element to the downstream node.

3. The solid-state imaging element according to claim 2, wherein, The first upstream circuit includes: First photoelectric conversion element; A first upstream transport transistor transfers charge from the first photoelectric conversion element to the first floating diffusion layer; A first reset transistor initializes the first floating diffusion layer; and A first upstream amplifying transistor amplifies the voltage of the first floating diffusion layer; and The second upstream circuit includes: Second photoelectric conversion element; The second upstream transport transistor transfers charge from the second photoelectric conversion element to the second floating diffusion layer; A second reset transistor initializes the second floating diffusion layer; and The second upstream amplifying transistor amplifies the voltage of the second floating diffusion layer.

4. The solid-state imaging element according to claim 3, wherein, The first upstream circuit also includes a first current source transistor connected to the first upstream node; The second upstream circuit also includes a second current source transistor connected to the second upstream node; The first upstream amplifying transistor amplifies the voltage of the first floating diffusion layer and outputs the amplified voltage to the first upstream node; The second upstream amplifying transistor amplifies the voltage of the second floating diffusion layer and outputs the amplified voltage to the second upstream node; The first capacitor element and the second capacitor element each have a first terminal and a second terminal connected to the first selection circuit. The first terminal of the first capacitor element and the first terminal of the second capacitor element are both connected to the first upstream node. The third capacitor element and the fourth capacitor element each have a first terminal and a second terminal connected to the second selection circuit. The first terminal of the third capacitor element and the first terminal of the fourth capacitor element are both connected to the second upstream node.

5. The solid-state imaging element according to claim 3 or 4, wherein, The first upstream transport transistor and the second upstream transport transistor transfer the charge to the first floating diffusion layer and the second floating diffusion layer at a predetermined exposure start time, and the first reset transistor and the second reset transistor, together with the first floating diffusion layer and the second floating diffusion layer, initialize the first photoelectric conversion element and the second photoelectric conversion element; and The first upstream transport transistor and the second upstream transport transistor transfer the charge to the first floating diffusion layer and the second floating diffusion layer at a predetermined exposure end time.

6. The solid-state imaging element according to claim 3 or 4, wherein, The selection unit sequentially executes: control to connect one of the first capacitor element and the second capacitor element to the downstream node, control to connect the other of the first capacitor element and the second capacitor element to the downstream node, control to connect one of the third capacitor element and the fourth capacitor element to the downstream node, and control to connect the other of the third capacitor element and the fourth capacitor element to the downstream node.

7. The solid-state imaging element according to claim 3 or 4, wherein, In a predetermined addition mode, the selection unit sequentially performs the following control: connecting one of the first capacitor element and the second capacitor element, and one of the third capacitor element and the fourth capacitor element, to the downstream node. Control of connecting the first capacitor element and the other of the second capacitor element, as well as the third capacitor element and the other of the fourth capacitor element, to the downstream node.

8. The solid-state imaging element according to claim 3, wherein, The first upstream circuit further includes a first upstream selection transistor, which outputs the voltage amplified by the first upstream amplification transistor to a predetermined upstream node according to a predetermined first selection signal; The second upstream circuit includes: The second upstream selection transistor outputs the voltage amplified by the second upstream amplification transistor to the upstream node according to a predetermined second selection signal; and A current source transistor connected to the upstream node; The first capacitor element and the second capacitor element each have a first terminal commonly connected to the upstream node and a second terminal connected to the first selection circuit; and The third capacitor element and the fourth capacitor element each have a first terminal that is connected to the upstream node and a second terminal that is connected to the second selection circuit.

9. The solid-state imaging element according to claim 8, wherein, The first upstream selection transistor and the second upstream selection transistor sequentially switch to a closed state before and after the predetermined exposure end time. When the first upstream selection transistor is in a closed state, the first reset transistor initializes the first floating diffusion layer; When the second upstream selection transistor is in a closed state, the second reset transistor initializes the second floating diffusion layer; The first upstream selection transistor and the second upstream selection transistor sequentially switch to a closed-circuit state immediately after the exposure ends; and The first upstream transfer transistor and the second upstream transfer transistor transfer charge at a predetermined exposure end time.

10. The solid-state imaging element according to claim 1, further comprising: A short-circuit transistor, which opens and closes the path between the first and second downstream nodes. The predetermined number of capacitor elements includes: a first capacitor element, a second capacitor element, a third capacitor element, a fourth capacitor element, a fifth capacitor element, a sixth capacitor element, a seventh capacitor element, and an eighth capacitor element; and The selection unit includes: A first selection circuit connects either the first capacitor element or the second capacitor element to the first downstream node; The second selection circuit connects either the third capacitor element or the fourth capacitor element to the first downstream node; A third selection circuit connects either the fifth or sixth capacitor element to the second downstream node; and The fourth selection circuit connects either the seventh capacitor element or the eighth capacitor element to the second downstream node.

11. The solid-state imaging element according to claim 10, wherein, The short-circuit transistor is in an open-circuit state in a predetermined non-additive mode, and In the non-additive mode, the selection unit executes the following in a predetermined order: controlling the sequential connection of each of the first and second capacitor elements to the first downstream node, controlling the sequential connection of each of the third and fourth capacitor elements to the first downstream node, controlling the sequential connection of each of the fifth and sixth capacitor elements to the second downstream node, and controlling the sequential connection of each of the seventh and eighth capacitor elements to the second downstream node.

12. The solid-state imaging element according to claim 10 or 11, wherein, The short-circuit transistor is in a closed-circuit state under a predetermined addition mode, and In the addition mode, the selection unit sequentially performs the following control: connecting one of the fifth and sixth capacitor elements and one of the seventh and eighth capacitor elements to the second downstream node, and simultaneously connecting one of the first and second capacitor elements and one of the third and fourth capacitor elements to the first downstream node. The control that connects the other of the fifth and sixth capacitor elements and the other of the seventh and eighth capacitor elements to the second downstream node, and simultaneously connects the other of the first and second capacitor elements and the other of the third and fourth capacitor elements to the first downstream node.

13. The solid-state imaging element according to claim 1, wherein, The predetermined number of capacitor elements includes a first capacitor element, a second capacitor element, and a third capacitor element; The upstream circuit block includes: First photoelectric conversion element; A first upstream transport transistor transfers charge from the first photoelectric conversion element to a predetermined floating diffusion layer; Second photoelectric conversion element; The second upstream transport transistor transfers charge from the second photoelectric conversion element to the predetermined floating diffusion layer; Initialize the reset transistor of the floating diffusion layer; and An upstream amplifying transistor amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node; and The first capacitor element, the second capacitor element, and the third capacitor element each have a first end that is connected to the upstream node and a second end that is connected to the selection section.

14. The solid-state imaging element according to claim 13, wherein, The first upstream transport transistor and the second upstream transport transistor transfer the charge to the floating diffusion layer at a predetermined exposure start time, and the reset transistor, together with the floating diffusion layer, initializes the first photoelectric conversion element and the second photoelectric conversion element; and The first upstream transport transistor and the second upstream transport transistor sequentially transport the charge to the floating diffusion layer at a predetermined exposure end time.

15. The solid-state imaging element according to claim 13 or 14, wherein, The selection unit sequentially performs: control to connect one of the first capacitor element and the second capacitor element to the downstream node, control to connect the other of the first capacitor element and the second capacitor element to the downstream node, and control to connect the third capacitor element to the downstream node.

16. The solid-state imaging element according to any one of claims 1 to 4, 8 to 11, and 13 to 14, wherein, The upstream circuit block is located on the first chip, and The predetermined number of capacitor elements, the selection section, the downstream reset transistor, and the downstream circuit are disposed on the second chip.

17. The solid-state imaging element of claim 16, further comprising: An analog-to-digital converter sequentially converts the output reset level and the plurality of output signal levels into digital signals. in, The analog-to-digital converter is located on the second chip.

18. The solid-state imaging element of claim 16, further comprising: An analog-to-digital converter sequentially converts the output reset level and the plurality of output signal levels into digital signals. in, The analog-to-digital converter is located on the third chip.

19. An imaging device, comprising: A predetermined number of capacitor components; An upstream circuit block generates a predetermined reset level and each of a plurality of signal levels corresponding to the exposure amount, and maintains the reset level and the plurality of signal levels by capacitive elements that are different from each other; The selection unit sequentially executes: control to connect the capacitor element that maintains the reset level among the predetermined number of capacitor elements to a predetermined downstream node, control to disconnect the predetermined number of capacitor elements from the downstream node, and control to connect the capacitor element that maintains any one of the plurality of signal levels among the predetermined number of capacitor elements to the downstream node. The downstream reset transistor initializes the level of the downstream node when the predetermined number of capacitor elements are disconnected from the downstream node; The downstream circuit sequentially reads the reset level and each of the plurality of signal levels via the downstream node; as well as The signal processing circuit sequentially converts the reset level and the plurality of signal levels into digital signals and processes the digital signals.

20. A solid-state imaging element, comprising: The first photoelectric conversion element that converts incident light into electrical charge; A second photoelectric conversion element that converts incident light into electrical charge; The upstream amplifying transistor converts the charge into voltage; A predetermined number of capacitor elements, each of which has a first terminal connected to an upstream node, the upstream node being the output destination of the upstream amplifying transistor; A predetermined number of selection transistors are inserted in the respective paths between the second terminal of each of the predetermined number of capacitor elements and a predetermined downstream node; A reset transistor having a source or drain connected to the downstream node; as well as A downstream amplifying transistor has a gate connected to the downstream node and outputs a pixel signal.

Images