Power transistor test system and test method

Abstract

The invention provides a testing system and a testing method for a power transistor. The power transistor testing system comprises: a first driving module, a second driving module, an equivalent parasitic parameter module, a power supply, a first inductor, a second inductor, a first switch, a second switch, a first NMOS tube, and a second NMOS tube; the power transistor testing system also comprises a temperature control device, a third NMOS tube, a third driving module, a fourth NMOS tube and a fourth driving module; the power transistor testing system can test the body diode reverse recovery characteristics, large current turn-on and large current turn-off characteristics or direct current short-circuit resistance characteristics of the power transistor or parallel transistor, and can also test the influence of high and low temperatures on the above characteristics; the circuit parameters of the power transistor testing system of the invention are adjustable, and the influence of adjustable parameters on the characteristics of the power transistor can be tested; the transistor located at the lower half bridge is not easily affected by external interference, and is convenient for testing.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging and testing, and in particular to a testing system and a testing method for a power transistor. Background Art

[0002] Power semiconductors are the core of power conversion and circuit control in electronic devices. They are mainly used to change the voltage and frequency, DC to AC conversion, etc. in electronic devices. Power semiconductors can be divided into two categories: power ICs and power discrete devices. Power discrete devices mainly include diodes, thyristors, transistors and other products. Transistors mainly include MOSFET, IGBT, etc. Power semiconductors are widely used in industrial control, consumer electronics, new energy, rail transportation, smart grids, variable frequency home appliances and other fields. Different market fields and topological structures have different requirements for power devices. The parameters of power devices are based on certain external environment tests. In order to evaluate the characteristics of power devices in actual applications, such as the opening process, conduction process, closing process, diode reverse recovery characteristics, and short-circuit resistance, a power transistor test system is urgently needed.

[0003] The schematic diagram of the traditional diode test system is as follows Figure 1 As shown, the reverse recovery characteristic waveform is as follows Figure 2 As shown, the first pulse of the gate-source voltage Vgs turns on the lower tube, the power supply voltage VDD is added to the load inductor, and the load inductor current rises; when the first pulse ends, the lower tube is turned off, and the load current is continued by the upper tube diode; at the second pulse, the lower tube is turned on again, the upper tube diode enters reverse recovery, and the reverse recovery current Irr flows through the lower tube. The oscilloscope can observe the upper tube diode reverse recovery current Irr and the upper tube gate-source power supply Vgs. The parasitic inductance, parasitic resistance and drive circuit parameters in the application environment have a significant impact on the reverse recovery characteristics of the diode. However, the traditional diode reverse recovery test system cannot change the equivalent parasitic inductance, equivalent parasitic resistance and drive circuit parameters of the application environment, and the diode characteristic transistor to be tested is fixed on the upper tube, the source potential changes greatly, and the common mode interference such as the oscilloscope test Vgs voltage is large. Therefore, how to propose a power transistor test system that can change circuit parameters and is convenient for testing with less interference has become one of the problems that technicians in this field need to solve. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power transistor test system and test method, which are used to solve the problems in the prior art that circuit parameters cannot be changed and test interference is large.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a power transistor test system, the power transistor test system comprising: a first driving module, a second driving module, an equivalent parasitic parameter module, a power supply, a first switch, a second switch, a first inductor, a second inductor, a first NMOS transistor and a second NMOS transistor;

[0006] The first NMOS transistor, the second NMOS transistor and the equivalent parasitic parameter module are connected in series and then in parallel to two ends of the power supply;

[0007] The first driving module is connected to the gate of the first NMOS tube and is used to control the state of the first NMOS tube;

[0008] The first switch and the first inductor are connected in series and then connected in parallel between the source and the drain of the first NMOS tube;

[0009] The second driving module is connected to the gate of the second NMOS tube and is used to control the state of the second NMOS tube;

[0010] The second switch and the second inductor are connected in series and then connected in parallel between the source and the drain of the second NMOS tube.

[0011] Optionally, the power transistor test system further includes a third NMOS transistor, a third driving module, a fourth NMOS transistor and a fourth driving module;

[0012] The drain of the third NMOS tube is connected to the drain of the first NMOS tube, and the source of the third NMOS tube is connected to the source of the first NMOS tube; the drain of the fourth NMOS tube is connected to the drain of the second NMOS tube, and the source of the fourth NMOS tube is connected to the source of the second NMOS tube;

[0013] The third NMOS tube has the same size and material as the first NMOS tube, and the fourth NMOS tube has the same size and material as the second NMOS tube.

[0014] Optionally, each driving module includes a driving chip and a driving circuit; the driving chip provides a driving signal; the driving circuit is connected to an output end of the driving chip, and drives a gate of a corresponding transistor based on the driving signal.

[0015] Optionally, the driving circuit includes a first resistor, a first diode, a second resistor and a first capacitor;

[0016] The first end of the first resistor is connected to the output end of the driving chip, and the second end is connected to the gate of the corresponding NMOS tube; the first end of the second resistor is connected to the first end of the first resistor, and the second end is connected to the cathode of the first diode; the anode of the first diode is connected to the second end of the first resistor; one end of the first capacitor is connected to the gate of the corresponding NMOS tube, and the other end is connected to the source of the corresponding NMOS tube.

[0017] Optionally, the equivalent parasitic parameter module includes an equivalent parasitic inductance and an equivalent parasitic resistance, and the equivalent parasitic inductance is connected in series with the equivalent parasitic resistance.

[0018] Optionally, the power transistor testing system further includes a temperature control device, wherein the temperature control device includes at least one of a heating module and a cooling module, respectively used to control the temperature of each transistor.

[0019] Optionally, each NMOS transistor is a silicon carbide power transistor or a gallium nitride power transistor.

[0020] The present invention also provides a power transistor testing method for testing the body diode reverse recovery characteristics of the power transistor, obtaining the reverse recovery characteristics of the body diode of the first NMOS tube based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube, comprising the following steps:

[0021] S11: turning off the first NMOS transistor, turning on the second NMOS transistor, closing the first switch, and opening the second switch, so that the current flowing through the second NMOS transistor, the first inductor, and the equivalent parasitic parameter module increases;

[0022] S12: turning off the second NMOS transistor, and allowing the current flowing through the first inductor to flow freely through the body diode of the first NMOS transistor;

[0023] S13: Turning on the second NMOS transistor, so that the body diode of the first NMOS transistor enters a reverse recovery state;

[0024] S14: turning off the second NMOS transistor, and allowing the current flowing through the first inductor to flow freely through the body diode of the first NMOS transistor.

[0025] The present invention also provides a power transistor testing method for testing the large current turn-on and turn-off characteristics of the power transistor, and obtaining the large current turn-on and turn-off characteristics of the first NMOS tube based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube, comprising the following steps:

[0026] S21: Turning on the first NMOS transistor, turning off the second NMOS transistor, closing the second switch, opening the first switch, and flowing through the equivalent parasitic parameter module, the current of the first NMOS transistor and the second inductor increases;

[0027] S22: the first NMOS tube is turned off, the current flowing through the second inductor is freewheeling through the body diode of the second NMOS tube, and the first NMOS tube undergoes a large current disconnection process;

[0028] S23: Turning on the first NMOS transistor, so that the first NMOS transistor undergoes a large current turn-on process.

[0029] The present invention also provides a method for testing a power transistor, which tests the through-power-on short-circuit resistance characteristics of the power transistor by adjusting the time interval between steps S31 and S32, and obtains the through-power-on short-circuit resistance characteristics of the first NMOS tube and the second NMOS tube based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube and the second NMOS tube, comprising the following steps:

[0030] S31: Turning on the first NMOS transistor and the second NMOS transistor, and turning off the first switch and the second switch, so that current flows through the first NMOS transistor, the second NMOS transistor and the equivalent parasitic parameter module;

[0031] S32: Turn off the first NMOS transistor, and turn off the second NMOS transistor.

[0032] Optionally, by setting a third NMOS tube in parallel with the first NMOS tube and a fourth NMOS tube in parallel with the second NMOS tube, the state of the third NMOS tube is the same as that of the first NMOS tube, and the state of the fourth NMOS tube is the same as that of the second NMOS tube, the characteristics of the parallel NMOS tubes are obtained.

[0033] Optionally, the power transistor testing method further includes: adjusting at least one parameter of an equivalent parasitic parameter module, a first driving module, a second driving module, a power supply, a first inductor, and a second inductor to detect the influence of the adjusted parameter on the NMOS tube characteristics.

[0034] Optionally, the power transistor testing method further includes: first adjusting the temperature of the NMOS tube to be tested to a preset temperature, and then performing a step of testing the characteristics of the NMOS tube to test the influence of high and low temperatures on the characteristics of the NMOS tube.

[0035] Optionally, the first NMOS transistor is arranged in the lower half bridge, and the second NMOS transistor is arranged in the upper half bridge.

[0036] As described above, the power transistor testing system and testing method of the present invention have the following beneficial effects:

[0037] The circuit parameters of the power transistor test system of the present invention can be adjusted, and the influence of the adjustable parameters on the power transistor characteristics can be tested;

[0038] The transistor located in the lower half bridge of the power transistor test system of the present invention is not easily disturbed by the outside world, so the measurement is convenient. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Shown is a schematic diagram of a power transistor test system in the prior art;

[0040] Figure 2 A waveform diagram showing the reverse recovery characteristics of a power transistor in the prior art;

[0041] Figure 3 Shown is a block diagram of a power transistor test system of the present invention;

[0042] Figure 4 Shown is a schematic diagram of a power transistor testing system of the present invention;

[0043] Figure 5 Shown is a test waveform schematic diagram of a power transistor test system of the present invention;

[0044] Figure 6 Shown is a block diagram of a test system for parallel power transistors of the present invention;

[0045] Figure 7 Shown is a schematic diagram of a parallel power transistor test system of the present invention;

[0046] Figure 8 Shown is a schematic diagram of the motor controller circuit topology in the prior art.

[0047] 1 First driver module 11 Driver chip 12 Drive circuit 2 Second driver module 3 Equivalent parasitic parameters module 4 The third driver module 5 Fourth drive module 6 Temperature control device DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figure 3~Figure 8It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated. Example

[0050] This embodiment provides a power transistor testing system. Figure 3 As shown, it includes: a first driving module 1, a second driving module 2, an equivalent parasitic parameter module 3, a power supply VDD, a first switch S1, a second switch S2, a first inductor L1, a second inductor L2, a first NMOS tube Q1, and a second NMOS tube Q2.

[0051] like Figure 4 As shown, the first NMOS transistor Q1, the second NMOS transistor Q2 and the equivalent parasitic parameter module 3 are connected in series and then in parallel to the two ends of the power supply VDD.

[0052] Specifically, in this embodiment, the equivalent parasitic parameter module 3 includes an equivalent parasitic inductance L3 and an equivalent parasitic resistance R3, and the equivalent parasitic inductance L3, the equivalent parasitic resistance R3, the first NMOS tube Q1 and the second NMOS tube Q2 are connected in series. As an example, the source of the second NMOS tube Q2 is connected to the drain of the first NMOS tube Q1; the source of the first NMOS tube Q1 is connected to the negative electrode of the power supply VDD through the equivalent parasitic resistance R3, and the drain of the second NMOS tube Q2 is connected to the positive electrode of the power supply VDD through the equivalent parasitic inductance L3. In actual use, the first NMOS tube Q1, the second NMOS tube Q2 and the equivalent parasitic parameter module 3 can be connected in series, and the specific relative position relationship is not limited, including but not limited to the position of the first NMOS tube Q1 and the second NMOS tube Q2 being interchanged.

[0053] It should be noted that the resistance of the equivalent parasitic resistor R3 is adjustable, the inductance of the equivalent parasitic inductor L3 is adjustable, and the equivalent parasitic parameter module 3 includes but is not limited to those listed in this embodiment. Any parasitic parameter module that may affect the characteristics of the transistor satisfies this embodiment and is not listed one by one here.

[0054] like Figure 4 As shown, the first driving module 1 is connected to the gate of the first NMOS tube Q1, and is used to control the state of the first NMOS tube Q1; the second driving module 2 is connected to the gate of the second NMOS tube Q2, and is used to control the state of the second NMOS tube Q2.

[0055] like Figure 4 As shown, as an example, each driving module has the same structure, including a driving chip 11 and a driving circuit 12; the driving chip 11 provides a driving signal; the driving circuit 12 is connected to the output end of the driving chip 11, and drives the gate of the corresponding NMOS tube based on the driving signal.

[0056] like Figure 4 As shown, in this embodiment, the driving circuit 12 includes a first resistor R1, a first diode D1, a second resistor R2 and a first capacitor C1.

[0057] The first end of the first resistor R1 is connected to the output end of the driving chip 11, and the second end is connected to the gate of the corresponding NMOS tube; the first end of the second resistor R2 is connected to the first end of the first resistor R1, and the second end is connected to the cathode of the first diode D1; the anode of the first diode D1 is connected to the second end of the first resistor R1; one end of the first capacitor C1 is connected to the gate of the corresponding NMOS tube, and the other end is connected to the source of the corresponding NMOS tube.

[0058] It should be noted that, in practical applications, any circuit structure that can drive a transistor is applicable to the present invention, and is not limited to this embodiment; the parameter values ​​of the corresponding devices (including the first resistor R1, the first diode D1, the second resistor R2 and the first capacitor C1) between each driving module can be the same or different, and are not limited here. Any parameter values ​​of each device that can meet the test requirements are applicable to the present invention.

[0059] like Figure 4 As shown, the first switch S1 and the first inductor L1 are connected in series and then connected in parallel between the source and drain of the first NMOS transistor Q1; the second switch S2 and the second inductor L2 are connected in series and then connected in parallel between the source and drain of the second NMOS transistor Q2.

[0060] like Figure 3 As shown, the power transistor test system also includes a temperature control device 6, which includes at least one of a heating module or a cooling module, which is used to control the temperature of each transistor respectively; thereby, the influence of high and low temperatures on the characteristics of the power transistor can be tested.

[0061] Specifically, each transistor is a silicon carbide power transistor or a gallium nitride power transistor.

[0062] It should be noted that the materials of each transistor include but are not limited to those listed in this embodiment, and power transistors made of any material meet the requirements of this invention.

[0063] It should be noted that if Figure 3In the power transistor test system shown in the figure, the first NMOS transistor Q1 and / or the second NMOS transistor Q2 can be used as the test transistor, but preferably, the source of the first NMOS transistor Q1 is a zero potential point and is not easily interfered by the outside world, so the first NMOS transistor Q1 is preferably the test transistor; as an example, Figure 3 The power transistor test system shown can be used to test the body diode reverse recovery characteristics of the first NMOS tube Q1, the large current turn-on and large current turn-off characteristics of the first NMOS tube Q1, and the direct current short-circuit withstand characteristics of the first NMOS tube Q1 and the second NMOS tube Q2. Example

[0064] like Figure 6 and Figure 7 As shown, this embodiment provides a power transistor testing system, which is different from the first embodiment in that the power transistor testing system further includes a third NMOS transistor Q3, a third driving module 4, a fourth NMOS transistor Q4 and a fourth driving module 5.

[0065] Specifically, the drain of the third NMOS tube Q3 is connected to the drain of the first NMOS tube Q1, and the source of the third NMOS tube Q3 is connected to the source of the first NMOS tube Q1; the drain of the fourth NMOS tube Q4 is connected to the drain of the second NMOS tube Q2, and the source of the fourth NMOS tube Q4 is connected to the source of the second NMOS tube Q2.

[0066] The third NMOS transistor Q3 has the same size and material as the first NMOS transistor Q1 , and the fourth NMOS transistor Q4 has the same size and material as the second NMOS transistor Q2 .

[0067] It should be noted that the structures of the third driving module 4 and the fourth driving module 5 are the same as those of the first driving module 1 and the second driving module 2, and are not described in detail here. The resistance values ​​of the first resistor R1 and the second resistor R2 in the third driving module 4 and the fourth driving module 5 are adjustable, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are adjustable; the inductance values ​​of the first inductor L1 and the second inductor L2 are adjustable, and the voltage and current output by the power supply VDD are adjustable; thereby, the influence of at least one of the above parameters on the characteristics of the power transistor or the parallel transistor can be tested.

[0068] like Figure 6 and Figure 7In the parallel power transistor test system shown, the transistor of the lower half bridge is preferably used as the test tube, which can be used to test the characteristics of the parallel power transistor; when testing the characteristics of the parallel transistor, the state of the first NMOS tube Q1 is the same as the state of the third NMOS tube Q3, and the state of the second NMOS tube Q2 is the same as the state of the fourth NMOS tube Q4.

[0069] The other structures and functions of the power transistor testing system of this embodiment are the same as those of the first embodiment, and are not described in detail here. Example

[0070] This embodiment discloses a test method for testing the reverse recovery characteristics of a power transistor body diode. Figure 3 and Figure 4 The corresponding power transistor test system is implemented. In this embodiment, the first NMOS transistor Q1 is the tested transistor, and the second NMOS transistor Q2 is the driving transistor. The test includes the following steps:

[0071] S11: At time t0, the first switch S1 is closed and the second switch S2 is opened, and the first NMOS transistor Q1 is turned off by controlling the driving chip 11, and the second NMOS transistor Q2 is turned on by controlling the driving chip 11; at this time, the current through the equivalent parasitic inductance L3, the equivalent parasitic resistance R3 and the first inductance L1 increases; the time interval from t0 to t1 determines the size of this current, and the longer the time interval, the greater the current.

[0072] S12: at time t1, the second NMOS transistor Q2 is turned off by controlling the driving chip 21, and the current flowing through the first inductor L1 is freewheeled through the body diode of the first NMOS transistor Q1, and the current slowly decreases;

[0073] S13: At time t2, the second NMOS transistor Q2 is turned on again by controlling the second driver chip 21; the body diode of the first NMOS transistor Q1 enters the reverse recovery state, and the reverse recovery current flows through the second NMOS transistor Q2; Figure 5 As shown, the larger leakage current change rate of the first NMOS tube Q1 during the reverse recovery process, combined with the equivalent parasitic inductance L3 and the parasitic inductance of the first NMOS tube Q1 pin, will produce a high Vds1 voltage spike and a high Vgs1 voltage spike. The Vds1 voltage spike is likely to cause avalanche breakdown damage to the first NMOS tube Q1, and the Vgs1 voltage spike is likely to cause the first NMOS tube Q1 to be turned on by mistake and break down the gate oxide layer of the first NMOS tube Q1, etc.

[0074] S14: the second NMOS transistor Q2 is turned off by controlling the driving chip 11, and the current flowing through the first inductor L1 is freewheeled through the body diode of the first NMOS transistor Q1, and the current slowly decreases.

[0075] like Figure 5 The waveform diagram shows the reverse recovery characteristic of the body diode of the first NMOS tube Q1 . The reverse recovery characteristic of the body diode of the first NMOS tube is obtained based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube.

[0076] The test method for testing the reverse recovery characteristics of the body diode of a power transistor of the present invention also includes: when testing the reverse recovery characteristics of the body diode of the first NMOS tube Q1 under high and low temperature conditions, firstly adjusting the first temperature control device 6 so that the temperature of the first NMOS tube Q1 reaches a preset value, and then performing the above test steps.

[0077] The testing method for testing the reverse recovery characteristics of the body diode of a power transistor of the present invention also includes: when testing the influence of changes in external parameters on the reverse recovery characteristics of the body diode of the first NMOS tube Q1, at least one parameter of the devices in the driving circuit 12 in the first driving module 1 and the second driving module 2, the first inductor L1, the second inductor L2, the equivalent parasitic inductance L3, the equivalent parasitic resistance R3, and the power supply VDD can be adjusted as needed.

[0078] It should be noted that when it is necessary to test the reverse recovery characteristics of the body diodes of the parallel transistors, the reverse recovery characteristics of the body diodes of the parallel transistors can be tested based on the reverse recovery characteristics of the body diodes of the parallel transistors. Figure 7 The power transistor test system shown in the figure is implemented, the state of the first NMOS tube Q1 is the same as the state of the third NMOS tube Q3, and the state of the second NMOS tube Q2 is the same as the state of the fourth NMOS tube Q4; similarly, the influence of at least one parameter of each driving circuit 12, the equivalent parasitic parameter module 3, and the power supply VDD on the reverse recovery characteristics of the body diode of the parallel transistor can also be tested.

[0079] It should be further explained that, in actual use, the positions of the first NMOS tube Q1 and the second NMOS tube Q2 are interchangeable, that is, the body diode reverse recovery characteristic test is performed on the NMOS tube located in the upper half bridge. However, more preferably, the first NMOS tube Q1 is set in the lower half bridge, and the source of the lower half bridge transistor is a zero potential point, which is not easily affected by external interference, so it is easier for the oscilloscope to accurately capture the gate-source voltage Vgs, drain-source voltage Vds, drain current Id and other parameters of the lower half bridge transistor. Through these parameters, the reverse recovery characteristics of the body diode of the first NMOS tube Q1 and the reverse recovery characteristics of the body diode of the first NMOS tube Q1 and the third NMOS tube Q3 in parallel can be analyzed. Example

[0080] This embodiment discloses a test method for testing the large current turn-on and turn-off characteristics of a power transistor. Figure 3 and Figure 4 The power transistor test system is implemented. In this embodiment, the first NMOS transistor Q1 is the tested transistor, and the second NMOS transistor Q2 is the freewheeling transistor. The test includes the following steps:

[0081] S21: At time t0, the first switch S1 is opened, and the second switch S2 is closed. The first NMOS tube Q1 is turned on by controlling the driving chip 11, and the second NMOS tube Q2 is turned off by controlling the driving chip 11. The power supply voltage VDD is applied to the second inductor L2, the equivalent parasitic inductor L3, and the equivalent parasitic resistor R3, and the current gradually increases. The time interval from t0 to t1 determines the current size. The longer the time interval, the greater the current.

[0082] S22: At time t1, the first NMOS transistor Q1 is turned off by controlling the driving chip 11, and the current flowing through the second inductor L2 is continued through the body diode of the second NMOS transistor Q2. The first NMOS transistor Q1 undergoes a large current shutdown process, wherein the parameters of the first resistor R1, the second resistor R2, and the first capacitor C1 control the speed of the shutdown process.

[0083] S23: At time t2, the first NMOS transistor Q1 is turned on by controlling the driving chip 11, and the first NMOS transistor Q1 undergoes a large current turn-on process, wherein the parameters of the first resistor R1 and the first capacitor C1 control the speed of the turn-on process.

[0084] The test method for testing the large current on and off characteristics of a power transistor of the present invention also includes: when testing the high and low temperature effects on the large current on and off characteristics of a transistor, first adjust the temperature control device 6 so that the temperature of the transistor to be tested reaches a preset value, and then perform the above test steps.

[0085] The testing method for testing the large current turn-on and turn-off characteristics of a power transistor of the present invention also includes: when testing the influence of external parameters on the large current turn-on and turn-off characteristics of the first NMOS tube Q1, the components in the driving circuit 12 in the first driving module 1 and the second driving module 2, the first inductor L1, the second inductor L2, the equivalent parasitic inductance L3, the equivalent parasitic resistance R3, and at least one parameter of the power supply VDD can be adjusted as needed; similarly, the influence of at least one parameter in each driving circuit 12, the equivalent parasitic parameter module 3, and the power supply VDD on the large current turn-on and turn-off characteristics of the parallel transistor can also be tested.

[0086] It should be noted that when it is necessary to test the large current turn-on and turn-off characteristics of the parallel transistors, the method described in the second embodiment can be used. Figure 7The power transistor test system shown is implemented, the state of the first NMOS transistor Q1 is the same as the state of the third NMOS transistor Q3, and the state of the second NMOS transistor Q2 is the same as the state of the fourth NMOS transistor Q4.

[0087] It should be further explained that, similarly, the positions of the first NMOS tube Q1 and the second NMOS tube Q2 can be interchanged. However, more preferably, because the first NMOS tube Q1 is in the lower half bridge, the source of the first NMOS tube Q1 is a zero potential point and is not easily interfered by the outside world, so it is easier for the oscilloscope to accurately capture the gate-source voltage Vgs, drain-source voltage Vds, drain current Id and other parameters of the first NMOS tube Q1, and these parameters can be analyzed to obtain the large current turn-on and turn-off characteristics of the first NMOS tube Q1 and the large current turn-on and turn-off characteristics of the first NMOS tube Q1 and the third NMOS tube Q3 in parallel. Example

[0088] In such Figure 8 In the full-bridge topology application such as the motor controller shown in the figure, the drains of the two transistors Q2A and Q2B of the upper half bridge are connected, and the sources are connected through the inductor L. The sources of the two transistors Q1A and A1B of the lower half bridge are connected, and the drains are connected through the inductor L. There is a probability of short circuit between the two bridge arms, and L being short-circuited is equivalent to the upper and lower bridges being directly connected. This embodiment discloses a test method for testing the direct-connection short-circuit resistance characteristics of a power transistor, based on the first embodiment. Figure 3 and Figure 4 The power transistor test system is implemented, in this embodiment, the test includes the following steps:

[0089] S31: At time t0, the first switch S1 and the second switch S2 are both turned off, and the first NMOS transistor Q1 is turned on by controlling the driving chip 11, so that the second NMOS transistor Q2 is turned on, and the current flowing through the first NMOS transistor Q1 and the second NMOS transistor Q2 is mainly controlled by the conduction internal resistance of the first NMOS transistor Q1 and the second NMOS transistor Q2 and the equivalent parasitic inductance L3 and the equivalent parasitic resistance R3;

[0090] S32 : at time t1 , the first NMOS transistor Q1 is turned off by controlling the driving chip 11 , and the second NMOS transistor Q2 is turned off by controlling the driving chip 11 .

[0091] It should be noted that the time from t1 to t0 is the short-circuit withstand time of the first NMOS tube Q1 and the second NMOS tube Q2. By continuously adjusting the time t1 and the voltage and current of the power supply voltage VDD, the gate-source voltage Vgs, the drain-source voltage Vds, the drain current Id and other parameters of the first NMOS tube Q1 and the second NMOS tube Q2 can be read through an oscilloscope to obtain the short-circuit withstand voltage, short-circuit withstand current and short-circuit withstand time of the first NMOS tube Q1 and the second NMOS tube Q2.

[0092] The test method for testing the through-current short-circuit withstand characteristics of a power transistor of the present invention also includes: when testing the through-current short-circuit withstand characteristics of high and low temperatures, first adjusting the temperature control device 6 so that the temperature of the first NMOS tube Q1 and the second NMOS tube Q2 reaches a preset value, and then performing the above test steps.

[0093] The testing method for testing the through-current short-circuit withstand characteristics of a power transistor of the present invention also includes: when testing the influence of external parameters on the large current turn-on and turn-off characteristics of the first NMOS tube Q1, the devices in the driving circuit 12 in the first driving module 1 and the second driving module 2, the first inductor L1, the second inductor L2, the equivalent parasitic inductance L3, the equivalent parasitic resistance R3, and at least one parameter of the power supply VDD can be adjusted as needed; similarly, the influence of at least one parameter in each driving circuit 12, the equivalent parasitic parameter module 3, and the power supply VDD on the through-current short-circuit withstand characteristics of the parallel transistor can also be tested.

[0094] It should be noted that when it is necessary to test the through-current short-circuit resistance characteristics of the parallel transistors, the method described in the second embodiment can be used. Figure 7 The power transistor test system shown is implemented, the state of the first NMOS transistor Q1 is the same as the state of the third NMOS transistor Q3, and the state of the second NMOS transistor Q2 is the same as the state of the fourth NMOS transistor Q4.

[0095] In summary, the present invention provides a power transistor test system and test method, the power transistor test system comprises: a first driving module 1, a second driving module 2, an equivalent parasitic parameter module 3, a power supply VDD, a first inductor L1, a second inductor L2, a first switch S1, a second switch S2, a first NMOS transistor Q1, and a second NMOS transistor Q2; each driving module comprises a driving chip 11 and a driving circuit 12, the driving chip 11 outputs a driving signal, which is output to a corresponding transistor through the driving circuit 12 to control the state of the corresponding transistor; the power transistor test system further comprises a third NMOS transistor Q3, a third driving module 4 , the fourth NMOS tube Q4, the fourth driving module 5; the power transistor test system also includes a temperature control device 6 for heating or cooling the transistor, which can test the influence of at least one of the adjustable parameters on the body diode reverse recovery characteristics, large current opening and large current closing characteristics or direct current short-circuit resistance characteristics of the power transistor or parallel power transistor, and can also test the influence of high and low temperatures on the above characteristics; the circuit parameters of the power transistor test system of the present invention are adjustable, and the influence of the adjustable parameters on the characteristics of the power transistor can be tested; the transistor in the lower half-bridge branch of the power transistor test system of the present invention is not easily affected by external interference and is convenient for measurement. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power transistor test system, characterized in that: The power transistor test system comprises: a first driving module, a second driving module, an equivalent parasitic parameter module, a power supply, a first switch, a second switch, a first inductor, a second inductor, a first NMOS tube and a second NMOS tube; The first NMOS transistor, the second NMOS transistor and the equivalent parasitic parameter module are connected in series and then in parallel to two ends of the power supply; The first driving module is connected to the gate of the first NMOS tube and is used to control the state of the first NMOS tube; The first switch and the first inductor are connected in series and then connected in parallel between the source and the drain of the first NMOS tube; The second driving module is connected to the gate of the second NMOS tube and is used to control the state of the second NMOS tube; The second switch and the second inductor are connected in series and then connected in parallel between the source and the drain of the second NMOS tube; The power transistor testing system detects the influence of the adjusted parameters on the NMOS tube characteristics by adjusting at least one parameter of the equivalent parasitic parameter module, the first driving module, the second driving module, the power supply, the first inductor, and the second inductor.

2. The power transistor test system according to claim 1, characterized in that: The power transistor test system further includes a third NMOS transistor, a third driving module, a fourth NMOS transistor and a fourth driving module; The drain of the third NMOS tube is connected to the drain of the first NMOS tube, and the source of the third NMOS tube is connected to the source of the first NMOS tube; the drain of the fourth NMOS tube is connected to the drain of the second NMOS tube, and the source of the fourth NMOS tube is connected to the source of the second NMOS tube; The third NMOS tube has the same size and material as the first NMOS tube, and the fourth NMOS tube has the same size and material as the second NMOS tube.

3. The power transistor test system according to any one of claims 1 or 2, characterized in that: Each driving module includes a driving chip and a driving circuit; the driving chip provides a driving signal; the driving circuit is connected to the output end of the driving chip, and drives the gate of the corresponding NMOS tube based on the driving signal.

4. The power transistor test system according to claim 3, characterized in that: The driving circuit includes a first resistor, a first diode, a second resistor and a first capacitor; The first end of the first resistor is connected to the output end of the driving chip, and the second end is connected to the gate of the corresponding NMOS tube; the first end of the second resistor is connected to the first end of the first resistor, and the second end is connected to the cathode of the first diode; the anode of the first diode is connected to the second end of the first resistor; one end of the first capacitor is connected to the gate of the corresponding NMOS tube, and the other end is connected to the source of the corresponding NMOS tube.

5. The power transistor test system according to claim 1, characterized in that: The equivalent parasitic parameter module includes an equivalent parasitic inductance and an equivalent parasitic resistance, and the equivalent parasitic inductance is connected in series with the equivalent parasitic resistance.

6. The power transistor test system according to any one of claims 1 or 2, characterized in that: The power transistor test system further comprises a temperature control device, wherein the temperature control device comprises at least one of a heating module and a cooling module, which are respectively used to control the temperature of each NMOS tube.

7. The power transistor test system according to any one of claims 1 or 2, characterized in that: Each NMOS tube is a silicon carbide power transistor or a gallium nitride power transistor.

8. A method for testing a power transistor, implemented based on the power transistor testing system according to any one of claims 1 to 7, characterized in that: The method is used to test the reverse recovery characteristics of the body diode of a power transistor, and obtain the reverse recovery characteristics of the body diode of the first NMOS tube based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube, including the following steps: S11: turning off the first NMOS transistor, turning on the second NMOS transistor, closing the first switch, and opening the second switch, so that the current flowing through the second NMOS transistor, the first inductor, and the equivalent parasitic parameter module increases; S12: turning off the second NMOS transistor, and allowing the current flowing through the first inductor to flow freely through the body diode of the first NMOS transistor; S13: Turning on the second NMOS transistor, so that the body diode of the first NMOS transistor enters a reverse recovery state; S14: turning off the second NMOS transistor, and allowing the current flowing through the first inductor to flow freely through the body diode of the first NMOS transistor.

9. A method for testing a power transistor, implemented based on the power transistor testing system according to any one of claims 1 to 7, characterized in that: The method is used to test the large current turn-on and turn-off characteristics of a power transistor, and obtain the large current turn-on and turn-off characteristics of the first NMOS tube based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube, including the following steps: S21: Turning on the first NMOS transistor, turning off the second NMOS transistor, closing the second switch, opening the first switch, and flowing through the equivalent parasitic parameter module, the current of the first NMOS transistor and the second inductor increases; S22: turning off the first NMOS transistor, allowing the current flowing through the second inductor to flow through the body diode of the second NMOS transistor, and the first NMOS transistor undergoes a large current disconnection process; S23: Turning on the first NMOS transistor, so that the first NMOS transistor undergoes a large current turn-on process.

10. A power transistor testing method, implemented based on the power transistor testing system according to any one of claims 1 to 7, characterized in that: The short-circuit resistance characteristics of the power transistor during power-on are tested by adjusting the time interval between steps S31 and S32, and the short-circuit resistance characteristics of the power-on during power-on of the first NMOS tube and the second NMOS tube are obtained based on the drain-source voltage, drain current and gate-source voltage of the first NMOS tube and the second NMOS tube, including the following steps: S31: turning on the first NMOS transistor and the second NMOS transistor, turning off the first switch and the second switch, and allowing current to flow through the first NMOS transistor, the second NMOS transistor and the equivalent parasitic parameter module; S32: Turn off the first NMOS transistor and the second NMOS transistor.

11. The method for testing a power transistor according to any one of claims 8 to 10, characterized in that: By setting a third NMOS tube connected in parallel with the first NMOS tube and a fourth NMOS tube connected in parallel with the second NMOS tube, the state of the third NMOS tube is the same as that of the first NMOS tube, and the state of the fourth NMOS tube is the same as that of the second NMOS tube, the characteristics of the parallel NMOS tubes are obtained.

12. The method for testing a power transistor according to any one of claims 8 to 10, characterized in that: The power transistor testing method further includes: adjusting at least one parameter of the equivalent parasitic parameter module, the first driving module, the second driving module, the power supply, the first inductor, and the second inductor to detect the influence of the adjusted parameter on the NMOS tube characteristics.

13. The method for testing a power transistor according to any one of claims 8 to 10, characterized in that: The power transistor testing method further includes: first adjusting the temperature of the NMOS tube to be tested to a preset temperature, and then performing a step of testing the characteristics of the power transistor to test the influence of high and low temperatures on the characteristics of the NMOS tube.

14. The method for testing a power transistor according to any one of claims 8 to 10, characterized in that: The first NMOS tube is arranged in the lower half bridge, the second NMOS tube is arranged in the upper half bridge, and the first NMOS tube is a tube under test.

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