Testing device of power semiconductor device and testing method based on testing device

Abstract

The invention provides a testing device of a power semiconductor device and a testing method based on the testing device, and relates to the field of semiconductors, and the testing device comprises a first probe loop which comprises a first probe which can be separated from or electrically contacted with a tested power semiconductor device; when the first probe is in electric contact with the tested power semiconductor device, the dynamic voltage change rate applying circuit applies dynamic voltage to the tested power semiconductor device through the first probe loop; the second probe loop comprises a second probe which is electrically contacted with the tested power semiconductor device; when the first probe is separated from the tested power semiconductor device, the parameter measuring circuit measures the electrical parameters of the tested power semiconductor device through the second probe loop; and the first stray inductance of the first probe loop is smaller than the second stray inductance of the second probe loop, so that the electrical parameters of the power semiconductor device can be accurately extracted under the condition that high dV / dt dynamic voltage is applied to the power semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a test apparatus for power semiconductor devices and a test method based thereon. Background Technology

[0002] Compared to traditional silicon devices, silicon carbide materials have the characteristics of high temperature resistance and high voltage resistance. In the field of power semiconductor devices, silicon carbide power devices have been increasingly used in power conversion due to their low switching losses and high frequency, especially in high voltage applications, where they have shown superior characteristics compared to traditional silicon devices.

[0003] Given the high dV / dt (voltage change rate) environment of power device applications, the reliability of power semiconductor devices under dV / dt conditions remains a challenge. Current industry requirements (especially for high-reliability applications) necessitate dynamic reverse bias testing and screening of power semiconductor devices, achieved by applying dV / dt to the devices.

[0004] To assess the reliability of power semiconductor devices, precise measurements of the device-under-test's (DUT) fundamental electrical parameters (e.g., leakage current Idss, threshold voltage Vth) are required at the start, during, and end of reverse bias testing. However, the circuitry that applies dV / dt to the power semiconductor device can affect the measurement of electrical parameters such as leakage current and threshold voltage, making accurate extraction of these parameters difficult.

[0005] Currently, the commonly used approach in related technologies is to add mechanical switches such as relays between the application circuit and the power semiconductor device under test, and to disconnect the mechanical switches during parameter measurement to isolate the influence of the application circuit on the measurement circuit.

[0006] While existing solutions can isolate the application circuit and eliminate its influence on the measurement circuit, the addition of mechanical switches (mechanical relays) increases stray inductance in the circuit. This increased stray inductance severely limits the dV / dt of the dynamic voltage applied to the power semiconductor device under test (stray inductance reduces dV / dt, making it difficult to achieve the testing objective), and may even cause oscillations in the device under test, affecting the reliability screening and testing of the device. Currently, this solution faces a bottleneck in the field of dynamic reverse biasing of power semiconductor devices, and existing technologies cannot resolve or reconcile this contradiction. Summary of the Invention

[0007] The main objective of this disclosure is to provide a test apparatus for power semiconductor devices and a test method based thereon, so as to accurately extract the electrical parameters of power semiconductor devices when a dynamic voltage of high dV / dt is applied to the power semiconductor device.

[0008] To achieve the above objectives, a first aspect of this disclosure provides a testing apparatus for power semiconductor devices, the testing apparatus comprising: The semiconductor device under test; A dynamic voltage change rate application circuit is used to generate a dynamic voltage with a voltage change rate greater than a set threshold. A first probe circuit coupled to the dynamic voltage change rate application circuit includes a first probe that is separable from or electrically contacted with the power semiconductor device under test; wherein, when the first probe is electrically contacted with the power semiconductor device under test, the dynamic voltage change rate application circuit applies the dynamic voltage to the power semiconductor device under test through the first probe circuit; Parameter measurement circuit; A second probe circuit coupled to the parameter measurement circuit includes a second probe that is electrically in contact with the power semiconductor device under test; wherein, when the first probe is separated from the power semiconductor device under test, the parameter measurement circuit measures the electrical parameters of the power semiconductor device under test through the second probe circuit. Wherein, the first stray inductance of the first probe circuit is less than the second stray inductance of the second probe circuit.

[0009] In some embodiments of this disclosure, the total length of the first probe in the first probe circuit is less than the total length of the second probe in the second probe circuit.

[0010] In some embodiments of this disclosure, the dynamic voltage change rate application circuit includes: a dynamic voltage generating unit, the dynamic voltage generating unit being used to generate a dynamic voltage with a voltage change rate greater than the set threshold; The power semiconductor device under test includes a first electrode structure under test, a second electrode structure under test, and a control electrode structure under test that controls the conduction or cutoff between the first electrode structure under test and the second electrode structure under test. The first probe includes a first sub-probe and a second sub-probe. The first end of the first sub-probe is coupled to the first electrode of the dynamic voltage generating unit, and the second end of the first sub-probe is separable from or electrically connected to the first electrode structure of the power semiconductor device under test. The first end of the second sub-probe is coupled to the second electrode of the dynamic voltage generating unit, and the second end of the second sub-probe is separable from or electrically connected to the second electrode structure of the power semiconductor device under test.

[0011] In some embodiments of this disclosure, the second probe includes a third sub-probe and a fourth sub-probe; The first end of the third sub-probe is coupled to the first electrode of the parameter measurement circuit, and the second end of the third sub-probe is electrically connected to the first electrode structure of the power semiconductor device under test. The first end of the fourth sub-probe is coupled to the second electrode of the parameter measurement circuit, and the second end of the fourth sub-probe is electrically contacted with the second electrode structure of the power semiconductor device under test. The lengths of the first sub-probe and the second sub-probe are both less than the lengths of the third sub-probe and the fourth sub-probe.

[0012] In some embodiments of this disclosure, the power semiconductor device under test includes a first electrode structure under test, a second electrode structure under test, and a control electrode structure under test for controlling the conduction or de-conduction between the first electrode structure under test and the second electrode structure under test. The dynamic voltage change rate application circuit includes: a capacitor and an auxiliary power semiconductor device; The auxiliary power semiconductor device includes a first auxiliary electrode structure, a second auxiliary electrode structure, and an auxiliary control electrode structure for controlling the conduction or cutoff between the first auxiliary electrode structure and the second auxiliary electrode structure; the first electrode structure under test is electrically connected to the second auxiliary electrode structure. The first probe includes a first sub-probe and a second sub-probe. The first end of the first sub-probe is coupled to the first electrode of the capacitor, and the second end of the first sub-probe is separable from or electrically connected to the first auxiliary electrode structure of the auxiliary power semiconductor device. The first end of the second sub-probe is coupled to the second electrode of the capacitor, and the second end of the second sub-probe is separable from or electrically connected to the second electrode structure of the power semiconductor device under test.

[0013] In some embodiments of this disclosure, the second probe includes a third sub-probe and a fourth sub-probe; The first end of the third sub-probe is coupled to the first electrode of the parameter measurement circuit, and the second end of the third sub-probe is electrically contacted with the first auxiliary electrode structure of the auxiliary power semiconductor device. The first end of the fourth sub-probe is coupled to the second electrode of the parameter measurement circuit, and the second end of the fourth sub-probe is electrically contacted with the second electrode structure of the power semiconductor device under test. The lengths of the first sub-probe and the second sub-probe are both less than the lengths of the third sub-probe and the fourth sub-probe.

[0014] In some embodiments of this disclosure, the testing apparatus further includes: a PWM signal generator, which is coupled to the control electrode structure under test and the auxiliary control electrode structure; The PWM signal generator is configured to send a PWM signal to the control electrode structure under test and the auxiliary control electrode structure, triggering the power semiconductor device under test and the auxiliary power semiconductor device to turn on or off, thereby cooperating with the capacitor to generate a dynamic voltage in the power semiconductor device under test with a voltage change rate greater than the set threshold.

[0015] In some embodiments of this disclosure, the auxiliary power semiconductor device and the power semiconductor device under test are located on the same wafer; or, The auxiliary power semiconductor device and the power semiconductor device under test are located in the same or different power semiconductor packages.

[0016] In some embodiments of this disclosure, the testing apparatus further includes: A moving component connected to the first probe, the moving component being configured to: drive the first probe to abut against the power semiconductor device to make electrical contact with the power semiconductor device; and drive the first probe to move away from the power semiconductor device to separate the first probe from the power semiconductor device.

[0017] According to a second aspect of this disclosure, a testing method for a power semiconductor device is provided, the testing method being based on the testing apparatus for a power semiconductor device provided in the first aspect, the method comprising: When the first probe is in electrical contact with the power semiconductor device under test and the second probe is in electrical contact with the power semiconductor device under test, the dynamic voltage change rate application circuit applies a dynamic voltage to the power semiconductor device under test through the first probe circuit to perform a dynamic reverse bias test on the power semiconductor device under test. When the first probe is separated from the power semiconductor device under test and the second probe is in electrical contact with the power semiconductor device under test, the parameter measurement circuit measures the electrical parameters of the power semiconductor device under test through the second probe loop.

[0018] The power semiconductor device testing apparatus and testing method provided in this disclosure embodiment achieve the following: First, the stray inductance of the first probe circuit is less than the second stray inductance of the second probe circuit; second, the first probe is separable from or electrically connected to the power semiconductor device under test. When the first probe is electrically connected to the power semiconductor device under test, a dynamic voltage change rate application circuit applies a dynamic voltage with a voltage change rate greater than a set threshold to the power semiconductor device under test through the first probe circuit, thereby applying a high dV / dt dynamic voltage to the power semiconductor device. When the first probe is separated from the power semiconductor device under test, a parameter measurement circuit measures the electrical parameters of the power semiconductor device under test through the second probe circuit, thereby achieving accurate extraction of the electrical parameters of the power semiconductor device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A circuit schematic block diagram of a test apparatus for a power semiconductor device provided in an embodiment of this disclosure; Figure 2 A circuit schematic block diagram of a test apparatus for a power semiconductor device provided in another embodiment of this disclosure; Figure 3 A schematic diagram of the three-dimensional structure of a test apparatus for a power semiconductor device provided in an embodiment of this disclosure under dynamic voltage application; Figure 4 A schematic diagram of the three-dimensional structure of a test apparatus for a power semiconductor device provided in an embodiment of this disclosure during electrical parameter measurement; Figure 5 This is a schematic flowchart of a testing method for a power semiconductor device provided in an embodiment of the present disclosure.

[0021] Figure label: 101 - Semiconductor device under test; 102 - Dynamic voltage generation unit 103-First probe 1031-First sub-probe 1032-Second sub-probe 104 - Parameter Measurement Circuit; 105 - Second Probe; 1051 - Third Sub-Probe 1052 - Fourth Sub-probe; 106 - Moving Part Detailed Implementation

[0022] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] In this disclosure, the terms “upper,” “lower,” “left,” “right,” “front,” “rear,” “top,” “bottom,” “inner,” “outer,” and “middle,” etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are primarily for the purpose of better describing this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.

[0025] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain circumstances to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0026] Furthermore, the terms "set up," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection via an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Example 1 To address at least some of the aforementioned problems, embodiments of this disclosure provide a testing apparatus for power semiconductor devices, with reference to... Figure 1 and Figure 2 The testing apparatus includes: a power semiconductor device under test 101, a dynamic voltage change rate application circuit, a first probe circuit, a parameter measurement circuit 104, and a second probe circuit; wherein, the dynamic voltage change rate application circuit is used to generate a dynamic voltage with a voltage change rate greater than a set threshold; the first probe circuit is coupled to the dynamic voltage change rate application circuit, and the first probe circuit includes a first probe 103 that is separable from or electrically connected to the power semiconductor device under test 101; wherein, when the first probe 103 is electrically connected to the power semiconductor device under test 101, the dynamic voltage change rate application circuit applies a dynamic voltage to the power semiconductor device under test 101 through the first probe circuit; the second probe circuit is coupled to the parameter measurement circuit, and the second probe circuit includes a second probe 105 that is electrically connected to the power semiconductor device under test 101; wherein, when the first probe 103 is separated from the power semiconductor device under test 101, the parameter measurement circuit 104 measures the electrical parameters of the power semiconductor device under test 101 through the second probe circuit; the first stray inductance of the first probe circuit is smaller than the second stray inductance of the second probe circuit.

[0029] In the above scheme, the first stray inductance of the first probe circuit is made smaller than the second stray inductance of the second probe circuit, and the first probe 103 can be separated from or electrically contacted with the power semiconductor device 101 under test. When the first probe 103 is electrically contacted with the power semiconductor device 101 under test, the dynamic voltage change rate application circuit applies a dynamic voltage with a voltage change rate greater than a set threshold to the power semiconductor device 101 under test through the first probe circuit with smaller stray inductance, thereby enabling the application of a high dV / dt dynamic voltage to the power semiconductor device (when the stray inductance of the circuit is large due to the addition of mechanical switches, etc., it is impossible to apply a dynamic voltage with a voltage change rate greater than the set threshold to the power semiconductor device, i.e., it is impossible to apply a high dV / dt dynamic voltage). When the first probe 103 is separated from the power semiconductor device 101 under test, the parameter measurement circuit 104 measures the electrical parameters of the power semiconductor device 101 under test through the second probe circuit with larger stray inductance, thereby achieving accurate extraction of the electrical parameters of the power semiconductor device. The disclosed solution employs a graded probe structure, which enables physical separation between the power semiconductor device under test (101) and the dynamic voltage change rate application circuit during parameter measurement, thus eliminating the influence of the dynamic voltage change rate application circuit on parameter measurement. This solution avoids and eliminates the influence of the mechanical relay added in conventional solutions on stray inductance.

[0030] The following is in conjunction with the appendix Figures 1 to 4 The apparatus of this disclosure will be described in detail.

[0031] For example, refer to Figure 1 and Figure 2 The total length of the first probe 103 in the first probe circuit is less than the total length of the second probe 105 in the second probe circuit. Because the probe structure is relatively complex, its parasitic inductance is directly proportional to its length. In this embodiment, by making the total length of the first probe 103 in the first probe circuit less than the total length of the second probe 105 in the second probe circuit, the stray inductance in the first probe circuit is reduced to that in the second probe circuit. Using a short probe in the first probe circuit ensures low stray inductance in the high dV / dt circuit (the dynamic voltage application circuit of the dynamic voltage change rate application circuit), while effectively eliminating the influence of the high dV / dt dynamic voltage change rate application circuit on the measured electrical parameters.

[0032] There are several ways to set up the dynamic voltage change rate application circuit, and some of them are exemplified below.

[0033] First, it should be noted that the dynamic voltage (dV / dt) can be generated by an external circuit (passive mode) or by the switching of the device itself (active mode). In some of the following embodiments, an N-type MOSFET device is used as an example. It should be understood that the power semiconductor device 101 under test is not limited to an N-type MOSFET device; other device types are also possible.

[0034] For example, refer to Figure 1 and Figure 2 The dynamic voltage change rate application circuit may include a dynamic voltage generating unit 102, which generates a dynamic voltage with a voltage change rate greater than a set threshold. The power semiconductor device under test 101 includes a first electrode structure under test, a second electrode structure under test, and a control electrode structure for controlling the conduction or cutoff between the first and second electrode structures under test. The first probe 103 includes a first sub-probe 1031 and a second sub-probe 1032. The first end of the first sub-probe 1031 is coupled to the first electrode of the dynamic voltage generating unit 102, and the second end of the first sub-probe 1031 is separable from or electrically connected to the first electrode structure under test of the power semiconductor device under test 101. The first end of the second sub-probe 1032 is coupled to the second electrode of the dynamic voltage generating unit 102, and the second end of the second sub-probe 1032 is separable from or electrically connected to the second electrode structure under test of the power semiconductor device under test 101. In this embodiment, the sampling passive mode generates dynamic voltage (dV / dt). At this time, the first sub-probe 1031 and the second sub-probe 1032 are directly coupled to the electrode structure of the power semiconductor device under test 101, thereby further reducing the stray inductance in the circuit that applies dynamic voltage to the power semiconductor device under test 101.

[0035] For example, refer to Figure 1 and Figure 2 The second probe 105 includes a third sub-probe 1051 and a fourth sub-probe 1052. The first end of the third sub-probe 1051 is coupled to the first electrode of the parameter measurement circuit 104, and the second end of the third sub-probe 1051 is electrically contacted with the first electrode structure of the power semiconductor device under test 101. The first end of the fourth sub-probe 1052 is coupled to the second electrode of the parameter measurement circuit 104, and the second end of the fourth sub-probe 1052 is electrically contacted with the second electrode structure of the power semiconductor device under test 101. The lengths of both the first sub-probe 1051 and the second sub-probe 1052 are less than the lengths of both the third and fourth sub-probes 1051 and 1052. This facilitates ensuring that the total length of the first probe 105 is less than the total length of the second probe 105, and reduces the stray inductance of the first probe circuit.

[0036] For example, refer to Figure 1 and Figure 2 The first sub-probe 1031 and the second sub-probe 1032 are short probes relative to the third sub-probe 1051 and the fourth sub-probe 1052, and the third sub-probe 1051 and the fourth sub-probe 1052 are long probes relative to the first sub-probe 1031 and the second sub-probe 1032. Exemplarily, the lengths of the first sub-probe 1031 and the second sub-probe 1032 can be equal. Exemplarily, the lengths of the third sub-probe 1051 and the fourth sub-probe 1052 can be equal.

[0037] Of course, in other embodiments, an active mode can also be used to generate the dynamic voltage (dV / dt). This will be described in detail below.

[0038] For example, refer to Figure 1 and Figure 2 The power semiconductor device under test 101 may include a first electrode structure under test, a second electrode structure under test, and a control electrode structure for controlling the conduction or cutoff between the first electrode structure under test and the second electrode structure under test. The dynamic voltage change rate application circuit may include a capacitor and an auxiliary power semiconductor device. The auxiliary power semiconductor device includes a first auxiliary electrode structure, a second auxiliary electrode structure, and an auxiliary control electrode structure for controlling the conduction or cutoff between the first auxiliary electrode structure and the second auxiliary electrode structure; the first electrode structure under test is electrically connected to the second auxiliary electrode structure. The first probe 103 includes a first sub-probe 1031 and a second sub-probe 1032. The first end of the first sub-probe 1031 is coupled to the first electrode of the capacitor, and the second end of the first sub-probe 1031 is separable from or electrically connected to the first auxiliary electrode structure of the auxiliary power semiconductor device; the first end of the second sub-probe 1032 is coupled to the second electrode of the capacitor, and the second end of the second probe 1032 is separable from or electrically connected to the second electrode structure of the power semiconductor device under test 101. By employing an active mode to generate the dynamic voltage (dV / dt), only one capacitor is required, simplifying the structure of the dynamic voltage change rate application circuit. In the above mode, PWM signals are applied to the control electrode structures of the power semiconductor device under test 101 and the auxiliary power semiconductor device, respectively, to control the alternating opening and closing of the power semiconductor device under test 101, thereby achieving the application of a dynamic voltage to the power semiconductor device under test 101.

[0039] For example, refer to Figure 1 and Figure 2The second probe 105 may include a third sub-probe 1051 and a fourth sub-probe 1052. The first end of the third sub-probe 1051 is coupled to the first electrode of the parameter measurement circuit 104, and the second end of the third sub-probe 1051 is electrically contacted with the first auxiliary electrode structure of the auxiliary power semiconductor device. The first end of the fourth sub-probe 1052 is coupled to the second electrode of the parameter measurement circuit 104, and the second end of the fourth sub-probe 1052 is electrically contacted with the second measured electrode structure of the power semiconductor device 101 under test. The lengths of both the first sub-probe 1051 and the second sub-probe 1052 are less than the lengths of both the third and fourth sub-probes 1051 and 1052. This facilitates ensuring that the total length of the first probe 105 is less than the total length of the second probe 105, and reduces the stray inductance of the first probe circuit.

[0040] For example, refer to Figure 1 and Figure 2 The testing apparatus may further include a PWM signal generator (not shown in the figure), which is coupled to the control electrode structure under test and the auxiliary control electrode structure. The PWM signal generator is configured to send PWM signals to the control electrode structure under test and the auxiliary control electrode structure, triggering the conduction or cutoff of the power semiconductor device 101 under test and the auxiliary power semiconductor device, thereby generating a dynamic voltage in the power semiconductor device 101 under test with a voltage change rate greater than a set threshold in conjunction with a capacitor. By applying PWM signals to the control electrode structures of the power semiconductor device 101 under test and the auxiliary power semiconductor device respectively, the alternating opening and closing of the power semiconductor device 101 under test is controlled, thereby achieving the application of a dynamic voltage to the power semiconductor device 101 under test.

[0041] For example, refer to Figure 1 and Figure 2 The auxiliary power semiconductor device and the power semiconductor device under test 101 are located on the same wafer. In this way, the power semiconductor device on the wafer itself can be used as an auxiliary power semiconductor device to apply dynamic voltage to the power semiconductor device under test 101, thereby simplifying the structure.

[0042] For example, refer to Figure 1 and Figure 2The auxiliary power semiconductor device and the power semiconductor device under test 101 can be located within the same or different power semiconductor packages. Various package types can be used for the power semiconductor packages. Specifically, the auxiliary power semiconductor device and the power semiconductor device under test 101 can be located on power semiconductor devices with different package types. When a power semiconductor package includes multiple power semiconductor devices, another power semiconductor device can be selected from the power semiconductor package containing the power semiconductor device under test 101 as the auxiliary power semiconductor device. In this case, the auxiliary power semiconductor device and the power semiconductor device under test 101 are located within the same power semiconductor package. When a power semiconductor package contains only one power semiconductor device, and this device is currently being tested as the power semiconductor device under test 101, a power semiconductor device can be selected from other power semiconductor packages as the auxiliary power semiconductor device. In this case, the auxiliary power semiconductor device and the power semiconductor device under test 101 are located within different power semiconductor packages.

[0043] For example, refer to Figure 1 and Figure 2 The testing apparatus may further include a moving component 106 connected to the first probe 103. The moving component 106 is used to: drive the first probe 103 to abut against the power semiconductor device to make electrical contact with the power semiconductor device; and drive the first probe 103 to move away from the power semiconductor device to separate the first probe 103 from the power semiconductor device. By setting the moving component 106 to drive the movement of the first probe 103, the electrical contact or separation of the first probe 103 with the power semiconductor device can be automatically achieved, thereby simplifying the operation.

[0044] refer to Figure 3 and Figure 4 Taking a three-dimensional image of one of the tested power semiconductor devices 101 as an example, the results are presented. Figure 3 As shown, the first sub-probe 1031 and the second sub-probe 1032 in the first probe 103, and the third sub-probe 1051 and the fourth sub-probe 1052 in the second probe 105 are all connected to the electrical terminals (first electrode structure and second electrode structure) of the power semiconductor device 101 under test. The test device can perform dynamic bias reliability testing on the power semiconductor device 101 under test and apply high dV / dt stress (dynamic voltage with a voltage change rate greater than a set threshold) to the device.

[0045] like Figure 4As shown, during the parameter measurement process, the third sub-probe 1051 and the fourth sub-probe 1052 of the second probe 105 are both connected to the electrical terminals (first electrode structure and second electrode structure) of the power semiconductor device 101 under test; the first sub-probe 1031 and the second sub-probe 1032 of the first probe 103 are both separated from the electrical terminals (first electrode structure and second electrode structure) of the power semiconductor device 101 under test. By separating the dynamic voltage change rate application circuit from the power semiconductor device 101 under test while maintaining contact with the parameter measurement circuit 104, electrical parameter measurements can be performed on the power semiconductor device 101 under test.

[0046] It should be noted that, in the above embodiments, the number of each electrode structure in the first electrode structure, the second electrode structure, and the control electrode structure included in the power semiconductor device under test 101 is not limited to one, and can also be multiple. For example, the number of first electrode structures can be two or more, and different first electrode structures are all coupled to the same first electrode region within the substrate of the power semiconductor device 101. Similarly, the number of each electrode structure in the first auxiliary electrode structure, the second auxiliary electrode structure, and the auxiliary control electrode structure included in the auxiliary power semiconductor device is not limited to one, and can also be multiple.

[0047] For example, refer to Figures 1 to 4 The first electrode structure under test, the second electrode structure under test, and the control electrode structure under test included in the power semiconductor device under test 101 can be a source electrode structure (S), a drain electrode structure (D), and a gate electrode structure (G), respectively. For example, referring to... Figure 1 and Figure 2 The first electrode structure under test can be a drain electrode structure (D), and the second electrode structure under test can be a source electrode structure (S).

[0048] It should also be noted that the number of probes included in the first sub-probe 1031, the second sub-probe 1032, the third sub-probe 1051, and the fourth sub-probe 1052 can be one or more. For example, the number of first sub-probes 1031 can be one or more.

[0049] Regarding the types of the first probe 103 and the second probe 105 described above, they can be any type of probe. For example, the first probe 103 and the second probe 105 can be spring probes, thereby increasing the stability of the electrical contact. Of course, in other embodiments, other types of probes can also be used (e.g., spring sheets).

[0050] The electrical parameter measurements performed on the power semiconductor device 101 under test can be of any type. For example, the electrical parameters of the power semiconductor device 101 under test can include, but are not limited to, leakage current testing (Idss and Igss), threshold voltage testing (Vth), and breakdown voltage testing (BV).

[0051] The power semiconductor device 101 under test described above can be any type of power semiconductor device. For example, the power semiconductor device can be, but is not limited to, a MOSFET device. Exemplarily, the power semiconductor device can also be a silicon-based IGBT device, a GaN-based power semiconductor device, a silicon carbide-based power device, etc.

[0052] The moving component 106 can be configured in various ways. For example, the moving component 106 may include a probe connector, with a first probe 103 fixedly connected to the probe connector. The probe connector is configured to: drive the first probe 103 to abut against the surface of the first electrode structure and / or the second electrode structure of the power semiconductor device 101 under test, to make electrical contact with the power semiconductor device 101 under test; and drive the first probe 103 to move away from the power semiconductor device 101 under test, to separate the first probe 103 from the surface of the first electrode structure and / or the second electrode structure of the power semiconductor device 101 under test. This simplifies the configuration of the moving component 106.

[0053] The probe connector can be configured in various ways; for example, it can use, but is not limited to, a probe sleeve as the probe connector. The moving part 106 can also be configured in various ways; for example, it can include, but is not limited to, a power output device such as a motor, or a transmission device such as, but is not limited to, a robotic arm, to drive the probe connector.

[0054] Example 2 This disclosure also provides a testing method for power semiconductor devices. This testing method is based on any of the power semiconductor device testing apparatuses provided in Embodiment 1 of this disclosure, and refers to... Figures 1 to 5 The method mainly includes the following steps: In step 510, when the first probe 103 is in electrical contact with the power semiconductor device under test 101 and the second probe 105 is in electrical contact with the power semiconductor device under test 101, the dynamic voltage change rate application circuit applies a dynamic voltage to the power semiconductor device under test 101 through the first probe circuit to perform a dynamic reverse bias test on the power semiconductor device under test 101. In step 520, when the first probe 103 is separated from the power semiconductor device 101 under test and the second probe 105 is in electrical contact with the power semiconductor device 101 under test, the parameter measurement circuit 104 measures the electrical parameters of the power semiconductor device 101 under test through the second probe circuit.

[0055] In summary, the various embodiments described above have the following beneficial effects: Addressing the shortcomings of existing technical solutions, this disclosure proposes a test device for power semiconductor devices based on a hierarchical probe structure, employing a time-sharing technique between dynamic reverse bias (applying a high dV / dt dynamic voltage to the power semiconductor device) and electrical parameter measurement. Specifically, the first probe 103 of the dynamic voltage change rate application circuit and the second probe 105 of the parameter measurement circuit 104 are connected to the power semiconductor device under test 101 using probes of different lengths. The power semiconductor device under test 101 or the first probe 103 makes contact with each other using a time-sharing scheme via a moving part 106. During the reverse bias test or aging process of the power semiconductor device under test 101, the first probe 103 of the dynamic voltage change rate application circuit of this disclosure reliably contacts all electrical terminals (first electrode structure, second electrode structure, and control electrode structure) of the power semiconductor device under test 101. The dynamic voltage change rate application circuit can apply a high dV / dt dynamic voltage to the power semiconductor device under test 101, achieving reverse bias stress assessment of the device. When electrical parameters of the power semiconductor device 101 under test need to be measured, the moving part 106 actuates, causing the first probe 103 of the dynamic voltage change rate application circuit to separate from the electrical terminals of the power semiconductor device 101 under test, while the second probe 105 of the parameter measurement circuit 104 remains in contact with the electrical terminals of the power semiconductor device 101 under test. This disclosed solution employs a graded probe structure, which enables physical separation of the power semiconductor device 101 under test from the dynamic voltage change rate application circuit during parameter measurement, eliminating the influence of the dynamic voltage change rate application circuit on parameter measurement. This solution avoids and eliminates the influence of the mechanical relay added in conventional solutions on stray inductance.

[0056] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A testing apparatus for power semiconductor devices, characterized in that, include: The semiconductor device under test; A dynamic voltage change rate application circuit is used to generate a dynamic voltage with a voltage change rate greater than a set threshold. A first probe circuit coupled to the dynamic voltage change rate application circuit includes a first probe that is separable from or electrically contacted with the power semiconductor device under test; wherein, when the first probe is electrically contacted with the power semiconductor device under test, the dynamic voltage change rate application circuit applies the dynamic voltage to the power semiconductor device under test through the first probe circuit; Parameter measurement circuit; A second probe circuit coupled to the parameter measurement circuit includes a second probe that is electrically in contact with the power semiconductor device under test; wherein, when the first probe is separated from the power semiconductor device under test, the parameter measurement circuit measures the electrical parameters of the power semiconductor device under test through the second probe circuit. Wherein, the first stray inductance of the first probe circuit is less than the second stray inductance of the second probe circuit.

2. The testing apparatus as described in claim 1, characterized in that, The total length of the first probe in the first probe circuit is less than the total length of the second probe in the second probe circuit.

3. The testing apparatus as described in claim 2, characterized in that, The dynamic voltage change rate application circuit includes: a dynamic voltage generating unit, which is used to generate a dynamic voltage with a voltage change rate greater than the set threshold. The power semiconductor device under test includes a first electrode structure under test, a second electrode structure under test, and a control electrode structure under test that controls the conduction or cutoff between the first electrode structure under test and the second electrode structure under test. The first probe includes a first sub-probe and a second sub-probe. The first end of the first sub-probe is coupled to the first electrode of the dynamic voltage generating unit, and the second end of the first sub-probe is separable from or electrically connected to the first electrode structure of the power semiconductor device under test. The first end of the second sub-probe is coupled to the second electrode of the dynamic voltage generating unit, and the second end of the second sub-probe is separable from or electrically connected to the second electrode structure of the power semiconductor device under test.

4. The testing apparatus as described in claim 3, characterized in that, The second probe includes a third sub-probe and a fourth sub-probe; The first end of the third sub-probe is coupled to the first electrode of the parameter measurement circuit, and the second end of the third sub-probe is electrically connected to the first electrode structure of the power semiconductor device under test. The first end of the fourth sub-probe is coupled to the second electrode of the parameter measurement circuit, and the second end of the fourth sub-probe is electrically contacted with the second electrode structure of the power semiconductor device under test. The lengths of the first sub-probe and the second sub-probe are both less than the lengths of the third sub-probe and the fourth sub-probe.

5. The testing apparatus as described in claim 2, characterized in that, The power semiconductor device under test includes a first electrode structure under test, a second electrode structure under test, and a control electrode structure under test that controls the conduction or cutoff between the first electrode structure under test and the second electrode structure under test. The dynamic voltage change rate application circuit includes: a capacitor and an auxiliary power semiconductor device; The auxiliary power semiconductor device includes a first auxiliary electrode structure, a second auxiliary electrode structure, and an auxiliary control electrode structure for controlling the conduction or cutoff between the first auxiliary electrode structure and the second auxiliary electrode structure; the first electrode structure under test is electrically connected to the second auxiliary electrode structure. The first probe includes a first sub-probe and a second sub-probe. The first end of the first sub-probe is coupled to the first electrode of the capacitor, and the second end of the first sub-probe is separable from or electrically connected to the first auxiliary electrode structure of the auxiliary power semiconductor device. The first end of the second sub-probe is coupled to the second electrode of the capacitor, and the second end of the second sub-probe is separable from or electrically connected to the second electrode structure of the power semiconductor device under test.

6. The testing apparatus as described in claim 5, characterized in that, The second probe includes a third sub-probe and a fourth sub-probe; The first end of the third sub-probe is coupled to the first electrode of the parameter measurement circuit, and the second end of the third sub-probe is electrically contacted with the first auxiliary electrode structure of the auxiliary power semiconductor device. The first end of the fourth sub-probe is coupled to the second electrode of the parameter measurement circuit, and the second end of the fourth sub-probe is electrically contacted with the second electrode structure of the power semiconductor device under test. The lengths of the first sub-probe and the second sub-probe are both less than the lengths of the third sub-probe and the fourth sub-probe.

7. The testing apparatus as described in claim 5, characterized in that, Also includes: A PWM signal generator, wherein the PWM signal generator is coupled to the control electrode structure under test and the auxiliary control electrode structure; The PWM signal generator is configured to send a PWM signal to the control electrode structure under test and the auxiliary control electrode structure, triggering the power semiconductor device under test and the auxiliary power semiconductor device to turn on or off, thereby cooperating with the capacitor to generate a dynamic voltage in the power semiconductor device under test with a voltage change rate greater than the set threshold.

8. The testing apparatus as described in claim 5, characterized in that, The auxiliary power semiconductor device and the power semiconductor device under test are located on the same wafer; or... The auxiliary power semiconductor device and the power semiconductor device under test are located in the same or different power semiconductor packages.

9. The testing apparatus as described in claim 1, characterized in that, Also includes: A moving component connected to the first probe, the moving component being configured to: drive the first probe to abut against the power semiconductor device to make electrical contact with the power semiconductor device; and drive the first probe to move away from the power semiconductor device to separate the first probe from the power semiconductor device.

10. A testing method for power semiconductor devices, characterized in that, The test method is based on the test apparatus for power semiconductor devices as described in any one of claims 1 to 9, and the method includes: When the first probe is in electrical contact with the power semiconductor device under test and the second probe is in electrical contact with the power semiconductor device under test, the dynamic voltage change rate application circuit applies a dynamic voltage to the power semiconductor device under test through the first probe circuit to perform a dynamic reverse bias test on the power semiconductor device under test. When the first probe is separated from the power semiconductor device under test and the second probe is in electrical contact with the power semiconductor device under test, the parameter measurement circuit measures the electrical parameters of the power semiconductor device under test through the second probe loop.

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