Chip and chip debugging system for interface multiplexing

Abstract

The application discloses a chip and a chip debugging system, and relates to the technical field of chip debugging. The chip comprises a controller, a reset signal generating unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module and a general interface. The general interface is used for connecting with a debugger, and the instruction receiving unit is connected with the general interface. The reset signal generating unit is used for generating an effective first reset signal and a second reset signal. The release time of the first reset signal is earlier than the release time of the second reset signal. The instruction receiving unit is used for detecting whether an instruction sent by the debugger is received after the release of the first reset signal and before the release of the second reset signal. When the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to select the general interface and the debugging module. When the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to select the general interface and the functional module. According to the application, no additional multiplexing control pin is needed, and flexible multiplexing of a debugging interface and a functional interface is realized.

Description

Technical Field

[0001] This invention relates to the field of chip design, and more particularly to an interface-multiplexed chip and a chip debugging system. Background Technology

[0002] Debugging is an essential step to ensure the correct operation of the program within a chip. A debugger can download the program through a debug interface and test and modify it. Common debug interfaces include the Joint Test Action Group (JTAG) interface and the C2 interface. Typically, chips can reserve dedicated pins for programming and debugging; for example, the JTAG interface requires four pins for debugging, and the C2 interface requires two. For chips with a limited number of pins, designing debug pins can lead to a waste of pin resources. Furthermore, many mass-produced circuit boards do not retain debug interfaces, requiring rewiring to connect them when debugging the chip program. To save chip pin resources and retain debug interfaces on the circuit board, debug interfaces can be multiplexed with functional interfaces. When multiplexing debug and functional interfaces, a multiplexer can be used to select between the debug interface and the functional interface. However, after the multiplexer selects the functional interface, the external debugger cannot control the multiplexer to select the debug interface, causing debugging problems because the debugger cannot connect to the debug interface.

[0003] To address this issue, one existing method involves using the level signal of the multiplexing control pin and whether the multiplexing control register receives a debug mode trigger command to determine whether the signal multiplexing unit selects the functional interface signal or the debug interface signal, thus choosing to use either the functional interface or the debug interface. The debug mode trigger command is issued by the user via a button, toggle switch, or menu selection. However, this method requires an additional multiplexing control pin.

[0004] Another approach is to multiplex the serial interface and the debug interface. When the serial interface receives a simulation / debugging switching command with a special instruction format, the serial communication signal is identified as a simulation / debugging signal. The serial interface can be a Serial Peripheral Interface (SPI) or a Universal Asynchronous Receiver / Transmitter (UART) serial interface. However, the debug interface in this method can only be multiplexed with the interface of a specific functional module, which limits its application.

[0005] In summary, the following problems exist when the debugging interface and the functional interface are reused in the existing technology: (1) additional multiplexing control pins are required; (2) it can only be reused with specific functional modules, which limits its application. Summary of the Invention

[0006] The technical problem solved by this invention is how to flexibly reuse the debugging interface and the functional interface without setting up additional multiplexed control pins.

[0007] To address the aforementioned problems, this invention provides an interface multiplexing chip. The chip includes a controller, a reset signal generation unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module, and a general-purpose interface. The general-purpose interface is used to connect to a debugger, and the instruction receiving unit is connected to the general-purpose interface to receive instructions sent by the debugger. The reset signal generation unit generates valid first and second reset signals, with the release time of the first reset signal preceding the release time of the second reset signal; release refers to the signal transitioning from valid to invalid. The instruction receiving unit detects the first and second reset signals, and... After the first reset signal is released and before the second reset signal is released, it is detected whether an instruction issued by the debugger has been received; the control terminal of the interface multiplexing unit is connected to the instruction receiving unit and the controller respectively. Under the control of the instruction receiving unit or the controller, the interface multiplexing unit selects the general interface with the debug module or the functional module; wherein, when the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to select the general interface with the debug module; when the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to select the general interface with the functional module.

[0008] Optionally, when controlling the interface multiplexing unit, the priority of the instruction receiving unit is higher than the priority of the controller.

[0009] Optionally, the instruction receiving unit is further configured to detect whether a valid first reset signal has been received, and the instruction receiving unit resets when a valid first reset signal is detected.

[0010] Optionally, a valid second reset signal is used to reset at least one of the other circuit units in the chip besides the instruction receiving unit.

[0011] Optionally, a low-level signal for the first reset signal and / or the second reset signal indicates that the first reset signal and / or the second reset signal is valid.

[0012] Optionally, the reset signal generation unit is used to generate a valid first reset signal and a second reset signal after the chip is powered on.

[0013] Optionally, after the chip is powered on, the interface multiplexing unit selects the general interface and the debugging module.

[0014] Optionally, the instruction receiving unit is further configured to return a response signal to the debugger after detecting that the instruction has been received.

[0015] Optionally, the debug module interface includes a JTAG interface and / or a C2 interface.

[0016] This invention also provides a chip debugging system, which includes the above-mentioned interface multiplexing chip and a debugger.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0018] The interface multiplexing chip proposed in this invention receives instructions sent by the debugger during the reset period (specifically, the time interval between the release of the first and second reset signals). If the instruction receiving unit does not receive an instruction during the reset period, the controller controls the interface multiplexing unit to select either the debug module's interface or the functional module's interface. If the instruction receiving unit receives an instruction during the reset period, it controls the interface multiplexing unit to select the debug module's interface. Cases where the debugger does not send an instruction, sends an incorrectly formatted instruction, or the instruction content is mismatched, all fall under the category of the instruction receiving unit not receiving an instruction and will not trigger the instruction receiving unit to control the interface multiplexing unit to select the debug module's interface. This invention does not impose any restrictions on functional modules or their interfaces. Regardless of which functional module's interface the controller controls the interface multiplexing unit to select, the debugger can send instructions during the reset period, causing the interface multiplexing unit to reselect the debug module's interface until a reset occurs again. In other words, when this invention multiplexes the debug interface and the functional interface, the debug module can multiplex its interface with any functional module, breaking the limitations of traditional interface multiplexing. In addition, the above instructions are received through a general-purpose interface during reset, without the need for additional multiplexed control pins. This general-purpose interface can be any interface available to the chip, thus saving pin resources. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a chip for interface multiplexing according to the first embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of a reset signal according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of data transmission between a debugger and an instruction receiving unit according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the specific structure of a chip debugging system according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the specific structure of a chip debugging system according to another embodiment of the present invention. Detailed Implementation

[0024] Those skilled in the art will understand that the JTAG interface employs a four-wire serial communication protocol. The four signal lines of the JTAG interface include a Test Mode Selection (TMS) signal, a Test Clock (TCK) input signal, a Test Data Input (TDI) signal, and a Test Data Output (TDO) signal. Chips containing a JTAG interface internally have a Test Access Port (TAP) controller. The TAP controller's state machine changes state via TCK and TMS to input data and instructions. Data is stored in the data register, and instructions are stored in the instruction register.

[0025] The C2 interface uses a two-wire serial communication protocol. Communication devices using the C2 interface include the interface host (also called the debugger) and the interface slave (also called the device to be debugged). The C2 interface protocol includes two lines: a data line (C2D) and a clock line (C2CK). The operation of the C2 interface is similar to JTAG, mapping three JTAG data signals (TDI, TDO, and TMS) to a bidirectional C2 data line (C2D). The signal direction of C2D is strictly controlled by the instruction protocol. The debugger implements in-system programming and debugging functions through a set of data registers in the C2 interface. The address register defines which data registers the debugger can access (similar to the instruction register in JTAG).

[0026] As mentioned in the background art, when the debugging interface (such as the JTAG interface and C2 interface mentioned above) is reused with the functional interface in the prior art, the following problems exist: (1) additional multiplexing control pins are required; (2) it can only be reused with specific functional modules, which limits its application.

[0027] To address the aforementioned problems, this invention provides an interface multiplexing chip. The chip includes a controller, a reset signal generation unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module, and a general-purpose interface. The general-purpose interface is used to connect to a debugger, and the instruction receiving unit is connected to the general-purpose interface to receive instructions sent by the debugger. The reset signal generation unit generates valid first and second reset signals, with the release time of the first reset signal preceding the release time of the second reset signal; release refers to the signal transitioning from valid to invalid. The instruction receiving unit receives the first and second reset signals and... After receiving the first reset signal and before receiving the second reset signal, the system checks whether an instruction from the debugger has been received. The control terminal of the interface multiplexing unit is connected to both the instruction receiving unit and the controller. Under the control of the instruction receiving unit or the controller, the interface multiplexing unit selects the general interface with the debug module or the functional module. Specifically, when the instruction receiving unit receives the instruction, it controls the interface multiplexing unit to select the general interface with the debug module; when the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to select the general interface with the functional module. Therefore, when designing a chip, any functional module interface can be multiplexed with the debug module interface without adding control pins, saving pin resources.

[0028] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a first type of interface multiplexing chip according to an embodiment of the present invention. Specifically, the chip 10 includes a controller 101, a reset signal generation unit 102, an instruction receiving unit 103, an interface multiplexing unit 104, a debugging module 105, a functional module 106, and a general interface 107. The general interface 107 is used to connect to a debugger 20, and the instruction receiving unit 103 is connected to the general interface 107 to receive instructions sent by the debugger 20.

[0030] Among them, the general interface 107 is an interface reused by the debugging module 105 and the functional module 106.

[0031] Functional module 106 can be a module that implements various functions. For example, functional module 106 can be a Universal Serial Bus (USB) module, a Pulse Width Modulation (PWM) module, or any other module. The USB module is used for communication with a host computer or other computer. This solution uses an example with two signal lines: USB_DP for transmitting positive USB data signals and USB_DM for transmitting negative USB data signals. The PWM module outputs a square wave with a fixed period and adjustable width. This solution uses an example with two signal lines: PWM0 and PWM1.

[0032] The interfaces of the debug module 105 include, but are not limited to, the JTAG interface and / or the C2 interface.

[0033] Debugger 20 is a debugging device separate from chip 10; that is, debugger 20 and chip 10 are two independent devices. If programming and debugging of the chip are required, debugger 20 can be connected to the general interface 107 of chip 10. Debugger 20 can send instructions to instruction receiving unit 103 through general interface 107.

[0034] The controller 101 can be various processors or processor cores, such as a central processing unit (CPU), which can execute corresponding operations and output various appropriate signals by running instructions.

[0035] The reset signal generation unit 102 generates a valid first reset signal and a valid second reset signal, wherein the release time of the first reset signal is earlier than the release time of the second reset signal, and the release refers to the signal changing from valid to invalid. The instruction receiving unit 103 detects the first reset signal and the second reset signal, and detects whether an instruction issued by the debugger 20 is received after the first reset signal is released and before the second reset signal is released. In other words, the instruction receiving unit 103 detects whether an instruction issued by the debugger 20 is received within a time window defined between the release time of the first reset signal and the release time of the second reset signal. The release time of the first reset signal refers to the time when the first reset signal changes from valid to invalid, and the release time of the second reset signal refers to the time when the second reset signal changes from valid to invalid.

[0036] Optional, please see Figure 2 , Figure 2This is a schematic diagram of a reset signal. When the chip 10 is powered on, the voltage at the power supply port VDD gradually rises to the operating voltage, and the reset signal generation unit 102 generates a valid first reset signal (i.e., Figure 2 The reset signal 1) and the second reset signal (i.e. Figure 2 The reset signal 2 in the middle is released, and the first reset signal and the second reset signal are released in sequence.

[0037] The time interval between the release times of the first reset signal and the second reset signal is t. The value of t can be preset as needed, and it must be ensured that the instruction receiving unit 103 can successfully receive the instruction within the time interval t. Within the time interval t, the debugger 20 can send an instruction to the instruction receiving unit 103 to control the general interface 107 to be connected to the debug module 105, that is, to form a path between the general interface 107 and the debug module 105.

[0038] Optionally, the generation and release timing of the first reset signal and the second reset signal can be other than after the chip 10 is powered on. For example, after the chip 10 detects that the debugger 20 is connected to the general interface 107, the reset signal generation unit 102 can be controlled to generate a valid first reset signal and a second reset signal, and then release the first reset signal and the second reset signal, and the release time of the first reset signal is earlier than the release time of the second reset signal.

[0039] Optionally, the instruction receiving unit 103 is further configured to detect whether the first reset signal is valid, and the instruction receiving unit 103 resets when a valid first reset signal is detected. That is, the first reset signal is used to reset the instruction receiving unit 103.

[0040] Optionally, the valid second reset signal is used to reset at least one of the other circuit units in the chip 10 besides the instruction receiving unit 103. That is, the second reset signal is used to reset other circuit units in the chip.

[0041] Optionally, a low-level signal for the first reset signal and / or the second reset signal indicates that the first reset signal and / or the second reset signal is valid. Please continue to see... Figure 2 When the first reset signal / second reset signal is low, it indicates that the first reset signal / second reset signal is valid; when it changes from low to high, it indicates that the first reset signal / second reset signal is released. It should be noted that the relationship between the high / low level and the validity of the first reset signal / second reset signal includes, but is not limited to, […]. Figure 2 The limitation.

[0042] Furthermore, the instruction receiving unit 103 resets when it detects that the first reset signal is valid, and other circuit units of the chip 10 reset when they detect that the second reset signal is valid. Furthermore, the instruction receiving unit 103 ceases operation after detecting that the second reset signal has been released; that is, it no longer checks whether an instruction has been received.

[0043] The control terminal 1041 of the interface multiplexing unit 104 is connected to the instruction receiving unit 103 and the controller 101, respectively. Under the control of the instruction receiving unit 103 or the controller 101, the interface multiplexing unit 104 selects the general interface 107 to connect with the debugging module 105 or the functional module 106. Selection means choosing one of the debugging module 105 and the functional module 106 to connect with the general interface 107. Specifically, when the instruction receiving unit 103 receives the instruction, it controls the interface multiplexing unit 104 to connect the general interface 107 to the debugging module 105; when the instruction receiving unit 103 does not receive the instruction, the controller 101 controls the interface multiplexing unit 104 to connect the general interface 107 to the functional module 106. As a non-limiting example, the interface multiplexing unit 104 may include a multiplexer.

[0044] The interface multiplexing unit 104 controls which module among the general interface 107, debug module 105, and functional module 106 is selected. When one of the modules is selected, the general interface 107 serves as the input / output interface for the selected module. If the instruction receiving unit 103 does not receive an instruction from the debugger 20 within the time interval t, the chip 10 can control the interface multiplexing unit 104 to select which module based on software or other control signals stored in its memory (flash) via the controller 101. That is, the control signal sources of the control terminal 1041 of the interface multiplexing unit 104 can include two sets: the first set of control signals comes from the instructions issued by the debugger 20 through the instruction receiving unit 103, and the second set of control signals comes from the signals issued by the controller 101 of the chip 10.

[0045] Optionally, the instruction receiving unit 103 and the controller 101 can be connected to the interface multiplexing unit 104 through an arbitration module. The arbitration module is used to process the two sets of control signals to determine which set of control signals to select to control the interface multiplexing unit 104.

[0046] Optionally, when controlling the interface multiplexing unit 104, the instruction receiving unit 103 has a higher priority than the controller 101. That is, the first set of control signals has a higher priority than the second set of control signals. In other words, if both the first set of control signals and the second set of control signals exist simultaneously, the first set of control signals is preferentially selected to control the interface multiplexing unit 104.

[0047] In one embodiment, the instruction issued by the debugger 20 for controlling the interface multiplexing unit 104 to select the general interface 107 and the debugging module 105 has a preset information structure. The instruction receiving unit 103 is considered to have received the instruction only when it receives an instruction that satisfies this information structure. Further, the information structure of the instruction includes: a start command + instruction content. After receiving the start command, the instruction receiving unit 103 begins receiving and parsing the instruction content. If the parsing result is correct, it indicates that the instruction receiving unit 103 has received the instruction.

[0048] Optionally, the instruction receiving unit 103 is further configured to return an acknowledgment signal to the debugger 20 after detecting that the instruction has been received; if the instruction receiving unit 103 receives an incorrect instruction, it will not return an acknowledgment signal. That is, the instruction receiving unit 103 informs the debugger 20 through the acknowledgment signal that it has controlled the general interface 107 to be selected with the debugging module 105, and the debugger 20 can debug the chip 10 through the debugging module 105.

[0049] For further information, please see [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of data transmission between a debugger and an instruction receiving unit. The instructions transmitted in the connection path between the two include "start command + instruction content + response signal". The signal lines of the instruction receiving unit 103 may include data lines and clock lines, which can be connected to any one of the signal lines of the general interface 107, that is, the general interface 107 includes at least two signal lines.

[0050] During the period between the release of the first reset signal and the non-release of the second reset signal, the instruction receiving unit 103 uses at least two signal lines of the general interface 107 to receive instructions. During this period, the general interface 107 will not be occupied by any functional module until the second reset signal is released. After the second reset signal is released, the instruction receiving unit 103 no longer receives instructions and no longer occupies the general interface 107, which can be used by other functional modules.

[0051] The start command (taking a low level for four clock cycles as an example) and the instruction content (taking 0Xa5 as an example) are output from debugger 20 to instruction receiving unit 103; the acknowledge signal (taking 0X55 as an example) is output from instruction receiving unit 103 to debugger 20 after receiving the start command and instruction content. The signal transmission between the two is sent through data lines and clock lines. For chip 10, the clock line is an input signal, and the data line is an input signal during the period when debugger 20 sends the start command and instruction content, and an output signal during the period when instruction receiving unit 103 returns the acknowledge signal.

[0052] Therefore, the instructions of this invention are sent via the data line and clock line during reset, eliminating the need for additional multiplexed control pins. The data line and clock line can use any available interface on the chip, thus saving pin resources.

[0053] In one embodiment, the interface multiplexing unit 104 selects the general interface 107 and the debugging module 105 by default. That is, after the chip 10 is powered on, the interface multiplexing unit 104 selects the general interface 107 and the debugging module 105.

[0054] Figure 1 During the reset period (i.e., the period between the release of the first reset signal and the second reset signal), the chip 10 receives instructions sent by the debugger 20 through the instruction receiving unit 103. If the instruction receiving unit 103 does not receive an instruction during the reset period, the controller 101 controls the interface multiplexing unit 104 to select the interface of the debug module 105 or the interface of the function module 106. If the instruction receiving unit 103 receives an instruction during the reset period, the interface multiplexing unit 104 can only select the interface of the debug module 105. If the debugger 20 does not send an instruction, sends an incorrect instruction format, or the instruction content does not match, these are all considered cases where the instruction receiving unit 103 has not received an instruction, and will not trigger the instruction receiving unit 103 to control the interface multiplexing unit 104 to select the interface of the debug module 105. This invention places no restrictions on functional module 106 or its interface. Regardless of which functional module's interface is selected by the interface multiplexing unit 104 controlled by the controller 101, the debugger 20 can always send instructions during a reset to allow the interface multiplexing unit 104 to reselect the debug module 105's interface until a reset occurs. In other words, when this invention multiplexes the debug interface with the functional interface, the debug module can multiplex its interface with any functional module, breaking the limitations of traditional interface multiplexing.

[0055] This invention also provides a chip debugging system, characterized in that the debugging system includes, as described in the following embodiments: Figures 1 to 3 The interface reuses chip 10 and debugger 20. The present invention will be further described in detail below through two specific embodiments.

[0056] Please see Figure 1 and Figure 4 , Figure 4 This is a schematic diagram of the specific structure of a chip debugging system. The functional module 106 includes a USB module 1061 and a PWM module 1062. The debugging module 105 has a C2 interface (the debugging module 105 can also be called a C2 debugging module). The general interface 107 includes pins P40 and P41. The USB module 1061 is connected to the interface multiplexing unit 104 via signal lines 408 and 409. The PWM module 1062 is connected to the interface multiplexing unit 104 via signal lines 406 and 407. The C2 debugging module 105 is connected to the interface multiplexing unit 104 via signal lines 404 and 405. The interface multiplexing unit 104 selects one of the USB module 1061, PWM module 1062, and C2 debugging module 105 to be connected to the general interface 107. Signal line 401 is used to transmit the first reset signal output by the reset signal generation unit 102; signal line 402 is used to transmit the second reset signal output by the reset signal generation unit 102. Signal line 403 is used to transmit control signals from the instruction receiving unit 103 to the interface multiplexing unit 104; signal line 404 is the data line C2D of the C2 debugging module 105; signal line 405 is the clock line C2CK of the C2 debugging module 105; signal line 406 is the signal line PWM0 of the PWM module 1062; signal line 407 is the signal line PWM1 of the PWM module 1062; signal line 408 is the signal line USB_DP of the USB module 1061; signal line 409 is the signal line USB_DM of the USB module 1061. Signal line 410 is the clock line of the instruction receiving unit 103, that is, the instruction receiving unit 103 receives the clock signal sent by the debugger 20 through signal line 410; signal line 411 is the data line of the instruction receiving unit 103, that is, the instruction receiving unit 103 receives the data signal sent by the debugger 20 through signal line 411. In this embodiment, the interface multiplexing unit 104 defaults to selecting the signal line of the C2 debugging module 105.

[0057] In this embodiment, the debugger first downloads the software program 1 executed by the USB module 1061 to the chip 10 and runs program 1. Then, it downloads the software program 2 executed by the PWM module 1062 to the chip 10 and runs program 2. Program 1 is controlled by the controller 101 ( Figure 4(Not shown) The control interface multiplexing unit 104 selects pins P40 and P41 to connect with the interface of the USB module 1061 (i.e., signal lines 408 and 409). That is, the interface multiplexing unit 104 selects the interface of the USB module 1061 to connect with pins P40 and P41, and starts the USB module. Program 2 controls the interface multiplexing unit 104 through the controller 101 to select pins P40 and P41 to connect with the interface of the PWM module 1062 (i.e., signal lines 406 and 407), and starts the PWM module.

[0058] Figure 4 The specific usage of the example is as follows:

[0059] Method 1: Multiplex pins P40 and P41 into the interface of USB module 1061. The specific usage process includes the following actions: (1) Connect the debugger to pins P40 and P41 of chip 10; (2) Power on and reset chip 10; During the first download, there is no software program in chip 10, and the interface multiplexing unit 104 selects the interface of debug module 105 by default after the reset is released, so no command needs to be sent during this power-on reset process. (3) After the second reset signal is released, debugger 20 downloads program 1 to chip 10 through pins P40 and P41. (4) After the download is completed, disconnect debugger 20 from pins P40 and P41; (5) Chip 10 runs program 1, and controller 101 controls interface multiplexing unit 104 to select the interface of USB module 1061 and start USB module 1061.

[0060] Method 2: Multiplex pins P40 and P41 as the interface of the C2 debug module 105. After program 1 starts running, P40 and P41 are occupied by the USB module 1061. After the debugger 20 is connected to pins P40 and P41, it cannot be directly connected to the C2 debug module 105. Even if the program 1 is restarted after power-on reset, there will be a short time before the program 1 control interface multiplexing unit 104 selects the interface of the USB module 1061. If this time is relatively long, the debugger 20 will have enough time to occupy pins P40 and P41 and start debugging. If this time is very short, the debugger 20 cannot start debugging. Therefore, the following steps need to be performed to maintain the debugger 20's occupation of pins P40 and P41: (1) Connect the debugger 20 to the chip pins P40 and P41; (2) Power-on reset the chip 10. During the power-on reset (i.e., after the first reset signal is released and before the second reset signal is released), the debugger 20 sends an instruction (such as 0xa5) until the debugger receives an acknowledgment signal (such as 0x55). After the instruction receiving unit 103 receives 0xa5, the control interface multiplexing unit 104 selects the interface of the debug module. (3) After the power-on reset is completed, since the instruction receiving unit 103 has a higher priority for controlling the interface multiplexing unit 104 than the controller 101, pins P40 and P41 are still occupied by the interface of the debug module.

[0061] Method 3: Multiplex pins P40 and P41 as the interface of PWM module 1062. After using method 2, debugger 20 is connected to debug module 105 through pins P40 and P41. The specific usage process includes the following actions: (1) Debugger 20 downloads program 2 to chip 10 through pins P40 and P41. (2) After downloading, debugger 20 is disconnected from pins P40 and P41. (3) Chip 10 runs program 2, controls interface multiplexing unit 104 to select the interface of PWM module 1062, and starts PWM module 1062 to work.

[0062] Please see Figure 1 and Figure 5 , Figure 5This is a schematic diagram of the specific structure of a debugging system for another chip, showing a JTAG debugging module and an SPI module (i.e., the interface of this module is a Serial Peripheral Interface, abbreviated as SPI). The instruction receiving unit, the debugging module 105 with a C2 interface and a JTAG interface (the debugging module 105 can also be called a JTAG debugging module), the functional module 106 including the SPI module, and the general interface 107 including multiplexed pins P50, P51, P52, and P53, allowing the debugger 20 to be connected to at least two of pins P50, P51, P52, and P53. Figure 5 (This is illustrated using a connection to P50 and P51 as an example). SPI is a high-speed, full-duplex, synchronous communication bus.

[0063] Among them, signal line 501 is used to transmit the first reset signal output by the reset signal generation unit 102; signal line 502 is used to transmit the second reset signal output by the reset signal generation unit 102; signal line 503 is used to transmit the control signal from the instruction receiving unit 103 to the interface multiplexing unit 104. Signal line 504 is the TMS signal line of the JTAG debugging module 105; signal line 505 is the clock line TCK of the JTAG debugging module 105; signal line 506 is the input signal line TDI of the JTAG debugging module 105; and signal line 507 is the output signal line TDO of the JTAG debugging module 105. Signal line 508 is the slave enable signal line SSN of SPI module 106; signal line 509 is the clock signal line SCK of SPI module 106; signal line 510 is the master input and slave data input signal line MOSI of SPI module 106; signal line 511 is the master data input and slave data output signal line MISO of SPI module 106; signal line 512 is the clock line of instruction receiving unit 103, through which instruction receiving unit 103 receives the clock signal sent by debugger 20; signal line 513 is the data line of instruction receiving unit, through which instruction receiving unit 103 receives the clock signal sent by debugger 20.

[0064] Optionally, the program in chip 10 has already multiplexed pins P50, P51, P52, and P53 into an interface for SPI module 106. Now, a new program needs to be downloaded to chip 10 and debugged. This new program will not control the interface multiplexing unit 104. The specific steps are as follows:

[0065] (1) Connect debugger 20 to pins P50 and P51; (2) Power-on reset chip 10. During power-on reset, debugger 20 is connected to instruction receiving unit 103 via P50 and P51. Debugger 20 sends instruction 0xa5 until it receives acknowledgment signal 0x55. After instruction receiving unit 103 receives 0xa5, control interface multiplexing unit 104 selects the interface of JTAG debug module 105. After power-on reset, because the priority of instruction receiving unit 103 in controlling interface multiplexing unit 104 is greater than the priority of controller 101, pins P50, P51, P52, and P53 are still occupied by the interface of JTAG debug module 105. (3) After the reset is released, the debugger 20 connects to the interface of the JTAG debug module 105 through pins P50, P51, P52 and P53 to download the new program to the chip 10; (4) After the new program is downloaded, the debugger 20 sends a debugging command to the JTAG debug module 105 to perform the debugging work.

[0066] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0067] In the embodiments of this application, "multiple" refers to two or more.

[0068] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0069] In this application's embodiments, "connection" refers to various connection methods, such as direct or indirect connection, to achieve communication between devices. This application's embodiments do not impose any limitations on this. The arrows on the signal lines in the various figures indicate the direction of signal flow.

[0070] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip for interface multiplexing, characterized in that, The chip includes a controller, a reset signal generation unit, an instruction receiving unit, an interface multiplexing unit, a debugging module, a functional module, and a general interface. The general interface is used to connect to a debugger, and the instruction receiving unit is connected to the general interface to receive instructions sent by the debugger. The reset signal generation unit is used to generate a valid first reset signal and a valid second reset signal, and the release time of the first reset signal is earlier than the release time of the second reset signal, wherein the release refers to the signal changing from valid to invalid; The instruction receiving unit is used to detect the first reset signal and the second reset signal, and to detect whether an instruction issued by the debugger is received after the first reset signal is released and before the second reset signal is released; The control terminal of the interface multiplexing unit is connected to the instruction receiving unit and the controller respectively. Under the control of the instruction receiving unit or the controller, the interface multiplexing unit selects the general interface with the debugging module or the functional module. When the instruction receiving unit receives the instruction, the instruction receiving unit controls the interface multiplexing unit to select the general interface and the debugging module. When the instruction receiving unit does not receive the instruction, the controller controls the interface multiplexing unit to select the general interface with the functional module; the debugger sends the instruction through the clock line and data line during the reset period.

2. The chip according to claim 1, characterized in that, When controlling the interface multiplexing unit, the instruction receiving unit has a higher priority than the controller.

3. The chip according to claim 1, characterized in that, The instruction receiving unit is also used to detect whether a valid first reset signal has been received, and the instruction receiving unit resets when a valid first reset signal is detected.

4. The chip according to claim 3, characterized in that, A valid second reset signal is used to reset at least one of the other circuit units in the chip besides the instruction receiving unit.

5. The chip according to claim 1, characterized in that, When the first reset signal and / or the second reset signal are low-level signals, it indicates that the first reset signal and / or the second reset signal are valid.

6. The chip according to any one of claims 1 to 5, characterized in that, The reset signal generation unit is used to generate a valid first reset signal and a second reset signal after the chip is powered on.

7. The chip according to any one of claims 1 to 5, characterized in that, After the chip is powered on, the interface multiplexing unit selects the general interface and the debugging module.

8. The chip according to claim 1, characterized in that, The instruction receiving unit is also configured to return a response signal to the debugger after detecting that the instruction has been received.

9. The chip according to claim 1, characterized in that, The debugging module interface includes a JTAG interface and / or a C2 interface.

10. A chip debugging system, characterized in that, The debugging system includes an interface multiplexing chip as described in any one of claims 1 to 9, and a debugger.

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