Memory training method and system

Abstract

The present application discloses a memory training method. The method provided by the present application includes: obtaining training data, writing the training data to an external memory particle according to an address signal; reading the training data from the external memory particle; obtaining a verification result according to the written training data and the read training data; if the verification result is a training failure, looping the aforementioned steps; if the verification result is a training success, writing the training result data to a preset flash memory. The present application also provides a memory training system, comprising at least one training controller and a physical layer controller connected to the training controller; the training controller is used to send a control instruction to the physical layer controller and obtain a training result from the physical layer controller; the physical layer controller transmits the address signal and the training data with the external memory particle, and obtains a verification result according to the written training data and the read training data.

Description

Technical Field

[0001] The present application relates to the field of field programmable logic gate arrays, and in particular to a memory training method and system. Background Art

[0002] With the rapid development of technologies such as cloud computing, 5G, Internet of Things, and artificial intelligence, the demand for memory has increased greatly. The physical layer of memory, as a key module of memory technology, also needs to meet new requirements of high speed and high bandwidth. At the same time, higher training requirements are also generated for the training of the physical layer of memory.

[0003] However, in the existing memory physical layer training technology, the memory physical layer training control part is an integral part of the memory physical layer itself, resulting in that in the actual memory physical layer training process, not only too many logic resources or chip area are occupied, but also the training scheme is not flexible enough and inconvenient to update. Summary of the invention

[0004] The embodiments of the present application provide a memory training method and system to solve the problem that the existing memory training occupies a lot of logic resources or chip area.

[0005] In a first aspect of the present application, a memory training method is provided, comprising:

[0006] Acquire training data, and write the training data into the external memory particle according to the address signal, wherein the training data is used for transmission between the physical layer controller and the external memory particle;

[0007] Reading the training data from the external memory particle;

[0008] Obtaining a verification result according to the written training data and the read training data, wherein the verification result is obtained by verifying whether the left and right boundaries of the data signal corresponding to the training data are on the rising edge;

[0009] If the verification result is that the training fails, the aforementioned steps are looped; if the verification result is that the training succeeds, the training result data is written to the preset flash memory.

[0010] A second aspect of the present application provides a memory training system, comprising:

[0011] at least one training controller, a physical layer controller connected to the training controller;

[0012] The training controller is used to send a control instruction to the physical layer controller, control the operation of the physical layer controller, generate first delay data for controlling address signal transmission and second delay data for training data transmission, and obtain training results from the physical layer controller;

[0013] The physical layer controller is connected to an external memory particle, transmits the address signal and the training data to the external memory particle according to the first delay data and the second delay data, and obtains a verification result according to the written training data and the read training data.

[0014] According to a third aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned memory training method are implemented.

[0015] The above-mentioned memory training method, device, computer equipment and storage medium send control instructions to the physical layer controller through the training controller, control the operation of the physical layer controller, generate the first delay data for controlling the transmission of the address signal and the second delay data for the transmission of the training data, and obtain the training result from the physical layer controller, and then connect the external memory particles through the physical layer controller, transmit the address signal and the training data with the external memory particles according to the first delay data and the second delay data, and obtain the verification result according to the written training data and the read training data. Not only is the training control part separated from the memory chip, reducing the occupation of the memory chip logic resources or chip area, but also the memory training scheme can be flexibly changed or updated through the training controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 is a flow chart of a memory training method in one embodiment of the present application;

[0018] Figure 2 is a structural schematic diagram of a memory training system in one embodiment of the present application;

[0019] Figure 3 is another structural schematic diagram of a memory training system in one embodiment of the present application;

[0020] Figure 4 is a schematic diagram of a structure in which a memory training system in one embodiment of the present application includes a flash memory and a sensor;

[0021] Figure 5It is a structural schematic diagram of a memory training system including at least two training controllers in one embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] In order to facilitate the understanding of this application, the titles of the technical terms involved in this application are as follows:

[0024] 1.FPGA (Field Programmable Gate Array), field programmable logic gate array, is a semi-custom circuit in special application integrated circuits, generally consisting of three parts: logic blocks, programmable interconnect channels and I / O blocks.

[0025] 2.DDR (Double Data Rate SDRAM), double data rate synchronous dynamic random access memory, is a type of memory.

[0026] In one embodiment, if Figure 1 As shown, a memory training method is provided, comprising the following steps S101 to S104:

[0027] S101. Acquire training data, and write the training data into an external memory cell according to an address signal, wherein the training data is used for transmission between a physical layer controller and the external memory cell.

[0028] Furthermore, the acquisition of training data, before writing the training data to the external memory particles according to the address signal, also includes: acquiring first delay data and second delay data, wherein the first delay data is used to control the transmission delay of the address signal, and the second delay data is used to control the transmission delay of the training data. The first delay data and the second delay data are pre-configured according to the result of successful physical layer training of the historical memory. Configuring data according to the result of successful training not only increases the probability that the verification result is a successful training, but also further improves the execution efficiency of the memory training method.

[0029] S102: Read the training data from the external memory cell.

[0030] Furthermore, the training data is generated by the physical layer controller, and then the physical layer controller writes the training data into the external memory particle according to the second delay data, and then reads the training data from the external memory particle according to the second delay data.

[0031] S103, obtaining a verification result according to the written training data and the read training data, wherein the verification result is obtained by verifying whether the left and right boundaries of the data signal corresponding to the training data are on a rising edge.

[0032] Wherein, the training data is transmitted between the physical layer controller and the external memory particles in the form of corresponding data signals. Whether it is the data signal when the physical layer controller sends the training data, or the data signal when the physical layer controller reads the training data, it should follow the standard of the Solid State Technology Association (JEDEC, Joint Electron Device Engineering Council), that is, the left and right boundaries of the data signal corresponding to the training data are on the rising edge, offsetting the passive delay caused by the packaging process and PCB routing differences, external factors such as temperature and voltage to the data signal corresponding to the training data during the transmission process. That is, the second delay data is used to offset the passive delay, maintaining the integrity and correctness of the data signal sampled during the transmission process. Wherein, the effect of the first delay data on the address signal is similar to this, so it will not be repeated here.

[0033] S104, if the verification result is that the training fails, the above steps are repeated; if the verification result is that the training succeeds, the training result data is written to the preset flash memory.

[0034] Furthermore, the obtaining of the first delay data and the second delay data includes: obtaining the first delay data and the second delay data according to the training result, wherein the first delay data and the second delay data are derived from the training result data. That is, the step of obtaining the first delay data and the second delay data from the training result data that has been successfully trained for executing a new round of the memory training method. Directly obtaining the first delay data and the second delay data from the training result data that has been successfully trained not only omits the step of configuring the first delay data and the second delay data, thereby improving the execution efficiency of the memory training method, but also the first delay data and the second delay data obtained according to the training result data that has been successfully trained can greatly reduce the probability and number of occurrences of the verification result being a training failure during the training process, thereby further improving the execution efficiency of the memory training method.

[0035] Furthermore, if the verification result is that the training is successful, after writing the training result data to the preset flash memory, it also includes: first, obtaining temperature data and voltage data, wherein the temperature data is the ambient temperature obtained from the temperature sensor, and the voltage data is the system voltage. Because it is well known that changes in temperature and voltage will also affect the transmission delay of the data signal corresponding to the training data during the transmission process. Then, after obtaining the temperature data and the voltage data, the first change amount of the temperature data and the second change amount of the voltage data are obtained. Then, the judgment result is obtained using the preset judgment rule, the first change amount and the second change amount. If the judgment result is that adjustment is required, the first delay data and / or the second delay data are adjusted according to the preset adjustment rule.

[0036] Furthermore, if the verification result is that the training is successful, after writing the training result data to the preset flash memory, it also includes: first, obtaining the training result data stored in different flash memories, wherein the different flash memories contain the training result data corresponding to different external memory particles. Then, obtaining comparative analysis result data according to the training result data, wherein the comparative analysis result data is obtained by comparative analysis of the training result data stored in the different flash memories. Among them, by comparative analysis of the result data, occasional errors generated during the training process can be found. For example, by comparative analysis of the result data, it is found that the second delay data in the training result data of a certain training process is obviously too large or too small than the second delay data corresponding to other training processes. Then, the training process corresponding to the occasional error is retrained or the occasional error is directly modified, for example, the second delay data corresponding to the occasional error is modified to be within a range close to other second delay data.

[0037] Furthermore, after obtaining the first change amount of the temperature data and the second change amount of the voltage data, the method further includes: judging whether it is necessary to perform a memory resetting training step or adjusting the training result data according to a preset algorithm based on the first change amount and / or the second change amount. The adjustment result of adjusting the training result data according to the preset algorithm is recorded, and historical experience data is generated based on the adjustment result. Furthermore, judging whether it is necessary to adjust the training result according to the historical experience data based on the first change amount and / or the second change amount.

[0038] The memory training method provided in this embodiment obtains training data, writes the training data to an external memory particle according to an address signal, then reads the training data from the external memory particle, obtains verification results according to the written training data and the read training data, and finally writes the training result data of successful training to a preset flash memory. Not only is the training control part separated from the memory chip, reducing the occupation of the memory chip logic resources or chip area, but also the memory training scheme can be flexibly changed or updated.

[0039] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0040] In one embodiment, a memory training system 100 is provided. Figure 2 As shown, the memory training system 100 includes at least one training controller 10 and a physical layer controller 20 connected to the training controller. The components are described in detail as follows:

[0041] The training controller 10 is used to send a control instruction to the physical layer controller 20, control the operation of the physical layer controller 20, generate first delay data for controlling address signal transmission and second delay data for training data transmission, and obtain training results from the physical layer controller 20;

[0042] The physical layer controller 20 is connected to the external memory particle 50, transmits the address signal and the training data with the external memory particle 50 according to the first delay data and the second delay data, and obtains the verification result according to the written training data and the read training data.

[0043] Furthermore, if Figure 3 As shown, the physical layer controller 20 includes a register module 201 , a command queue module 202 , a training data module 203 , a first delay module 204 and a second delay module 205 .

[0044] The register module 201 is used to receive the control instruction, the first delay data and the second delay data sent by the training controller 10, and output a first control signal to the command queue module 202 and a second control signal to the training data module 203 according to the control instruction;

[0045] A first delay module 204, configured to obtain the first delay data from the register module 201, and use the first delay data to control the transmission delay of the address signal;

[0046] A second delay module 205, configured to obtain the second delay data from the register module 201, and use the second delay data to control the transmission delay of the training data;

[0047] A command queue module 202, configured to send an address signal to the external memory chip 50 through the first delay module 204 according to the first control signal, and send a data read / write signal to the training data module 203;

[0048] The training data module 203 is used to generate the training data according to the second control signal, write the training data to the external memory particle 50 or read the training data from the external memory particle 50 through the second delay module 205 according to the data read and write signal, and obtain a verification result based on the written training data and the read training data.

[0049] Furthermore, if Figure 4 As shown, the training controller 10 is also connected to the flash memory 30 and the sensor 40 .

[0050] A flash memory 30, used for storing the training results;

[0051] Sensor 40 is used to obtain the training environment temperature and the training system voltage.

[0052] Furthermore, if Figure 5 As shown, the memory training system 100 includes at least two training controllers 10, and a single training controller 10 is connected to at least two physical layer controllers 20; the training controller 10 compares and analyzes the training results of the at least two physical layer controllers 20 to obtain a comparison analysis result; and the at least two training controllers 10 share the comparison analysis result.

[0053] The memory training system 100 provided in this embodiment sends a control instruction to the physical layer controller through a training controller, controls the operation of the physical layer controller, generates a first delay data for controlling the transmission of address signals and a second delay data for the transmission of training data, and obtains training results from the physical layer controller, and then connects to external memory particles through the physical layer controller, transmits the address signal and the training data with the external memory particles according to the first delay data and the second delay data, and obtains verification results according to the written training data and the read training data. Not only is the training control part separated from the memory chip, reducing the occupation of the memory chip logic resources or chip area, but also the memory training scheme can be flexibly changed or updated through the training controller. And through the training controller, hardware resources and training results can be shared, further improving the training efficiency of the memory.

[0054] The meaning of "first" and "second" in the above modules / units is only to distinguish different modules / units, and is not used to define which module / unit has a higher priority or other limiting meanings. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules in this application is only a logical division, and there may be other division methods when implemented in actual applications.

[0055] For the specific definition of the memory training system, please refer to the definition of the memory training method above, which will not be repeated here. Each module in the above-mentioned memory training system can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0056] In one embodiment, a computer-readable storage medium is provided on which a computer program is stored. When the computer program is executed by a processor, the steps of the memory training method in the above embodiment are implemented, such as Figure 1 Alternatively, when the computer program is executed by a processor, the functions of each module / unit of the memory training system in the above embodiment are realized, for example, Figure 3 The functions of the modules 10 to 50 are shown in Figure 1. To avoid repetition, they will not be described here.

[0057] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0058] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0059] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A memory training method, characterized in that: include: Acquire training data, and write the training data into an external memory particle according to an address signal, wherein the training data is used for transmission between a physical layer controller and the external memory particle; Reading the training data from the external memory particle; Acquire a verification result according to the written training data and the read training data, wherein the verification result is obtained by verifying whether the left and right boundaries of the data signal corresponding to the training data are obtained at a rising edge, and the training data is transmitted between the physical layer controller and the external memory particle in the form of a corresponding data signal; If the verification result is that the training fails, the aforementioned steps are repeated; if the verification result is that the training succeeds, the training result data is written to the preset flash memory; Wherein, the acquiring of training data, before writing the training data to the external memory particle according to the address signal, further comprises: acquiring first delay data and second delay data, wherein the first delay data is used to control the transmission delay of the address signal, and the second delay data is used to control the transmission delay of the training data; Wherein, if the verification result is that the training is successful, after writing the training result data to the preset flash memory, it also includes: obtaining temperature data and voltage data, wherein the temperature data is the ambient temperature obtained from the temperature sensor, and the voltage data is the system voltage; obtaining a first change amount of the temperature data and a second change amount of the voltage data; obtaining a judgment result according to a preset judgment rule, the first change amount and the second change amount; if the judgment result needs to be adjusted, adjusting the first delay data and / or the second delay data according to the preset adjustment rule; Among them, after obtaining the first change amount of the temperature data and the second change amount of the voltage data, it also includes: judging whether it is necessary to reset the memory training step according to the first change amount and / or the second change amount, or adjusting the training result data according to a preset algorithm.

2. The memory training method according to claim 1, characterized in that: The obtaining of the first delay data and the second delay data comprises: The first delay data and the second delay data are acquired according to the training result, wherein the first delay data and the second delay data are derived from the training result data.

3. The memory training method according to claim 1, characterized in that: If the verification result is that the training is successful, after writing the training result data to the preset flash memory, the method further includes: Acquire the training result data stored in different flash memories, wherein the different flash memories contain the training result data corresponding to different external memory particles; The comparative analysis result data is acquired according to the training result data, wherein the comparative analysis result data is acquired by comparatively analyzing the training result data stored in the different flash memories.

4. A memory training system, characterized in that: comprising at least one training controller and a physical layer controller connected to the training controller; The training controller is used to send a control instruction to the physical layer controller, control the operation of the physical layer controller, generate first delay data for controlling address signal transmission and second delay data for training data transmission, and obtain training results from the physical layer controller; The physical layer controller is connected to an external memory particle, transmits the address signal and the training data with the external memory particle according to the first delay data and the second delay data, and obtains a verification result according to the written training data and the read training data; The training controller is also connected to a flash memory and a sensor; the flash memory is used to store the training results; and the sensor is used to obtain the training environment temperature and the training system voltage.

5. The memory training system according to claim 4, characterized in that: The physical layer controller includes a register module, a command queue module, a training data module, a first delay module and a second delay module, wherein: A register module, used for receiving the control instruction, the first delay data and the second delay data sent by the training controller, and outputting a first control signal to the command queue module and a second control signal to the training data module according to the control instruction; A first delay module, used for obtaining the first delay data from the register module, and using the first delay data to control the transmission delay of the address signal; A second delay module, used for obtaining the second delay data from the register module, and using the second delay data to control the transmission delay of the training data; A command queue module, configured to send an address signal to the external memory particle and send a data read / write signal to the training data module through the first delay module according to the first control signal; A training data module is used to generate the training data according to the second control signal, write the training data to the external memory particle or read the training data from the external memory particle through the second delay module according to the data read and write signal, and obtain a verification result according to the written training data and the read training data.

6. The memory training system according to claim 4, characterized in that: comprising at least two of the training controllers, wherein a single training controller is connected to at least two of the physical layer controllers; The training controller compares and analyzes the training results of the at least two physical layer controllers to obtain a comparison and analysis result; The at least two training controllers share the comparative analysis result.

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