Accelerator chip-based image convolution method, chip, device and medium

Abstract

The disclosure provides an accelerator chip-based image convolution method, chip, device and medium. The method comprises: allocating a first weight and image data for storage to each computing unit at one time; alternately performing a preset convolution calculation operation and a data flow conversion operation until a first number of convolution calculation operations are completed; the convolution calculation operation comprises: performing convolution calculation on the first weight and the image data currently stored in the computing unit to obtain the convolution result of the image data currently stored in the computing unit; the data flow conversion operation comprises: converting the first weight or the image data currently stored in each computing unit to an adjacent computing unit for storage according to a preset flow conversion direction; after the first number of convolution calculation operations are completed, for each image data, a target convolution result of the image data is generated based on the first number of convolution results of the image data. The above image convolution can improve the calculation efficiency and data throughput of the accelerator chip at the same time.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chips, and in particular to an image convolution method based on an accelerator chip, a chip, a device and a medium. BACKGROUND

[0002] An accelerator chip is a chip that can be used to perform machine learning (ML) operations, for example, the accelerator chip can be used to perform convolution calculation on images. In order to improve the calculation speed and data throughput of the chip, some data used in the calculation process is usually multiplexed, but the existing data multiplexing method has limited effect on improving the calculation speed and data throughput of the chip. SUMMARY

[0003] The present disclosure provides an image convolution method based on an accelerator chip, a chip, a device and a medium.

[0004] According to a first aspect of the present disclosure, an image convolution method based on an accelerator chip is provided, the pulse array of the accelerator chip has a first number of cyclically connected calculation units, and the method comprises:

[0005] allocating one first weight and one image data to each calculation unit for storage at one time;

[0006] alternately performing a preset convolution calculation operation and a data flow operation until a first number of convolution calculation operations are completed;

[0007] the convolution calculation operation comprises: performing convolution calculation on the first weight and the image data currently stored in the calculation unit to obtain the convolution result of the image data currently stored in the calculation unit;

[0008] the data flow operation comprises: transferring the first weight or the image data currently stored in each calculation unit to an adjacent calculation unit for storage according to a preset flow direction;

[0009] after the first number of convolution calculation operations are completed, for each image data, a target convolution result of the image data is generated based on the first number of convolution results of the image data.

[0010] In the embodiments of the present disclosure, allocating one first weight and one image data to each calculation unit for storage at one time comprises:

[0011] reading a first number of first weights and a first number of image data from a preset storage device at one time;

[0012] allocating each first weight to a corresponding calculation unit for storage, and allocating each image data to a corresponding calculation unit for storage.

[0013] In the embodiments of the present disclosure, the first quantity of first weights are obtained by splitting the original weight in a depth direction into the first quantity of shares, wherein the original weight is a three-dimensional array and the first weight is a two-dimensional array.

[0014] In the embodiments of the present disclosure, the first weight or the image data currently stored by each computing unit is transferred to an adjacent computing unit for storage, including:

[0015] Each first weight is retained in the computing unit where it is first allocated;

[0016] The image data currently stored by each computing unit is transferred to an adjacent computing unit for storage in a preset transfer direction.

[0017] In the embodiments of the present disclosure, for each image data, a target convolution result of the image data is generated based on a first quantity of convolution results of the image data, including:

[0018] For each image data, the convolution results of the image data are extracted from the respective computing units to obtain the first quantity of convolution results of the image data;

[0019] The first quantity of convolution results of the image data are summed to obtain the target convolution result of the image data.

[0020] In the embodiments of the present disclosure, the first weight or the image data currently stored by each computing unit is transferred to an adjacent computing unit for storage, including:

[0021] Each image data is retained in the computing unit where it is first allocated;

[0022] The first weight currently stored by each computing unit is transferred to an adjacent computing unit for storage in a preset transfer direction.

[0023] In the embodiments of the present disclosure, for each image data, a target convolution result of the image data is generated based on a first quantity of convolution results of the image data, including:

[0024] For each image data, the first quantity of convolution results of the image data are extracted from the computing unit where the image data is first allocated;

[0025] The first quantity of convolution results of the image data are summed to obtain the target convolution result of the image data;

[0026] All the target convolution results of the image data are output at one time.

[0027] According to a second aspect of the present disclosure, an accelerator chip is provided, a pulse array of the accelerator chip has a first number of cyclically connected computing units, and the accelerator chip is capable of performing the method provided in the first aspect of the present disclosure.

[0028] According to a third aspect of the present disclosure, an electronic device is provided, comprising:

[0029] the accelerator chip provided in the second aspect of the present disclosure; and

[0030] a memory in communication connection with the accelerator chip; wherein

[0031] the memory stores instructions executable by the accelerator chip, and the instructions are executed by the accelerator chip to enable the at least one processor to perform the method provided in the first aspect of the present disclosure.

[0032] According to a fourth aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to perform the method provided in the first aspect of the present disclosure.

[0033] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

[0034] The technical solutions provided by the present disclosure have the following beneficial effects:

[0035] The image convolution method based on the accelerator chip provided by the embodiments of the present disclosure can allocate a first weight and an image data to each computing unit of the accelerator chip through only one data output step, so that multiple first weights and multiple image data can be quickly deployed in the chip, and the first weight or the image data is circulated in the multiple cyclically connected computing units, so that one image data can be convolved with each first weight once, thereby obtaining multiple convolution results of each image data, and then the convolution results of the multiple image data are output through one data output step. The above image convolution process can simultaneously reuse multiple image data and multiple weights, all computing units can perform convolution calculation synchronously, the calculation parallelism is high, and all computing units can synchronously circulate data to adjacent computing units, thereby saving the progressive delay and waiting process of data transmission. Based on the method, the convolution results of multiple image data can be obtained simultaneously, the calculation efficiency and data throughput rate of the accelerator chip can be improved simultaneously, and the process of obtaining the convolution results of multiple image data only needs one data input step and one data output step, which can significantly reduce the data access times of the chip, thereby reducing the power consumption of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings are used to better understand the present scheme, and do not constitute a limitation on the present disclosure. Among them:

[0037] Figure 1 An exemplary structural schematic diagram of an accelerator chip is shown, which is provided by an embodiment of the present disclosure;

[0038] Figure 2 A flow schematic diagram of an image convolution method based on an accelerator chip is shown, which is provided by an embodiment of the present disclosure;

[0039] Figure 3 A schematic diagram of storing first weights and image data in a computing unit of an accelerator chip is shown, which is provided by an embodiment of the present disclosure;

[0040] Figure 4 A flow schematic diagram of performing a data flow operation is shown, which is provided by an embodiment of the present disclosure;

[0041] Figure 5 Another flow schematic diagram of performing a data flow operation is shown, which is provided by an embodiment of the present disclosure;

[0042] Figure 6 A schematic block diagram of an electronic device for implementing the method provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to help understanding, and should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.

[0044] An accelerator chip is a chip that can be used to perform machine learning (ML) operations, for example, the accelerator chip can be used to perform convolution calculation on images. In order to improve the computing speed and data throughput of the chip, some data used in the computing process is usually multiplexed. Specifically, the commonly used data multiplexing methods in the prior art include input feature data multiplexing (Input feature map reuse), filter multiplexing (Filter reuse) and convolution multiplexing (Convolutional reuse).

[0045] Input feature data multiplexing refers to repeatedly using the same input feature data for calculation, that is, inputting an input feature data into a chip, sequentially calculating the convolution results of the input feature data corresponding to multiple convolution weights, and after obtaining the multiple convolution results of the input feature data, inputting the next input feature data to perform the convolution calculation again. For the input feature data multiplexing mode, only the convolution result of one input feature data can be obtained in a complete data input and output process, and the data throughput rate is low. Filter multiplexing refers to inputting a batch of input feature data (i.e., multiple input feature data) into a chip, calculating the convolution results of each input feature data corresponding to the same convolution weight, and after obtaining the convolution result of each input feature data, inputting the next batch of input feature data to perform the convolution calculation again. In the filter multiplexing scenario, the convolution weight used is usually a higher-dimensional array (such as a three-dimensional or higher array), which will result in a higher complexity of convolution calculation, which will seriously affect the calculation speed of the chip. Convolution multiplexing is similar to input feature data multiplexing, which refers to inputting an input feature data into a chip, using the same convolution weight to perform convolution calculation with different position sub-data of the input feature data, and after obtaining the convolution results of the multiple sub-data of the input feature data, inputting the next input feature data to perform the convolution calculation again. For the convolution multiplexing mode, only the convolution result of one input feature data can be obtained in a complete data input and output process, and the data throughput rate is low. It can be seen that the existing data multiplexing can usually only multiplex one-dimensional data, such as only multiplexing input feature data or only multiplexing convolution weight. The existing data multiplexing mode has limited effect on improving the calculation speed and data throughput rate of the chip, and cannot simultaneously improve the calculation speed and data throughput rate.

[0046] The image convolution method based on the accelerator chip, the chip, the device and the medium provided by the embodiments of the present disclosure aim to solve at least one of the above technical problems in the prior art.

[0047] The accelerator chip provided by the embodiments of the present disclosure is specifically a neural network accelerator chip, which can be used for machine learning (ML) operation. The main component of the accelerator chip for various machine learning operations is an NxM pulse array. It can be understood that N is the number of rows of the pulse array, and M is the number of columns of the pulse array. In the embodiments of the present disclosure, the pulse array has a first number of calculation units, which are usually referred to as Processing Elements (PEs) for short. The first number of calculation units in the embodiments of the present disclosure are cyclically connected, so that data can enter each calculation unit in turn according to a preset flow direction. It should be noted that generally, the first number is usually an integer not less than 4. Figure 1An exemplary structure diagram of an accelerator chip is shown in the embodiment of the present disclosure, and Figure 1 The pulse array of the accelerator chip has 16 computing units, which are PE1-PE16 respectively, wherein the PE1-PE16 are sequentially connected, and the PE16 is also connected with the PE1, thereby forming a loop structure.

[0048] Figure 2 A flow diagram of an image convolution method based on the accelerator chip is shown in the embodiment of the present disclosure, and Figure 2 The method can mainly include the following steps:

[0049] S210: allocating a first weight and image data for each computing unit for storage at one time.

[0050] S220: alternately performing a preset convolution calculation operation and a data flow operation until the convolution calculation operation is completed for the first number of times.

[0051] In the embodiment of the present disclosure, after the convolution calculation is performed by the computing unit, the convolution result of the corresponding image data can be obtained. Here, the convolution calculation operation includes: performing convolution calculation on the first weight and the image data currently stored by the computing unit to obtain the convolution result of the image data currently stored by the computing unit.

[0052] In the embodiment of the present disclosure, the data flow operation includes: transferring the first weight or the image data currently stored by each computing unit to an adjacent computing unit for storage according to a preset flow direction. It should be noted that in step S220, the first weight or the image data is transferred alternatively, that is, all the computing units can only transfer the first weight in step S220, or all the computing units can only transfer the image data in step S220.

[0053] S230: after the convolution calculation operation is completed for the first number of times, for each image data, generating a target convolution result of the image data based on the first number of convolution results of the image data.

[0054] It can be understood that after the convolution calculation operation is completed for the first number of times, each image data is convolved with the first number of first weights, and thus each image data corresponds to the first number of convolution results. The convolution result of the image data is saved in the computing unit, and in S230, the first number of convolution results of each image data can be extracted from the computing unit, and the target convolution result of the image data is generated based on the first number of convolution results of the image data.

[0055] S240: outputting all the target convolution results of the image data at one time.

[0056] The image convolution method based on the accelerator chip provided by the embodiments of the present disclosure can allocate one first weight and one image data to each computing unit of the accelerator chip through one data output step, so that multiple first weights and multiple image data can be quickly deployed in the chip. The first weight or image data is circulated in multiple loop-connected computing units, so that one image data can be convoluted with each first weight once, thereby obtaining multiple convolution results of each image data. Then, the convolution results of the multiple image data are output through one data output step. The above image convolution process can simultaneously reuse multiple image data and multiple weights, all the computing units can synchronously perform convolution calculation, the calculation parallelism is high, and all the computing units can synchronously transfer data to the adjacent computing units, thereby saving the progressive delay and waiting process of data transmission. Based on the method, the convolution results of multiple image data can be obtained simultaneously, the calculation efficiency and data throughput rate of the accelerator chip can be improved simultaneously, and the process of obtaining the convolution results of multiple image data only needs one data input step and one data output step, which can significantly reduce the data access times of the chip, thereby reducing the power consumption of the chip.

[0057] In the embodiments of the present disclosure, the first weight and the image data can be stored in the storage device. When one first weight and one image data are allocated to each computing unit for storage at one time, the first quantity of first weights and the first quantity of image data can be read from the storage device at one time, each first weight is allocated to a corresponding computing unit for storage, and each image data is allocated to a corresponding computing unit for storage. The embodiments of the present disclosure can read multiple first weight image data at one time, and the convolution calculation of multiple image data can be completed by circulating the data in the chip without reading data from the outside of the chip multiple times, which can significantly reduce the access times of the storage device outside the chip and help to reduce the power consumption of the chip.

[0058] Specifically, as Figure 2As shown, the storage device can include a data storage, a first cache and a second cache. The data storage can store a plurality of image data and weights used for convolution calculation. Before step S210 is performed, a first number of image data required for convolution this time can be saved in the first cache, and a first number of first weights corresponding to the first number of image data can be saved in the second cache. When one first weight and one image data are allocated to each computing unit for storage at a time, the first number of image data can be read from the first cache at a time, and the first number of first weights can be read from the second cache at a time. Optionally, the storage device can further include a third cache, which can be used to store the final target convolution result of each image data. In step 240, the accelerator chip can output the target convolution result of all the image data to the third cache at a time.

[0059] Figure 3 A schematic diagram of storing first weights and image data in the computing units of the accelerator chip is shown, as shown in FIG. 3. Figure 3 As shown, the pulse array of the accelerator chip has 16 computing units, which are PE1 to PE16 respectively, and 16 image data LA1 to LA16 and 16 first weights W1 to W16 are obtained. When the image data and the first weights are allocated, the computing unit PE1 can be allocated the image data LA1 and the first weight W1 for storage, the computing unit PE2 can be allocated the image data LA2 and the first weight W2 for storage, and so on, and the computing unit PE16 can be allocated the image data LA16 and the first weight W16 for storage.

[0060] In the embodiment of the present disclosure, the first number of first weights is obtained by splitting the original weights into the first number of shares in the depth direction, wherein the original weights are a three-dimensional array, and the first weights are a two-dimensional array. It should be noted that in the field, when the convolution result of the image data is calculated, the convolution calculation is usually based on the original weights and the image data. Since the original weights are a three-dimensional array, the complexity of the convolution calculation based on the direct original weights is high. The embodiment of the present disclosure can split the original weights of the three-dimensional array into the first number of shares of the first weights of the two-dimensional array in the depth direction, so as to perform the convolution calculation based on the first weights of the two-dimensional array, greatly simplify the calculation process, and help to improve the calculation speed of the chip and reduce the power consumption of the chip.

[0061] As described above, in step S220, the data flow needs to be transferred in the first weight or the image data. In the case that all the computing units can only transfer the first weight in step S220, the embodiment of the present disclosure can keep each first weight in the computing unit where the first weight is first allocated, and transfer the image data currently stored in each computing unit to the adjacent computing unit for storage according to the preset flow direction, when the first weight or the image data currently stored in each computing unit is transferred to the adjacent computing unit for storage. It can be understood that the computing unit where the first weight is first allocated refers to the computing unit where the first weight is allocated in S210. In the process of alternately performing the preset convolution calculation operation and the data flow operation, the first weight in each computing unit is fixed and unchanged, and the image data in the computing unit is replaced once each time the data flow operation is performed. In this way, in the process of different convolution calculation operations, each computing unit performs convolution calculation based on the fixed first weight and different image data, and therefore, one computing unit can obtain the convolution result of each data image in the first number of data images by performing the first number of convolution calculation operations.

[0062] In the embodiment of the present disclosure, the flow direction of the data in the computing unit can be determined in advance, and it is specified that each computing unit only needs to transfer the image data to the adjacent computing unit, so that the data transmission across the computing units is not needed, the routing relationship is simple and constant, and the routing algorithm is greatly simplified; and only the image data needs to be transferred between the adjacent computing units, the transmission distance is short and the data type is single, so that the chip does not need to consume excessive power and the computing resources are saved.

[0063] Figure 4 A flowchart for performing a data flow operation is shown in the embodiment of the present disclosure, in which Figure 4In the accelerator chip, four computing units are included, which are computing unit PE1 to computing unit PE4. The computing unit PE1 stores the first weight W1, the computing unit PE2 stores the first weight W2, the computing unit PE3 stores the first weight W3, and the computing unit PE4 stores the first weight W4. P1 to P4 represent four convolution calculation operations in four stages. In stage P1, the computing unit PE1 stores the image data LA1, the computing unit PE2 stores the image data LA2, the computing unit PE3 stores the image data LA3, and the computing unit PE4 stores the image data LA4. Taking the computing unit PE as an example, in stage P1, the computing unit PE1 calculates the convolution result corresponding to the image data LA1 based on the image data LA1 and the first weight W1, and then transfers the image data LA1 to the computing unit PE2 and the image data LA4 to the computing unit PE1. In stage P2, the computing unit PE1 calculates the convolution result corresponding to the image data LA4 based on the image data LA4 and the first weight W1, and then transfers the image data LA4 to the computing unit PE2, and so on until each computing unit completes four convolution calculation operations.

[0064] In the embodiment of the present disclosure, in the case that all the computing units can only transfer the first weight in step S220, one computing unit can obtain the convolution result of each data image in the first number of data images by performing the first number of convolution calculation operations. Therefore, when the target convolution result of the image data is generated based on the first number of convolution results of the image data, the convolution results of the image data can be extracted from each computing unit respectively to obtain the first number of convolution results of the image data, and the first number of convolution results of the image data are summed to obtain the target convolution result of the image data.

[0065] As described above, in step S220, the data flow needs to be transferred in the first weight or the image data. In the case that all the computing units can only transfer the first weight in step S220, the embodiment of the present disclosure can keep each image data in the computing unit where the image data is first allocated, and transfer the first weight currently stored in each computing unit to the adjacent computing unit for storage according to the preset flow direction, when the first weight or the image data currently stored in each computing unit is transferred to the adjacent computing unit for storage. It can be understood that the computing unit where the image data is first allocated refers to the computing unit to which the image data is allocated in S210. In the process of alternately performing the preset convolution calculation operation and the data flow operation, the image data in each computing unit is fixed, and the first weight in the computing unit is replaced once each time the data flow operation is performed. In this way, in the process of different convolution calculation operations, each computing unit performs convolution calculation based on the fixed image data and different first weights, and therefore, one computing unit can obtain the first number of convolution results of the same data image by performing the first number of convolution calculation operations.

[0066] In the embodiment of the present disclosure, the flow direction of the data in the computing unit can be determined in advance, and it is specified that each computing unit only needs to transfer the first weight to the adjacent computing unit, without the need for cross-computing unit data transmission, the routing relationship is simple and constant, greatly simplifying the routing algorithm; and only the image data needs to be transferred between adjacent computing units, the transmission distance is short and the data type is single, which saves the power consumption of the chip and saves the computing resources. In addition, the data amount of the first weight is usually smaller than the data amount of the image data, and transferring the first weight can further save the power consumption of the chip.

[0067] Figure 5 Another flowchart for performing the data flow operation is shown in the embodiment of the present disclosure, in which Figure 5In the accelerator chip, the four computing units are computing unit PE1 to computing unit PE4, computing unit PE1 stores image data LA1, computing unit PE2 stores image data LA2, computing unit PE3 stores image data LA3, and computing unit PE4 stores image data LA4. P1 to P4 represent four convolution calculation operations performed in sequence. In stage P1, computing unit PE1 stores first weight W1, computing unit PE2 stores first weight W2, computing unit PE3 stores first weight W3, and computing unit PE4 stores first weight W4. Taking computing unit PE as an example, in stage P1, computing unit PE1 calculates the convolution result corresponding to image data LA1 based on image data LA1 and first weight W1, and then transfers first weight W1 to computing unit PE2 and first weight W4 to computing unit PE1; in stage P2, computing unit PE1 calculates the convolution result corresponding to image data LA1 based on image data LA1 and first weight W4, and then transfers first weight W4 to computing unit PE2, and the same is true for the subsequent stages until each computing unit completes four convolution calculation operations.

[0068] In the embodiment of the present disclosure, in the case where all computing units can only transfer image data in step S220, one computing unit can obtain first number of convolution results of the same data image by performing first number of convolution calculation operations, and therefore, when generating a target convolution result of image data based on first number of convolution results of the image data, first number of convolution results of the image data can be extracted from the computing unit to which the image data is first allocated, and first number of convolution results of the image data are summed to obtain the target convolution result of the image data.

[0069] Optionally, the computing unit can sum the latest obtained convolution result and the previously obtained convolution result to achieve the storage of multiple convolution results. Here, the latest obtained convolution result can be regarded as the loading of the initial membrane potential in the current convolution calculation. The summation process of the computing unit can be achieved by the following formula:

[0070]

[0071] In the above formula, y(i) is the summation result, wi represents the first weight used in the convolution calculation, S is the number of computing units of the pulse array of the accelerator chip (i.e., the first number described above), wi, C in wi represents the corresponding depth of wi in the original weight.

[0072] The embodiment of the present disclosure provides an accelerator chip, a pulse array of the accelerator chip has a first number of cyclically connected computing units, and the accelerator chip is capable of executing the above-mentioned image convolution method based on the accelerator chip. The accelerator chip executes the image convolution method, and details are not repeated here.

[0073] The embodiment of the present disclosure also provides an electronic device, which comprises the above-mentioned accelerator chip and a memory in communication connection with the accelerator chip. The memory stores instructions executable by the accelerator chip, and the instructions are executed by the accelerator chip to enable at least one processor to execute the above-mentioned image convolution method based on the accelerator chip. The accelerator chip executes the image convolution method, and details are not repeated here.

[0074] Figure 6 A schematic block diagram of an electronic device for implementing the method provided by the embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as servers, laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections, and their functions, are meant to be examples only, and are not intended to limit the implementations of the present disclosure described and / or claimed herein.

[0075] As shown in Figure 6 The electronic device 600 includes an accelerator chip 601, which can perform various appropriate actions and processes according to computer programs stored in a read-only memory (ROM) 602 or computer programs loaded from a storage unit 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 can also be stored. The accelerator chip 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0076] A plurality of components in the electronic device 600 are connected to the I / O interface 605, including an input unit 606, such as a keyboard, a mouse, etc., an output unit 607, such as various types of displays, a speaker, etc., a storage unit 608, such as a magnetic disk, an optical disk, etc., and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the electronic device 600 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunications networks.

[0077] The accelerator chip 601 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the accelerator chip 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The accelerator chip 601 performs various methods and processes described above, such as the accelerator chip-based image convolution method. For example, in some embodiments, the accelerator chip-based image convolution method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded onto the RAM 603 and executed by the accelerator chip 601, one or more steps of the accelerator chip-based image convolution method described above can be performed. Alternatively, in other embodiments, the accelerator chip 601 can be configured to perform the accelerator chip-based image convolution method by any other appropriate means, such as by means of firmware.

[0078] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0079] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0080] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0081] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0082] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0083] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0084] It should be understood that the various forms of flow shown above can be re-ordered, added to, or have steps deleted, using the steps. For example, the steps described in the present disclosure can be executed in parallel, in series, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, which are not limited herein.

[0085] The above detailed description does not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for image convolution based on an accelerator chip, a pulse array of the accelerator chip having a first number of cyclically connected computing units, the method comprising: allocating a first weight and an image data to each of the computing units for storage at one time; alternately performing a preset convolution calculation operation and a data flow operation until a first number of times of the convolution calculation operation is completed; the convolution calculation operation comprising: performing convolution calculation on the first weight and the image data currently stored in the computing unit to obtain a convolution result of the image data currently stored in the computing unit; the data flow operation comprising: flowing the first weight or the image data currently stored in each of the computing units to an adjacent one of the computing units for storage according to a preset flow direction; after the first number of times of the convolution calculation operation is completed, generating a target convolution result of each of the image data based on a first number of convolution results of the image data; outputting all of the target convolution results of the image data at one time; the first number of the first weights being obtained by splitting an original weight into the first number of parts in a depth direction, wherein the original weight is a three-dimensional array and the first weight is a two-dimensional array.

2. The method of claim 1, wherein, the allocating of the first weight and the image data to each of the computing units for storage at one time comprising: reading the first number of first weights and the first number of image data from a preset storage device at one time; allocating each of the first weights to a corresponding one of the computing units for storage and allocating each of the image data to a corresponding one of the computing units for storage.

3. The method of claim 1, wherein, the flowing of the first weight or the image data currently stored in each of the computing units to an adjacent one of the computing units for storage according to a preset flow direction comprising: keeping each of the first weights in the computing unit to which the first weight is allocated for the first time; flowing the image data currently stored in each of the computing units to an adjacent one of the computing units for storage according to a preset flow direction.

4. The method of claim 3, wherein, the generating of a target convolution result of each of the image data based on the first number of convolution results of the image data comprising: extracting the convolution results of the image data from each of the computing units to obtain the first number of convolution results of the image data for each of the image data; summing the first number of convolution results of the image data to obtain a target convolution result of the image data.

5. The method of claim 1, wherein, the flowing of the first weight or the image data currently stored in each of the computing units to an adjacent one of the computing units for storage according to a preset flow direction comprising: keeping each of the image data in the computing unit to which the image data is allocated for the first time; flowing the first weight currently stored in each of the computing units to an adjacent one of the computing units for storage according to a preset flow direction.

6. The method of claim 5, wherein, The generating, for each of the image data, a target convolution result of the image data based on the first number of convolution results of the image data comprises: The extracting, for each of the image data, the first number of convolution results of the image data from the computing unit to which the image data is first assigned comprises: The summing the first number of convolution results of the image data to obtain a target convolution result of the image data.

7. An accelerator chip, a pulse array of the accelerator chip having the first number of cyclically connected computing units, the accelerator chip being capable of performing the method of any one of claims 1-6.

8. An electronic device comprising: The accelerator chip of claim 7; and A memory in communication connection with the accelerator chip; wherein The memory stores instructions executable by the accelerator chip, the instructions being executed by the accelerator chip to enable the at least one processor to perform the method of any one of claims 1-6. The computer instructions are for causing a computer to perform the method of any one of claims 1-6.

9. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, ​

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