Data reading and writing method, resistive random access memory, and electronic device

Abstract

The present invention provides a data reading and writing method, a resistive random access memory, and an electronic device. The method includes: when a data reading instruction is received, sequentially reading data of n memory cells in a read target memory cell as first data, converting the first data into second data of m bits through the data converter and outputting the second data, where at most one of the bits of the first data is 1, and m is a positive integer less than or equal to; and / or when a data writing instruction is received, converting third data of m bits into fourth data of n bits through the data converter, and writing the bits of the fourth data into n memory cells of a write target memory cell, where at most one of the bits of the fourth data is 1. The method can be applied to a resistive random access memory having a 1TnR structure.

Description

Technical Field

[0001] The present invention relates to a read - write method, and particularly to a data read - write method, a resistive random access memory, and an electronic device. Background Art

[0002] Resistive Random Access Memory (ReRAM) has received increasing attention due to its advantages such as low voltage, high speed, low power consumption, simple structure, compatibility with CMOS (Complementary Metal Oxide Semiconductor) traditional process, low cost, and high density. It is considered a new type of memory that may replace flash memory and become the mainstream storage product in the next generation. Traditional resistive random access memories are mostly of the 1T1R structure, and its schematic diagram is as Figure 1A shown. However, due to the relatively large size of the introduced MOSFET (Metal - Oxide Semiconductor Field - Effect Transistor) in this 1T1R - structured resistive random access memory, it is difficult to continuously improve the storage density as the semiconductor technology node continues to advance.

[0003] In order to improve the storage density of resistive random access memories, a large amount of research has been carried out on resistive random access memories in the industrial and academic fields. Among them, resistive random access memories with a 1TnR structure have received extensive attention in the industry. Figure 1B The schematic diagram of a resistive random access memory with a 1TnR structure is shown as follows. As shown in the figure, such a resistive random access memory controls multiple resistive memories through 1 transistor to achieve the purpose of improving the storage density. However, the traditional read - write method applicable to the 1T1R - structured resistive random access memory is not applicable to the resistive random access memory with a 1TnR structure. Therefore, how to provide a data read - write method applicable to the resistive random access memory with a 1TnR structure has become one of the problems that need to be urgently solved by those skilled in the relevant fields. Summary of the Invention

[0004] In view of the above - mentioned disadvantages of the prior art, the purpose of the present invention is to provide a data read - write method, a resistive random access memory, and an electronic device, which are used to solve the problem that the existing data read - write method is difficult to be applicable to the resistive random access memory with a 1TnR structure.

[0005] To achieve the above and other related objectives, a first aspect of the present invention provides a data reading and writing method for a resistive random access memory having a 1TnR structure. The resistive random access memory includes a data converter, a plurality of memory cells, and n sense amplifiers. Each of the memory cells includes n memory elements and a transistor. Each of the memory elements in each memory cell is connected to the data converter through a corresponding sense amplifier. The method includes: when a data reading instruction is received, sequentially reading the data of the n memory elements in the read target memory cell as a first data, and converting the first data into an m-bit second data through the data converter and outputting it, where at most one of the bits of the first data is 1, and m is a positive integer less than or equal to ; and / or when a data writing instruction is received, converting an m-bit third data into an n-bit fourth data through the data converter, and writing the bits of the fourth data into the n memory elements of the write target memory cell, where at most one of the bits of the fourth data is 1.

[0006] In an embodiment of the first aspect, sequentially reading the data of the n memory elements in the read target memory cell as a first data when a data reading instruction is received includes: selecting the read target memory cell through a word line according to the data reading instruction; turning on the transistor of the read target memory cell and grounding its source line; sequentially reading the data stored in each of the memory elements in the read target memory cell and obtaining the first data according to the read data.

[0007] In an embodiment of the first aspect, for any one of the memory elements in the read target memory cell, reading the data stored in the memory element includes: configuring the sense amplifier corresponding to the memory element to be turned on and configuring the remaining sense amplifiers to be turned off; applying a reading voltage to the bit line of the memory element to obtain the current of the memory element, and the current of the memory element is amplified and latched by the sense amplifier corresponding to the memory element.

[0008] In an embodiment of the first aspect, when all the bits of the fourth data are zero, writing the bits of the fourth data into the n memory elements of the write target memory cell includes: selecting the write target memory cell through a word line according to the data writing instruction; turning on the transistor of the write target memory cell and applying a write zero voltage to its source line; configuring the sense amplifiers corresponding to each of the memory elements in the write target memory cell to be turned on; applying a zero voltage to the bit lines of each of the memory elements in the write target memory cell.

[0009] In an embodiment of the first aspect, the method further includes: before writing the fourth data into the write target storage unit, performing a read operation verification on the write target storage unit; if the read operation verification passes, not writing the fourth data into the write target storage unit; otherwise, writing each bit of the fourth data into n storage elements of the write target storage unit; and / or after writing each bit of the fourth data into n storage elements of the write target storage unit, performing a read operation verification on the write target storage unit; if the read operation verification fails, writing each bit of the fourth data into n storage elements of the write target storage unit again.

[0010] In an embodiment of the first aspect, when there is a non-zero data bit in the fourth data, writing each bit of the fourth data into n storage elements of the write target storage unit includes: selecting the write target storage unit through a word line according to the data write instruction; writing zeros into n storage elements of the write target storage unit; turning on the transistor of the write target storage unit and grounding its source line; configuring the sense amplifier corresponding to the target storage element to be turned on and configuring the remaining sense amplifiers to be turned off, where the target storage element refers to the storage element for storing the non-zero data in the fourth data; applying a write-one voltage to the bit line of the target storage element.

[0011] In an embodiment of the first aspect, the data converter includes a first conversion module and a second conversion module, where: when receiving the data read instruction, the first conversion module is configured to convert the first data input through the first port into the second data and output the second data through the second port; when receiving the data write instruction, the second conversion module is configured to convert the third data input through the second port into the fourth data and output the fourth data through the first port.

[0012] In an embodiment of the first aspect, the resistive random access memory has a 1T3R structure, where: the first output data of the first conversion module is the result of an OR operation between its first input data and second input data, and the second output data of the first conversion module is the result of an OR operation between its first input data and third input data; the first output data of the second conversion module is the result of an AND operation between its first input data and second input data, the second output data of the second conversion module is the result of an AND operation between the non-value of its second input data and its first input data, and the third output data of the second conversion module is the result of an AND operation between the non-value of its first input data and its second input data.

[0013] The second aspect of the present invention provides a resistive random access memory having a 1TnR structure. The resistive random access memory includes a plurality of memory cells, a data converter, and n sense amplifiers. Each of the memory cells includes n memory elements and a transistor. Each of the memory elements in each memory cell is connected to the data converter through a corresponding sense amplifier. The resistive random access memory is configured to perform data reading and / or writing by using the method according to any one of the first aspect of the present invention.

[0014] The third aspect of the present invention provides an electronic device, which includes: a memory storing a computer program; and a processor communicatively connected to the memory, and when calling the computer program, executing the method according to any one of the first aspect of the present invention.

[0015] As described above, the data reading and writing method, the resistive random access memory, and the electronic device provided in one or more embodiments of the present invention have the following beneficial effects:

[0016] When receiving a data reading instruction, the data reading and writing method can read the data of each memory element in the read target memory cell as the first data, and output the first data after converting it into the second data through the data converter. When receiving a data writing instruction, the data reading and writing method can convert the third data into the fourth data through the data converter and write the fourth data into each memory element of the write target memory cell respectively. Therefore, the data reading and writing method can be applied to a resistive random access memory having a 1TnR structure.

[0017] In addition, during the data reading process, at most one of the bits of the first data read from the read target memory cell is 1. During the data writing process, at most one of the bits of the fourth data written into the write target memory cell is 1. Therefore, during the data reading and writing process, at most only one memory element is in the on state. In this way, the current in the transistor can be prevented from being too large, ensuring its normal operation.

[0018] Further, in some embodiments, the specific structure of the data converter is also provided. Through this data converter, the conversion between the n-bit data stored in the memory cell and the m-bit data input (or output) can be realized. Description of the Drawings

[0019] Figure 1A Schematic structural diagram of a resistive random access memory shown as a 1T1R structure.

[0020] Figure 1B Schematic structural diagram of a resistive random access memory shown as a 1TnT structure.

[0021] Figure 2ASchematic diagram of the memory cell in the resistive random access memory shown as a 1T1R structure.

[0022] Figure 2B Schematic diagram of the memory cell in the resistive random access memory shown as a 1TnR structure.

[0023] Figure 3A Schematic diagram of the resistive random access memory of the 1T3R structure in the embodiment of the present invention.

[0024] Figure 3B Flowchart of the data reading and writing method in the embodiment of the present invention.

[0025] Figure 4A Flowchart of the data reading method in the embodiment of the present invention.

[0026] Figure 4B Detailed flowchart of step S43 in the embodiment of the present invention.

[0027] Figure 5 Flowchart of the write-zero operation in the embodiment of the present invention.

[0028] Figure 6 Flowchart of the write-one operation in the embodiment of the present invention.

[0029] Figure 7A Schematic diagram of the data converter in the embodiment of the present invention.

[0030] Figure 7B Schematic example diagram of the data converter in the embodiment of the present invention.

[0031] Figure 8 Schematic diagram of the electronic device in the embodiment of the present invention.

[0032] Description of component labels

[0033] 3 Resistive random access memory

[0034] 31 Data converter

[0035] 311 First conversion module

[0036] 3111, 3112 OR gate

[0037] 312 Second conversion module

[0038] 3121, 3122, 3123 AND gate

[0039] 3124, 3125 NOT gate

[0040] 321, 322, 323 Sense amplifier

[0041] 331 storage units

[0042] 8 electronic devices

[0043] 81 memories

[0044] 82 processors

[0045] Steps S1 to Sn

[0046] Steps S31 to S32

[0047] Steps S41 to S43

[0048] Steps S431 to S432

[0049] Steps S51 to S54

[0050] Steps S61 to S65 Specific implementation manners

[0051] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0052] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. The diagrams only show the components related to the present invention rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. In addition, in this article, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0053] Such as Figure 2AAs shown, each memory cell (ReRAM Cell) in the resistive random access memory with a 1T1R structure can be regarded as a storage unit, that is, each storage unit can store 1 Bit of data. Therefore, for the resistive random access memory with a 1T1R structure, its read and write methods are relatively simple. Specifically, when writing data to it, only the corresponding write voltage needs to be applied to the selected storage unit (including a single memory cell) to complete the data writing. When reading data from it, only the corresponding read voltage needs to be applied to the selected storage unit (including a single memory cell) to complete the data reading. However, as Figure 2B shown, for the resistive random access memory with a 1TnR structure, one transistor needs to control multiple memory cells simultaneously, and the data read and write method applicable to the resistive random access memory with a 1T1R structure cannot be applied to the resistive random access memory with a 1TnR structure.

[0054] At least for the above problems, the present invention provides a data read and write method applied to the resistive random access memory with a 1TnR structure. Next, the data read and write method will be introduced by means of specific embodiments in combination with the drawings.

[0055] In an embodiment of the present invention, the resistive random access memory includes a data converter, a plurality of storage units, and n sense amplifiers, where n is a positive integer. Each storage unit includes n memory cells and one transistor. For any storage unit, the n memory cells therein correspond to the n sense amplifiers one by one, and any one of the memory cells in this storage unit is connected to a port of the data converter through the corresponding sense amplifier.

[0056] For example, Figure 3A shows a structural example diagram of the resistive random access memory 3 when n = 3. As Figure 3A shown, the resistive random access memory 3 includes a data converter 31, 1024 storage units, and three sense sensors 321, 322, and 323. Among them, each storage unit contains three memory cells and one transistor. Taking the storage unit 331 as an example, it contains three memory cells Cell_1, Cell_2, and Cell_3. The memory cell Cell_1 corresponds to the sense sensor 321, the memory cell Cell_2 corresponds to the sense sensor 322, and the memory cell Cell_3 corresponds to the sense sensor 323. The memory cell Cell_1 is connected to the port A of the data converter 31 through the sense sensor 321, the memory cell Cell_2 is connected to the port B of the data converter 31 through the sense sensor 322, and the memory cell Cell_1 is connected to the port C of the data converter 31 through the sense sensor 323.

[0057] Figure 3B shows the flowchart of the data read and write method in this embodiment. AsFigure 3B As shown in Figure 3B , the data reading and writing method in this embodiment includes the following steps S31 and S32.

[0058] S31, when a data reading instruction is received, sequentially read the data of n memory cells in the read target memory cell as the first data, and convert the first data into the second data of m bits (Bit) through a data converter and output it. Among them, at most one of the data bits of the first data is 1, and m is a positive integer less than or equal to . For example, when n = 3, m can be 2.

[0059] S32, when a data writing instruction is received, convert the third data of m bits into the fourth data of n bits through a data converter, and write the data bits of the fourth data into n memory cells of the write target memory cell. Among them, at most one of the data bits of the fourth data is 1.

[0060] According to the above description, it can be known that in this embodiment, when a data reading instruction is received, the data reading and writing method can read the data of each memory cell in the read target memory cell as the first data, and convert the first data into the second data through a data converter and then output it. When a data writing instruction is received, the data reading and writing method can convert the third data into the fourth data through a data converter and write the fourth data into each memory cell of the write target memory cell respectively. Therefore, the data reading and writing method can be applied to a resistive random access memory with a 1TnR structure. In addition, during the data reading process, at most one of the data bits of the first data read from the read target memory cell is 1. During the data writing process, at most one of the data bits of the fourth data written into the write target memory cell is 1. Therefore, during the data reading and writing process, at most only one memory cell can be in the on state. In this way, the current in the transistor can be prevented from being too large, ensuring its normal operation.

[0061] In addition, it should be noted that in some embodiments, only step S31 can be used to perform a read operation on the data in the resistive random access memory, and in some other embodiments, only step S32 can be used to perform a write operation on the memory cells in the resistive random access memory.

[0062] Please refer to Figure 4A , in an embodiment of the present invention, sequentially reading the data of n memory cells in the read target memory cell as the first data when a data reading instruction is received includes the following steps S41 to S43.

[0063] S41, select the read target memory cell through a word line according to the data reading instruction.

[0064] S42, turn on the transistor of the read target memory cell and ground its source line.

[0065] S43, sequentially read the data stored in each memory cell of the read target memory cell and obtain first data according to the read data.

[0066] For example, for Figure 3A the resistive random access memory 3 shown, in step S41, the memory cell 331 can be selected as the read target memory cell through the word line WL0. In step S42, the transistor M0 of the memory cell 331 can be turned on and its source line SL can be grounded. In step S43, the data of each memory cell Cell_1, Cell_2, and Cell_3 in the memory cell 331 can be sequentially read in sequence and the first data can be obtained according to the read data.

[0067] Taking the memory cell Cell_1 in the memory cell 331 as an example, Figure 4B it shows the flowchart of reading the data stored in the memory cell Cell_1 in this embodiment. As Figure 4B shown, reading the data stored in the memory cell Cell_1 in this embodiment includes the following steps S431 and S432.

[0068] S431, configure the sense amplifier 321 corresponding to the memory cell Cell_1 to be enabled and configure the remaining sense amplifiers 322 and 323 to be disabled.

[0069] S432, apply a read voltage Vbl_rd on the bit line BL0 of the memory cell Cell_1 to obtain the current of the memory cell Cell_1, and this current is amplified and latched by the sense amplifier 321. In this way, 1-bit data stored in the memory cell Cell_1 can be obtained.

[0070] In addition, this embodiment can adopt a manner similar to the above steps S431 and S432, amplify and latch the current of the memory cell Cell_2 through the sense amplifier 322, and amplify and latch the current of the memory cell Cell_3 through the sense amplifier 323. After obtaining the data of all memory cells, in this embodiment, the 3-bit data latched in the sense amplifiers 321, 322, and 323 can be simultaneously converted into corresponding 2-bit data and output through the data converter 31.

[0071] Please refer to Figure 5 , in an embodiment of the present invention, when each bit of the fourth data is zero, writing each bit of the fourth data into n memory cells of the write target memory cell includes the following steps S51 to step S54.

[0072] S51, select the write target memory cell through the word line according to the data write instruction.

[0073] S52. Turn on the transistor of the write target storage cell and apply a write zero voltage to its source line.

[0074] S53. Configure the sense amplifiers corresponding to each memory cell in the write target storage cell to be turned on.

[0075] S54. Apply a zero voltage to the bit lines of each memory cell in the write target storage cell.

[0076] For example, for Figure 3A the resistive random access memory 3 shown, in step S51, the storage cell 331 can be selected as the write target storage cell through the word line WL0. In step S52, the transistor M0 of the storage cell 331 can be turned on and a write zero voltage Vsl_w0 can be applied to its source line SL. In step S53, all the sense amplifiers 321, 322, and 323 can be configured to be turned on. In step S54, a zero voltage can be simultaneously applied to the bit lines BL0, BL1, and BL2 of all the memory cells Cell_1, Cell_2, and Cell_3 in the storage cell 331, so as to implement the write zero operation for the three memory cells Cell_1, Cell_2, and Cell_3 in the storage cell 331.

[0077] Optionally, before step S52, the data reading and writing method may further include: performing a read operation verification on the write target storage cell. If the read operation verification passes, the fourth data is not written into the write target storage cell, that is, the above steps S52 to S54 are not executed; otherwise, the above steps S52 to S54 are executed to rewrite the fourth data into the write target storage cell.

[0078] Optionally, after step S54, the data reading and writing method may further include: performing a read operation verification on the write target storage cell. If the read operation verification fails, each bit of the fourth data is written into each memory cell of the write target storage cell again, that is, the above steps S52 to S54 are executed again; otherwise, the write operation on the write target storage cell is completed.

[0079] Please refer to Figure 6 , in an embodiment of the present invention, when there is a non-zero data bit in the fourth data center, writing each bit of the fourth data into n memory cells of the write target storage cell includes the following steps S61 to S64.

[0080] S61. Select the write target storage cell through the word line according to the data write instruction.

[0081] S62. Perform a write zero operation on the n memory cells of the write target storage cell.

[0082] S63. Turn on the transistor of the write target storage cell and ground its source line.

[0083] S64, configure the sense amplifier corresponding to the target storage element to be turned on and configure the remaining sense amplifiers to be turned off, where the target storage element refers to the storage element used to store the non-zero data in the fourth data. For example, if the k-th bit data in the fourth data is 1, the target storage element can be the k-th storage element in the write target storage unit, where k is a positive integer and k ≤ n.

[0084] S65, apply a write-one voltage Vbl_w1 to the bit line of the target storage element.

[0085] For example, for Figure 3A the resistive random access memory 3 shown, if the fourth data is 010, the target storage element is Cell_2. In step S61, the storage unit 331 can be selected as the write target storage unit through the word line WL0. In step S62, the write-zero operation can be performed on Cell_1, Cell_2, and Cell_3 in a similar manner to steps S51 to S54. In step S63, the transistor M0 of the storage unit 331 can be turned on and its source line SL can be grounded. In step S64, the sense amplifier 322 corresponding to the storage element Cell_2 can be configured to be turned on and the sense amplifiers 321 and 323 can be configured to be turned off. In step S65, a write-one voltage can be applied to the bit line BL1 of the storage element Cell_2 to complete the write-one operation on Cell_2.

[0086] Optionally, before step S62, the data reading and writing method may further include: performing a read operation verification on the write target storage unit. If the read operation verification passes, the fourth data is not written into the write target storage unit, that is, steps S62 to S65 are not executed; otherwise, steps S62 to S65 are executed to write the fourth data into the write target storage unit.

[0087] Optionally, after step S65, the data reading and writing method may further include: performing a read operation verification on the write target storage unit. If the read operation verification fails, steps S62 to S65 are executed again to rewrite the fourth data into the write target storage unit; otherwise, the write operation on the write target storage unit is completed.

[0088] Please refer to Figure 7A , in an embodiment of the present invention, the data converter 31 includes a first conversion module 311 and a second conversion module 312. When receiving a data reading instruction, the first conversion module 311 is used to convert the first data input from the first port into the second data and output it through the second port. When receiving a data writing instruction, the second conversion module 312 is used to convert the third data input from the second port into the fourth data and output it through the first port.

[0089] Optionally, the resistive random access memory has a 1T3R structure. At this time, the data converter 31 includes three first ports A, B, and C and two second ports X and Y. The first output data of the first conversion module 311 (i.e., the data output from port X) is the result of the OR operation of its first input data (i.e., the data input from port A) and the second input data (i.e., the data input from port B). The second output data of the first conversion module 311 (i.e., the data output from port Y) is the result of the OR operation of its first input data and the third input data (i.e., the data input from port C). The first output data of the second conversion module 312 (i.e., the data output from port A) is the result of the AND operation of its first input data (i.e., the data input from port X) and the second input data (i.e., the data input from port Y). The second output data of the second conversion module 312 (i.e., the data output from port B) is the result of the AND operation of the non-value of its second input data and its first input data. The third output data of the second conversion module 312 (i.e., the data output from port C) is the result of the AND operation of the non-value of its first input data and its second input data.

[0090] Optionally, as Figure 7B shown, the first conversion module 311 has two OR gates 3111 and 3112. The first input data and the second input data of the first conversion module 311 form the first output data after passing through the OR gate 3111. The first input data and the third input data of the first conversion module 311 form the second output data after passing through the OR gate 3112. The second conversion module 312 includes three AND gates 3121, 3122, 3123 and two NOT gates 3124 and 3125. The first input data and the second input data of the second conversion module 312 form the first output data after passing through the AND gate 3121. The first input data of the second conversion module 312 and the second input data after passing through the NOT gate 3124 form the second output data through the AND gate 3122. The second input data of the second conversion module 312 and the first input data after passing through the NOT gate 3125 form the third output data through the AND gate 3123.

[0091] According to the above description, for the resistive random access memory 3, the data converter 31 can implement the conversion between the data of three memory cells in the memory cell 331 and the 2-bit data input or output. The specific conversion relationship is shown in Table 1.

[0092] Table 1 Conversion Relationship Correspondence Table

[0093]

[0094] Based on the above description of the data reading and writing method, the present invention further provides a resistive random access memory having a 1TnR structure. The resistive random access memory includes a plurality of memory cells, a data converter, and n sense amplifiers. Each memory cell includes n memory elements and a transistor, and each memory element in each memory cell is connected to the data converter through a corresponding sense amplifier. The resistive random access memory is configured to perform data reading and / or writing by using the method provided in the above embodiment.

[0095] Based on the above description of the data reading and writing method, the present invention further provides an electronic device. Figure 8 Shown is a schematic structural diagram of the electronic device 8 in an embodiment of the present invention. As Figure 8 shown, the electronic device 8 includes a memory 81 and a processor 82. Among them, the memory 81 stores a computer program. The processor 82 is communicatively connected to the memory 81 and executes the method provided in the above embodiment when calling the computer program.

[0096] Preferably, the processor 82 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc., and may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0097] In addition, the bus in the electronic device 8 represents one or more of several bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure in a variety of bus structures. For example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0098] The protection scope of the data reading and writing method described in the present invention is not limited to the execution order of the steps listed in this embodiment. Any solution achieved by adding or reducing steps of the prior art and replacing steps according to the principle of the present invention is included in the protection scope of the present invention.

[0099] In summary, one or more embodiments of the present invention provide a data reading and writing method applied to a resistive random access memory having a 1TnR structure. When receiving a data reading instruction, the data reading and writing method can read the data of each memory cell in the read target memory cell as the first data, and output the second data after converting the first data through a data converter. When receiving a data writing instruction, the data reading and writing method can convert the third data into the fourth data through the data converter and write the fourth data into each memory cell of the write target memory cell respectively. Therefore, the data reading and writing method can be applied to a resistive random access memory having a 1TnR structure.

[0100] In addition, during the data reading process, at most one of the bits of the first data read from the read target memory cell is 1. During the data writing process, at most one of the bits of the fourth data written into the write target memory cell is 1. Therefore, during the data reading and writing process, at most only one memory cell can be in the on state. In this way, the current in the transistor can be prevented from being too large, ensuring its normal operation.

[0101] Furthermore, in some embodiments, the specific structure of the data converter is also provided. Through this data converter, the conversion between the bit data stored in the memory cell and the input (or output) bit data can be achieved.

[0102] Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0103] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A data reading and writing method applied to a resistive random access memory with a 1TnR structure, characterized in that, the resistive random access memory includes a data converter, a plurality of memory cells and n sense amplifiers. Each of the memory cells includes n memory elements and a transistor. Each of the memory elements in each memory cell is connected to the data converter through a corresponding sense amplifier. The method includes: When receiving a data reading instruction, the data of n memory cells in the read target storage unit are sequentially read as first data, and the first data is converted into second data of m bits by the data converter and output, where at most one of the data bits of the first data is 1, and m is a positive integer less than or equal to ; and / or When receiving a data writing instruction, converting m-bit third data into n-bit fourth data through the data converter, and writing each bit of the fourth data into n memory elements of a write target memory cell, wherein at most one of each bit of the fourth data is 1.

2. The method according to claim 1, characterized in that, when receiving a data reading instruction, sequentially reading the data of n memory elements in a read target memory cell as first data includes: selecting the read target memory cell through a word line according to the data reading instruction; turning on the transistor of the read target memory cell and grounding its source line; sequentially reading the data stored in each of the memory elements in the read target memory cell and obtaining the first data according to the read data.

3. The method according to claim 2, characterized in that, for any one of the memory elements in the read target memory cell, reading the data stored in the memory element includes: configuring the sense amplifier corresponding to the memory element to be turned on and configuring the remaining sense amplifiers to be turned off; applying a reading voltage to the bit line of the memory element to obtain the current of the memory element, and the current of the memory element is amplified and latched by the sense amplifier corresponding to the memory element.

4. The method according to claim 1, characterized in that, when each bit of the fourth data is zero, writing each bit of the fourth data into n memory elements of a write target memory cell includes: selecting the write target memory cell through a word line according to the data writing instruction; turning on the transistor of the write target memory cell and applying a write zero voltage to its source line; configuring the sense amplifiers corresponding to each of the memory elements in the write target memory cell to be turned on; applying a zero voltage to the bit lines of each of the memory elements in the write target memory cell.

5. The method according to claim 4, characterized in that, further includes: before writing the fourth data into the write target memory cell, performing a read operation verification on the write target memory cell. If the read operation verification passes, the fourth data is not written into the write target memory cell. Otherwise, each bit of the fourth data is written into n memory elements of the write target memory cell; and / or after writing each bit of the fourth data into n memory elements of the write target memory cell, performing a read operation verification on the write target memory cell. If the read operation verification fails, each bit of the fourth data is written into n memory elements of the write target memory cell again.

6. The method according to claim 1, characterized in that, When there is a non-zero data bit in the fourth data, writing each bit of the fourth data into n memory cells of the write target memory cell includes: Selecting the write target memory cell through a word line according to the data write instruction; Performing a zero-writing operation on the n memory cells of the write target memory cell; Turning on the transistor of the write target memory cell and grounding its source line; Configuring the sense amplifier corresponding to the target memory cell to be turned on and configuring the remaining sense amplifiers to be turned off, where the target memory cell refers to the memory cell used to store the non-zero data in the fourth data; Applying a write-one voltage to the bit line of the target memory cell.

7. The method according to claim 1, wherein, the data converter includes a first conversion module and a second conversion module, wherein: When receiving the data read instruction, the first conversion module is configured to convert the first data input from the first port into the second data and output the second data through the second port; When receiving the data write instruction, the second conversion module is configured to convert the third data input from the second port into the fourth data and output the fourth data through the first port.

8. The method according to claim 7, wherein, the resistive random access memory has a 1T3R structure, wherein: The first output data of the first conversion module is the result of an OR operation of its first input data and second input data, and the second output data of the first conversion module is the result of an OR operation of its first input data and third input data; The first output data of the second conversion module is the result of an AND operation of its first input data and second input data, the second output data of the second conversion module is the result of an AND operation of the non-value of its second input data and its first input data, and the third output data of the second conversion module is the result of an AND operation of the non-value of its first input data and its second input data.

9. A resistive random access memory having a 1TnR structure, wherein, the resistive random access memory includes a plurality of memory cells, a data converter, and n sense amplifiers. Each of the memory cells includes n memory cells and a transistor. Each of the memory cells in each memory cell is connected to the data converter through a corresponding sense amplifier. The resistive random access memory is configured to perform data reading and / or writing by using the method according to any one of claims 1-8.

10. An electronic device, wherein, the electronic device includes: a memory storing a computer program; a processor communicatively connected to the memory and executing the method according to any one of claims 1-8 when calling the computer program.

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