A power semiconductor device, its fabrication method and application

Abstract

This application provides a power semiconductor device, its fabrication method, and its application. The power semiconductor device includes a ceramic substrate, a cladding body, multiple chips, and multiple lead frames. The ceramic substrate includes a ceramic wafer, an inner metal foil, and an outer metal foil. The inner metal foil is disposed on one side of the ceramic wafer, and the outer metal foil is disposed on the opposite side of the ceramic wafer. The cladding body covers the ceramic substrate, exposing the side of the outer metal foil away from the inner metal foil to the external space. The chips are located within the cladding body and disposed on the inner metal foil. The multiple chips are spaced apart from each other. The side of a single chip not in contact with the inner metal foil is electrically connected to the inner metal foil through a lead frame. This application replaces the lead bonding in traditional power semiconductor devices with lead frames, which not only improves the heat dissipation performance of the chips but also reduces thermal resistance, achieving miniaturization and weight reduction of the device, thereby improving the reliability of the power semiconductor device.

Description

[Technical Field]

[0001] This application relates to the field of power electronic device technology, and in particular to a power semiconductor device, its fabrication method, and its application. [Background Technology]

[0002] In related technologies, to meet the heat dissipation requirements of high-frequency applications, power semiconductor devices often increase their size, resulting in larger parasitic inductance. This leads to higher overshoot voltage and increased power loss in high-frequency applications, preventing them from reaching their full performance potential. With the continuous improvement and development of power electronics technology, power semiconductor devices are driven by a strong desire for higher power density, but their packaging structure severely hinders further increases in power density. In addition to the aforementioned drawbacks, power semiconductor devices suffer from many other problems, such as poor heat dissipation, large stray inductance, and small creepage distances and clearances. These drawbacks are all major factors that negatively impact the reliability of power semiconductor devices.

[0003] Therefore, it is necessary to improve the structure of the aforementioned power semiconductor devices. [Summary of the Invention]

[0004] This application provides a power semiconductor device, its fabrication method, and its application, aiming to solve the problem of poor reliability of power semiconductor devices in related technologies.

[0005] To address the aforementioned technical problems, the first aspect of this application provides a power semiconductor device, including a ceramic substrate, a cladding body, multiple chips, and multiple lead frames;

[0006] The ceramic substrate includes a ceramic substrate, an inner metal foil, and an outer metal foil; wherein the inner metal foil is disposed on one side of the ceramic substrate, and the outer metal foil is disposed on the opposite side of the ceramic substrate from the inner metal foil.

[0007] The encapsulation body covers the ceramic substrate and exposes the side of the outer metal foil away from the inner metal foil to the external space. The chip is located inside the encapsulation body and disposed on the inner metal foil. The multiple chips are spaced apart from each other. The side of a single chip that is not in contact with the inner metal foil is electrically connected to the inner metal foil through a lead frame.

[0008] The second aspect of this application provides a method for fabricating a power semiconductor device, the power semiconductor device including a ceramic substrate, a cladding body, multiple chips and multiple lead frames; wherein, the ceramic substrate includes a ceramic substrate, an inner metal foil and an outer metal foil, the inner metal foil is disposed on one side of the ceramic substrate, and the outer metal foil is disposed on the opposite side of the ceramic substrate opposite to the inner metal foil;

[0009] The method for fabricating the power semiconductor device includes:

[0010] The plurality of chips are respectively disposed on the inner metal foil; wherein the plurality of chips are spaced apart from each other;

[0011] The side of each chip that is not in contact with the inner metal foil is electrically connected to the inner metal foil through a lead frame.

[0012] The ceramic substrate is encapsulated using a molding process; wherein, after molding, an encapsulation body is formed covering the ceramic substrate, and the side of the outer metal foil away from the inner metal foil is exposed to the external space, and the chip and the lead frame are both located within the encapsulation body.

[0013] The third aspect of this application provides an application of the power semiconductor device described in the first aspect of this application, or the power semiconductor device manufactured by the method described in the second aspect of this application, in power electronic equipment.

[0014] As can be seen from the above description, compared with related technologies, the beneficial effects of this application are as follows:

[0015] A power semiconductor device is constructed using a ceramic substrate (including a ceramic wafer, an inner metal foil, and an outer metal foil), a cladding, multiple chips, and multiple lead frames. The chips are disposed on the inner metal foil within the cladding. The side of each chip that is not in contact with the inner metal foil (i.e., the side of the chip opposite to the inner metal foil) is electrically connected to the inner metal foil via a lead frame. It is understood that in traditional power semiconductor devices, the electrical connection between the chip and the inner metal foil is achieved through wire bonding. However, in this application, the electrical connection between the chip and the inner metal foil is achieved by using lead frames. That is, this application replaces the wire bonding in traditional power semiconductor devices with lead frames. This not only meets the basic requirements for circuit construction but also enables heat conduction through the lead frames. On the one hand, it improves the chip's heat dissipation performance and meets the requirements of high current; on the other hand, it reduces thermal resistance and achieves miniaturization and lightweighting of the power semiconductor device, thereby improving the reliability of the power semiconductor device. [Attached Image Description]

[0016] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a power semiconductor device provided in an embodiment of this application;

[0018] Figure 2 This is a first exploded view of a power semiconductor device provided in an embodiment of this application;

[0019] Figure 3 Provided for the embodiments of this application Figure 2 A magnified view of a portion of point A in the middle;

[0020] Figure 4 This is a second exploded view of the power semiconductor device provided in the embodiments of this application;

[0021] Figure 5 Provided for the embodiments of this application Figure 4 A magnified view of a portion of point B in the middle;

[0022] Figure 6 This is a schematic diagram of the structure of a power semiconductor device after the cladding has been removed, as provided in an embodiment of this application.

[0023] Figure 7 Provided for the embodiments of this application Figure 6 A magnified view of a portion of point C in the middle;

[0024] Figure 8 Provided for the embodiments of this application Figure 6 A magnified view of a portion of point D in the middle;

[0025] Figure 9 Provided for the embodiments of this application Figure 6 A magnified view of a portion of point E in the middle;

[0026] Figure 10 This is a schematic diagram of the partitioning of the inner metal foil after etching, provided in an embodiment of this application;

[0027] Figure 11 This is a top view of a power semiconductor device after the cladding has been removed, as provided in an embodiment of this application.

[0028] Figure 12 This is a schematic flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this application.

Detailed Implementation Methods

[0029] To make the objectives, technical solutions, and advantages of this application more apparent and understandable, the application will be clearly and completely described below in conjunction with the embodiments and corresponding drawings. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. It should be understood that the various embodiments of this application described below are merely illustrative and not intended to limit the application. That is, all other embodiments obtained by those skilled in the art based on the various embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0030] Power electronic devices, also known as power semiconductor devices, are primarily used in power electronic devices composed of numerous power semiconductor devices to achieve electrical energy conversion and control. Currently, the semiconductor materials used in power semiconductor devices include two types: SiC (Silicon Carbide) and Si (Silicon). SiC, as a typical representative of third-generation semiconductor materials, boasts characteristics such as bandgap, critical breakdown electric field, thermal conductivity, and carrier saturation drift velocity that are more than three times that of Si, making it an excellent material for manufacturing power semiconductor devices. SiC power semiconductor devices offer numerous advantages over Si power semiconductor devices, such as higher operating frequency and temperature, lower power loss, and higher voltage ratings. This explains the rapid development of SiC power semiconductor devices in the new energy vehicle sector in recent years; in other words, SiC power semiconductor devices can further promote the application of new energy vehicles.

[0031] In related technologies, to meet the heat dissipation requirements of high-frequency applications, SiC power semiconductor devices often increase in size, resulting in larger parasitic inductance. This leads to larger overshoot voltage and increased power loss in high-frequency applications, preventing the SiC power semiconductor device from achieving its full performance. SiC power semiconductor devices have a strong pursuit of higher power density, but their packaging structure severely hinders further increases in power density. In addition to the aforementioned drawbacks, SiC power semiconductor devices also suffer from many other disadvantages, such as poor heat dissipation, large stray inductance, and small creepage distances and clearances. These drawbacks are major factors adversely affecting the reliability of SiC power semiconductor devices. Therefore, this application provides a power semiconductor device that can be applied to various power electronic devices, such as switching power supplies, frequency converters, inverters, laptops, mobile phones, and smart wearable devices.

[0032] Please see Figures 1 to 3 , Figure 1 This is a schematic diagram of the structure of the power semiconductor device provided in the embodiments of this application. Figure 2 This is a first exploded view of the power semiconductor device provided in the embodiments of this application. Figure 3 Provided for the embodiments of this application Figure 2 A partially enlarged schematic diagram at point A. The power semiconductor device provided in this application includes a ceramic substrate 10, a cladding body 20, multiple chips 30, and multiple lead frames 40; wherein, the ceramic substrate 10 includes a ceramic sheet 11, an inner metal foil 12, and an outer metal foil 13, and the inner metal foil 12 is disposed on one side of the ceramic substrate 11, and the outer metal foil 13 is disposed on the other side of the ceramic substrate 11 opposite to the inner metal foil 12. Specifically, the cladding 20 covers the ceramic substrate 10, exposing the side of the outer metal foil 13 away from the inner metal foil 12 to the external space (this means that the cladding 20 does not completely cover the ceramic substrate 10, that is, only the side of the outer metal foil 13 away from the inner metal foil 12 in the ceramic substrate 10 is exposed to the external space, while the rest of the ceramic substrate 10 is covered). The chip 30 is located inside the cladding 20 and disposed on the inner metal foil 12. Multiple chips 30 are spaced apart from each other. The side of a single chip 30 that is not in contact with the inner metal foil 12 (that is, the side opposite to the inner metal foil 12) is electrically connected to the inner metal foil 12 through a lead frame 40 to meet the basic requirements for forming a circuit. Among them, the side of all chips 30 that is not in contact with the inner metal foil 12 is electrically connected to the inner metal foil 12 through the corresponding lead frame 40, forming the main circuit of the power semiconductor device. It is necessary to explain here that the purpose of exposing the side of the outer metal foil 13 away from the inner metal foil 12 to the external space is to connect with the external heat dissipation structure in order to improve the heat dissipation effect of the power semiconductor device.

[0033] In this embodiment, the thickness difference between the inner metal foil 12 and the outer metal foil 13 in the ceramic substrate 10 can be 0–0.2 mm, depending on the warpage requirements of different processes. The chip 30 and the inner metal foil 12, the chip 30 and the lead frame 40, and the lead frame 40 and the inner metal foil 12 can all be bonded by sintering processes, such as silver sintering and copper sintering, and the sintering thickness can be 10–200 μm. That is, the bonding points between the chip 30 and the inner metal foil 12, the chip 30 and the lead frame 40, and the lead frame 40 and the inner metal foil 12 all have sintered layers formed by the sintering process, such as silver sintered layers and copper sintered layers. The gate of the chip 30 can be electrically connected to the inner metal foil 12 through finer metal interconnects (such as aluminum wires), thereby forming an auxiliary circuit for a power semiconductor device. Furthermore, the thickness of the lead frame 40 in this embodiment can be 0.3–1.5 mm.

[0034] In this embodiment, a power semiconductor device is constructed by a ceramic substrate 10 (including a ceramic substrate 11, an inner metal foil 12, and an outer metal foil 13), a cladding body 20, a plurality of chips 30, and a plurality of lead frames 40. The chips 30 are disposed on the inner metal foil 12 within the cladding body 20. At the same time, the side of each chip 30 that is not in contact with the inner metal foil 12 (i.e. the side of the chip 30 opposite to the inner metal foil 12) is electrically connected to the inner metal foil 12 through a lead frame 40. It is understood that in traditional power semiconductor devices, the electrical connection between the chip and the inner metal foil is achieved through wire bonding. However, in this embodiment, the electrical connection between the chip 30 and the inner metal foil 12 is achieved by setting a lead frame 40. That is, this embodiment replaces the wire bonding in traditional power semiconductor devices with a lead frame 40. This not only meets the basic requirements for circuit construction but also enables heat conduction through the lead frame 40. On the one hand, it improves the heat dissipation performance of the chip 30 and meets the requirements of high current. On the other hand, it reduces the thermal resistance of the power semiconductor device and achieves miniaturization and weight reduction, thereby improving the reliability of the power semiconductor device. Therefore, the lead frame 40-based press-fit packaging structure used in this embodiment significantly enhances the electrical characteristics, thermal characteristics, heat dissipation effect, and current carrying capacity of the power semiconductor device, which is extremely beneficial for improving the reliability of the power semiconductor device.

[0035] As one possible implementation method, please refer to further information. Figure 4 and Figure 5 , Figure 4 This is a second exploded view of the power semiconductor device provided in the embodiments of this application. Figure 5 Provided for the embodiments of this application Figure 4A partially enlarged schematic diagram at point B. The lead frame 40 may include a first contact portion 41 disposed on the side of the chip 30 that is not in contact with the inner metal foil 12, a second contact portion 42 disposed on the inner metal foil 12, and a connecting portion 43 connecting the first contact portion 41 and the second contact portion 42; wherein, the connecting portion 43 extends and bends from the end of the first contact portion 41 near the second contact portion 42 toward the second contact portion 42. It is necessary to explain here that the lead frame 40 in this embodiment includes three parts (i.e., the first contact portion 41, the second contact portion 42, and the connecting portion 43), and the lead frame 40 can be integrally molded in actual manufacturing.

[0036] As another implementation, based on the previous implementation, grooves 44 can be formed on both sides of the first contact portion 41 away from the connecting portion 43, and on one end of the second contact portion 42 away from the connecting portion 43. It can be understood that forming grooves 44 on the first contact portion 41 and the second contact portion 42 can, on the one hand, release the stress when the lead frame 40 is bonded to the chip 30, and on the other hand, release the stress brought about by subsequent molding, thereby further improving the reliability of the power semiconductor device.

[0037] It should be noted that the above two implementation methods are only preferred implementations of the embodiments of this application, and are not the only limitation on the specific structure of the lead frame 40; those skilled in the art can make flexible settings based on the embodiments of this application and according to the actual application scenario.

[0038] In some embodiments, please refer to further information. Figure 6 , Figure 6 This is a schematic diagram of the structure of the power semiconductor device provided in this embodiment after removing the cladding. In addition to the ceramic substrate 10, cladding 20, multiple chips 30, and multiple lead frames 40, the power semiconductor device provided in this embodiment may also include a first main terminal 50 and a second main terminal 60. One end of the first main terminal 50 is disposed on the inner metal foil 12, and the opposite end protrudes through the cladding 20 and is exposed to the external space. One end of the second main terminal 60 is disposed on the inner metal foil 12, and the opposite end protrudes through the cladding 20 and is exposed to the external space. The first main terminal 50 and the second main terminal 60 are located at opposite ends of the inner metal foil 12, that is, at opposite ends of the ceramic substrate 10 / cladding 20. It is understood that since both the first main terminal 50 and the second main terminal 60 are partially encased within the cladding 20, and the mechanical properties of the cladding 20 are stable, the positions of the first main terminal 50 and the second main terminal 60 are not easily changed, thereby further improving the reliability of the power semiconductor device.

[0039] For example, the first main terminal 50 in this document can be used as an output terminal, and the second main terminal 60 can be used as a DC (Direct Current) terminal. In this case, the second main terminal 60 can include three terminals spaced apart from each other, namely one N terminal and two P terminals, with the two P terminals located on opposite sides of the N terminal.

[0040] As one possible implementation method, please refer to further information. Figure 7 and Figure 8 , Figure 7 Provided for the embodiments of this application Figure 6 A magnified view of a portion of point C in the middle. Figure 8 Provided for the embodiments of this application Figure 6 A partially enlarged schematic diagram at point D. The first main terminal 50 may include a first embedded portion 51 located within the cover body 20 and disposed on the inner metal foil 12, a first exposed portion 52 exposed to the external space, and a first connecting portion 53 connecting the first embedded portion 51 and the first exposed portion 52; wherein, the first connecting portion 53 extends from the end of the first embedded portion 51 near the first exposed portion 52 toward the first exposed portion 52 and passes through the cover body 20, the side of the first embedded portion 51 away from the inner metal foil 12 is lower than the side of the first exposed portion 52 near the inner metal foil 12, and the extension directions of the first embedded portion 51 and the first exposed portion 52 are both parallel to the surface of the ceramic substrate 10, that is, parallel to the surface of the inner metal foil 12. It is understood that in this embodiment, the side of the first embedded part 51 away from the inner metal foil 12 is lower than the side of the first exposed part 52 close to the inner metal foil 12, thereby increasing the distance between the first exposed part 52 and the outer metal foil 13, so as to meet the requirements of creepage distance and clearance of power semiconductor devices.

[0041] The specific configuration of the second main terminal 60 can be the same as or similar to that of the first main terminal 50. That is, the second main terminal 60 may include a second embedded portion 61 located inside the cover body 20 and disposed on the inner metal foil 12, a second exposed portion 62 exposed to the external space, and a second connecting portion 63 connecting the second embedded portion 61 and the second exposed portion 62. The second connecting portion 63 extends from the end of the second embedded portion 61 near the second exposed portion 62 toward the second exposed portion 62 and passes through the cover body 20. The side of the second embedded portion 61 away from the inner metal foil 12 is lower than the side of the second exposed portion 62 near the inner metal foil 12. The extension directions of the second embedded portion 61 and the second exposed portion 62 are both parallel to the surface of the ceramic substrate 10, that is, parallel to the surface of the inner metal foil 12. It is understood that in this embodiment, the side of the second embedded part 61 away from the inner metal foil 12 is lower than the side of the second exposed part 62 close to the inner metal foil 12, thereby increasing the distance between the second exposed part 62 and the outer metal foil 13, so as to meet the requirements of creepage distance and clearance of power semiconductor devices.

[0042] In another implementation, based on the previous implementation, a circular through-hole 521 can be formed on the first exposed portion 52 of the first main terminal 50, and an elliptical through-hole 621 can be formed on the second exposed portion 62 of the second main terminal 60. The circular through-hole 521 is used to engage with a nut to connect the first main terminal 50 to other devices; similarly, the elliptical through-hole 621 is also used to engage with a nut to connect the second main terminal 60 to other devices. It is understood that, compared to the circular through-hole 521, the nut in the elliptical through-hole 621 can be adjusted back and forth along the long axis of the elliptical through-hole 621. This allows for greater tolerance in the position of the second main terminal 60 when connected to other devices, and also reduces stray inductance at the second main terminal 60, thereby further improving the reliability of the power semiconductor device.

[0043] It should be noted that the above two implementation methods are only preferred implementations of this embodiment, and are not the only limitation on the specific configuration of the first main terminal 50 and the second main terminal 60; those skilled in the art can make flexible settings based on this embodiment and according to the actual application scenario.

[0044] In some embodiments, please combine Figure 1 , Figure 6 and Figure 8 In addition to the ceramic substrate 10, cladding 20, first main terminal 50, second main terminal 60, multiple chips 30, and multiple lead frames 40, the power semiconductor device provided in this embodiment may also include multiple auxiliary terminals 70. One end of each auxiliary terminal 70 is located within the cladding 20 and disposed on the inner metal foil 12, while the other end extends out of the cladding 20 and is exposed to the external space. The extending direction of the auxiliary terminal 70 is perpendicular to the surface of the ceramic substrate 10, i.e., perpendicular to the surface of the inner metal foil 12. It is understood that because the auxiliary terminal 70 is partially encased within the cladding 20, and the cladding 20 has stable mechanical properties, the auxiliary terminal 70 is less prone to tilting or deformation, thereby further improving the reliability of the power semiconductor device.

[0045] Furthermore, as mentioned earlier, the extension directions of the first embedded portion 51, the first exposed portion 52, the second embedded portion 61, and the second exposed portion 62 are all parallel to the surface of the ceramic substrate 10. That is, the extension directions of the first main terminal 50 and the second main terminal 60 are all parallel to the surface of the ceramic substrate 10. However, in this embodiment, the extension direction of the auxiliary terminal 70 is perpendicular to the surface of the ceramic substrate 10. This means that the extension direction of the auxiliary terminal 70 is not parallel to the extension directions of the first main terminal 50 and the second main terminal 60, but perpendicular to them. This design makes the spatial distance between the main terminals (i.e., the first main terminal 50 and the second main terminal 60) and the auxiliary terminal 70 as long as possible, thereby increasing the creepage distance and clearance of the power semiconductor device, that is, reducing the mutual interference between the main circuit and the auxiliary circuit of the power semiconductor device, and further improving the reliability of the power semiconductor device. In addition to the main circuit described above, where "the chip 30 is electrically connected to the inner metal foil 12 via the lead frame 40 to form the main circuit", the main terminals (i.e., the first main terminal 50 and the second main terminal 60) are electrically connected to the chip 30 and other devices located inside the enclosure 20 via the inner metal foil 12 to form the main circuit as well. In addition to the auxiliary circuit described above, where "the chip 30 is electrically connected to the inner metal foil 12 via the metal connecting wire to form the auxiliary circuit", the auxiliary terminal 70 is electrically connected to the chip 30 and other devices located inside the enclosure 20 via the inner metal foil 12 to form the auxiliary circuit as well.

[0046] As one implementation, still referring to 8, the cross-sectional area of ​​the portion of the auxiliary terminal 70 located within the enclosure 20 is set as a first area, and the cross-sectional area of ​​the portion of the auxiliary terminal 70 extending out of the enclosure 20 is set as a second area, and in this embodiment, the first area is larger than the second area; wherein, the cross-sectional area of ​​the portion of the auxiliary terminal 70 located within the enclosure 20 can be maintained at the first value, while the cross-sectional area of ​​the portion of the auxiliary terminal 70 extending out of the enclosure 20 can be maintained at a second value smaller than the first value; or, the cross-sectional area of ​​the auxiliary terminal 70 gradually decreases along the direction from the outer metal foil 13 to the inner metal foil 12. It is understood that by designing the first area to be larger than the second area in this embodiment, the welding area between the auxiliary terminal 70 and the inner metal foil 12 can be effectively increased, thereby further improving the reliability of the power semiconductor device.

[0047] As another implementation, the cross-sectional shape of the auxiliary terminal 70 can be a common shape in the art, including but not limited to circular, elliptical, rectangular, trapezoidal, and polygonal shapes. For example, when fabricating the auxiliary terminal 70, the cross-sectional shape of the auxiliary terminal 70 can be adjusted to give it a pin-wing structure, meaning the top of the auxiliary terminal 70 away from the ceramic substrate 10 is pin-wing shaped. Furthermore, since the extension direction of the auxiliary terminal 70 is perpendicular to the surface of the ceramic substrate 10, the length of the auxiliary terminal 70 along its extension direction is a major factor determining the overall thickness of the power semiconductor device. In this document, the overall thickness of the power semiconductor device can be 3–25 mm.

[0048] It should be noted that the above two implementation methods are only preferred implementations of this embodiment, and are not the only limitation on the cross-section of the auxiliary terminal 70; those skilled in the art can make flexible settings based on this embodiment and the actual application scenario.

[0049] In some embodiments, please refer to further information. Figure 9 , Figure 9 Provided for the embodiments of this application Figure 6 A partially enlarged schematic diagram at point E. In addition to the first main terminal 50, the second main terminal 60, the ceramic substrate 10, the cladding 20, multiple chips 30, multiple lead frames 40, and multiple auxiliary terminals 70, the power semiconductor device provided in this embodiment may also include a thermal resistor 80. The thermal resistor 80 is located within the cladding 20 and disposed on the inner metal foil 12, and the thermal resistor 80 is electrically connected to at least one auxiliary terminal 70. It is understood that the purpose of electrically connecting the thermal resistor 80 to at least one auxiliary terminal 70 is to form a thermal monitoring circuit. In this case, the thermal resistor 80 needs to be placed near the chip 30, so that the thermal monitoring function of the power semiconductor device can be realized through the auxiliary terminal 70 electrically connected to the thermal resistor 80.

[0050] For example, the thermal resistor 80 and the inner metal foil 12 can be bonded by a sintering process (such as silver sintering and copper sintering), and the sintering thickness can be 10-200 μm. That is, the junction between the thermal resistor 80 and the inner metal foil 12 has a sintered layer formed by the sintering process, such as a silver sintered layer and a copper sintered layer. In addition, the side of the thermal resistor 80 that is not bonded to the inner metal foil 12 (i.e., the side opposite to the inner metal foil 12) can be electrically connected to at least one auxiliary terminal 70 through a metal connecting wire (such as an aluminum wire), thereby forming an auxiliary circuit for thermal monitoring of power semiconductor devices. It is understandable that not only is the thermal resistor 80 bonded to the inner metal foil 12 through a sintering process, but as mentioned earlier, the chip 30 is also bonded to the inner metal foil 12, the chip 30 to the lead frame 40, and the lead frame 40 to the inner metal foil 12 through a sintering process. That is, the sintered layer formed by the sintering process in this paper realizes the electrical and thermal connections between devices. This not only improves the temperature cycle life of power semiconductor devices, enabling them to operate in high-temperature environments exceeding 175°C, but also reduces the thermal resistance of power semiconductor devices, thereby further realizing the miniaturization and lightweighting of power semiconductor devices. This is of great benefit to improving the reliability of power semiconductor devices.

[0051] Typically, chips in power semiconductor devices are divided into chips located in the upper bridge circuit and chips located in the lower bridge circuit. Therefore, in this paper, chip 30 can be divided into two types: upper bridge circuit chip and lower bridge circuit chip. Furthermore, the inner metal foil 12 is not a single, continuous metal foil; it is actually obtained by etching a single continuous metal foil. This results in the inner metal foil 12 being composed of multiple spaced-apart partitions. The purpose of this design is to facilitate the construction of the main and auxiliary circuits of the power semiconductor device, and to facilitate the implementation of functions such as thermal monitoring of the power semiconductor device. Please refer to further reading. Figure 10 and Figure 11 , Figure 10 This is a schematic diagram of the partitioning of the inner metal foil after etching, provided in an embodiment of this application. Figure 11This is a top view of the power semiconductor device provided in an embodiment of this application after the cladding has been removed. In one example, the inner metal foil 12 may have six mutually spaced partitions, namely partition 1, partition 2, partition 3, partition 4, partition 5, and partition 6; six upper bridge circuit chips are included, respectively disposed at six solid pentagram positions in partition 3; six lower bridge circuit chips are included, respectively disposed at six solid pentagram positions in partition 2; twelve lead frames 40 are included, wherein six lead frames 40 are used for electrically connecting the six upper bridge circuit chips to the inner metal foil 12, and the other six lead frames 40 are used for electrically connecting the six lower bridge circuit chips to the inner metal foil 12. The junctions between the corresponding lead frames 40 of the six upper bridge circuit chips and the inner metal foil 12 are located at six solid trapezoidal positions in partition 2, and the junctions between the corresponding lead frames 40 of the six lower bridge circuit chips and the inner metal foil 12 are located at six solid trapezoidal positions in partition 1; the gates of the six upper bridge circuit chips are connected to the inner metal foil 12 via metal interconnects. An auxiliary terminal 70 is provided at each of the six solid triangles in Zone 4 and the two solid circles in Zone 4. The gates of the six lower bridge circuit chips are connected to the inner metal foil 12 via metal connecting wires at the six solid triangles in Zone 5 and the two solid circles in Zone 5 are provided with auxiliary terminals 70. The N terminal is connected to the inner metal foil 12 at the solid rectangle in Zone 1, the two P terminals are connected to the inner metal foil 12 at the two solid rectangles in Zone 3, the first main terminal 50 is connected to the inner metal foil 12 at the solid rectangle in Zone 2, an auxiliary terminal 70 is provided at the solid circle in Zone 3, and an auxiliary terminal 70 is provided at the two solid circles in Zone 6. The thermal resistor 80 is located in Zone 1 near Zone 6 and is electrically connected to the two auxiliary terminals 70 in Zone 6 via metal connecting wires to form an auxiliary circuit for thermal monitoring.

[0052] Please see Figure 12 , Figure 12 This is a schematic flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this application. This application also provides a method for fabricating a power semiconductor device, which includes the following steps 1201 to 1203.

[0053] Step 1201: Place multiple chips on the inner metal foil respectively.

[0054] In the embodiments of this application, when manufacturing power semiconductor devices, it is necessary to first place multiple chips 30 on the inner metal foil 12 in the ceramic substrate 10, and the multiple chips 30 are spaced apart from each other.

[0055] Step 1202: Electrically connect the side of each chip that is not in contact with the inner metal foil to the inner metal foil through a lead frame.

[0056] In this embodiment, after multiple chips 30 are respectively disposed on the inner metal foil 12, the side of each chip 30 that is not in contact with the inner metal foil 12 (i.e. the side opposite to the inner metal foil 12) needs to be electrically connected to the inner metal foil 12 through a lead frame 40 to form the main circuit of the power semiconductor device.

[0057] Step 1203: The ceramic substrate is encapsulated using a molding process.

[0058] In this embodiment, after the main circuit of the power semiconductor device is formed, the ceramic substrate 10 needs to be encapsulated using a molding process. Specifically, after molding, a covering body 20 is formed covering the ceramic substrate 10. The covering body 20 does not completely cover the ceramic substrate 10; that is, only the side of the outer metal foil 13 away from the inner metal foil 12 is exposed to the external space, while the remaining portion of the ceramic substrate 10 is covered. Simultaneously, the chip 30 and the lead frame 40 are both located within the covering body 20. It is understood that conventional power semiconductor devices typically use silicone filling to encapsulate the ceramic substrate. However, this embodiment uses a molding process to encapsulate the ceramic substrate 10. In other words, this embodiment replaces the silicone filling in conventional power semiconductor devices with a molding process. This design can effectively reduce the adverse effects of the thermal stress generated by the lead frame 40 on the bonding strength between it and the inner metal foil 12, thereby further improving the reliability of the power semiconductor device. For example, the ceramic substrate 10 can be encapsulated with epoxy resin, in which case the material of the encapsulation body 20 is epoxy resin.

[0059] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For product-related embodiments, since they are similar to method-related embodiments, the descriptions are relatively simple, and relevant parts can be referred to the descriptions of the method-related embodiments.

[0060] It should also be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] The above description of the disclosed embodiments enables those skilled in the art to implement or use the content of this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this application may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power semiconductor device, comprising a ceramic substrate, said ceramic substrate comprising a ceramic wafer, an inner metal foil, and an outer metal foil; wherein, The inner metal foil is disposed on one side of the ceramic substrate, and the outer metal foil is disposed on the opposite side of the ceramic substrate from the inner metal foil. The power semiconductor device is characterized in that it further includes an enclosure, a plurality of chips, and a plurality of lead frames; wherein the enclosure covers the ceramic substrate and exposes the side of the outer metal foil away from the inner metal foil to the external space, the chips are located inside the enclosure and disposed on the inner metal foil, the plurality of chips are spaced apart from each other, and the side of a single chip that is not in contact with the inner metal foil is electrically connected to the inner metal foil through a lead frame; The lead frame includes a first contact portion on the side of the chip that does not contact the inner metal foil, a second contact portion on the inner metal foil, and a connecting portion connecting the first contact portion and the second contact portion. The connecting portion bends and extends from the end of the first contact portion toward the second contact portion. Grooves are provided on both sides of the first contact portion away from the connecting portion and on one end of the second contact portion away from the connecting portion.

2. The power semiconductor device as described in claim 1, characterized in that, It also includes a first main terminal and a second main terminal; wherein, one end of the first main terminal is disposed in the inner metal foil and the other end protrudes through the cover to be exposed to the external space, one end of the second main terminal is disposed in the inner metal foil and the other end protrudes through the cover to be exposed to the external space, and the first main terminal and the second main terminal are respectively located at opposite ends of the inner metal foil.

3. The power semiconductor device as described in claim 2, characterized in that, Both the first main terminal and the second main terminal include an embedded portion located within the enclosure and disposed on the inner metal foil, an exposed portion exposed to the external space, and a connecting portion connecting the embedded portion and the exposed portion. The connecting portion extends from the end of the embedded portion toward the exposed portion and passes through the enclosure. The side of the embedded portion away from the inner metal foil is lower than the side of the exposed portion near the inner metal foil. The extending directions of the embedded portion and the exposed portion are both parallel to the surface of the ceramic substrate.

4. The power semiconductor device as described in claim 3, characterized in that, The exposed portion of the first main terminal has a circular through hole, and the exposed portion of the second main terminal has an elliptical through hole.

5. The power semiconductor device as described in claim 1, characterized in that, It also includes multiple auxiliary terminals, one end of which is located within the enclosure and disposed on the inner metal foil, and the other end of which extends out of the enclosure and is exposed to the external space. The extension direction of the auxiliary terminal is perpendicular to the surface of the ceramic substrate.

6. The power semiconductor device as described in claim 5, characterized in that, It also includes a thermal resistor located within the enclosure and disposed on the inner metal foil, the thermal resistor being electrically connected to at least one of the auxiliary terminals.

7. A method for fabricating a power semiconductor device, the power semiconductor device comprising a ceramic substrate, said ceramic substrate comprising a ceramic wafer, an inner metal foil, and an outer metal foil; wherein, The inner metal foil is disposed on one side of the ceramic substrate, and the outer metal foil is disposed on the opposite side of the ceramic substrate from the inner metal foil. The power semiconductor device is characterized in that it further includes an cladding, multiple chips, and multiple lead frames; the method for fabricating the power semiconductor device includes: The plurality of chips are respectively disposed on the inner metal foil; wherein the plurality of chips are spaced apart from each other; The side of each chip that is not in contact with the inner metal foil is electrically connected to the inner metal foil through a lead frame. The ceramic substrate is encapsulated using a molding process; wherein, after molding, an encapsulation body is formed covering the ceramic substrate, and the side of the outer metal foil away from the inner metal foil is exposed to the external space, and the chip and the lead frame are both located within the encapsulation body; The lead frame includes a first contact portion on the side of the chip that does not contact the inner metal foil, a second contact portion on the inner metal foil, and a connecting portion connecting the first contact portion and the second contact portion. The connecting portion bends and extends from the end of the first contact portion toward the second contact portion. Grooves are provided on both sides of the first contact portion away from the connecting portion and on one end of the second contact portion away from the connecting portion.

8. The application of a power semiconductor device as described in any one of claims 1-6 in power electronic equipment.

9. The application of a power semiconductor device manufactured by the method of manufacturing a power semiconductor device as described in claim 7 in power electronic equipment.

Images