Message transmission method, device and equipment, and storage medium

Abstract

The application discloses a message transmission method and device, equipment and storage medium, and relates to the technical field of communication. The method comprises the following steps: in response to the failure or nonexistence of a second slave port of a network device, a second master port of the network device acquires a second data set, the second data set being obtained by modifying a first data set, the first data set comprising a timestamp carried by a first clock message received by a first slave port and data generated by the first slave port according to the first clock message; and the network device sends a second clock message through the second master port according to the second data set, the timestamp carried by the second clock message being the timestamp carried by the first clock message. The method enables the network device to still send a clock message carrying accurate time through a master port when a slave port of a certain clock domain in the network device fails or does not exist, thereby improving the reliability of a communication system.

Description

[0001] This application claims priority to the Chinese Patent Application No. 202110518908.1, filed on May 12, 2021, and entitled "A Clock Data Transmission Method", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular to a message transmission method and device, equipment and a storage medium. BACKGROUND

[0003] The institute of electrical and electronics engineers (IEEE) 1588 protocol standard defines a set of message-based synchronization protocols in the technical specification, through periodic sending of messages with time stamps, the time of each node in the network is corrected, so as to realize the time synchronization of the whole network. Among them, the IEEE 1588 protocol standard is called precision time protocol (PTP) for short, which is the precision clock synchronization protocol standard for network measurement and control system.

[0004] For IEEE 802.1AS-2020 application standard defined based on IEEE 1588 protocol standard (IEEE 802.1AS-2020 is called generalized precision time protocol (gPTP)), IEEE 802.1AS-2020 defines that each device can support multiple 1588 entities, and each entity is distinguished by different domains. The following is called multi-domain 1588 entity for the device supporting multiple 1588 entities, multi-domain entity, multi-domain 1588 device or multi-domain device. Each entity can support boundary clock (BC) or grand master clock (GM). Each BC entity includes a slave port and at least one master port, each GM entity includes at least one master port, and the processing of 1588 messages between BC entities or GM entities of different domains is independent of each other.

[0005] Currently, the IEEE 802.1AS-2020 protocol standard has been applied to the time sensitive networking (TSN) industrial field and the TSN vehicle field. Considering the high reliability requirement of the industrial field and the vehicle field, it is particularly important to realize that even if a slave port corresponding to a 1588 entity in multiple entities is lost, the 1588 entity can still continue to send 1588 packets carrying accurate time from a master port corresponding to the 1588 entity. SUMMARY

[0006] The present application provides a message transmission method, device, equipment and storage medium, so that when the slave port of a certain clock domain of the network device is invalid or does not exist, the network device can still send clock messages carrying accurate time through the master port.

[0007] In a first aspect, a message transmission method is provided, which includes: in response to a second slave port of a network device being invalid or not existing, a second master port of the network device acquires a second data set, the second data set being modified based on a first data set, the first data set including a timestamp carried by a first clock message received by a first slave port and data generated by the first slave port according to the first clock message, the first slave port belonging to a first clock domain, the second master port belonging to a second clock domain, the first clock domain being different from the second clock domain; and the network device sends a second clock message through the second master port according to the second data set, the timestamp carried by the second clock message being the timestamp carried by the first clock message, the first clock message and the second clock message including a synchronization (sync) message or a follow-up (follow_up) message in a precise time protocol (PTP).

[0008] The timestamp is an origin timestamp (originTimestamp) in the sync message or a precise origin timestamp (preciseOriginTimestamp) in the follow_up message. The precise time protocol refers to a precise time protocol (PTP) defined by IEEE 1588 or a generalized precise time protocol (gPTP) defined by IEEE 802.1AS.

[0009] Since the network device can modify the second data set based on the first data set and send the second clock message through the second master port based on the second data set, when the second slave port of the network device is invalid or does not exist, the network device can still maintain sending the second clock message carrying accurate time through the second master port, so as to ensure that the second clock domain continues to deliver accurate time, thereby improving the reliability of the communication system.

[0010] In a possible implementation, the second master port of the network device acquires the second data set, including: the second master port receiving the first data set, modifying the first data set according to information of the second clock domain to obtain the second data set. The network device receives and modifies the first data set through the second master port to obtain the data set belonging to the second clock domain.

[0011] In a possible implementation, the second master port and the first slave port include an IWF module, and the IWF module is configured to modify the first data set according to information of the second clock domain to obtain the second data set; the second master port of the network device acquires the second data set, including: the second master port receiving the second data set sent by the IWF module. The network device adds the IWF module, the IWF module can be implemented by software without additional hardware support, the first data set is received and modified by the IWF module to obtain the data set belonging to the second clock domain, and the reliability and flexibility of message transmission are improved.

[0012] In a possible implementation, the first data set includes a domain name domainNumber; and the modifying the first data set according to information of the second clock domain includes: modifying the value of domainNumber to a domain name of the second clock domain of the network device. Since the first data set is obtained through the first slave port of the first clock domain, the domain name in the first data set is the domain name of the first clock domain, and the domain name of the first clock domain in the first data set is modified to the domain name of the second clock domain, so the second data set is obtained.

[0013] In a possible implementation, the first data set includes a domain name domainNumber, a local port number localPortNumber, a synchronization receipt time syncReceiptTimeoutTime, a source port identity sourcePortIdentity and a log message interval logMessageInterval; and the modifying the first data set according to information of the second clock domain includes: modifying the value of domainNumber to a domain name of the second clock domain of the network device, modifying the value of localPortNumber to a first value, modifying the value of syncReceiptTimeoutTime to a second value, modifying the clock identity clockIdentity in sourcePortIdentity to the clockIdentity of the second clock domain, modifying the port number portnumber in sourcePortIdentity to a third value, and modifying logMessageInterval to a time interval at which the clock master of the second clock domain sends a message.

[0014] In a possible implementation, the network device comprises a second switch; and the second master port of the network device acquires the second data set in response to the second slave port being invalid or not existing, comprising: in response to the second slave port being invalid or not existing, the second master port of the network device acquires the second data set based on the control of the second switch according to the first data set corresponding to the first slave port.

[0015] In a possible implementation, the network device comprises a second switch; and the method further comprises: in response to the second slave port existing and being valid, the second slave port belonging to a second clock domain, the second master port of the network device sends a third clock packet according to a third data set corresponding to the second slave port based on the control of the second switch, the third clock packet comprising a sync packet or a follow_up packet in the precision time protocol.

[0016] The network device comprises the second switch capable of controlling the manner in which the second master port acquires the second data set, and if the network device has the second slave port belonging to the second clock domain, when the second slave port exists and is valid, the second master port receives the data set from the second slave port based on the control of the second switch, and when the second slave port is invalid or does not exist, the second master port receives the data set from the first slave port based on the control of the second switch, so that the second master port can acquire the second data set in any case.

[0017] In a possible implementation, the network device further comprises a first switch, and the first master port belongs to a first clock domain; and the method further comprises: in response to the first slave port existing and being valid, the first master port of the network device sends a fourth clock packet according to a first data set corresponding to the first slave port based on the control of the first switch, the fourth clock packet comprising a sync packet or a follow_up packet in the precision time protocol; and in response to the first slave port being invalid or not existing, and the second slave port existing and being valid, the first master port of the network device sends a fifth clock packet according to a third data set corresponding to the second slave port based on the control of the first switch, the fifth clock packet comprising a sync packet or a follow_up packet in the precision time protocol.

[0018] When the network device has the first master port and the second master port, the first master port and the second master port send the clock packet in the manner controlled by the first switch and the second switch, so that the first master port and the second master port can send the clock packet carrying the precision time regardless of whether the first slave port is invalid or does not exist or whether the second slave port is invalid or does not exist.

[0019] In a possible implementation, before the second master port of the network device acquires the second data set, the method further includes: receiving, by the first slave port of the network device, a first clock packet sent by a third master port, the third master port being a master port corresponding to a first clock domain of the clock source device of the network device; acquiring data generated according to the first clock packet based on the received first clock packet; and generating the first data set based on a timestamp carried in the first clock packet and the data generated according to the first clock packet.

[0020] In a second aspect, a packet transmission apparatus is provided, and the apparatus includes:

[0021] The first acquiring module is configured to acquire, in response to failure or nonexistence of the second slave port of the network device, a second data set by the second master port of the network device, the second data set being obtained by modifying a first data set, the first data set including a timestamp carried in a first clock packet received by the first slave port and data generated according to the first clock packet by the first slave port, the first slave port belonging to a first clock domain, the second master port belonging to a second clock domain, and the first clock domain being different from the second clock domain.

[0022] The sending module is configured to send, by the network device, a second clock packet through the second master port according to the second data set, the timestamp carried in the second clock packet being the timestamp carried in the first clock packet, and the first clock packet and the second clock packet including a sync packet or a follow_up packet in a precision time protocol.

[0023] The timestamp is an originTimestamp in the sync packet or a preciseOriginTimestamp in the follow_up packet.

[0024] In a possible implementation, the first acquiring module is configured to receive, by the second master port, the first data set, and modify the first data set according to information of the second clock domain to obtain the second data set.

[0025] In a possible implementation, the second master port and the first slave port include an IWF module, the IWF module being configured to modify the first data set according to information of the second clock domain to obtain the second data set, and the first acquiring module is configured to receive, by the second master port, the second data set sent by the IWF module.

[0026] In a possible implementation, the first data set includes a domain name domainNumber, and the first acquiring module is further configured to modify the value of the domainNumber to be the domain name of the second clock domain of the network device.

[0027] In a possible implementation, the first data set comprises a domain name domainNumber, a local port number localPortNumber, a synchronization receipt time syncReceiptTimeoutTime, a source port identity sourcePortIdentity, and a log message interval logMessageInterval; the first obtaining module is further configured to modify the value of the domainNumber to a domain name of a second clock domain of the network device, modify the value of the localPortNumber to a first value, modify the value of the syncReceiptTimeoutTime to a second value, modify a clock identity clockIdentity in the sourcePortIdentity to a clockIdentity of the second clock domain, modify a port number portNumber in the sourcePortIdentity to a third value, and modify the logMessageInterval to a time interval at which the clock master of the second clock domain sends a message.

[0028] In a possible implementation, the network device comprises a second switch; the first obtaining module is configured to, in response to the second slave port being invalid or not existing, obtain, by the second master port of the network device, a second data set based on a first data set corresponding to the first slave port, based on control of the second switch.

[0029] In a possible implementation, the network device comprises a second switch, and the second slave port belongs to a second clock domain; the apparatus further comprises:

[0030] The first control module is configured to, in response to the second slave port existing and being valid, send, by the second master port of the network device, a third clock message based on a third data set corresponding to the second slave port, based on control of the second switch, the third clock message comprising a sync message or a follow_up message in the precision time protocol.

[0031] In a possible implementation, the network device further comprises a first switch, and the first master port belongs to a first clock domain; the apparatus further comprises:

[0032] The second control module is configured to, in response to the first slave port existing and being valid, send, by the first master port of the network device, a fourth clock message based on a first data set corresponding to the first slave port, based on control of the first switch, the fourth clock message comprising a sync message or a follow_up message in the precision time protocol.

[0033] The third control module is configured to, in response to the first slave port being invalid or not existing, the second slave port existing and being valid, and the first master port of the network device being controlled based on the first switch, transmit a fifth clock message according to a third data set corresponding to the second slave port based on the first master port, the fifth clock message comprising a sync message or a follow_up message in the precision time protocol.

[0034] In a possible implementation, the apparatus further includes:

[0035] The receiving module is configured to receive, by the first slave port of the network device, a first clock message transmitted by a third master port, the third master port being a master port corresponding to a first clock domain of a clock source device of the network device.

[0036] The second obtaining module is configured to obtain, based on the received first clock message, data generated according to the first clock message.

[0037] The generating module is configured to generate a first data set based on a timestamp carried by the first clock message and the data generated according to the first clock message.

[0038] In a third aspect, a network device is provided, which includes a processor coupled with a memory, and the memory stores at least one program instruction or code, which is loaded and executed by the processor to enable the network device to implement the message transmission method according to any one of the preceding aspects.

[0039] As an exemplary embodiment, the processor is one or more, and the memory is one or more.

[0040] As an exemplary embodiment, the memory can be integrated with the processor, or the memory and the processor are separately arranged.

[0041] In the implementation process, the memory can be a non-transitory memory, for example, a read only memory (ROM), which can be integrated on the same chip with the processor, or can be separately arranged on different chips, and the type of the memory and the arrangement manner of the memory and the processor are not limited in the embodiments of the present application.

[0042] In a fourth aspect, a communication apparatus is provided, which comprises a transceiver, a memory and a processor. The transceiver, the memory and the processor are in communication with each other through internal connection paths. The memory is configured to store instructions, and the processor is configured to execute the instructions stored in the memory to control the transceiver to receive a signal and control the transceiver to send a signal. When the processor executes the instructions stored in the memory, the communication apparatus performs the method in the first aspect or any possible implementation manner of the first aspect.

[0043] In a fifth aspect, a computer readable storage medium is provided, which stores at least one instruction. The instruction is loaded and executed by a processor to enable a computer to implement the packet transmission method according to any one of the above aspects.

[0044] In a sixth aspect, a computer program (product) is provided, which comprises computer program code. When the computer program code is run on a computer, the computer program code enables the computer to perform the method in the above aspects.

[0045] In a seventh aspect, a chip is provided, which comprises a processor configured to call and run instructions stored in a memory to enable a communication device in which the chip is installed to perform the method in the above aspects.

[0046] In an eighth aspect, another chip is provided, which comprises an input interface, an output interface, a processor and a memory. The input interface, the output interface, the processor and the memory are connected through internal connection paths. The processor is configured to execute code in the memory. When the code is executed, the processor is configured to perform the method in the above aspects.

[0047] It should be understood that the beneficial effects achieved by the second aspect of the embodiments of the present application and the corresponding possible implementation manners can be referred to the technical effects of the first aspect and the corresponding possible implementation manners described above, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 A structure diagram of a PTP packet header provided by the embodiments of the present application is shown in the figure;

[0049] Figure 2 A structure diagram of a sync packet in a one-step mode provided by the embodiments of the present application is shown in the figure;

[0050] Figure 3 A structure diagram of a sync packet in a two-step mode provided by the embodiments of the present application is shown in the figure;

[0051] Figure 4A follow_up packet structure diagram provided by an embodiment of the present application;

[0052] Figure 5 A Follow_Up information TLV field structure diagram provided by an embodiment of the present application;

[0053] Figure 6 A network device structure diagram provided by an embodiment of the present application;

[0054] Figure 7 A network device structure diagram provided by an embodiment of the present application;

[0055] Figure 8 A message transmission method flowchart provided by an embodiment of the present application;

[0056] Figure 9 A network device structure diagram provided by an embodiment of the present application;

[0057] Figure 10 A network device structure diagram provided by an embodiment of the present application;

[0058] Figure 11 A network device structure diagram provided by an embodiment of the present application;

[0059] Figure 12 A message transmission device structure diagram provided by an embodiment of the present application;

[0060] Figure 13 A message transmission device structure diagram provided by an embodiment of the present application;

[0061] Figure 14 A message transmission device structure diagram provided by an embodiment of the present application;

[0062] Figure 15 A message transmission device structure diagram provided by an embodiment of the present application;

[0063] Figure 16 A network device structure diagram provided by an embodiment of the present application;

[0064] Figure 17 A network device structure diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0066] The IEEE 1588 protocol standard supports synchronization of a local clock (also referred to as a slave clock) of a device (also referred to as a slave device) with a clock or time of a root grand master (GM) clock device, so as to enable a distributed communication network to have strict timing synchronization. In the application process, the IEEE 1588 protocol defines a set of message-based synchronization protocols in the technical specification, through periodic publication of messages with timestamps, so that the clocks or times of various nodes in the network are corrected, so as to realize synchronous operation of the entire system. For example, the clocks in sensors, actuators and terminal devices in a standard Ethernet or other distributed bus system using multicast technology are synchronized at the sub-microsecond level.

[0067] For the IEEE 802.1AS-2020 application standard defined based on the IEEE 1588 protocol standard, it is mainly used in the TSN industrial field and the TSN vehicle field, etc. The various PTP messages defined by IEEE 802.1AS-2020 include a PTP message header. For example, the structure of the PTP message header is as shown in FIG. 1. The PTP message header includes a major SDO ID field, a message type field, a PTP minor version field, a PTP version field, a message length field, a domain number field, a minor SDO ID field, a flag field, a correction field, a message type specific field, a source port identity field, a sequence ID field, a control field and a log message interval field. The various fields of the PTP message header are introduced as follows. Figure 1

[0068] ​Message type (messageType): Different values represent different types of PTP messages. versionPTP and minorVersionPTP represent the version number of the 1588 protocol. If versionPTP is 1 and minorVersionPTP is 0, it means that the 1588 message conforms to the IEEE 1588v1 protocol (IEEE 1588-2002); if versionPTP is 2 and minorVersionPTP is 0, it means that the 1588 message conforms to the IEEE 1588v2 protocol (IEEE 1588-2008); if versionPTP is 2 and minorVersionPTP is 10, it means that the 1588 message conforms to the IEEE 1588v2.1 protocol (IEEE 1588-2019). PTP domain sequence number (domainNumber): The value of this PTP domain sequence number (domainNumber) field is the variable defaultDS.domainNumber. Flags (flags): Carrying various flags. Correction field (correctionField): Transmitting the residence time, link delay, or link asymmetric delay of the 1588 message, etc. Source port identification (sourcePortIdentity): The identification of the sending port. Sequence number (sequence Id): In order to distinguish multiple messages of the same type sent by a sending port. Control field (controlField): It can be filled as 0, or determined by the value of the message type field, that is, the value is different according to the different message types. Log message interval (logMessageInterval): Carrying the logarithmic time interval of sending messages, their values are the logarithm with base 2.

[0069] Among them, the IEEE 802.1AS-2020 standard defines that the sync message is sent by the Master port of the GM clock device. If the Master port is a one-step mode clock, see Figure 2 , the format of the sync message includes the header field, the origin timestamp field, and the Follow_Up information type-length-value (TLV) field. Among them, Figure 2 The structure diagram of the header field in Figure 1, the originTimestamp field is defined as a value of 0 or the time when the Master port sends the sync packet, at this time, the timestamp of the sync packet is carried in the originTimestamp of the sync packet, and a structure diagram of the Follow_Up information TLV field can be seen from Figure 5 . If the Master port is a clock in a two-step mode, see Figure 3 , the format of the sync packet includes a header field and an originTimestamp field. Among them, Figure 3 , a structure diagram of the header field in the Figure 1 , in the two-step mode, the originTimestamp information of the sync packet is 0, and the actual timestamp information is carried in the preciseOriginTimestamp of the follow_up packet associated with the sync packet. See Figure 4 , the format of the follow_up packet includes a header field, a preciseOriginTimestamp, and a Follow_Up information TLV field.

[0070] Among them, Figure 4 , a structure diagram of the header field in the Figure 1 , a structure diagram of the Follow_Up information TLV field is shown in Figure 5 , the Follow_Up information TLV field includes a tlvType field, a lengthField field, an organizationID field, an organizationSubType field, a cumulativeScaledRateOffset field, a gmTimeBaseIndicator field, a lastGMPhaseChange field, and a scaledLastGMFreqChange field. The various fields included in the Follow_Up information TLV field are introduced as follows.

[0071] The value of the TLV type (tlvType) field is 0x3, which indicates that the TLV is a vendor and standards organization extension TLV. The value of the length field (lengthField) is 28, the organization identification (organizationID) field is 00-80-C2, and the value of the organization subtype (organizationSubType) field is 1. The cumulative scaled rate offset (cumulativeScaledRateOffset) field is the value of the cumulativeScaledRateOffset. The grand master time base indicator (gmTimeBaseIndicator) field is the value of the timeBaseIndicator of the lockSource entity of the current Grandmaster PTP instance (see the content of section 9.2.2.3 of the IEEE 802.1AS-2020 protocol). The value of the last grand master phase change (lastGMPhaseChange) field is the time of the current grand master clock minus the time of the last grand master clock, which is copied from the lastGmPhaseChange field of the Sync message structure. The value of the scaled last grand master frequency change (scaledLastGMFreqChange) field is the fractional frequency offset of the current grand master clock relative to the last grand master clock.

[0072] In the IEEE 802.1AS-2020 protocol standard, a device can support multiple 1588 entities, each of which corresponds to a different clock domain (domain for short), and each entity can be a BC entity or a GM entity. Each BC entity includes a slave port and at least one master port, each GM entity includes at least one master port, and the processing of clock messages in different domains is independent of each other.

[0073] For example, the network device includes entity 1 and entity 2, both of which are BC entities. Referring to Figure 6, the clock domain corresponding to entity 1 is domain 1, and the clock domain corresponding to entity 2 is domain 2. The slave 1 port receives the clock message of domain 1 sent by the clock source device corresponding to entity 1 of the device, and the slave 1 port obtains the clock data set based on receiving the clock message, the clock data set including the data carried by the clock message and the data generated when the slave 1 port receives the clock message. Entity 1 transmits the clock data set obtained by the slave 1 port to the master 1 port, the master 1 port updates the clock data set based on sending the clock message, and the master 1 port sends the clock message of domain 1 to the downstream device according to the updated clock data set. The slave 2 port receives the clock message of domain 2 sent by the clock source device corresponding to entity 2 of the device, and the slave 2 port obtains the clock data set based on receiving the clock message. The clock data set includes the data carried by the clock message and the data generated when the slave 2 port receives the clock message, and entity 2 transmits the clock data set obtained by the slave 2 port to the master 2 port. The master 2 port updates the clock data set based on sending the clock message, and the master 2 port sends the clock message of domain 2 to the downstream device according to the updated clock data set.

[0074] With the increasing application of IEEE 802.1AS-2020 protocol standard in the TSN industrial field and the TSN vehicle field, the high reliability requirement for clock synchronization of 1588 messages is higher and higher. Based on IEEE 802.1AS-2020, IEEE standard is studying to develop a 1588 multi-domain hot backup scheme, which needs to use the functions of the slave clock module (ClockSlave) and the master clock module (ClockMaster) modules. Among them, the ClockSlave module is used to restore the time of the clock source corresponding to entity 1 according to the information of the slave port, and the ClockMaster module is used to synchronize the time of the ClockSlave module.

[0075] Referring to Figure 7When the slave2 port of the domain2 corresponding to the entity 2 is invalid or does not exist, the ClockSlave module of the entity 1 recovers the time of the time source corresponding to the entity 1 according to the information of the slave1 port, and the device transmits the time of the time source recovered by the ClockSlave module of the entity 1 to the ClockMaster module of the entity 2. The ClockMaster module of the entity 2 can obtain information from the ClockSlave module of the entity 1, and then the time of the ClockMaster module of the entity 2 is synchronized to the time of the ClockSlave module of the entity 1, so that the master2 port can continue to send the 1588 message of the entity 2 based on the time of the ClockMaster module. Thus, the timestamp carried by the 1588 message of the entity 2 is synchronized to the time recovered by the ClockSlave module of the entity 1, and the 1588 message sent by the master2 port can carry accurate time.

[0076] However, the above-mentioned Figure 7 The method shown in the figure needs the ClockSlave module to recover the time of the time source according to the slave1 port and synchronize to the ClockMaster module, so that the master2 port can send the clock message based on the time of the time source recovered by the ClockSlave module synchronized by the ClockMaster module. That is, the timestamp carried by the clock message sent by the master2 port is the time recovered by the ClockSlave module according to the slave1 port, rather than the timestamp carried by the clock message received by the slave1 port. For example, the timestamp carried by the clock message received by the slave1 port is 2021-01-01 0:0:0, and due to the transmission delay of 1 second between the ClockSlave module and the slave1 port, the time of the time source recovered by the ClockSlave module according to the slave1 port is 2021-01-01 0:0:1, and the ClockMaster module synchronizes the above-mentioned time 2021-01-01 0:0:1 and sends it to the master2 port, so that the timestamp carried by the clock message sent by the master2 port is 2021-01-01 0:0:1, rather than 2021-01-01 0:0:0.

[0077] And, referring to the IEEE 802.1AS-2020 standard requirement, the ClockMaster module is an optional requirement, that is, some devices do not have the ClockMaster module, so the above multi-domain hot backup method cannot be used for these devices. In addition, the ClockSlave time after slave port synchronization needs to be used as the ClockMaster time sent by the master port of another domain, and the ClockSlave module requires the device to support the time recovery function, that is, the ClockSlave module and the ClockMaster module also need to be implemented with the help of additional hardware devices, for example, a hardware module supporting clock phase-locked loop function, and the implementation process is complex.

[0078] To this end, the embodiments of the present application provide a packet transmission method to implement the multi-domain hot backup function of a network device in a simple manner. The method can be applied to a communication system including a plurality of network devices, the plurality of network devices at least including a GM device and a BC device, and each of the plurality of network devices being capable of supporting the transmission of clock packets of multiple clock domains at the same time. Exemplarily, the embodiments of the present application take any one of the plurality of network devices as an example to describe the packet transmission method provided by the embodiments of the present application. Referring to Figure 8 The method includes the following steps 801 and 802.

[0079] Step 801, in response to the failure or nonexistence of the second slave port of the network device, the second master port of the network device acquires a second data set, the second data set being obtained by modifying a first data set, the first data set including a timestamp carried by a first clock packet received by a first slave port and data generated by the first slave port according to the first clock packet, the first slave port belonging to a first clock domain, the second master port belonging to a second clock domain, and the first clock domain being different from the second clock domain.

[0080] In a possible implementation, the network device supports a plurality of entities, each entity being implemented as a BC or a GM, wherein each BC entity includes a slave port and at least one master port, each GM entity includes at least one master port, and the processing of clock packets between each BC entity or GM entity is independent of each other.

[0081] The second slave port of the network device can be a slave port corresponding to a certain BC entity included in the network device. The second slave port being invalid or not existing means that the second slave port of a certain BC entity of the network device is invalid or lost, or a slave port of a certain GM entity of the network device does not exist. The second master port of the network device can be a master port corresponding to a certain BC entity included in the network device, or a master port corresponding to a certain GM entity of the network device. The second master port belongs to a second clock domain. The first slave port of the network device can be a slave port of another certain BC entity of the network device. The first slave port exists and is valid, that is, the first slave port can normally process clock messages at this time. The first slave port belongs to a first clock domain. The first clock domain and the second clock domain are two different clock domains.

[0082] Exemplarily, taking that the network device includes two BC entities as an example, the first slave port and the first master port of the first BC entity belong to the first clock domain, and the second slave port and the second master port of the second BC entity belong to the second clock domain. Exemplarily, in the IEEE 802.1AS-2020 protocol standard, each clock domain supported by the network device is called an entity, that is, the first clock domain is called entity 1, and the second clock domain is called entity 2. In the embodiment of the application, entity 1 and entity 2 support the BC function, also called BC entity 1 and BC entity 2. The first slave port corresponding to the BC entity 1 is called slave1 port, the first master port corresponding to the BC entity 1 is called master1 port, the second slave port corresponding to the BC entity 2 is called slave2 port, and the second master port corresponding to the BC entity 2 is called master2 port.

[0083] In a possible implementation, the second master port of the BC entity 2 can also form a fusion BC entity with the first slave port of the BC entity 1. The fusion BC entity is different from the BC entity defined in the IEEE 802.1AS-2020 standard. The standard BC entity is limited to processing clock data and other functions within the same entity, wherein the clock data includes but is not limited to timestamp information. The fusion BC entity allows processing clock data and other functions between the fused different clock domains. For example, the fusion BC entity formed by the second master port of the BC entity 2 and the first slave port of the BC entity 1 allows the second master port to receive clock data originating from the first slave port.

[0084] In a possible implementation, the first data set includes a timestamp and related data carried by the first clock message received by the first slave port of the network device and data generated by the first slave port according to the received first clock message. In the embodiment of the application, the first clock message includes a sync message in the precision time protocol. Alternatively, in the two-step mode, the first clock message also includes a follow_up message. The precision time protocol includes the PTP protocol defined by IEEE 1588 or the gPTP defined by IEEE 802.1AS.

[0085] The embodiment of the application does not limit the acquisition manner of the first data set. In a possible implementation, before the second master port of the network device acquires the second data set, the method further includes: receiving, by the first slave port of the network device, a first clock message sent by a third master port, the third master port being a master port corresponding to the first clock domain of the clock source device of the network device; acquiring data generated according to the first clock message based on the received first clock message; and generating the first data set based on the timestamp carried by the first clock message and the data generated according to the first clock message.

[0086] In the embodiment of the application, the first slave port of the network device can receive a first clock message sent by a master port corresponding to the first clock domain, the first clock message carrying a timestamp of the clock source device, and the first slave port can generate corresponding data according to the received first clock message, for example, a reception timestamp of the first clock message or time delay information between the first slave port and the third master port. Therefore, the first slave port can generate the first data set carrying the clock data of the first clock domain based on the timestamp of the clock source device carried by the first clock message and the data generated according to the first clock message.

[0087] In a possible implementation, taking the sync message as an example, the first data set generated according to the sync message is called a portSyncSync data set in the IEEE 802.1AS-2020 protocol standard, and the members include: domainNumber, localPortNumber, syncReceiptTimeoutTime, followUpCorrectionField, sourcePortIdentity, logMessageInterval, preciseOriginTimestamp, upstreamTxTime, rateRatio, gmTimeBaseIndicator, lastGmPhaseChange and lastGmFreqChange.

[0088] For one-step mode, the first slave port will only receive sync messages, according to Figure 1 the structure of PTP message header as shown in Table 1, Figure 2 the structure of sync message as shown in Table 2, and Figure 5 the structure of Follow_Up information TLV field as shown in Table 3, it can be seen that the timestamp carried by the sync message received by the first slave port of the network device is originTimestamp, and the data carried by the sync message received by the first slave port of the network device includes: domainNumber, sourcePortIdentity, logMessageInterval, correctionField, cumulativeScaledRateOffset, gmTimeBaseIndicator, lastGmPhaseChange and scaledLastGmFreqChange. The domainNumber, followUpCorrectionField, sourcePortIdentity, logMessageInterval, preciseOriginTimestamp, gmTimeBaseIndicator, lastGmPhaseChange and lastGmFreqChange in the portSyncSync dataset generated by the first slave port are respectively derived from the domainNumber, correctionField, sourcePortIdentity, logMessageInterval, originTimestamp, gmTimeBaseIndicator, lastGmPhaseChange and scaledLastGmFreqChange of the sync message.

[0089] The localPortNumber in the portSyncSync dataset generated by the first slave port is the PTP port number of the first slave port. The rateRatio in the portSyncSync dataset generated by the first slave port is the cumulativeScaledRateOffset in the sync message plus the neighborRateRatio generated by the first slave port, and the neighborRateRatio is calculated according to the timestamps carried in the pdelay_req message, the pdelay_resp message and the pdelay_resp_follow_up message exchanged between the first slave port and the upstream port. The neighborRateRatio represents the frequency offset between the network device and the upstream device, the cumulativeScaledRateOffset represents the frequency offset between the upstream device of the network device and the GM clock device, and the rateRatio represents the frequency offset between the network device and the GM clock device.

[0090] The upstreamTxTime in the portSyncSync dataset generated by the first slave port needs to be obtained by the first slave port according to the received sync message. In a possible implementation, taking the first clock message as the sync message, the process of obtaining the data generated according to the sync message by the first slave port is described as follows. First, the first slave port obtains the ingress timestamp corresponding to the local clock when the network device receives the sync message, which is marked as Ta; upstreamTxTime = Ta - meanPathDelay / neighborRateRatio. The meanPathDelay is the fiber delay between the first slave port and the third master port of the upstream device, and the meanPathDelay is calculated according to the timestamp information carried in the pdelay_req message, the pdelay_resp message and the pdelay_resp_follow_up message.

[0091] For the two-step mode, the first slave port receives the sync message and the follow_up message, and according to the structure of the follow_up message shown in FIG. 2 and the structure of the sync message shown in FIG. 1, the first slave port can obtain the upstreamTxTime according to the following formula: Figure 4 Figure 5 ​As shown in the structure of the Follow_Up information TLV field, the data carried by the follow_up message received by the first slave port of the network device includes: domainNumber, sourcePortIdentity, logMessageInterval, followUpCorrectionField, preciseOriginTimestamp, cumulativeScaledRateOffset, gmTimeBaseIndicator, lastGmPhaseChange and scaledLastGmFreqChange. The domainNumber, followUpCorrectionField, sourcePortIdentity, logMessageInterval, preciseOriginTimestamp, gmTimeBaseIndicator, lastGmPhaseChange and lastGmFreqChange in the portSyncSync dataset generated by the first slave port are respectively derived from the domainNumber, followUpCorrectionField, sourcePortIdentity, logMessageInterval, preciseOriginTimestamp, gmTimeBaseIndicator, lastGmPhaseChange and scaledLastGmFreqChange of the follow_up message. The localPortNumber, rateRatio and upstreamTxTime in the portSyncSync dataset generated by the first slave port refer to the generation mode of the one-step.

[0092] In a possible implementation, since the first dataset is obtained by the first slave port according to the clock message of the first clock domain, the information included in the first dataset is the information of the first clock domain, and the first dataset needs to be modified according to the information of the second clock domain to obtain the second dataset including the information of the second clock domain, so that the second master port can send the clock message of the second clock domain based on the second dataset.

[0093] In a possible implementation, the second master port of the network device acquires the second data set, including: the second master port receiving the first data set, modifying the first data set according to information of the second clock domain to obtain the second data set. In this implementation, the second entity corresponding to the second clock domain or the second master port of the second entity corresponding to the second clock domain has the function of modifying the first data set.

[0094] In a possible implementation, the second master port of the network device acquires the second data set, including: the second entity receiving the first data set; the second entity modifying the first data set according to information of the second clock domain to obtain the second data set; and the second master port receiving the second data set sent by the second entity. In this implementation, the second entity has the function of modifying the first data set, and the second master port directly receives the second data set obtained by the second entity modifying the first data set.

[0095] In the embodiments of the present application, the network device can further include an interworking functionality (IWF) module, which has the function of transforming states or protocols into consistent network or user services, and can hide the differences in physical links and network technologies. That is, the IWF module is a network functional entity that can provide interconnection, and the IWF module can be part of one or more logical or physical entities in the network, and the entity refers to any independently viewable component, device, functional unit, device, subsystem or system, etc. The IWF module can be implemented only by software code.

[0096] In a possible implementation, the second master port and the first slave port include an IWF module; the second master port of the network device acquires the second data set, including: the second master port receiving the second data set sent by the IWF module. The IWF module is configured to modify the first data set according to information of the second clock domain to obtain the second data set.

[0097] In a possible implementation, the IWF module can be part of the second master port, part of the first slave port, or part of the network device. When the IWF module is part of the network device, the IWF module can also be configured to modify a data set generated by the second slave port according to parameters of the first clock domain when the first slave port fails or is lost, and the data set includes data carried by a clock message received by the second slave port and data generated by the second slave port according to the clock message.

[0098] Exemplarily, refer to Figure 9The structure diagram of the network device is shown. The IWF module is represented by IWF2 module, and at this time, the slave2 port does not exist or is lost in the domain2. The slave1 port sends the clock data set of the domain1, i.e., the first data set, to the IWF2 module, and the IWF2 module correspondingly modifies the clock data set of the domain1 into the clock data set of the domain2, i.e., the second data set. Then, the IWF2 module sends the second data set of the domain2 to the master2 port, so that the master2 port can continue to generate and send the clock message of the domain2 based on the second data set of the domain1, and the purpose of continuing to maintain the transmission of the clock message of the domain2 by the master2 port is achieved in the case that the slave2 port does not exist or is lost, and the clock message sent by the master2 port also carries accurate time.

[0099] In a possible implementation, modifying the first data set according to the information of the second clock domain includes the following two ways. Way one: only the value of the domainNumber is modified to be the domain name of the second clock domain of the network device, and the values of other parameters in the first data set do not need to be modified. Way two: the value of the domainNumber is modified to be the domain name of the second clock domain of the network device; the value of the localPortNumber is modified to be a first value; the value of the syncReceiptTimeoutTime is modified to be a second value; the clock identity clockIdentity in the sourcePortIdentity is modified to be the clockIdentity of the second clock domain of the network device, and the port number portnumber in the sourcePortIdentity is modified to be a third value; the logMessageInterval is modified to be the time interval of the clockMaster of the second clock domain sending the message; the values of the gmTimeBaseIndicator, the lastGmPhaseChange and the lastGmFreqChange do not need to be modified. The first value, the second value and the third value can be flexibly set according to requirements.

[0100] Exemplarily, taking the first clock message as the sync message as an example, modifying the first data set according to the information of the second clock domain includes the following two cases.

[0101] Case one: when the slave2 port is lost or does not exist, the network device acts as the BC entity of the second clock domain.

[0102] In this case, the first data set is modified according to the information of the second clock domain, including: the value of domainNumber is modified to the domain name of the second clock domain of the network device, for example, the domain name of the second clock domain of the network device is domain2, and the values of other parameters in the first data set do not need to be modified.

[0103] Case two, when the slave2 port is invalid or does not exist, the network device acts as a GM entity of the second clock domain.

[0104] In this case two, the network device acts as a GM clock node of the second clock domain, and the GM clock node periodically sends clock messages, and other BC nodes of the second clock domain keep time with the GM clock node. Optionally, the information of the second clock domain is modified (see the content of section 10.2.9 of IEEE 802.1AS-2020 protocol), including:

[0105] 1. Modify the value of domainNumber to the identifier domain2 of the second clock domain of the network device;

[0106] 2. Modify the value of localPortNumber to 0;

[0107] 3. Modify the value of syncReceiptTimeoutTime to FFFFFFFFFFFFFFFFF 16 ;

[0108] 4. Modify the clock identifier clockIdentity in sourcePortIdentity to the clockIdentity of the second clock domain of the network device, and modify the port number portnumber in sourcePortIdentity to 0;

[0109] 5. Modify logMessageInterval to the time interval at which the clockMaster of the second clock domain sends messages;

[0110] 6. The values of gmTimeBaseIndicator, lastGmPhaseChange and lastGmFreqChange do not need to be modified.

[0111] Thus, by the above manner, the information belonging to domain 1 in the first data set can be modified as the information of domain 2, and the second data set including the information of domain 2 and the synchronization clock information is generated. In the embodiment of the present application, the member parameters of the first data set and the second data set are not limited, that is, the number of members of the first data set and the second data set can be the same or different, as long as the second data set is obtained by modifying the first data set.

[0112] At step 802, the network device sends a second clock packet through the second master port according to the second data set, the timestamp carried by the second clock packet is the timestamp carried by the first clock packet, and the first clock packet and the second clock packet include sync packets or follow_up packets in the precision time protocol.

[0113] In the embodiment of the present application, the second clock packet includes a sync packet in the precision time protocol. Alternatively, in the two-step mode, the second clock packet also includes a follow_up packet, and the type of the second clock packet is the same as that of the first clock packet. Since the second data set is obtained by modifying the first data set, and the modification process does not modify the timestamp information, the timestamp included in the second data set is the timestamp in the first data set, that is, the timestamp carried by the first clock packet, and thus the timestamp carried by the second clock packet is the timestamp carried by the first clock packet. The timestamp refers to originTimestamp in the sync packet or preciseOriginTimestamp in the follow_up packet.

[0114] For example, the timestamp carried by the first clock packet received by the slave 1 port is January 1, 2021 0:0:0, and since the timestamp carried by the second clock packet is the timestamp carried by the first clock packet, the timestamp carried by the second clock packet sent by the master 2 port is January 1, 2021 0:0:0. For the delay inside the network device, other information can be carried in the clock packet, for example, the correctionField field in the header field of the sync packet or the follow_up packet. Thus, based on the timestamp carried by the clock packet and the delay, the time carried by the second packet can still be synchronized with the time of the time source.

[0115] For the way of using the ClockSlave module and the ClockMaster module, because there is a transmission delay of 1 second between the ClockSlave module and the slave1 port, the time of the time source recovered by the ClockSlave module according to the slave1 port is January 1, 2021, 0:0:1, the ClockMaster module synchronizes the above time January 1, 2021, 0:0:1 and sends it to the master2 port, therefore, the timestamp carried by the clock message sent by the master2 port is January 1, 2021, 0:0:1, not January 1, 2021, 0:0:0.

[0116] Therefore, it can be seen that the method provided in the embodiments of the application is different from the way of using the ClockSlave module and the ClockMaster module.

[0117] In a possible implementation, the network device can generate a second clock message according to the second data set and send the second clock message through the second master port. In this embodiment of the application, the way in which the network device generates the second clock message according to the second data set is not limited, the data carried by the second clock message can include all data in the second data set, or can include only part of the data in the second data set, as long as the second clock message sent through the second master port can be normally sent.

[0118] In a possible implementation, taking the first clock message and the second clock message as sync messages as an example, in the one-step mode, the network device sends the second clock message through the second master port master2 according to the second data set, the process is as follows: obtaining the egress timestamp corresponding to the local clock of the network device when sending the second clock message; updating the value of the followUpCorrectionField according to the egress timestamp; writing the preciseOriginTimestamp, rateRatio and updated followUpCorrectionField in the second data set into the originTimestamp, cumulativeScaledRateOffset and correctionField fields of the second clock message; sending the second clock message to the downstream device through the second master port. The originTimestamp carried in the second clock message is the originTimestamp carried in the first clock message.

[0119] In a possible implementation, taking the first clock packet and the second clock packet as sync packets as an example, in the two-step mode, the network device sends the second clock packet through the second master port master2 according to the second data set, which includes: obtaining an egress timestamp corresponding to a local clock of the network device when the second clock packet is sent; updating a value of the followUpCorrectionField according to the egress timestamp; writing the preciseOriginTimestamp, the rateRatio, and the updated followUpCorrectionField in the second data set into the preciseOriginTimestamp, the cumulativeScaledRateOffset, and the correctionField of the slave packet corresponding to the master packet; and sending the master packet and the slave packet to the downstream device through the second master port. Exemplarily, the master packet is a sync packet in the two-step mode, and the slave packet is a follow_up packet in the two-step mode.

[0120] Optionally, the process of updating the value of the followUpCorrectionField according to the egress timestamp includes but is not limited to: followUpCorrectionField=followUpCorrectionField+(Tb–upstreamTxTime)*rateRatio, where Tb is the egress timestamp corresponding to the local clock of the network device when the second clock packet is sent, and the followUpCorrectionField on the right side of the equation is a member in the second data set received by the second master port.

[0121] In the embodiment of the application, the second clock packet sent by the second master port of the network device carries the originTimestamp, the preciseOriginTimestamp, the followUpCorrectionField, and the rateRatio, and the originTimestamp carried by the second clock packet is the originTimestamp carried by the first clock packet, or the preciseOriginTimestamp carried by the second clock packet is the preciseOriginTimestamp carried by the first clock packet. In the case that the second slave port of the network device fails or does not exist, the second master port can keep sending the clock packet carrying accurate time information, so that the accurate time transfer of the clock packet of the entity 2 is uninterrupted, and the high reliability of the clock synchronization of the communication system is improved.

[0122] In a possible implementation, the network device further comprises a second switch; in response to the second slave port of the network device being invalid or not existing, the second master port of the network device acquires the second data set, comprising: in response to the second slave port being invalid or not existing, the second master port of the network device acquires the second data set from the first data set corresponding to the first slave port based on the control of the second switch. At this time, the second slave port belongs to the second clock domain, and the message transmission method further comprises: in response to the second slave port existing and being valid, the second master port of the network device sends a third clock message based on the control of the second switch according to a third data set corresponding to the second slave port, and the third clock message comprises a sync message or a follow_up message in the precision time protocol. The content of the third data set corresponding to the second slave port is not limited in the embodiments of the present application, and can be referred to the content of the first data set. For example, the third data set comprises a timestamp carried by a clock message received by the second slave port and data generated by the second slave port according to the received clock message.

[0123] Exemplarily, the first data set is modified by the IWF module, and referring to Figure 10 , wherein the second switch is denoted by D2, and the IWF module is denoted by IWF2. In Figure 10 , a structure diagram of the network device is shown, wherein the slave2 port of the domain2 exists, and the output of the IWF2 module and the switch D2 are connected. When the slave2 port is valid, the switch D2 controls the master2 port to receive the clock data set sent by the slave2 port, that is, the third data set in the embodiments of the present application. When the slave2 port is invalid or lost, the switch D2 controls the master2 port to receive the clock data set sent by the IWF2 module, that is, the second data set in the embodiments of the present application. Here, the IWF2 module can generate the second data set by modifying the received clock data set of the slave1 port, that is, the first data set in the embodiments of the present application. Thus, it can be ensured that the network device can control the switch D2 according to the state of the slave2 port, so that the master2 port can continue to maintain the transmission of the precision time of the clock message of the domain2 in the case of the slave2 port being invalid or lost.

[0124] In a possible implementation, the network device further comprises a first switch, the first master port belongs to a first clock domain, and the second slave port belongs to a second clock domain. The message transmission method further comprises the following steps: in response to the existence and validity of the first slave port, the first master port of the network device sends a fourth clock message according to a first data set corresponding to the first slave port based on the control of the first switch, and the fourth clock message comprises a sync message or a follow_up message in the precision time protocol; in response to the invalidity or nonexistence of the first slave port, and the existence and validity of the second slave port, the first master port of the network device sends a fifth clock message according to a third data set corresponding to the second slave port based on the control of the first switch, and the fifth clock message comprises a sync message or a follow_up message in the precision time protocol.

[0125] The embodiments of the present application do not limit the content of the third data set corresponding to the second slave port, and the content of the first data set can be referred to. For example, the third data set comprises a timestamp carried in a clock message received by the second slave port and data generated by the second slave port according to the received clock message. The first master port of the network device sends the fifth clock message according to the third data set corresponding to the second slave port based on the control of the first switch, which can refer to the manner in which the second master port sends the second clock message based on the second data set, and details are not described herein.

[0126] Exemplarily, the first data set is modified by the IWF module, and the network device is shown in FIG. 2. Figure 11 In the structure diagram of the network device shown in FIG. 2, the slave1 port of the domain1 and the slave2 port of the domain2 are not lost, the output of the slave1 port and the IWF1 module is connected with the switch D1, and the output of the slave2 port and the IWF2 module is connected with the switch D2. Figure 11 In the structure diagram of the network device shown in FIG. 2, the slave1 port of the domain1 and the slave2 port of the domain2 are not lost, the output of the slave1 port and the IWF1 module is connected with the switch D1, and the output of the slave2 port and the IWF2 module is connected with the switch D2.

[0127] When the slave1 port exists and is valid, the master1 port receives the clock data set sent by the slave1 port through the switch D1. When the slave1 port is invalid or lost, the master1 port receives the clock data set sent by the IWF1 module through the switch D1. Thus, the network device can control the switch D1 according to the state of the slave1 port, so that the master1 port can continue to transmit the clock message when the slave1 port is invalid or lost. Similarly, when the slave2 port exists and is valid, the master2 port receives the clock data set sent by the slave2 port through the switch D2. When the slave2 port is invalid or the second slave port is invalid or lost, the master2 port receives the clock data set sent by the IWF2 module through the switch D2. Thus, the network device can control the switch D2 according to the state of the slave2 port, so that the master2 port can continue to transmit the clock message when the slave2 port is invalid or lost.

[0128] In a possible implementation manner, Figure 11 The IWF1 module and the IWF2 module in the structural schematic diagram of the network device shown in the figure can also be the same IWF module. When the slave1 port is invalid or does not exist, the IWF module modifies the clock data set of the slave2 port and sends the clock data set to the master1 port. When the slave2 port is invalid or does not exist, the IWF module modifies the clock data set of the slave1 port and sends the clock data set to the master2 port.

[0129] The message transmission method provided by the embodiment of the application can enable the second master port to obtain the second data set modified based on the first data set when the second slave port of the network device is invalid or does not exist, and then continue to send the clock message carrying the accurate time according to the second data set. That is, the method provided by the embodiment of the application can enable the master port of a certain clock domain to continue to send the clock message carrying the accurate time when the slave port of the clock domain is invalid or does not exist, without using the ClockMaster module and the ClockSlave module. The method realizes the multi-domain hot-standby function of the multi-domain clock device in a simple way, and improves the reliability of the communication system. The multi-domain hot-standby function can also be realized for the BC device that does not support the ClockMaster module and the ClockSlave module.

[0130] In addition, the method provided by the embodiment of the present application improves the reliability and flexibility of message transmission by using a protection switch, when the slave port of a domain is normal, sending data and messages of the slave port of the domain to the Master port of the domain; and when the slave port of a domain does not exist or is invalid, sending data and messages of the slave port of another domain to the Master port of the domain through IWF conversion.

[0131] The above introduces the message transmission method of the embodiment of the present application. Corresponding to the above method, the embodiment of the present application also provides a message transmission device. Figures 12-15 is a structural schematic diagram of a message transmission device provided by the embodiment of the present application. The device is applied to a network device, which is the network device shown in the above Figures 6-7 , 9-11 or 16-17. Based on the following multiple modules of the message transmission device shown in Figures 12-15 , the message transmission device shown in Figures 12-15 can perform all or part of the operations performed by the network device. It should be understood that the device can include more additional modules than the shown modules or omit part of the shown modules, and the embodiment of the present application does not limit this. As shown in Figure 12 , the message transmission device includes:

[0132] The first acquisition module 1201 is configured to, in response to the second slave port of the network device being invalid or the second slave port not existing, acquire, by the second Master port of the network device, a second data set, the second data set being obtained by modifying a first data set, the first data set including a timestamp carried by a first clock message received by a first slave port and data generated by the first slave port according to the first clock message, the first slave port belonging to a first clock domain, and the second Master port belonging to a second clock domain, the first clock domain being different from the second clock domain.

[0133] The sending module 1202 is configured to send, by the network device, a second clock message through the second Master port according to the second data set, the timestamp carried by the second clock message being the timestamp carried by the first clock message, and the first clock message and the second clock message including a sync message or a follow_up message in a precision time protocol.

[0134] The timestamp refers to an originTimestamp in the sync message or a preciseOriginTimestamp in the follow_up message.

[0135] In a possible implementation, the first acquisition module 1201 is configured to receive, by the second Master port, the first data set, modify the first data set according to information of the second clock domain, and obtain the second data set.

[0136] In a possible implementation, the second master port and the first slave port comprise an IWF module, the IWF module being configured to modify the first data set according to information of the second clock domain to obtain a second data set; and the first obtaining module 1201 is configured to receive, by the second master port, the second data set sent by the IWF module.

[0137] In a possible implementation, the first data set comprises a domain name domainNumber; and the first obtaining module 1201 is further configured to modify the value of the domainNumber to a domain name of the second clock domain of the network device.

[0138] In a possible implementation, the first data set comprises a domain name domainNumber, a local port number localPortNumber, a synchronization receipt timeout time syncReceiptTimeoutTime, a source port identity sourcePortIdentity, and a log message interval logMessageInterval; and the first obtaining module 1201 is further configured to modify the value of the domainNumber to a domain name of the second clock domain of the network device, modify the value of the localPortNumber to a first value, modify the value of the syncReceiptTimeoutTime to a second value, modify a clock identity clockIdentity in the sourcePortIdentity to a clockIdentity of the second clock domain, modify a port number portNumber in the sourcePortIdentity to a third value, and modify the logMessageInterval to a time interval at which a clock master of the second clock domain sends a message.

[0139] In a possible implementation, referring to Figure 13 The apparatus further comprises:

[0140] The receiving module 1203 is configured to receive, by a first slave port of the network device, a first clock message sent by a third master port, the third master port being a master port corresponding to a first clock domain of a clock source device of the network device;

[0141] The second obtaining module 1204 is configured to obtain, based on the received first clock message, data generated according to the first clock message;

[0142] The generating module 1205 is configured to generate a first data set based on a time stamp carried in the first clock message and the data generated according to the first clock message.

[0143] In a possible implementation, the network device comprises a second switch; the first obtaining module 1201 is further configured to, in response to the second slave port being invalid or not existing, obtain, based on the second master port of the network device, a second data set from a first data set corresponding to a first slave port according to control of the second switch.

[0144] In a possible implementation, the network device comprises a second switch; see Figure 14 The apparatus further comprises:

[0145] The first control module 1206 is configured to, in response to the second slave port existing and being valid and the second slave port belonging to a second clock domain, transmit, based on the control of the second switch, a third clock packet from the second master port of the network device according to a third data set corresponding to the second slave port, the third clock packet comprising a sync packet or a follow_up packet in the precision time protocol.

[0146] In a possible implementation, the network device further comprises a first switch, and the first master port belongs to a first clock domain; see Figure 15 The apparatus further comprises:

[0147] The second control module 1207 is configured to, in response to the first slave port existing and being valid, transmit, based on the control of the first switch, a fourth clock packet from the first master port of the network device according to the first data set of the first slave port, the fourth clock packet comprising a sync packet or a follow_up packet in the precision time protocol.

[0148] The third control module 1208 is configured to, in response to the first slave port being invalid or not existing and the second slave port existing and being valid, transmit, based on the control of the first switch, a fifth clock packet from the first master port of the network device according to the third data set corresponding to the second slave port, the fifth clock packet comprising a sync packet or a follow_up packet in the precision time protocol.

[0149] It should be understood that the above Figures 12-15 The apparatus provided in the embodiments is only used as an example for dividing the above functions, and in actual applications, the above functions can be completed by different function modules according to requirements, that is, the internal structure of the apparatus is divided into different function modules to complete all or part of the above functions. In addition, the apparatus and the method provided in the above embodiments belong to the same concept, and the specific implementation process is described in the method embodiments, which will not be repeated here.

[0150] See Figure 16 , Figure 16 FIG. 2 shows a structural schematic diagram of a network device 2000 provided in an example embodiment of the present application. Figure 16 The network device 2000 shown is configured to perform the aboveFigure 8 The network device 2000 is involved in the operation of the packet transmission method shown. The network device 2000, for example, is a switch, a router, etc., which can be implemented by a general bus architecture.

[0151] As shown in Figure 16 The network device 2000 includes at least one processor 2001, a memory 2003, and at least one communication interface 2004.

[0152] The processor 2001 is, for example, a general central processing unit (CPU), a digital signal processor (DSP), a network processer (NP), a Graphics Processing Unit (GPU), a neural-network processing units (NPU), a Data Processing Unit (DPU), a microprocessor, or one or more integrated circuits used to implement a design in this application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic device, transistor logic, a hardware component, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logical blocks, modules, and circuits described in combination with the disclosure of the embodiments of the application. The processor can also be a combination of computing functions, such as including one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0153] Optionally, the network device 2000 also includes a bus. The bus is used to transmit information between the components of the network device 2000. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 16 In the figure, only one thick line is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0154] The memory 2003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 through the bus. The memory 2003 can also be integrated with the processor 2001.

[0155] The communication interface 2004 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), or Wireless Local Area Network (WLAN). The communication interface 2004 can include wired and wireless communication interfaces. Specifically, the communication interface 2004 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In this embodiment, the communication interface 2004 can be used by the network device 2000 to communicate with other devices.

[0156] In a specific implementation, as one example, the processor 2001 may include one or more CPUs, such as... Figure 16 The CPU0 and CPU1 shown are examples of processors. Each of these processors can be a single-core processor or a multi-core processor. A processor here can refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0157] In a specific implementation, as one example, the network device 2000 may include multiple processors, such as... Figure 16 The processors shown are 2001 and 2005. Each of these processors can be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).

[0158] In a specific implementation, as an example, the network device 2000 can further include an output device and an input device. The output device communicates with the processor 2001 and can display information in various ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, a projector, or the like. The input device communicates with the processor 2001 and can receive user input in various ways. For example, the input device can be a mouse, a keyboard, a touch screen device, a sensor device, or the like.

[0159] In some embodiments, the memory 2003 is configured to store program code 2010 for implementing the solutions of the present application, and the processor 2001 can execute the program code 2010 stored in the memory 2003. That is, the network device 2000 can implement the packet transmission method provided by the method embodiments through the processor 2001 and the program code 2010 in the memory 2003. The program code 2010 can include one or more software modules. Alternatively, the processor 2001 itself can also store program codes or instructions for implementing the solutions of the present application.

[0160] In specific embodiments, the network device 2000 of the embodiments of the present application can correspond to the network device in the above method embodiments. The processor 2001 in the network device 2000 reads the instructions in the memory 2003, so that the network device 2000 can perform all or part of the operations performed by the network device. Figure 16 The network device 2000 shown in the figure can perform all or part of the operations performed by the network device.

[0161] Specifically, the processor 2001 is configured to acquire, by the second master port of the network device through the communication interface, the second data set.

[0162] Other optional implementations are not described here for brevity.

[0163] The network device 2000 can also correspond to the network device described above Figures 12-15 The packet transmission device shown in the figure, each functional module in the packet transmission device is implemented by software of the network device 2000. In other words, the functional modules included in the packet transmission device are generated by the processor 2001 of the network device 2000 reading the program code 2010 stored in the memory 2003.

[0164] Among them, Figure 8The steps of the message transmission method shown are completed by integrated logic circuits of hardware in the processor of the network device 2000 or instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as execution completed by a hardware processor, or executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, or the like. The storage medium is located in the memory, and the processor reads information in the memory and combines the hardware to complete the steps of the above method. To avoid repetition, they will not be described in detail here.

[0165] Referring to Figure 17 , Figure 17 The structure schematic diagram of the network device 2100 provided by another exemplary embodiment of the present application is shown, Figure 17 The network device 2100 shown is used to execute all or part of the operations involved in the message transmission method described above. The network device 2100 is, for example, a switch, a router, etc., which can be implemented by a general bus architecture. Figure 8

[0166] As shown in the figure, the network device 2100 includes a main control board 2110 and an interface board 2130. Figure 17

[0167] The main control board is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is used for control and management of various components in the network device 2100, including route calculation, device management, device maintenance, and protocol processing functions. The main control board 2110 includes a central processing unit 2111 and a memory 2112.

[0168] The interface board 2130 is also called a line processing unit (LPU), a line card, or a service board. The interface board 2130 is used to provide various service interfaces and implement data packet forwarding. The service interfaces include, but are not limited to, Ethernet interfaces, POS (Packet over SONET / SDH) interfaces, etc. The Ethernet interface is, for example, a flexible Ethernet service interface (FlexE Clients). The interface board 2130 includes a central processing unit 2131, a network processor 2132, a forwarding table item memory 2134, and a physical interface card (PIC) 2133.

[0169] ​​The central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110.

[0170] The network processor 2132 is used to implement the forwarding processing of the message. The network processor 2132 can be a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward the received message based on the forwarding table stored in the forwarding table item memory 2134, and if the destination address of the message is the address of the network device 2100, the message is sent to the CPU (such as the central processor 2131) for processing; if the destination address of the message is not the address of the network device 2100, the next hop and the out interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the out interface corresponding to the destination address. The processing of the uplink message can include the processing of the message entry interface and the forwarding table lookup; the processing of the downlink message can include the forwarding table lookup, and the like. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the interface board does not need a forwarding chip.

[0171] The physical interface card 2133 is used to implement the interfacing function of the physical layer, and the original traffic enters the interface board 2130 through the physical interface card 2133, and the processed message is sent out from the physical interface card 2133. The physical interface card 2133 is also called a sub-card, which can be installed on the interface board 2130 and is responsible for converting the optical-electric signal into a message and forwarding the message to the network processor 2132 for processing after the legality check. In some embodiments, the central processor 2131 can also perform the function of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU, so that the physical interface card 2133 does not need a network processor 2132.

[0172] Optionally, the network device 2100 includes a plurality of interface boards, for example, the network device 2100 further includes an interface board 2140, the interface board 2140 includes a central processor 2141, a network processor 2142, a forwarding table item memory 2144 and a physical interface card 2143. The functions and implementation manners of the components in the interface board 2140 are the same as or similar to those of the interface board 2130, and are not described here again.

[0173] Optionally, the network device 2100 further includes a switch fabric 2120. The switch fabric 2120 can also be referred to as a switch fabric unit (SFU). In the case of a network device having multiple interface boards, the switch fabric 2120 is used to complete data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 can communicate through the switch fabric 2120.

[0174] The master board 2110 is coupled with the interface boards. For example, the master board 2110, the interface board 2130 and the interface board 2140, and the switch fabric 2120 are connected through a system bus and a system backplane to communicate with each other. In a possible implementation, an inter-process communication (IPC) channel is established between the master board 2110 and the interface board 2130 and the interface board 2140, and the master board 2110 and the interface board 2130 and the interface board 2140 communicate through the IPC channel.

[0175] In logic, the network device 2100 includes a control plane and a forwarding plane. The control plane includes the master board 2110 and the central processor 2111, and the forwarding plane includes various components performing forwarding, such as the forwarding table entry memory 2134, the physical interface card 2133 and the network processor 2132. The control plane performs functions such as generating a forwarding table, processing signaling and protocol packets, configuring and maintaining the state of the network device, and the like. The control plane generates a forwarding table and delivers the forwarding table to the forwarding plane. In the forwarding plane, the network processor 2132 performs table lookup and forwarding on a packet received by the physical interface card 2133 based on the forwarding table delivered by the control plane. The forwarding table delivered by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same network device.

[0176] It is worth mentioning that the master board can be one or more, and when there are multiple master boards, the master boards can include a main master board and a backup master board. The interface board can be one or more, and the more interface boards the network device provides, the stronger the data processing capability of the network device. The physical interface card on the interface board can also be one or more. The switching network board can be none or one or more, and when there are multiple switching network boards, the switching network boards can collectively implement load sharing and redundancy. Under the centralized forwarding architecture, the network device can not need the switching network board, and the interface board can undertake the processing function of the entire system. Under the distributed forwarding architecture, the network device can have at least one switching network board, and the switching network board can be used to realize data exchange between multiple interface boards and provide large-capacity data exchange and processing capability. Therefore, the data access and processing capability of the network device in the distributed architecture is greater than that of the network device in the centralized architecture. Alternatively, the network device can also be in the form of only one board, that is, the functions of the interface board and the master board are integrated on the one board, and at this time, the central processor on the interface board and the central processor on the master board can be combined into one central processor on the one board to perform the functions of the two superimposed central processors. The data exchange and processing capability of the network device in this form is relatively low (for example, low-end switches or routers, etc.). Which architecture to use depends on the specific network deployment scenario, and no limitation is made here.

[0177] In specific embodiments, the network device 2100 corresponds to the packet transmission device applied to the network device as shown in the above Figures 12-15 In some embodiments, the first acquisition module 1201 in the packet transmission device as shown in the above Figures 12-15 The sending module 1202 corresponds to the physical interface card 2133 in the network device 2100.

[0178] The embodiment of the present application also provides a communication device, which comprises a transceiver, a memory and a processor. The transceiver, the memory and the processor communicate with each other through an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to receive a signal and control the transceiver to send a signal. When the processor executes the instructions stored in the memory, the processor executes the method required to be executed by the network device.

[0179] It is to be understood that the above-described processor can be a CPU, and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic components, discrete hardware components, and the like. The general-purpose processor can be a microprocessor or any conventional processor, and the like. It is to be noted that the processor can be an advanced RISC machines (ARM) architecture processor.

[0180] Further, in an optional embodiment, the above-described memory can include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory can also include a non-volatile random access memory. For example, the memory can also store device type information.

[0181] The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DRAM) can be used.

[0182] The embodiment of the present application further provides a computer readable storage medium, at least one instruction is stored in the storage medium, the instruction is loaded and executed by a processor, so that the computer implements the packet transmission method described in any of the above.

[0183] The embodiment of the present application further provides a computer program (product), when the computer program is executed by a computer, can make the processor or the computer execute the corresponding steps and / or processes in the above method embodiment.

[0184] The embodiment of the present application further provides a chip, comprising a processor, for calling and running instructions stored in a memory, so that the communication device installed with the chip executes the packet transmission method described in any of the above.

[0185] The embodiment of the present application further provides another chip, comprising: an input interface, an output interface, a processor and a memory, the input interface, the output interface, the processor and the memory are connected through internal connection paths, the processor is used to execute the code in the memory, when the code is executed, the processor is used to execute the packet transmission method described in any of the above.

[0186] In the above embodiment, all or part of it can be realized by software, hardware, firmware or any combination thereof. When realized by software, it can be realized in the form of computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be magnetic medium (for example, floppy disk, hard disk, magnetic tape), optical medium (for example, DVD) or semiconductor medium (for example, solid state disk) and the like.

[0187] Those skilled in the art can appreciate that, in combination with the method steps and modules described in the embodiments disclosed herein, all or part of the steps can be implemented by software, hardware, firmware or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of the embodiments have been described in the above description in general terms. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0188] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by programs instructing related hardware, which can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0189] When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiments of the present application can be described in the context of machine-executable instructions, such as program modules that are executed by devices included in the target real or virtual processor. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., which perform specific tasks or implement specific abstract data structures. In various embodiments, the functions of the program modules can be combined or divided among the described program modules. Machine-executable instructions for program modules can be executed within a local or distributed device. In a distributed device, program modules can be located in both local and remote storage media.

[0190] The computer program code for implementing the method of the embodiments of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing apparatus, so that when the computer program codes are executed by the computer or other programmable data processing apparatus, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program codes can be executed entirely on the computer, partially on the computer, as a separate software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0191] In the context of the embodiments of the present application, computer program codes or related data can be carried by any appropriate carrier to enable the device, apparatus or processor to perform the various processes and operations described above. Examples of the carrier include a signal, a computer readable medium, etc.

[0192] Examples of a signal can include electrical, optical, radio frequency, sound, or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0193] A machine-readable medium can be any tangible medium that contains or stores the program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), and a digital versatile disc (DVD), or any suitable combination of the foregoing.

[0194] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and module can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0195] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the module is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be indirect coupling or communication connection through some interfaces, devices or modules, and can also be electrical, mechanical or other form of connection.

[0196] The module described as a separate component can or can not be physically separated, and the component displayed as a module can or can not be a physical module, that is, it can be located in one place, or can be distributed to a plurality of network modules. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0197] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically, or two or more modules can be integrated into one module. The above integrated module can be realized in the form of hardware or in the form of software functional module.

[0198] The integrated module, if implemented in the form of a software function module and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art, or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0199] The terms "first", "second", and the like in the present application are used to distinguish between items or similar items having substantially the same function and action. It should be understood that there is no logical or chronological dependency between "first", "second", and "nth", and the number and execution order are not limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various described examples, a first image can be referred to as a second image, and similarly, a second image can be referred to as a first image. The first image and the second image can both be images, and in some cases, can be separate and distinct images.

[0200] It should also be understood that in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0201] The term "at least one" in the present application means one or more, and the term "a plurality of" in the present application means two or more, for example, a plurality of second messages means two or more second messages. The terms "system" and "network" are often used interchangeably in this document.

[0202] It should be understood that the terms used in the description of various described examples herein are only for the purpose of describing specific examples and are not intended to be limiting. As used in the description of various described examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0203] It should also be understood that, as used in this specification, the terms "comprises", "comprising", "includes", "including", "with" or "comprising", specifies the presence of stated features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0204] It should also be understood that the terms "comprises", "comprising", "includes", "including", "with" or "comprising", specifies the presence of stated features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0205] It should also be understood that the terms "if' and "when" can be construed to mean "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be construed to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]", depending on the context.

[0206] It should be understood that a determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0207] It should also be understood that the terms "one embodiment", "an embodiment", "one possible implementation", as used in the specification are meant to indicate that a particular feature, structure, or characteristic described in connection with an embodiment or implementation is included in at least one implementation of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment", "one possible implementation", as well as variations thereof, in various places throughout the specification are not necessarily referring to the same embodiment or implementation, nor are they necessarily referring to any particular embodiment or implementation. Furthermore, these particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0208] The above description is only optional embodiments of the application, and is not used to limit the application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A method of transmitting a packet, characterized by, The method comprises: In response to a second slave port of the network device being disabled, the network device acquires a second data set through a second master port of the network device, the second data set being modified based on a first data set, the first data set comprising a timestamp carried by a first clock message received by a first slave port of the network device and data generated by the first slave port according to the first clock message, the first slave port belonging to a first clock domain, the second master port belonging to a second clock domain, the first clock domain being different from the second clock domain; The network device sends a second clock message through the second master port according to the second data set, the second clock message carrying the timestamp carried by the first clock message, the first clock message and the second clock message comprising a sync message or a follow_up message in a precision time protocol.

2. The method of claim 1, wherein, The network device acquires the second data set through the second master port of the network device, comprising: The network device receives the first data set through the second master port and modifies the first data set according to information of the second clock domain to obtain the second data set.

3. The method of claim 1, wherein, The second master port and the first slave port comprise an interworking function (IWF) module, and the IWF module is configured to modify the first data set according to information of the second clock domain to obtain the second data set; The network device acquires the second data set through the second master port of the network device, comprising: The network device receives the second data set sent by the IWF module through the second master port.

4. The method of claim 2, wherein, The first data set comprises a domain sequence number (domainNumber); The modification of the first data set according to the information of the second clock domain comprises: The value of the domainNumber is modified to a domain sequence number of the second clock domain of the network device.

5. The method of claim 2, wherein, The first data set comprises a domain sequence number (domainNumber), a local port number (localPortNumber), a synchronization receipt time (syncReceiptTimeoutTime), a source port identifier (sourcePortIdentity) and a log message interval (logMessageInterval); The modification of the first data set according to the information of the second clock domain comprises: modifying a value of the domainNumber to a domain sequence number of the second clock domain of the network device, modifying a value of the localPortNumber to a first value, modifying a value of the syncReceiptTimeoutTime to a second value, modifying a clock identity clockIdentity in the sourcePortIdentity to the clockIdentity of the second clock domain, modifying a port number portnumber in the sourcePortIdentity to a third value, and modifying the logMessageInterval to a time interval at which the clock master of the second clock domain sends a message.

6. The method of claim 1, wherein, the network device comprises a second switch; in response to the second slave port being invalid, the network device acquires a second data set through a second master port of the network device, comprising: in response to the second slave port being invalid, the network device acquires the second data set through the second master port of the network device based on control of the second switch according to a first data set corresponding to the first slave port.

7. The method of claim 1, wherein, the network device comprises a second switch; the method further comprises: in response to the second slave port existing and being valid, the second slave port belonging to a second clock domain, the network device sends a third clock message according to a third data set corresponding to the second slave port through the second master port of the network device based on control of the second switch, the third clock message comprising a sync message or a follow_up message in the precision time protocol.

8. The method according to claim 6 or 7, characterized in that, the network device further comprises a first switch, and a first master port of the network device belongs to the first clock domain; the method further comprises: in response to the first slave port existing and being valid, the network device sends a fourth clock message according to a first data set corresponding to the first slave port through the first master port of the network device based on control of the first switch, the fourth clock message comprising a sync message or a follow_up message in the precision time protocol; in response to the first slave port being invalid and the second slave port existing and being valid, the network device sends a fifth clock message according to a third data set corresponding to the second slave port through the first master port of the network device based on control of the first switch, the fifth clock message comprising a sync message or a follow_up message in the precision time protocol.

9. The method according to any one of claims 1 to 7, characterized in that, before the network device acquires the second data set through the second master port of the network device, the method further comprises: the network device receives a first clock message sent by a third master port through a first slave port of the network device, the third master port being one master port corresponding to the first clock domain of a clock source device of the network device; acquiring the data generated according to the first clock message based on the received first clock message; The first data set is generated based on a timestamp carried by the first clock message and data generated according to the first clock message.

10. A packet transmission apparatus characterized by comprising: The apparatus comprises: The first obtaining module is configured to, in response to failure of a second slave port of a network device, obtain a second data set through a second master port of the network device, the second data set being obtained by modifying a first data set, the first data set comprising a timestamp carried by a first clock message received by a first slave port of the network device and data generated by the first slave port according to the first clock message, the first slave port belonging to a first clock domain, the second master port belonging to a second clock domain, the first clock domain being different from the second clock domain. The sending module is configured to send a second clock message through the second master port according to the second data set, the second clock message carrying the timestamp carried by the first clock message, the first clock message and the second clock message comprising a sync message or a follow_up message in a precision time protocol.

11. The apparatus of claim 10, wherein, The first obtaining module is configured to receive the first data set through the second master port and modify the first data set according to information of the second clock domain to obtain the second data set.

12. The apparatus of claim 10, wherein, The second master port and the first slave port comprise an interworking function (IWF) module, the IWF module being configured to modify the first data set according to information of the second clock domain to obtain the second data set, and the first obtaining module is configured to receive the second data set sent by the IWF module through the second master port.

13. The apparatus of claim 11, wherein, The first data set comprises a domain sequence number (domainNumber), and the first obtaining module is configured to modify the value of the domainNumber to a domain sequence number of the second clock domain of the network device.

14. The apparatus of claim 11, wherein, The first data set comprises a domain sequence number (domainNumber), a local port number (localPortNumber), a sync receipt timeout time (syncReceiptTimeoutTime), a source port identity (sourcePortIdentity), and a log message interval (logMessageInterval), and the first obtaining module is configured to modify the value of the domainNumber to a domain sequence number of the second clock domain of the network device, modify the value of the localPortNumber to a first value, modify the value of the syncReceiptTimeoutTime to a second value, modify a clock identity (clockIdentity) in the sourcePortIdentity to a clockIdentity of the second clock domain, modify a port number (portnumber) in the sourcePortIdentity to a third value, and modify the logMessageInterval to a time interval of a message sent by a clock master of the second clock domain.

15. The apparatus of claim 10, wherein, The network device comprises a second switch; the first acquisition module is configured to, in response to the second slave port being invalid, acquire the second data set from the first data set corresponding to the first slave port based on the control of the second switch through the second master port of the network device.

16. The apparatus of claim 10, wherein, The network device comprises a second switch; the apparatus further comprises: The first control module is configured to, in response to the second slave port being valid and belonging to a second clock domain, send a third clock packet from a third data set corresponding to the second slave port based on the control of the second switch through the second master port of the network device, wherein the third clock packet comprises a sync packet or a follow_up packet in the precision time protocol.

17. The apparatus of claim 15 or 16, wherein, The network device further comprises a first switch, and the first master port of the network device belongs to the first clock domain; the apparatus further comprises: The second control module is configured to, in response to the first slave port being valid, send a fourth clock packet from the first data set corresponding to the first slave port based on the control of the first switch through the first master port of the network device, wherein the fourth clock packet comprises a sync packet or a follow_up packet in the precision time protocol. The third control module is configured to, in response to the first slave port being invalid and the second slave port being valid, send a fifth clock packet from the third data set corresponding to the second slave port based on the control of the first switch through the first master port of the network device, wherein the fifth clock packet comprises a sync packet or a follow_up packet in the precision time protocol.

18. The apparatus of any of claims 10-16, wherein, The apparatus further comprises: The receiving module is configured to receive a first clock packet sent by a third master port through the first slave port of the network device, wherein the third master port is a master port corresponding to the first clock domain of the clock source device of the network device; The second acquisition module is configured to acquire the data generated according to the first clock packet based on the received first clock packet; The generating module is configured to generate the first data set based on the timestamp carried by the first clock packet and the data generated according to the first clock packet.

19. A network device, comprising: The network device comprises a processor coupled with a memory, and the memory stores at least one program instruction or code, which is loaded and executed by the processor to enable the network device to implement the packet transmission method in any one of claims 1-9.

20. A computer-readable storage medium, characterized in that, The computer storage medium stores at least one instruction, which is loaded and executed by the processor to enable the computer to implement the packet transmission method in any one of claims 1-9.

21. A computer program product, characterised in that, The computer program product stores at least one instruction, which is loaded and executed by the processor to implement the packet transmission method in any one of claims 1-9.

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