Symbol synchronization circuit and receiver

Abstract

The present disclosure relates to a symbol synchronization circuit and a receiver, the circuit comprising: a differential phase detection module for obtaining a frequency deviation signal; a DC component removal module for removing the DC component in the frequency deviation signal; an interpolation module for obtaining an interpolation processing signal; a timing error detection module for determining timing error information; a loop filter module for filtering the timing error information; a digital control oscillation module for accumulating the filtered timing error information to obtain a corresponding interpolation coefficient; the interpolation module is also used to adjust the sampling clock of the interpolation processing according to the interpolation coefficient to achieve synchronization of the symbol clock. The embodiments of the present disclosure can quickly and accurately achieve synchronization of the symbol clock, so that the receiver can correctly receive and demodulate the data sent by the transmitter, improve the demodulation performance of the receiver, and improve the accuracy and efficiency of data communication.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a symbol synchronization circuit and a receiver. Background Art

[0002] During the communication process of a wireless digital receiver, the accuracy of the clocks at both the transmitter and receiver are inevitably affected by temperature drift. Therefore, in practical applications, the optimal sampling point obtained by frame synchronization cannot always be aligned with the middle position of the symbol period. As the sampling clock error accumulates, the demodulation performance of the receiver will be reduced. Summary of the invention

[0003] According to one aspect of the present disclosure, there is provided a symbol synchronization circuit, the circuit comprising:

[0004] A differential phase detection module is used to perform differential phase detection on the digital baseband signal to obtain a frequency deviation signal;

[0005] A DC component removal module, connected to the differential phase detection module, for removing the DC component in the frequency deviation signal;

[0006] An interpolation module, connected to the DC component removal module, for performing interpolation processing on the frequency deviation signal with the DC component removed to obtain an interpolation processing signal;

[0007] A timing error detection module, connected to the interpolation module, configured to perform high-pass filtering on the interpolation processing signal to obtain the sideband energy of the interpolation processing signal at different sampling points, and determine the timing error information according to the sideband energy at different sampling points;

[0008] A loop filtering module, connected to the timing error detection module, for filtering the timing error information;

[0009] A digital control oscillation module, connected to the loop filter module, for accumulating the filtered timing error information to obtain a corresponding interpolation coefficient;

[0010] The interpolation module is also used to adjust the sampling clock of the interpolation process according to the interpolation coefficient to achieve synchronization of the symbol clock.

[0011] In a possible implementation, the differential phase detection module includes:

[0012] A phase detection subunit, used for performing phase detection processing on the digital baseband signal to obtain a phase signal;

[0013] The differential subunit is connected to the phase detection subunit and is used to perform differential processing on the phase signal to obtain the frequency deviation signal.

[0014] In a possible implementation manner, the DC component removal module includes:

[0015] A DC component acquisition subunit, used for performing a sliding average filtering process on the frequency deviation signal to obtain the DC component;

[0016] The DC component removal subunit is electrically connected to the DC component acquisition subunit and is used to remove the DC component in the frequency deviation signal to obtain a processed frequency deviation signal.

[0017] In a possible implementation, the interpolation module includes:

[0018] A linear interpolation unit, used to perform linear interpolation on the frequency deviation signal with the DC component removed to obtain the interpolation processed signal; or

[0019] A cubic interpolation unit is used to perform cubic interpolation on the frequency deviation signal with the DC component removed to obtain the interpolation processing signal.

[0020] Wherein, the interpolation module operates at twice the symbol rate.

[0021] In a possible implementation manner, the timing error detection module includes:

[0022] A first high-pass filter is used to perform high-pass filtering on the frequency deviation signal with the DC component removed to obtain a sideband energy value of a first sampling point;

[0023] A second high-pass filter is used to perform high-pass filtering on the frequency deviation signal with the DC component removed to obtain a sideband energy value of a second sampling point;

[0024] A timing error determination unit is connected to the first high-pass filter and the second high-pass filter, and is used to determine the timing error information according to the sideband energy value of the first sampling point and the sideband energy value of the second sampling point.

[0025] In a possible implementation manner, the first high-pass filter and the second high-pass filter are both used to obtain the sideband energy value of the corresponding sampling point according to the product of the sideband energy value of the corresponding sampling point of the previous symbol and the first preset parameter and the sum of the frequency offset signal with the DC component removed;

[0026] The timing error determination unit is further configured to determine the timing error information according to a product of a sideband energy value of the first sampling point, a sideband energy value of the second sampling point, and a second preset parameter.

[0027] In a possible implementation manner, the first preset parameter is any value between -0.85 and -0.95, and the second preset parameter is any value between 0.1 and 0.25.

[0028] In a possible implementation, the loop filtering module includes a loop filter, and the loop filter filters the timing error information by using a proportional integral filtering method.

[0029] In a possible implementation, the digitally controlled oscillation module includes a digitally controlled oscillator, and is further used for:

[0030] In case the output of the numerically controlled oscillator overflows, a fractional delay interval is determined, and the interpolation coefficient is determined according to the fractional delay interval.

[0031] According to one aspect of the present disclosure, a receiver is provided, the receiver comprising:

[0032] The symbol synchronization circuit.

[0033] The symbol synchronization circuit of the embodiment of the present disclosure obtains a frequency deviation signal by performing differential phase detection processing on a digital baseband signal, removes a DC component from the frequency deviation signal, interpolates the frequency deviation signal with the DC component removed to obtain an interpolated signal, high-pass filters the interpolated signal to obtain sideband energy of the interpolated signal at different sampling points, determines timing error information based on the sideband energy at different sampling points, filters the timing error information, accumulates the filtered timing error information to obtain a corresponding interpolation coefficient, and adjusts the sampling clock of the interpolation processing based on the interpolation coefficient to achieve synchronization of the symbol clock. The embodiment of the present disclosure can quickly and accurately achieve synchronization of the symbol clock, so that the receiver can correctly receive and demodulate the data sent by the transmitter, improve the demodulation performance of the receiver, and improve the accuracy and efficiency of data communication.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0036] Figure 1 A block diagram of a symbol synchronization circuit according to an embodiment of the present disclosure is shown.

[0037] Figure 2 A block diagram of a symbol synchronization circuit according to an embodiment of the present disclosure is shown.

[0038] Figure 3A block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0039] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0041] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0044] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0045] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0046] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0047] See also Figure 1 , Figure 1 A block diagram of a symbol synchronization circuit according to an embodiment of the present disclosure is shown.

[0048] like Figure 1 As shown, the circuit comprises:

[0049] The differential phase detection module 10 is used to perform differential phase detection processing on the digital baseband signal to obtain a frequency deviation signal;

[0050] A DC component removal module 20, connected to the differential phase detection module 10, for removing the DC component in the frequency deviation signal;

[0051] An interpolation module 30, connected to the DC component removal module 20, for performing interpolation processing on the frequency deviation signal with the DC component removed to obtain an interpolation processing signal;

[0052] A timing error detection module 40, connected to the interpolation module 30, for performing high-pass filtering on the interpolation processing signal to obtain the sideband energy of the interpolation processing signal at different sampling points, and determining the timing error information according to the sideband energy at different sampling points;

[0053] A loop filtering module 50, connected to the timing error detection module 40, for filtering the timing error information;

[0054] A digital control oscillation module 60, connected to the loop filter module 50, for accumulating the filtered timing error information to obtain a corresponding interpolation coefficient;

[0055] The interpolation module 30 is further configured to adjust the sampling clock of the interpolation process according to the interpolation coefficient to achieve synchronization of the symbol clock.

[0056] The symbol synchronization circuit of the embodiment of the present disclosure obtains a frequency deviation signal by performing differential phase detection processing on a digital baseband signal, removes a DC component from the frequency deviation signal, interpolates the frequency deviation signal with the DC component removed to obtain an interpolated signal, high-pass filters the interpolated signal to obtain sideband energy of the interpolated signal at different sampling points, determines timing error information based on the sideband energy at different sampling points, filters the timing error information, accumulates the filtered timing error information to obtain a corresponding interpolation coefficient, and adjusts the sampling clock of the interpolation processing based on the interpolation coefficient to achieve synchronization of the symbol clock. The embodiment of the present disclosure can quickly and accurately achieve synchronization of the symbol clock, so that the receiver can correctly receive and demodulate the data sent by the transmitter, improve the demodulation performance of the receiver, and improve the accuracy and efficiency of data communication.

[0057] In a possible implementation, the digital baseband signal may be a GFSK (Gauss frequency shift keying) baseband signal, and the symbol synchronization circuit may be applied to a Bluetooth chip or other chips. Bluetooth uses GFSK modulation technology, which originates from FSK (Frequency Shift Keying) technology. GFSK Gaussian frequency shift keying modulation is a digital modulation method that performs FSK modulation after pre-modulation and filtering of input data by a Gaussian low-pass filter. While maintaining a constant amplitude, it can control the spectrum of the modulated signal by changing the 3dB bandwidth of the Gaussian low-pass filter, and has the desired characteristics of wireless communication systems such as constant amplitude envelope, concentrated power spectrum, and narrow spectrum.

[0058] See also Figure 2 , Figure 2 FIG. 1 is a block diagram of a symbol synchronization circuit according to an embodiment of the present disclosure. In a possible implementation, as shown in FIG. Figure 2 As shown, the differential phase detection module 10 may include:

[0059] The phase detection subunit 110 is used to perform phase detection processing on the digital baseband signal to obtain a phase signal;

[0060] The differential subunit 120 is connected to the phase detector subunit 110 and is used to perform differential processing on the phase signal to obtain the frequency deviation signal.

[0061] In one example, the phase detection subunit 110 may include a phase detection circuit, and the phase detection circuit may perform an arc tangent calculation on the digital baseband signal to obtain a phase signal in the digital baseband signal.

[0062] In one example, the differential subunit 120 may include a differential circuit, and the differential circuit may perform a differential operation on the phase signal to obtain a frequency deviation signal of the phase signal.

[0063] Through the differential phase detection module, the embodiment of the present disclosure can perform phase detection processing on the digital baseband signal to obtain a phase signal, and perform differential processing on the phase signal to obtain the frequency deviation signal.

[0064] In a possible implementation, Figure 2 As shown, the DC component removal module 20 may include:

[0065] A DC component acquisition subunit 210, configured to perform a sliding average filtering process on the frequency deviation signal to obtain the DC component;

[0066] The DC component removal subunit 220 is electrically connected to the DC component acquisition subunit 210, and is used to remove the DC component in the frequency deviation signal to obtain a processed frequency deviation signal.

[0067] In one example, the DC component acquisition subunit 210 may include a sliding window filter unit to acquire the DC component. The sliding window filter unit may be implemented by a digital circuit.

[0068] In one example, the DC component removal subunit 220 may include a DC component removal circuit, which may remove the DC component in the frequency deviation signal.

[0069] It should be noted that the embodiments of the present disclosure do not limit the specific implementations of the sliding window filtering unit and the DC component removal circuit, and those skilled in the art can implement them as needed and with reference to relevant technologies.

[0070] In one example, the embodiment of the present disclosure can also remove the DC component in the frequency deviation signal based on the peak and trough detection method. For example, the DC component acquisition subunit can perform peak detection on the frequency deviation signal to obtain the first peak value and the first trough value of the frequency deviation signal, and obtain DC component information based on the first peak value and the first trough value. When the first peak value and the first trough value are detected, they are used to filter the phase signal and obtain a stable DC component through the DC component information.

[0071] In one example, the DC component acquisition subunit can determine whether the second peak value of the phase signal in the current time period is less than a first threshold. When the second peak value is less than the first threshold and the second peak value is greater than the first peak value, the first peak value is replaced by the second peak value, wherein the first peak value is the peak value of the phase signal before the current time period. It is determined whether the second trough value of the phase signal in the current time period is greater than the second threshold. When the second trough value is greater than the second threshold and the second trough value is less than the first trough value, the first trough value is replaced by the second trough value, wherein the first trough value is the trough value of the phase signal before the current time period. The average value of the first peak value and the first trough value is obtained, and the average value is used as the DC component information.

[0072] Of course, the above description of obtaining the DC component is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure.

[0073] The disclosed embodiment removes the DC component so that the subsequent interpolation module and the timing error detection module will not be affected by the carrier frequency deviation when determining the timing error, thereby improving the accuracy and precision.

[0074] In a possible implementation, Figure 2 As shown, the interpolation module 30 may include:

[0075] A linear interpolation unit 310 is used to perform linear interpolation on the frequency deviation signal with the DC component removed to obtain the interpolation processed signal; or

[0076] The cubic interpolation unit 320 is used to perform cubic interpolation on the frequency deviation signal with the DC component removed to obtain the interpolation processing signal.

[0077] The interpolation module 30 operates at twice the symbol rate.

[0078] In one example, the linear interpolation unit 310 and the cubic interpolation unit 320 can both be implemented by digital circuits. For example, the linear interpolation unit 310 and the cubic interpolation unit 320 may include an interpolation filter (Interpolator). The interpolation filter can perform linear interpolation on the frequency deviation signal with the DC component removed based on a linear interpolation method to obtain the interpolation processing signal, or perform cubic interpolation on the frequency deviation signal with the DC component removed based on a cubic interpolation method to obtain the interpolation processing signal.

[0079] In a possible implementation, Figure 2 As shown, the timing error detection module 40 may include:

[0080] A first high-pass filter 410 is used to perform high-pass filtering on the frequency deviation signal with the DC component removed to obtain a sideband energy value of a first sampling point;

[0081] A second high-pass filter 420 is used to perform high-pass filtering on the frequency deviation signal with the DC component removed to obtain a sideband energy value of a second sampling point;

[0082] The timing error determination unit 430 is connected to the first high-pass filter and the second high-pass filter, and is used to determine the timing error information according to the sideband energy value of the first sampling point and the sideband energy value of the second sampling point.

[0083] In one example, the first sampling point may be at a positive Nyquist frequency, and the second sampling point may be at a negative Nyquist frequency.

[0084] The disclosed embodiment obtains the sideband energy at the positive and negative Nyquist frequencies respectively through two high-pass filters, so as to quickly and accurately obtain the sideband energy values ​​of the two sampling points, and extracts the timing error by using the principle of maximizing the sideband energy.

[0085] In a possible implementation, both the first high-pass filter and the second high-pass filter can be used to obtain the sideband energy value of the corresponding sampling point based on the product of the sideband energy value of the corresponding sampling point of the previous symbol and the first preset parameter, and the sum of the frequency deviation signal with the DC component removed.

[0086] In an example, the sideband energy value of the first sampling point may be obtained by Formula 1, and the sideband energy value of the second sampling point may be obtained by Formula 2.

[0087] t1(n)=k*t1(n-1)+x(n) Formula 1

[0088] t2(n)=k*t2(n-1)+x(n) Formula 1

[0089] Among them, t1(n) represents the sideband energy value of the first sampling point of symbol n, t1(n-1) represents the sideband energy value of the first sampling point of the previous symbol of symbol n, k represents the first preset parameter, x(n) represents the frequency deviation signal with the DC component removed, t2(n) represents the sideband energy value of the second sampling point of symbol n, and t2(n-1) represents the sideband energy value of the second sampling point of the previous symbol of symbol n.

[0090] In a possible implementation manner, the timing error determination unit is further configured to determine the timing error information according to a product of a sideband energy value at the first sampling point, a sideband energy value at the second sampling point, and a second preset parameter.

[0091] In an example, the timing error information can be obtained by Formula 3.

[0092] ted(n)=m*t1(n)*t2(n) Formula 3

[0093] Among them, ted(n) represents the timing error information of symbol n, and m represents the second preset parameter.

[0094] In an example, the timing error determination unit 430 may include a multiplication circuit to realize the product of the sideband energy value of the first sampling point, the sideband energy value of the second sampling point, and a second preset parameter.

[0095] In a possible implementation manner, the first preset parameter is any value between -0.85 and -0.95, and the second preset parameter is any value between 0.1 and 0.25.

[0096] By setting the first preset parameter to any value between -0.85 and -0.95, and setting the second preset parameter to any value between 0.1 and 0.25, the loop of the symbol synchronization circuit in the embodiment of the present disclosure has a higher convergence speed.

[0097] In one example, the first preset parameter is preferably -0.95, and the second preset parameter is preferably 0.25, so that the loop has the fastest convergence speed and higher stability.

[0098] In a possible implementation, the loop filter module 50 may include a loop filter (LPF), and the loop filter filters the timing error information by using a proportional integral filtering method.

[0099] In a possible implementation, the numerically controlled oscillator module 60 may include a numerically controlled oscillator (NCO), and may also be used for:

[0100] In case the output of the numerically controlled oscillator overflows, a fractional delay interval is determined, and the interpolation coefficient is determined according to the fractional delay interval.

[0101] The embodiments of the present disclosure do not limit the specific implementation of the loop filter module and the digital control oscillation module, and those skilled in the art can implement them according to relevant technologies.

[0102] The disclosed embodiment obtains a frequency deviation signal by performing differential phase detection on a baseband signal. After removing the DC component of the frequency deviation signal, the signal is processed by an interpolation filter and used as an input for timing error detection. Because the interpolator interpolates the frequency deviation signal in the real domain, the hardware complexity is reduced by half compared with a traditional interpolator for complex signals.

[0103] The interpolator of the disclosed embodiment operates at twice the symbol rate, uses two high-pass filters to calculate the sideband energy at the positive and negative Nyquist frequencies respectively, and uses the principle of maximizing the sideband energy to extract the timing error. The original data at the GFSK transmitter is usually whitened, so it can be ensured that there are frequent zero crossings between the previous and next symbols. At the same time, before performing zero crossing detection, the DC component introduced by the carrier frequency deviation is removed, so the timing error detector is not affected by the carrier frequency deviation. The detected timing error is fed back to the interpolation filter after passing through the loop filter, so that the sampling clock of the new sampling value is continuously adjusted, and finally the synchronization of the symbol clocks at the sending and receiving ends is completed.

[0104] According to one aspect of the present disclosure, a receiver is provided, the receiver comprising:

[0105] The symbol synchronization circuit.

[0106] The symbol synchronization circuit and the receiver of the embodiments of the present disclosure may be arranged in an electronic device, and the electronic device may be provided as a terminal, a server or other forms of devices.

[0107] Figure 3 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0108] Reference Figure 3 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0109] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0110] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0111] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0112] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0113] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0114] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0115] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of the components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a complementary metal oxide semiconductor (CMOS) or a charge coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0116] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as a wireless network (WiFi), a second generation mobile communication technology (2G) or a third generation mobile communication technology (3G), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0117] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0118] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 804 including computer program instructions, which can be executed by a processor 820 of an electronic device 800 to perform the above method.

[0119] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0120] For example, the electronic device 1900 may be provided as a server. Figure 4 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0121] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OSX TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0122] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0123] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A symbol synchronization circuit, characterized in that: The circuit comprises: A differential phase detection module is used to perform differential phase detection on the digital baseband signal to obtain a frequency deviation signal; A DC component removal module, connected to the differential phase detection module, for removing the DC component in the frequency deviation signal; An interpolation module, connected to the DC component removal module, for performing interpolation processing on the frequency deviation signal with the DC component removed to obtain an interpolation processing signal; A timing error detection module, connected to the interpolation module, configured to perform high-pass filtering on the interpolation processing signal to obtain the sideband energy of the interpolation processing signal at different sampling points, and determine the timing error information according to the sideband energy at different sampling points; A loop filtering module, connected to the timing error detection module, for filtering the timing error information; A digitally controlled oscillation module, connected to the loop filter module, for accumulating the filtered timing error information to obtain a corresponding interpolation coefficient; The interpolation module is also used to adjust the sampling clock of the interpolation process according to the interpolation coefficient to achieve synchronization of the symbol clock. The timing error detection module includes: a first high-pass filter, used to perform high-pass filtering on the frequency deviation signal with the DC component removed to obtain the sideband energy value of the first sampling point; a second high-pass filter, used to perform high-pass filtering on the frequency deviation signal with the DC component removed to obtain the sideband energy value of the second sampling point; a timing error determination unit, connected to the first high-pass filter and the second high-pass filter, used to determine the timing error information according to the sideband energy value of the first sampling point and the sideband energy value of the second sampling point, The first high-pass filter and the second high-pass filter are both used to obtain the sideband energy value of the corresponding sampling point according to the product of the sideband energy value of the corresponding sampling point of the previous symbol and the first preset parameter and the sum of the frequency offset signal with the DC component removed; the timing error determination unit is also used to determine the timing error information according to the product of the sideband energy value of the first sampling point, the sideband energy value of the second sampling point and the second preset parameter. The first preset parameter is any value between -0.85 and -0.95, and the second preset parameter is any value between 0.1 and 0.

25.

2. The circuit according to claim 1, characterized in that The differential phase detection module comprises: A phase detection subunit, used for performing phase detection processing on the digital baseband signal to obtain a phase signal; The differential subunit is connected to the phase detection subunit and is used to perform differential processing on the phase signal to obtain the frequency deviation signal.

3. The circuit according to claim 1, characterized in that The DC component removal module comprises: A DC component acquisition subunit, used for performing sliding average filtering on the frequency deviation signal to obtain the DC component; The DC component removal subunit is electrically connected to the DC component acquisition subunit and is used to remove the DC component in the frequency deviation signal to obtain a processed frequency deviation signal.

4. The circuit according to claim 1, characterized in that The interpolation module comprises: A linear interpolation unit, used to perform linear interpolation on the frequency deviation signal with the DC component removed to obtain the interpolation processed signal; or A cubic interpolation unit is used to perform cubic interpolation on the frequency deviation signal with the DC component removed to obtain the interpolation processing signal. Wherein, the interpolation module operates at twice the symbol rate.

5. The circuit according to claim 1, characterized in that The loop filter module includes a loop filter, and the loop filter filters the timing error information by using a proportional integral filtering method.

6. The circuit according to claim 1, characterized in that The digital controlled oscillation module includes a digital controlled oscillator, and is further used for: In case the output of the numerically controlled oscillator overflows, a fractional delay interval is determined, and the interpolation coefficient is determined according to the fractional delay interval.

7. A receiver, characterized in that: The receiver comprises: A symbol synchronization circuit as claimed in any one of claims 1 to 6.

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