A network processing chip package detection device and method

Abstract

The application discloses a network processing chip joint sealing detection device, which comprises a network processor joint sealing chip, joint sealing pins and JTAG pins, wherein the network processor joint sealing chip comprises a general multi-core processor core particle, a reconfigurable hardware acceleration core particle, a configurable switch core particle and a network interface core particle. The reconfigurable hardware acceleration core particle inside the network processor joint sealing chip is connected with the general multi-core processor core particle, the configurable switch core particle and the network interface core particle inside the network processor joint sealing chip, and the running state, the physical link connectivity, the signal integrity and the fault location of the general multi-core processor core particle, the reconfigurable hardware acceleration core particle, the configurable switch core particle and the network interface core particle can be monitored in real time, so that the detection time and the test cost of the network processing chip are effectively reduced, and the problem that the test time of different core particle dies of the chip is very long and the test cost is very high is solved.

Description

A device and method for detecting the packaging of network processing chips Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, specifically to a device and method for testing the packaging of network processing chips. Background Technology

[0002] With the rapid development of deep submicron technology, network processors have evolved from the first generation, which was geared towards low- and mid-range switching and routing, to the second generation, which adopted a unified external interface standard, to the third generation, which adopts on-chip multi-core / many-core and high-speed memory integration. The current network processor internal structure widely adopts three main parts: general-purpose multi-core processing module, configurable interface, and hardware accelerator engine. They are interconnected through the internal system high-performance bus and built in a monolithic integration manner. Performance and functionality are guaranteed based on two levels: advanced system architecture and acceleration engine design. However, this approach has a complex internal structure and a long iteration cycle.

[0003] With the increasing number of high-speed service types, the surge in service traffic, and the convergence of multiple services, network processing chips are forced to continuously iterate to meet the needs of application networks. Currently, single-chip network processors (including replacements for switching chips) are difficult to achieve a good compromise in terms of high performance, determinism, flexibility, and development cycle.

[0004] In the early days, due to technological limitations, finished chips were usually packaged as a single chip. Now, multi-chip co-packaging technology has emerged, which can package multiple chips together. Due to its advantages such as low manufacturing cost, high design and manufacturing process flexibility, and ease of implementation, multi-chip co-packaging technology has been widely used. Based on multi-chip co-packaging technology, network processors are decomposed into relatively independent and mature bare dies, and mature general-purpose multi-core processor chips, reconfigurable hardware acceleration chips, and configurable switching chips are integrated together. This effectively reduces the development risk, cost, and R&D barriers of network processor chips. Through the flexible recombination of multiple chips, it provides optimized layout options for performance and functions, thereby supporting faster iteration cycles and on-demand business deployment capabilities.

[0005] Compared to single-chip integration, network processor chips package multiple die-on chips together. Due to the limited number of pins, only some die-on chip pins can be brought out of the package for easy testing. The interconnects between the die-on chips inside are more difficult to test, especially after the chips are packaged together. The traditional method of using X-ray inspection to check the interconnects between die-on chips is a waste of a lot of time and testing costs when the number of packaged chips is large.

[0006] Currently, ATE (Automatic Test Equipment) is commonly used to check the integrity of integrated circuit functions within chips and ensure the quality of chip manufacturing. Network processor chips often package four or five bare dies, which leads to an increasing complexity and test time for ATE testing, resulting in rising test costs. ATE testing is also relatively ineffective in testing communication links between bare dies, and there may be interactions between different bare dies for test signals, making the test complex and time-consuming. Summary of the Invention

[0007] The purpose of this invention is to provide a network processing chip packaging and testing device and method, which has the advantages of being able to detect the operating status, physical link connectivity, signal integrity, fault location, and real-time monitoring of the chip die. It solves the problem that the test signals may interact between different chip dies, resulting in complex testing, long testing time, and high testing cost.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a network processor chip packaging detection device, comprising a network processor packaging chip, packaging pins and JTAG pins, wherein the network processor packaging chip includes a general-purpose multi-core processor chip, a reconfigurable hardware acceleration chip, a configurable switching chip and a network interface chip.

[0009] Preferably, the general-purpose multi-core processor chip, the configurable switching chip, and the network interface chip are all connected to the reconfigurable hardware acceleration chip, the network processor packaged chip is connected to the packaged pins via connecting wires, and the JTAG pins are connected to the reconfigurable hardware acceleration chip via connecting wires.

[0010] Preferably, the general-purpose multi-core processor core is mainly a multi-core CPU, used for user control, network data processing, routing management, and management and control of other cores in network processing.

[0011] Preferably, the reconfigurable hardware acceleration core is used to connect other cores such as general-purpose multi-core processor cores, configurable switching cores, and network interface cores. All data needs to be forwarded through the reconfigurable hardware acceleration core, which can not only meet the changing business needs, but also be used for detection of the operating status, physical link connectivity, signal integrity, fault location, and real-time monitoring of other cores.

[0012] Preferably, the network interface chip mainly provides various types of network interfaces for the network processor, such as Gigabit Ethernet, 10 Gigabit Ethernet, IIC, SPI, etc., but not limited to these interfaces, and converts the data of the network interface into the chip's internal transmission data format for data processing and exchange between other chips.

[0013] Preferably, the configurable switching core is mainly used for network switching table lookup, and supports user-defined mask matching and lookup for Ethernet layers 2 to 7 issued by general-purpose multi-core processor cores.

[0014] Preferably, the detection method includes the following steps:

[0015] Step S1: Load the automatic detection logic for the reconfigurable hardware acceleration chip through the JTAG pin to check whether the reconfigurable hardware acceleration chip can be loaded successfully. If it fails, the detection fails and the fault of the reconfigurable hardware acceleration chip can be located. If it succeeds, proceed to step S2.

[0016] The JTAG pin is an external pin of the network processing chip brought out by the reconfigurable hardware accelerator chip. It is the debugging pin of the reconfigurable hardware accelerator chip itself. Using the JTAG pin, the working status of the reconfigurable hardware accelerator chip can be directly detected, and it can be used as a detection module to detect the internal wiring and other chip status of the chip.

[0017] Step S2: The reconfigurable hardware acceleration chip collects the clock and reset status of the general multi-core processing chip core, network interface chip core, and configurable switching chip core through internal wiring. If it fails, the detection fails and the chip core with clock reset failure can be located. If it succeeds, proceed to step S3.

[0018] The reconfigurable hardware acceleration chip connects to the general-purpose multi-core processing chip core, network interface chip core, and configurable switching chip core via internal wiring. These connections include clock reset detection pins, which are no longer brought out to the packaged pins, thus reducing the number of external packaged pins and facilitating later testing.

[0019] Step S3: The reconfigurable hardware acceleration chip detects the physical communication link between itself and other chips through internal connections. If the detection fails, the physical link that could not be detected can be located. If the detection is successful, proceed to step S4.

[0020] Data communication between internal chips of a network processor co-packaged chip is mainly based on internal physical communication links, such as high-speed parallel bus, gigabit Ethernet, 10-gigabit Ethernet, PCIe interface, etc. The physical communication links between reconfigurable hardware acceleration chips and other chips can be detected to confirm whether both ends are ready and data communication can be carried out.

[0021] Step S4: The reconfigurable hardware acceleration chip detects signal integrity with other chips through internal connections. By comparing the values ​​of the transmitted and received data, the detection result is confirmed. If it fails, the detection fails and the chip with signal integrity fault can be located. If it succeeds, the next step of detection is performed.

[0022] After the physical communication link between the reconfigurable hardware acceleration chip and other chips is detected, data can be sent to other chips through the reconfigurable hardware acceleration chip. Other chips, with their interfaces set to internal loopback mode, will return the sent data to the reconfigurable hardware acceleration chip through the interface, thereby realizing the signal integrity detection of the physical communication link.

[0023] Step S5: The reconfigurable hardware acceleration chip detects the functionality of other chips through internal connections, sends functional data, compares the response data with the pre-made data, and confirms the detection result. If it fails, the detection fails and the chip with functional faults can be located. If it succeeds, the detection is completed automatically.

[0024] After the physical communication link between the reconfigurable hardware acceleration chip and other chips completes signal integrity detection, the other chips are set to normal mode. The reconfigurable hardware acceleration chip sends specific functional data, such as configuration messages. After receiving the specific functional data, the other chips generate corresponding response messages, such as configuration response messages. By comparing the pre-made response messages in the reconfigurable hardware acceleration chip, it can be determined whether the response is correct and meets the functional detection requirements.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] This invention connects the general-purpose multi-core processor chip, configurable switching chip, and network interface chip within the network processor encapsulated chip via a reconfigurable hardware acceleration chip. This allows for real-time monitoring of the operating status, physical link connectivity, signal integrity, and fault location of these components. This effectively reduces the testing time and cost of network processing chips and solves the problem of complex, time-consuming, and costly testing caused by interactions between different chip dies. Attached Figure Description

[0027] Figure 1 is a schematic diagram of a network processing chip packaging detection device according to the present invention;

[0028] Figure 2 is a schematic diagram of a network processing chip packaging detection method according to the present invention.

[0029] In the diagram: 1. Network processor packaged chip; 101. General-purpose multi-core processor chip; 102. Reconfigurable hardware acceleration chip; 103. Configurable switching chip; 104. Network interface chip; 2. Packaged pin; 3. JTAG pin. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] The network processor encapsulated chip 1, general-purpose multi-core processor chip 101, reconfigurable hardware acceleration chip 102, configurable switching chip 103, network interface chip 104, encapsulated pin 2, and JTAG pin 3 of the present invention are all general-purpose standard parts or parts known to those skilled in the art. Their structures and principles can be learned by those skilled in the art through technical manuals or conventional experimental methods.

[0032] Please refer to Figures 1-2. A network processing chip packaging detection device includes a network processor packaging chip 1, packaging pins 2 and JTAG pins 3. The network processor packaging chip 1 includes a general-purpose multi-core processor chip 101, a reconfigurable hardware acceleration chip 102, a configurable switching chip 103, and a network interface chip 104. The reconfigurable hardware acceleration chip 102 inside the network processor packaging chip 1 connects the general-purpose multi-core processor chip 101, the configurable switching chip 103, and the network interface chip 104 inside the network processor packaging chip 1. This allows for real-time monitoring of the operating status, physical link connectivity, signal integrity, and fault location of the general-purpose multi-core processor chip 101, the reconfigurable hardware acceleration chip 102, the configurable switching chip 103, and the network interface chip 104. This effectively reduces the detection time and testing cost of network processing chips and solves the problem that there may be interaction between different chip dies, leading to complex testing, long testing time, and high testing cost.

[0033] Specifically, the general-purpose multi-core processor chip 101, the configurable switching chip 103, and the network interface chip 104 are all connected to the reconfigurable hardware acceleration chip 102. The network processor package chip 1 is connected to the package pin 2 via a connecting wire, and the JTAG pin 3 is connected to the reconfigurable hardware acceleration chip 102 via a connecting wire.

[0034] Specifically, the general-purpose multi-core processor chip 101 is mainly a multi-core CPU used for user control, network data processing, routing management, and other chip management and control functions in network processing.

[0035] Specifically, the reconfigurable hardware acceleration core 102 is used to connect other cores such as the general-purpose multi-core processor core 101, the configurable switching core 103, and the network interface core 104. All data needs to be forwarded through the reconfigurable hardware acceleration core 102, which can not only meet the changing business needs, but also be used for the detection of the operating status, physical link connectivity, signal integrity, fault location, and real-time monitoring of other cores.

[0036] Specifically, the network interface chip mainly provides various types of network interfaces for the network processor, such as Gigabit Ethernet, 10 Gigabit Ethernet, IIC, SPI, etc., but not limited to these interfaces. It converts the data from the network interface into the chip's internal transmission data format for data processing and exchange between other chips.

[0037] Specifically, the configurable switching core 103 is mainly used for network switching table lookup, and supports user-defined mask matching and lookup for Ethernet layers 2 to 7 issued by the general-purpose multi-core processor core 101.

[0038] Specifically, the detection method includes the following steps:

[0039] Step S1: Load the automatic detection logic into the reconfigurable hardware acceleration chip 102 via JTAG pin 3 to check whether the reconfigurable hardware acceleration chip 102 can be loaded successfully. If it fails, the detection fails and the fault of the reconfigurable hardware acceleration chip 102 can be located. If it succeeds, proceed to step S2.

[0040] JTAG pin 3 is the pin outside the package of the network processing chip brought out by the reconfigurable hardware acceleration chip 102. It is the debugging pin of the reconfigurable hardware acceleration chip 102 itself. Using JTAG pin 3, the working status of the reconfigurable hardware acceleration chip 102 can be directly detected, and it can be used as a detection module to detect the status of the internal wiring and other chips of the packaged chip.

[0041] Step S2: The reconfigurable hardware acceleration chip 102 collects the clock and reset status of the general multi-core processing chip core, the network interface chip 104, and the configurable switching chip 103 through internal connections. If it fails, the detection fails and the chip with clock reset failure can be located. If it succeeds, proceed to step S3.

[0042] The reconfigurable hardware acceleration chip 102 is connected to the general-purpose multi-core processing chip core, the network interface chip 104, and the configurable switching chip 103 via internal wiring. These wirings include a clock reset detection pin. The clock reset detection pin is not brought out to the encapsulated pin 2, which reduces the number of external encapsulated pins 2 and facilitates later testing.

[0043] Step S3: The reconfigurable hardware acceleration chip 102 detects the physical communication link between itself and other chips through internal connections. If the detection fails, the physical link that could not be detected can be located. If the detection is successful, proceed to step S4.

[0044] Data communication between internal chips of the network processor co-packaged chip 1 is mainly based on internal physical communication links, such as: high-speed parallel bus, gigabit Ethernet, 10-gigabit Ethernet, PCIe interface, etc. The physical communication link between the reconfigurable hardware acceleration chip 102 and other chips can be detected to confirm whether both ends are ready and can perform data communication.

[0045] Step S4: The reconfigurable hardware acceleration chip 102 detects signal integrity with other chips through internal connections. By comparing the values ​​of the transmitted and received data, the detection result is confirmed. If it fails, the detection fails and the chip with signal integrity fault can be located. If it succeeds, the next detection step is performed.

[0046] After the physical communication link between the reconfigurable hardware acceleration chip 102 and other chips is detected, data can be sent to other chips through the reconfigurable hardware acceleration chip 102. Other chips, with their interfaces set to internal loopback mode, return the sent data to the reconfigurable hardware acceleration chip 102 through the interface, thereby realizing the signal integrity detection of the physical communication link.

[0047] Step S5: The reconfigurable hardware acceleration chip 102 detects the functionality of other chips through internal connections, sends functional data, compares the response data with the pre-made data, and confirms the detection result. If it fails, the detection fails and the chip with functional failure can be located. If it succeeds, the detection is completed automatically.

[0048] After the physical communication link between the reconfigurable hardware acceleration chip 102 and other chips completes signal integrity detection, the other chips are set to normal mode at the interface. The reconfigurable hardware acceleration chip 102 sends specific functional data, such as configuration messages. After receiving the specific functional data, the other chips generate corresponding response messages, such as configuration response messages. By comparing the pre-made response messages in the reconfigurable hardware acceleration chip 102, it can be determined whether the response is correct and whether it meets the functional detection requirements.

[0049] All standard parts used in this application can be purchased from the market, and can be customized according to the description and drawings. The specific connection methods of each part adopt conventional methods such as bolts, rivets, and welding that are mature in the prior art. The machinery, parts and equipment adopt conventional models in the prior art. The control method is automatic control through a controller. The control circuit of the controller can be implemented by simple programming by those skilled in the art and is common knowledge in the field. Since this application is mainly used to protect mechanical devices, the control method and circuit connection will not be explained in detail in this application.

[0050] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0051] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for detecting the packaging of network processing chips, characterized in that: The detection method is based on a network processor chip packaging detection device. The detection device includes a network processor packaging chip (1), packaging pins (2), and JTAG pins (3). The network processor packaging chip (1) includes a general-purpose multi-core processor chip (101), a reconfigurable hardware acceleration chip (102), a configurable switching chip (103), and a network interface chip (104). The general-purpose multi-core processor chip (101), the configurable switching chip (103), and the network interface chip (104) are all connected to the reconfigurable hardware acceleration chip (102). The network processor packaging chip (1) is connected to the packaging pins (2) via connecting wires, and the JTAG pins (3) are connected to the packaging pins (2) via connecting wires. The reconfigurable hardware acceleration core (102) is connected to the general-purpose multi-core processor core (101), which is a multi-core CPU used for user control, network data processing, routing management, and management and control functions of other cores in network processing. The reconfigurable hardware acceleration core (102) is used to connect the general-purpose multi-core processor core (101), the configurable switching core (103), and the network interface core (104). All data needs to be forwarded through the reconfigurable hardware acceleration core (102), which not only meets the changing business needs, but also detects the operating status, physical link connectivity, signal integrity, fault location, and real-time monitoring of other cores. The network interface core provides various types of network processors. The network interface converts the network interface data into the chip's internal transmission data format for data processing and exchange between other chips; the configurable switching chip (103) is used for network switching lookup, supporting user-defined mask matching lookup for Ethernet layers 2 to 7 issued by the general-purpose multi-core processor chip (101); the detection method includes the following steps: Step S1: Load automatic detection logic into the reconfigurable hardware acceleration chip (102) through the JTAG pin (3) to check whether the reconfigurable hardware acceleration chip (102) can be loaded successfully. If it fails, the detection fails, and the fault of the reconfigurable hardware acceleration chip (102) can be located. If it succeeds, proceed to step S2; JTAG pin Pin (3) is the pin outside the package of the network processing chip brought out by the reconfigurable hardware acceleration chip (102). It is the debugging pin of the reconfigurable hardware acceleration chip (102) itself. Using JTAG pin (3), the working status of the reconfigurable hardware acceleration chip (102) can be directly detected. It can be used as a detection module to detect the internal connection of the packaged chip and the status of other chips. Step S2: The reconfigurable hardware acceleration chip (102) collects the clock and reset status of the general multi-core processing chip core, the network interface chip (104), and the configurable switching chip (103) through the internal connection. If it fails, the detection fails and the chip with clock reset failure can be located. If it succeeds, it proceeds to step S3.The reconfigurable hardware acceleration chip (102) is connected to the general-purpose multi-core processing chip core, the network interface chip (104), and the configurable switching chip (103) via internal wiring. These connections include a clock reset detection pin, which is not brought out to the encapsulated pin (2), thus reducing the number of external encapsulated pins (2) and facilitating later testing. Step S3: The reconfigurable hardware acceleration chip (102) detects the physical communication link between itself and other chips via internal wiring. If the detection fails, the physical link that cannot be detected can be located. If successful, proceed to step S4; Data communication between internal chips of the network processor co-packaged chip (1) is based on the internal physical communication link. The reconfigurable hardware acceleration chip (102) performs link detection on the physical communication link between other chips to confirm whether both ends are ready and to perform data communication; Step S4: The reconfigurable hardware acceleration chip (102) detects the signal integrity between other chips through internal connections. By comparing the values ​​of the sent data and the received data, the detection result is confirmed. If it fails, the detection fails, and the chip with signal integrity failure can be located. If successful, proceed to the next step of detection; after the physical communication link between the reconfigurable hardware acceleration chip (102) and other chips is detected, data is sent to other chips through the reconfigurable hardware acceleration chip (102). Other chips, with their interfaces set to internal loopback mode, return the sent data to the reconfigurable hardware acceleration chip (102) through the interface, thereby realizing the signal integrity detection of the physical communication link; Step S5: The reconfigurable hardware acceleration chip (102) detects the functional detection between itself and other chips through internal connections, sends functional data, response data and pre-built data. The test results are compared and confirmed. If the test fails, the test fails and the faulty chip can be located. If the test succeeds, the test is completed automatically. After the physical communication link between the reconfigurable hardware acceleration chip (102) and other chips completes the signal integrity test, the other chips are set to normal mode at the interface. The reconfigurable hardware acceleration chip (102) sends functional data. After receiving the functional data, the other chips generate corresponding response messages. By comparing the pre-made response messages in the reconfigurable hardware acceleration chip (102), it can be determined whether the response is correct and whether it meets the functional test requirements.

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