An array substrate and a display device

Abstract

The present invention discloses an array substrate and a display device. In a specific embodiment, the array substrate includes a substrate, a display area and a non-display area. The non-display area includes a bonding area and a fan-out routing area. The fan-out routing area includes a first routing area, a second routing area and a third routing area. The fan-out routing area further includes a plurality of fan-out line groups arranged in an array along the second direction. One end of the fan-out line group is connected to the display area and sequentially passes through the first routing area, the second routing area and the third routing area to be connected to the bonding area. Among them, the fan-out line group includes a first fan-out line, a second fan-out line and a third fan-out line. Two fan-out lines of the same type in two fan-out line groups located in the second routing area overlap at least partially in the projection on the substrate to form a first overlapping area, and the two fan-out lines at each overlapping area are arranged in different layers.

Description

Technical Field

[0001] The present invention relates to the field of display technologies. More specifically, it relates to an array substrate and a display device. Background Art

[0002] Currently, in order to improve the smooth experience of the screen for mobile phones or tablet products, the refresh rate of the screen is getting higher and higher. For the increasing requirements of the refresh rate, one of the major challenges is the problem of visible display non-uniformity (Mura) in the display screen of the display device under high-frequency applications. Figure 1 The schematic diagram of the defective display non-uniformity generated in the display screen is shown. Summary of the Invention

[0003] The purpose of the present invention is to provide an array substrate and a display device to solve at least one of the problems existing in the prior art.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] In a first aspect of the present invention, an array substrate is provided, including a substrate, a display area disposed on the substrate, and at least a part of a non-display area surrounding the display area. The non-display area includes a bonding area and a fan-out routing area disposed between the bonding area and the display area.

[0006] The fan-out routing area includes: a first routing area, a second routing area, and a third routing area arranged in sequence along a first direction perpendicular to the second direction. The first routing area is located on the side close to the display area.

[0007] The fan-out routing area further includes a plurality of fan-out line groups arranged in an array along the second direction. One end of each fan-out line group is connected to the display area, sequentially passing through the first routing area, the second routing area, and the third routing area, and the other end is connected to the bonding area.

[0008] Wherein, each fan-out line group includes a first fan-out line, a second fan-out line, and a third fan-out line arranged in sequence along the second direction.

[0009] Two first fan-out lines in two fan-out line groups located in the second routing area overlap at least partially in the projection on the substrate to form a first overlapping area, and the two first fan-out lines at the first overlapping area are arranged on different layers.

[0010] Two second fan-out lines in two fan-out line groups located in the second routing area overlap at least partially in the projection on the substrate to form a second overlapping area, and the two second fan-out lines at the first overlapping area are arranged on different layers.

[0011] Two third fan-out lines in the two fan-out line groups located in the second wiring area overlap at least partially in the projection on the substrate to form a third overlapping area, and the two third fan-out lines at the third overlapping area are arranged on different layers.

[0012] Furthermore, the array substrate further includes a first conductive layer formed on the substrate, a first insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the first insulating layer.

[0013] At the first overlapping area, one of the first fan-out lines is located on the first conductive layer or the second conductive layer, and the other first fan-out line is located on the second conductive layer or the first conductive layer.

[0014] At the second overlapping area, one of the second fan-out lines is located on the first conductive layer or the second conductive layer, and the other second fan-out line is located on the second conductive layer or the first conductive layer.

[0015] At the third overlapping area, one of the third fan-out lines is located on the first conductive layer or the second conductive layer, and the other third fan-out line is located on the second conductive layer or the first conductive layer.

[0016] Furthermore, the display area includes a plurality of display terminals disposed at a position surrounded by the non-display area, and the display terminals are arranged along a second direction.

[0017] The first fan-out line includes a first connection portion located in the first wiring area and connecting the display terminal, the second fan-out line includes a second connection portion located in the first wiring area and connecting the display terminal, and the third fan-out line includes a third connection portion located in the first wiring area and connecting the display terminal.

[0018] When any two connection portions in the two fan-out line groups located in the first wiring area form a fourth overlapping area in the orthographic projection on the substrate, the two connection portions at the fourth overlapping area are located on different layers.

[0019] Furthermore, the bonding area is provided with a plurality of bonding terminals arranged along the second direction.

[0020] The first fan-out line further includes a seventh connection portion located in the third wiring area and connecting the bonding terminal, the second fan-out line further includes an eighth connection portion located in the third wiring area and connecting the bonding terminal, and the third fan-out line further includes a ninth connection portion located in the third wiring area and connecting the bonding terminal.

[0021] When any two fan-out lines in the two fan-out line groups located in the third wiring area form a fifth overlapping area in the orthographic projection on the substrate, the two connection portions at the fifth overlapping area are located on different layers.

[0022] Further, the first fan-out line further includes a fourth connection portion located in the second wiring area. The fourth connection portion includes the first fan-out line corresponding to the first overlapping area. The fourth connection portion is connected to the first connection portion through a first via hole and is connected to the seventh connection portion through a fourth via hole;

[0023] The second fan-out line further includes a fifth connection portion located in the second wiring area. The fifth connection portion includes the second fan-out line corresponding to the second overlapping area. The fifth connection portion is connected to the second connection portion through a second via hole and is connected to the eighth connection portion through a fifth via hole;

[0024] The third fan-out line further includes a sixth connection portion located in the second wiring area. The sixth connection portion further includes the third fan-out line corresponding to the third overlapping area. The sixth connection portion is connected to the third connection portion through a third via hole and is connected to the ninth connection portion through a sixth via hole.

[0025] Further, when the orthographic projections of the connection portions located in the first wiring area on the substrate do not overlap each other,

[0026] the first connection portion, the second connection portion, and the third connection portion are located in the first conductive layer or the second conductive layer,

[0027] the first via hole, the second via hole, and the third via hole are arranged in sequence in the second direction.

[0028] Further, when the orthographic projections of the connection portions located in the third wiring area on the substrate do not overlap each other,

[0029] the connection portions located in the third wiring area are located in the first conductive layer or the second conductive layer, and the fourth via hole, the fifth via hole, and the sixth via hole are arranged in sequence in the second direction.

[0030] Further, in the two fan-out line groups located in the first wiring area, when any two of the first connection portion, the second connection portion, and the third connection portion form a fourth overlapping area in the orthographic projection on the substrate, among the two connection portions forming the fourth overlapping area, one connection portion is located in the first conductive layer or the second conductive layer, and the other connection portion is located in the second conductive layer or the first conductive layer.

[0031] Further, in the two fan-out line groups located in the first wiring area,

[0032] the first via hole corresponding to the first connection portion of one fan-out line group and the first via hole corresponding to the first connection portion of the other fan-out line group are arranged adjacent to each other,

[0033] The second vias corresponding to the second connection parts of one of the fan-out wire groups are arranged adjacent to the second vias corresponding to the second connection parts of the other fan-out wire group.

[0034] The third vias corresponding to the third connection parts of one of the fan-out wire groups are arranged adjacent to the third vias corresponding to the third connection parts of the other fan-out wire group.

[0035] Furthermore, in the two fan-out wire groups located in the third wiring area, when any two of the seventh connection part, the eighth connection part, and the ninth connection part form a fifth overlapping area in the orthographic projection on the substrate, among the two connection parts forming the fifth overlapping area S5, one connection part is located in the first conductive layer or the second conductive layer, and the other connection part is located in the second conductive layer or the first conductive layer.

[0036] Furthermore, in the two fan-out wire groups located in the third wiring area,

[0037] The fourth vias corresponding to the seventh connection part of one of the fan-out wire groups are arranged adjacent to the fourth vias corresponding to the seventh connection part of the other fan-out wire group;

[0038] The fifth vias corresponding to the eighth connection part of one of the fan-out wire groups are arranged adjacent to the fifth vias corresponding to the eighth connection part of the other fan-out wire group;

[0039] The sixth vias corresponding to the ninth connection part of one of the fan-out wire groups are arranged adjacent to the sixth vias corresponding to the ninth connection part of the other fan-out wire group;

[0040] When any two of the seventh connection part, the eighth connection part, and the ninth connection part form an overlapping area in the orthographic projection on the substrate, among the two connection parts forming the overlapping area, one connection part is located in the first conductive layer or the second conductive layer, and the other is located in the second conductive layer or the first conductive layer.

[0041] Furthermore, the display area includes driving thin film transistors located on the substrate, and the driving thin film transistors include:

[0042] Gate electrodes,

[0043] A gate insulating layer covering the gate electrodes; and

[0044] Source-drain electrode layers located on the gate electrodes;

[0045] Wherein, the first conductive layer is arranged on the same layer as the gate electrodes, the second conductive layer is arranged on the same layer as the source-drain electrode layers, and the first insulating layer is arranged on the same layer as the gate insulating layer.

[0046] Further, the central axes of the two first fan-out lines at the first overlapping region coincide in the orthographic projection on the substrate, the central axes of the two second fan-out lines at the second overlapping region coincide in the orthographic projection on the substrate, and the central axes of the two third fan-out lines at the third overlapping region coincide in the orthographic projection on the substrate.

[0047] Further, the first fan-out line and the second fan-out line are data signal lines, and the polarities of the first fan-out line and the second fan-out line data signal lines are opposite;

[0048] The third fan-out line is a touch signal line.

[0049] In a second aspect of the present invention, a display device is provided, including an array substrate as in the first aspect of the present invention.

[0050] The beneficial effects of the present invention are as follows:

[0051] In the technical solution of the present invention, the traces connecting the third connection region between the first trace region and the second trace region are designed, and each fan-out line of the fan-out line group located in the third trace region is designed, so that in adjacent fan-out line groups, the fan-out lines of the same type form at least partial overlap in the orthographic projection on the substrate, and the fan-out lines of the same type in the overlapping region are arranged in different layers. This setting can reduce the coupling of the fan-out lines, improve the display defect, effectively reduce the Panel power consumption, and has a wide application prospect. Description of the Drawings

[0052] The following further describes in detail the specific embodiments of the present invention with reference to the drawings.

[0053] Figure 1 A schematic diagram showing the display non-uniformity defect generated by the display screen of the related art;

[0054] Figure 2 A top view schematic diagram of the display area of the array substrate of the related art;

[0055] Figure 3 A schematic diagram showing the waveform changes of the pixel electrode and the common electrode when writing a gate signal at refresh frequencies of 60 Hz and 120 Hz;

[0056] Figure 4 A schematic diagram showing the voltage jump of the pixel under a heavy load screen;

[0057] Figure 5 A top view schematic diagram of the array substrate according to an embodiment of the present invention;

[0058] Figure 6 A schematic diagram showing the arrangement of the fan-out trace region according to an embodiment of the present invention;

[0059] Figure 7 Another layout schematic diagram of the first routing area according to an embodiment of the present invention;

[0060] Figure 8 Another layout diagram of the first routing area according to an embodiment of the present invention;

[0061] Figure 9 Showing an embodiment of the present invention Figure 8 Layer structure schematic diagram at the BB cross-section;

[0062] Figure 10 Another layout schematic diagram of the third routing area according to an embodiment of the present invention;

[0063] Figure 11 Another layout schematic diagram of the third routing area according to an embodiment of the present invention;

[0064] Figure 12 Showing an embodiment of the present invention Figure 11 Layer structure schematic diagram at the CC cross-section;

[0065] Figure 13 Showing an embodiment of the present invention Figure 6 Layer structure schematic diagram at the DD cross-section;

[0066] Figure 14 Another layout schematic diagram of the second routing area according to an embodiment of the present invention;

[0067] Figure 15a Layout schematic diagram of the fan-out routing area in the related art;

[0068] Figure 15b Showing Figure 15a Layer structure schematic diagram at the EE cross-section;

[0069] Figure 16 Showing Figure 15a Coupling capacitance schematic diagram between fan-out routings at the EE cross-section;

[0070] Figure 17 Showing Figure 11 Coupling capacitance schematic diagram between fan-out routings at the CC cross-section;

[0071] Figure 18 Schematic diagram of the screen display of the array substrate according to an embodiment of the present invention;

[0072] Figure 19 Another layout schematic diagram of the fan-out routing area according to an embodiment of the present invention;

[0073] Figure 20 Schematic diagram of the structure of the thin film transistor in the display area according to an embodiment of the present invention. DETAILED DESCRIPTION

[0074] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with the embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present invention.

[0075] for Figure 1 The inventors have conducted a large number of experiments and studied the circuits of the display devices to propose that the main reasons for the poor display are: the voltage of the common electrode (Vcom) of the pixel is coupled and pulled off, and the voltage of the common electrode cannot be restored in time, resulting in the continuous accumulation of voltage offset, making the coupling problem of Vcom more serious, resulting in visually visible Mura-type defects.

[0076] The inventors have further studied the problem of voltage deviation of the common electrode of the pixel and proposed that in the display device, there is a parasitic capacitance between the common electrode and the metal wiring layer above it, such as the pixel signal line (Source line). When the voltage of the Source line jumps, Vcom will be coupled with the voltage jump of the Source line and deviate from the original set voltage. After coupling, Vcom will be rewritten into the set voltage by the signal output by the driver chip. Due to the existence of Vcom load, such as the resistance of the Vcom wiring, and the parasitic capacitance between Vcom and the metal wiring layer, there is a delay in the Vcom write signal. Under the application of high refresh frequency, the signal writing time of a row of pixels is reduced, and Vcom cannot be restored to the set voltage before the signal is written, causing the voltage difference between the pixel electrode and Vcom to deviate from the set grayscale voltage, resulting in a difference between the display brightness of the display screen and the set grayscale brightness.

[0077] Taking the refresh rates of 60 Hz and 120 Hz as examples, the display device adopts a self-capacitive touch control solution, and the top view schematic diagram of the display area of ​​the array substrate is as follows: Figure 2 As shown, the common electrode Vcom is divided into several blocks, which are arranged in an array in the row direction and the column direction in the form of touch blocks, and each block is connected to the signal source end of the driving chip through a touch signal line (Tx signal line).

[0078] Figure 3 The following is a schematic diagram of the waveform changes of the pixel electrode and the common electrode when writing the gate signal at a refresh frequency of 60 Hz and 120 Hz. Figure 3As shown, when the gate is turned on, the pixel electrode is charged and pulled high. Due to the parasitic capacitance between the pixel electrode and the common electrode, when the pixel electrode is charged and pulled high, Vcom is also coupled and pulled high, and then the set voltage is rewritten through the IC signal source. As can be seen from the foregoing, due to the existence of the Vcom load, such as the resistance of the Vcom trace, or the parasitic capacitance between Vcom and the metal trace layer, it takes a certain amount of time for Vcom to recover after being pulled high, and there is a delay in this recovery time.

[0079] As Figure 3 shown, at 60 Hz, the time for each row of the gate to be turned on is relatively long. When Vcom is pulled high, Vcom can recover to the set value during the period when the gate is turned on. The voltage difference between the pixel electrode Pixel and the common electrode Vcom is the designed value, and the voltage difference remains stable, and the displayed gray scale brightness is normal.

[0080] When the refresh rate is 120 Hz, the time for each row of the gate to be turned on is reduced to half of that at 60 Hz. When Vcom is pulled high, Vcom cannot recover to the set value during the period when the gate is turned on, that is, when the gate is turned off, Vcom has not yet recovered to the set voltage. At this time, the voltage difference between the pixel electrode Pixel and the common electrode Vcom deviates from the designed value, resulting in abnormal displayed gray scale brightness.

[0081] When the next row of the gate is turned on for charging, Vcom will be coupled again at this voltage, and so on. The problem of Vcom coupling accumulates continuously until all the pixels in all rows within the Touch block are scanned, resulting in differences in the holding voltages of each row of pixels within the touch block (Touch block). Then, all the pixel rows within the next Touch block start to be scanned, and the above coupling process is continued. In this way, the pixels with the largest difference in pixel holding voltage are those between two Touch blocks. There is a large difference in the displayed brightness between the upper and lower rows of pixels at the boundary of the Touch block, resulting in the problem of visible display unevenness at the Touch block boundary.

[0082] Furthermore, under a heavy-load screen, the voltage of the Source line jumps frequently, which couples to Vcom more severely, and the problem of display unevenness becomes more serious. Figure 4 shows a schematic diagram of the voltage jump of the pixels under a heavy-load screen. As Figure 4 shown, the red sub-pixels, green sub-pixels, and blue sub-pixels of each row are arranged in sequence. When the first row is scanned, when the first red sub-pixel is applied with voltage to display the gray scale, when the second row is scanned, the first red sub-pixel is not applied with voltage to display the black gray scale, and when the third row is scanned, the first red sub-pixel is applied with voltage again. That is to say, the Source voltage jumps during the scanning of each row.

[0083] Moreover, the coupling direction of the Vcom caused by the voltage jump of the Source line in the same row is consistent. That is to say, during the scanning process from the second green sub-pixel in the first row to the second green sub-pixel in the second row, the direction of the voltage jump of this green sub-pixel is the same as that of the red sub-pixel in the same row. When going from the first row to the second row, the voltages of all sub-pixels decrease, and when going from the second row to the third row, the voltages of all sub-pixels increase. This phenomenon causes more serious coupling to the Vcom of each row.

[0084] Based on the above problems and research, the present invention proposes an array substrate and a display device to solve the above problems.

[0085] The first embodiment of the present invention proposes an array substrate, as Figure 5 shown. The array substrate includes a substrate 10, a display area AA disposed on the substrate 10, and a non-display area NA at least partially surrounding the display area AA. The non-display area NA includes a bonding area 20 and a fan-out routing area 30 disposed between the bonding area 20 and the display area AA;

[0086] Figure 6 shows Figure 5 a layout schematic diagram of the routing design in the Q1 area in

[0087] The fan-out routing area 30 includes a first routing area 31, a second routing area 32, and a third routing area 33 arranged in sequence along the first direction Y. The first routing area 31 is located on the side close to the display area AA: Figure 6 The fan-out routing area 30 further includes a plurality of fan-out line groups 34 arranged in an array along the second direction X. For example,

[0088] shown as the first fan-out line group 34A and the second fan-out line group 34B. One end of the fan-out line group 34 is connected to the display area AA, and after sequentially passing through the first routing area 31, the second routing area 32, and the third routing area 33, the other end of the fan-out line group 34 is connected to the bonding area 20;

[0089] Among them, each fan-out line group 34 includes a first fan-out line 341, a second fan-out line 342, and a third fan-out line 343 arranged in sequence along the second direction.

[0090] Two second fan-out lines 342 in the two fan-out line groups 34A and 34B located in the second wiring area 32 overlap at least partially in the projection on the substrate 10 to form a second overlapping area S2, and the two second fan-out lines 342 at the location where the first overlapping area S1 is formed are arranged in different layers;

[0091] Two third fan-out lines 343 in the two fan-out line groups 34 located in the second wiring area 32 overlap at least partially in the projection on the substrate 10 to form a third overlapping area S3, and the two third fan-out lines 343 at the third overlapping area S3 are arranged in different layers.

[0092] In this embodiment, the wiring connecting the third connection area between the first wiring area and the second wiring area is designed, and each fan-out line of the fan-out line group located in the third wiring area is designed, so that in adjacent fan-out line groups, the fan-out lines of the same type overlap at least partially in the projection on the substrate, and the fan-out lines of the same type in the overlapping area are arranged in different layers. This setting can reduce the coupling of the fan-out lines, improve the display defect, and effectively reduce the Panel power consumption.

[0093] As Figure 5 shown, the non-display area NA of this embodiment surrounds the bottom of the display area AA, and forms the fan-out wiring area 30 connecting the display area AA and the driving chip at the bottom. The fan-out wiring area 30 of this embodiment includes three wiring areas extending in the Y direction as shown in Figure 5 shown. The fan-out lines of the fan-out wiring area 30 start from the first wiring area 31, pass through the second wiring area 32 and the third wiring area 33, and end at the bonding terminals of the driving chip. That is to say, the first wiring area 31 of this embodiment is the area where the fan-out line group 34 is connected to the display terminals of the display area AA, the third wiring area 33 is the area where the fan-out line group 34 is connected to the bonding terminals, and the second wiring area 32 is the connection area connecting the first wiring area 31 and the second wiring area 32. Exemplarily, the second wiring area 32 includes a plurality of vias for making jumpers.

[0094] As Figure 6 shown, a fan-out line group includes a first fan-out line 341, a second fan-out line 342, and a third fan-out line 343 arranged in sequence along the second direction, that is, the X direction.

[0095] In an optional embodiment, the first fan-out line 341 and the second fan-out line 342 are data signal lines for transmitting data signals, and the third fan-out line 343 is a touch signal line for transmitting touch signals.

[0096] It can be understood that in the embodiments of the present invention, the numbers of the first fan-shaped outgoing line 341 and the second fan-shaped outgoing line 342 are both exemplary, and the present invention does not make specific limitations on the numbers. Taking the fan-shaped outgoing line area including multiple fan-shaped outgoing line groups 34 arranged in an array as the design criterion, it will not be elaborated here.

[0097] In an optional embodiment, the polarities of the first fan-shaped outgoing line 341 and the second fan-shaped outgoing line 342 are opposite. Exemplarily, the voltage of the first fan-shaped outgoing line 341 can be a positive voltage, denoted as 341+, and the voltage of the second fan-shaped outgoing line 342 can be a negative voltage, denoted as 342-. Or, the voltage of the second fan-shaped outgoing line 342 can be a positive voltage, and the voltage of the first fan-shaped outgoing line 341 can be a negative voltage. The pixel polarity is column-inverted, and this setting can ensure the uniformity of the polarity of the entire display screen.

[0098] As Figure 6 shown, taking the arrangement of the fan-shaped outgoing line group 34 as an example: the first fan-shaped outgoing line 341 is a data signal line with a positive polarity, the second fan-shaped outgoing line 342 is a data signal line with a negative polarity, and the third fan-shaped outgoing line 343 is a touch signal line (Tx signal line), the routing design of the present invention will be described.

[0099] Exemplarily, in the related art, the bonding terminals of the driving chip (IC end) are arranged in a cycle of data signal, data signal, and touch signal line (SST). Correspondingly, the AA area is arranged to match the IC end, and the rule for leading out the display terminals in the AA area is also the arrangement of the SST. Taking the first fan-shaped outgoing line 341, the second fan-shaped outgoing line 342, and the third fan-shaped outgoing line 343 as a fan-shaped outgoing line group 34, Figure 6 shows two fan-shaped outgoing line groups 34, the corresponding arrangement methods of the first fan-shaped outgoing line group 34A and the second fan-shaped outgoing line group 34B, that is, the polarities and types of the 6 signal lines are arranged as follows: the first fan-shaped outgoing line 341 with a positive polarity in the first fan-shaped outgoing line group 34A, the second fan-shaped outgoing line 342 with a negative polarity in the first fan-shaped outgoing line group 34A, the third fan-shaped outgoing line 343 in the first fan-shaped outgoing line group 34A, the first fan-shaped outgoing line 341 with a positive polarity in the second fan-shaped outgoing line group 34B, the second fan-shaped outgoing line 342 with a negative polarity in the second fan-shaped outgoing line group 34B, and the third fan-shaped outgoing line 343 in the second fan-shaped outgoing line group 34B. That is to say, the display terminals 41 in the AA area and the bonding terminals 21 in the bonding area 20 are all led out in the current way.

[0100] In an optional embodiment, the display area AA includes a plurality of display terminals 41 arranged at the place surrounded by the non-display area NA. The display terminals 41 are arranged along the second direction X. As shown above, the signals of the display terminals 41 are also arranged in a cycle of data signal with a positive polarity, data signal with a negative polarity, and touch signal line (S+, S-, T).

[0101] In this embodiment, the first wiring area 31 includes the portions where each fan-out line is connected to the display terminal 41. The first fan-out line 341 includes a first connection portion 3411 located in the first wiring area 31 and connected to the display terminal 41. The second fan-out line 342 includes a second connection portion 3422 located in the first wiring area 31 and connected to the display terminal 41. The third fan-out line 343 includes a third connection portion 3433 located in the first wiring area 31 and connected to the display terminal 41.

[0102] In a specific example, one end of each connection portion is respectively connected to the corresponding display terminal 41, and the other end realizes the overlapping design of the fan-out lines of the same type in the second wiring area 32 through via jumper design. Exemplarily, as Figure 6 shown, one end of the first connection portion 3411 is connected to the display terminal 41, and the other end is connected to the first via K1. One end of the second connection portion 3422 is connected to the display terminal 41, and the other end is connected to the second via K2. One end of the third connection portion 3433 is connected to the display terminal 41, and the other end is connected to the third via K3.

[0103] In a specific example, the display terminal 41 includes a first metal layer provided on the substrate and a second metal layer insulatingly provided on the first metal layer. When the first connection portion 3411, the second connection portion 3422, and the third connection portion 3433 are connected, they can be connected to any metal layer of the corresponding display terminal 41 through a conductive layer. Exemplarily, as Figure 6 shown, in the first fan-out line group 34A, the first connection portion 3411, the second connection portion 3422, and the third connection portion 3433 are all connected to the second metal layer through a conductive layer. In the second fan-out line group 34B, the first connection portion 3411, the second connection portion 3422, and the third connection portion 3433 are all connected to the first metal layer through a conductive layer.

[0104] In another specific example, as Figure 7 shown, in the first fan-out line group 34A, the first connection portion 3411 and the second connection portion 3422 are connected to the second metal layer, and the third connection portion 3433 is connected to the first metal layer. In the second fan-out line group 34B, the first connection portion 3411 and the second connection portion 3422 are connected to the first metal layer, and the third connection portion 3433 is connected to the second metal layer.

[0105] That is to say, in this embodiment, when the orthographic projections of the connection portions located in the first wiring area 31 on the substrate 10 do not overlap, each connection portion is connected to any metal layer of the display terminal 41 through a conductive layer. This setting further expands the connection method of the fan-out lines on the basis of ensuring the connection performance.

[0106] In another alternative embodiment, as Figure 8 shown, when the positive projections of any two connection parts in two adjacent fan-out line groups 34 located in the first wiring area 31 form a fourth overlapping area S4 on the substrate 10, the two connection parts at the fourth overlapping area S4 are located on different layers. In this embodiment, considering the overlapping design of the fan-out lines of the same type in the second wiring area 32, there will be a phenomenon where the projections of different fan-out lines overlap in the first wiring area 31. To avoid signal interference between the fan-out lines, in this embodiment, the two connection parts forming the overlap are arranged on different layers.

[0107] In a specific example, as Figure 8 shown, the first connection part 3411 of the second fan-out line group 34B forms two fourth overlapping areas S4 with the second connection part 3422 of the first fan-out line group 34A and the third connection part 3433 of the first fan-out line group 34A respectively. Then, the second connection part 3422 of the first fan-out line group 34A and the first connection part 3411 of the second fan-out line group 34B are designed with different layers, and the third connection part 3433 of the first fan-out line group 34A and the first connection part 3411 of the second fan-out line group 34B are designed with different layers. Exemplarily, Figure 9 shows Figure 8 a schematic diagram of the layer structure at the BB cross-section. For example, the second connection part 3422 of the first fan-out line group 34A and the third connection part 3433 of the first fan-out line group 34A are arranged on the second conductive layer 37, and the first connection part 3411 of the second fan-out line group 34B is arranged on the first conductive layer 35. The first insulating layer 36 between the first conductive layer 35 and the second conductive layer 37 is used to keep the signals independent and avoid signal interference.

[0108] Based on the design principle of the first wiring area 31, in an alternative embodiment, as Figure 10 shown, the bonding area 20 is provided with a plurality of bonding terminals 21 arranged along the second direction X. As shown above, to achieve signal matching between the display area and the bonding area, the signals of the bonding terminals 21 are also arranged in a cycle of positive-polarity data signals, negative-polarity data signals, and touch signal lines (S+, S-, T).

[0109] In this embodiment, the third wiring area 33 includes the parts where each fan-out line is connected to the bonding terminal 21. The first fan-out line 341 includes a seventh connection part 3417 located in the third wiring area 33 and connected to the bonding terminal 21. The second fan-out line 342 includes an eighth connection part 3428 located in the third wiring area 33 and connected to the bonding terminal 21. The third fan-out line 343 includes an eighth connection part 3439 located in the third wiring area 33 and connected to the bonding terminal 21.

[0110] In a specific example, one end of each connecting portion is respectively connected to the corresponding bonding terminal 21, and the other end is jump-wired through a via hole to implement an overlapping design of the same type of fan-out lines in the second routing area 32. Exemplarily, as Figure 10 shown, one end of the seventh connecting portion 3417 is connected to the bonding terminal 21, and the other end is connected to the fourth via hole K4. One end of the eighth connecting portion 3428 is connected to the bonding terminal 21, and the other end is connected to the fifth via hole K5. One end of the eighth connecting portion 3439 is connected to the bonding terminal 21, and the other end is connected to the sixth via hole K6.

[0111] In a specific example, the bonding terminal 21 includes a third metal layer provided on the substrate 10 and a fourth metal layer insulatingly provided on the third metal layer. When the seventh connecting portion 3417, the eighth connecting portion 3428, and the eighth connecting portion 3439 are connected, they can be connected to any metal layer of the corresponding bonding terminal 21.

[0112] In a specific example, the third metal layer and the first metal layer are formed by the same process, that is, the third metal layer and the first metal layer are provided on the same layer. Similarly, the fourth metal layer and the second metal layer are formed by the same process, that is, the fourth metal layer and the second metal layer are provided on the same layer, thereby improving the manufacturing efficiency. In a specific example, the metal layer of the bonding terminal can be formed on the same layer as the conductive layer of the fan-out line, further improving the manufacturing efficiency.

[0113] Exemplarily, as Figure 10 shown, in the first fan-out line group 34A, the seventh connecting portion 3417, the eighth connecting portion 3428, and the eighth connecting portion 3439 are all connected to the fourth metal layer of the bonding terminal 21 through the second conductive layer (filled with oblique lines). In the second fan-out line group 34B, the seventh connecting portion 3417, the eighth connecting portion 3428, and the eighth connecting portion 3439 are all connected to the third metal layer of the bonding terminal 21 through the first conductive layer (filled with dots).

[0114] The connection manners of the seventh connecting portion 3417, the eighth connecting portion 3428, and the eighth connecting portion 3439 with the metal layer of the bonding terminal 21 are also diverse. Specifically, reference can be made to the connection manners of the first connecting portion 3411, the second connecting portion 3422, and the third connecting portion 3433 with the metal layer of the display terminal 41, which will not be elaborated here.

[0115] That is to say, in this embodiment, when the orthographic projections of the respective connecting portions located in the third routing area 33 on the substrate 10 do not overlap, each connecting portion is connected to any metal layer of the bonding terminal 21. This setting further expands the connection manners of the fan-out lines on the basis of ensuring the connection performance.

[0116] In another alternative embodiment, as Figure 11 shown, when any two connection portions in two adjacent fan-out line groups 34 located in the third routing area 33 form a fifth overlapping area S5 in the orthographic projection on the substrate 10, the two connection portions at the fifth overlapping area S5 are located on different layers. In this embodiment, considering the overlapping design of the fan-out lines of the same type in the second routing area 32, there will be a phenomenon where the projections of different fan-out lines overlap in the third routing area 33. To avoid signal interference between the fan-out lines, in this embodiment, the two connection portions forming the overlap are arranged on different layers.

[0117] In a specific example, as Figure 11 shown, the seventh connection portion 3417 of the second fan-out line group 34B respectively forms two fifth overlapping areas S5 with the eighth connection portion 3428 of the first fan-out line group 34A and the eighth connection portion 3439 of the first fan-out line group 34A. Then, the seventh connection portion 3417 of the second fan-out line group 34B and the eighth connection portion 3428 of the first fan-out line group 34A are designed with different layers, and the seventh connection portion 3417 of the second fan-out line group 34B and the eighth connection portion 3439 of the fan-out line group 34A are designed with different layers. Exemplarily, Figure 12 shows Figure 11 a schematic diagram of the layer structure at the CC cross-section. For example, the eighth connection portion 3428 of the first fan-out line group 34A and the eighth connection portion 3439 of the first fan-out line group 34A are arranged on the first conductive layer, and the seventh connection portion 3417 of the second fan-out line group 34B is arranged on the second conductive layer. The insulating layer between the first conductive layer and the second conductive layer is used to keep the signals independent and avoid signal interference.

[0118] In an alternative embodiment, as Figure 6 shown, the second routing area 32 is a part of the fan-out lines connecting the first routing area 31 and the third routing area 33.

[0119] The first fan-out line 341 includes a fourth connection portion 3414 located in the second routing area 32. The fourth connection portion 3414 includes the first fan-out line 341 corresponding to the first overlapping area S1. That is to say, the fourth connection portion 3414 not only includes the traces in the overlapping area, but also includes the connection lines connecting to the first connection portion 3411 and the seventh connection portion 3417. The fourth connection portion 3414 is connected to the first connection portion 3411 through the first via K1 and is connected to the seventh connection portion 3417 through the fourth via K4.

[0120] The second outgoing line 342 further includes a fifth connection portion 3425 located in the second wiring area 32. The fifth connection portion 3425 includes the second outgoing line 342 corresponding to the second overlapping area S2. That is to say, the fifth connection portion 3425 not only includes the wiring in the overlapping area, but also includes the connection lines connecting to the second connection portion 3422 and the eighth connection portion 3428. The fifth connection portion 3425 is connected to the second connection portion 3422 through the second via hole K2 and is connected to the eighth connection portion 3428 through the fifth via hole K5.

[0121] The third outgoing line 343 further includes a sixth connection portion 3436 located in the second wiring area 32. The sixth connection portion 3436 further includes the third outgoing line 343 corresponding to the third overlapping area S3. That is to say, the sixth connection portion 3436 not only includes the wiring in the overlapping area, but also includes the connection lines connecting to the third connection portion 3433 and the eighth connection portion 3439. The sixth connection portion 3436 is connected to the third connection portion 3433 through the third via hole K3 and is connected to the eighth connection portion 3439 through the sixth via hole K6.

[0122] In this embodiment, the connection portions in the third wiring area 33 are connected to the respective connection portions in the corresponding first wiring area 31 and second wiring area 32 through the via holes at both ends.

[0123] As Figure 6 shown, in the third wiring area 33, the first outgoing lines 341 of the same type in the adjacent outgoing line groups 34 form a first overlapping area S1. That is, the first outgoing lines 341 of the first outgoing line group 34A and the first outgoing lines 341 of the second outgoing line group 34B form the first overlapping area S1. To avoid signal interference in the overlapping area, the two first outgoing lines 341 are located on different layers. This way of making the projection of the signal lines of the same type on the substrate 10 form an overlap can reduce the coupling of the first outgoing lines 341 in the stacked wiring design.

[0124] That is to say, when the positive projections of the same first outgoing lines 341 on the substrate 10 form an overlap, that is, the fourth connection portion 3414 of one first outgoing line 341 is located above the fourth connection portion 3414 of the other first outgoing line 341. At this time, when signals are written into these two outgoing lines, the voltage changes of the two outgoing lines are the same. Therefore, the influence on the capacitance between the two outgoing lines is small, the coupling voltage between the two outgoing lines is small, the degree of Vcom being coupled and pulled offset at this position is small, and it can be restored in time under high-frequency conditions, thereby effectively improving the display defect of the Touch block at this position.

[0125] Similarly, the second fan-out lines 342 of the same type in the two fan-out line groups 34 form a second overlapping region S2. That is, the second fan-out lines 342 of the first fan-out line group 34A and the second fan-out lines 342 of the second fan-out line group 34B form the second overlapping region S2. When the orthographic projections of the second fan-out lines 342 of the same type on the substrate 10 overlap, that is, the fifth connection portion 3425 of one second fan-out line 342 is located above the fifth connection portion 3425 of the other second fan-out line 342. Similarly, when signals are written to these two second fan-out lines 342, the voltage changes of the two second fan-out lines 342 are the same, the capacitance between the two second fan-out lines is less affected, the coupled voltage between the two fan-out lines is small, the degree of Vcom being coupled and offset at this position is small, and it can be restored in time under high-frequency conditions, thus effectively improving the display defect of the Touch block at this position.

[0126] In the two first fan-out line groups 34A and the second fan-out line group 34B, the design of the third overlapping region S3 formed by the third fan-out lines 343 of the same type is the same as described above, and the sixth connection portion 3436 of one third fan-out line 343 is located above the sixth connection portion 3436 of the other second fan-out line 342. This design can also reduce the capacitance between the third fan-out lines 343 at this position.

[0127] In an optional embodiment, the central axes of the two first fan-out lines 341 at the first overlapping region S1 coincide in the orthographic projection on the substrate 10, the central axes of the two second fan-out lines 342 at the second overlapping region S2 coincide in the orthographic projection on the substrate 10, and the central axes of the two third fan-out lines 343 at the third overlapping region S3 coincide in the orthographic projection on the substrate 10. This setting can maximize the overlapping area of the first connection portions 3411 of the two first fan-out lines 341 and further reduce the coupling between the signal lines at the overlapping portion.

[0128] Therefore, in this embodiment, by designing the routing of the fan-out routing area of the double-layer routing, and forming an overlapping design for the same fan-out signal lines in the two fan-out line groups, the coupling between the signal lines in the third routing area is reduced, so that when signals are written, Vcom is less affected by the load coupling offset and can be restored in time under high-frequency conditions, effectively improving the display defect.

[0129] It should be noted that the present invention does not limit that the two first fan outwires 341 forming the first overlapping region S1 are of the same type of fan outwires located in adjacent fan outwire groups 34. That is to say, since the fan outwire groups 34 are arranged in sequence in the second direction, i.e., the X direction, there are multiple first fan outwires 341, second fan outwires 342, and third fan outwires 343 arranged in a cycle with the fan outwire group 34 in this direction. Therefore, the first overlapping region S1 formed in the second wiring region 32 in this embodiment can be formed by two first fan outwires 341 in the first fan outwire group 34 and the second fan outwire group 34. In another example, the first overlapping region can also be formed by two first fan outwires in the first fan outwire group and the third fan outwire group. In another example, the first overlapping region can also be formed by two first fan outwires in the first fan outwire group and the fourth fan outwire group. Therefore, based on the above examples, the present invention does not limit the positions of the fan outwire groups 34 to which the two first fan outwires 341 forming the first overlapping region S1 belong. With the design criterion that two first fan outwires 341 in two fan outwire groups 34 form the first overlapping region S1 and the two overlapping fan outwires are located in different layers when the fan outwires in the second wiring region 32 form an overlap, both the connection performance is ensured and the display defect is improved.

[0130] In an alternative embodiment, as Figure 13 shown, the array substrate further includes a first conductive layer 35 formed on the substrate 10, a first insulating layer 36 disposed on the first conductive layer 35, and a second conductive layer 37 disposed on the first insulating layer 36.

[0131] As Figure 6 shown, the orthographic projections of the first conductive layer 35 and the second conductive layer 37 on the substrate 10 are disposed in the first wiring region 31, the second wiring region 32, and the third wiring region 33. Due to the double-layer wiring design in this embodiment, the first wiring region 31, the second wiring region 32, and the third wiring region 33 are jumper-connected through a plurality of vias to ensure that the fan outwires in each wiring region are of different-layer design, and the insulating layer is used to avoid interference between signals.

[0132] In an alternative embodiment, at the first overlapping region S1, one of the first fan outwires 341 is located on the first conductive layer 35 or the second conductive layer 37, and the other first fan outwire 341 is located on the second conductive layer 37 or the first conductive layer 35.

[0133] At the second overlapping region S2, one of the second fan outwires 342 is located on the first conductive layer 35 or the second conductive layer 37, and the other second fan outwire 342 is located on the second conductive layer 37 or the first conductive layer 35.

[0134] At the third overlapping region S3, one of the third fan-out lines 343 is located on the first conductive layer 35 or the second conductive layer 37, and the other third fan-out line 343 is located on the second conductive layer 37 or the first conductive layer 35.

[0135] That is to say, the fan-out lines of the same type in the two fan-out line groups 34 of this embodiment are designed with different layers in the overlapping region. Exemplarily, Figure 13 shows Figure 6 the layer structure schematic diagram at the DD cross-section in

[0136] As Figure 13 and Figure 6 shown, in the first overlapping region S1, the first connection portion 3411 of the first fan-out line 341 with positive polarity in the first fan-out line group 34A is located on the second conductive layer 37, and the first connection portion 3411 of the first fan-out line 341 with positive polarity in the second fan-out line group 34B is located on the first conductive layer 35. In the second overlapping region S2, the second connection portion 3422 of the second fan-out line 342 with negative polarity in the first fan-out line group 34A is located on the second conductive layer 37, and the second connection portion 3422 of the second fan-out line 342 with negative polarity in the second fan-out line group 34B is located on the first conductive layer 35. In the third overlapping region S3, the third connection portion 3433 of the third fan-out line 343 in the first fan-out line group 34A is located on the second conductive layer 37, and the third connection portion 3433 of the third fan-out line 343 in the second fan-out line group 34B is arranged on the first conductive layer 35, thus forming the overlap and different-layer design of the fan-out lines of the same type in different fan-out line groups 34.

[0137] It should be noted that the present invention does not limit the specific different-layer structure design of each fan-out line forming the first overlapping region S1, the second overlapping region S2, and the third overlapping region S3, that is, different from Figure 13 shown, in this embodiment, all the fan-out lines (the first fan-out line 341, the second fan-out line 342, and the third fan-out line 343) in the first fan-out line group 34A can also be arranged on the first conductive layer 35, and all the fan-out lines (the first fan-out line 341, the second fan-out line 342, and the third fan-out line 343) in the second fan-out line group 34B can be arranged on the second conductive layer 37.

[0138] In another example, as Figure 14As shown, the present invention can also arrange the first fan outgoing line 341 with positive polarity in the first fan outgoing line group 34A on the first conductive layer 35, and arrange the second fan outgoing line 342 with negative polarity in the first fan outgoing line group 34A and the second fan outgoing line 342 with negative polarity in the second fan outgoing line group 34B on the second conductive layer 37. Correspondingly, the first fan outgoing signal line 342 with positive polarity in the second fan outgoing line group 34B is located on the second conductive layer 37, and the second fan outgoing line 342 with negative polarity in the second fan outgoing line group 34B and the second fan outgoing line 342 with negative polarity in the first fan outgoing line group 34A are arranged on the first conductive layer 35, which not only ensures the wiring connection performance of the fan outgoing line area but also enables an overlapping design.

[0139] Based on the foregoing embodiments, the display terminal 41 includes a first metal layer and a second metal layer, and the bonding terminal 21 includes a third metal layer and a fourth metal layer. In an optional embodiment, the first metal layer and the third metal layer can be arranged on the same layer as the first conductive layer 35, and the second metal layer and the fourth metal layer can be arranged on the same layer as the second conductive layer 37, thereby improving the manufacturing efficiency.

[0140] As Figure 6 shown, in an optional embodiment, when the orthographic projections of the respective connection portions located in the first wiring area 31 on the substrate 10 do not overlap, that is, in the first wiring area 31, for the first fan outgoing line group 34A, the projections of the first connection portion 3411, the second connection portion 3422, and the third connection portion 3433 on the substrate 10 are arranged in parallel, and for the second fan outgoing line group 34B, the projections of the first connection portion 3411, the second connection portion 3422, and the third connection portion 3433 on the substrate 10 are also arranged in parallel. At this time, no overlapping area is formed between the respective connection portions, that is to say, even if the respective connection portions are arranged on the same layer, no interference of the wiring will be formed.

[0141] Therefore, in this embodiment, the positions of the respective connection portions are not limited. On the one hand, the positions of the connection portions of the same type in different fan outgoing line groups 34 are not restricted. Exemplarily, in the first fan outgoing line group 34A, the first connection portion 3411 can be arranged on any one of the first conductive layer 35 or the second conductive layer 37, and in the second fan outgoing line group 34B, the first connection portion 3411 can also be arranged on any one of the first conductive layer 35 or the second conductive layer 37.

[0142] On the other hand, the positions of different types of connection parts in the same outgoing line group 34 are not restricted. Exemplarily, in the first outgoing line group 34A, the first connection part 3411 can be arranged on either the first conductive layer 35 or the second conductive layer 37. In this outgoing line group 34, the second connection part 3422 can also be arranged on either the first conductive layer 35 or the second conductive layer 37. Similarly, in the first wiring area 31, the connection between each connection part and the metal layer of the display terminal 41 is not restricted. Therefore, the outgoing line arrangement design of this embodiment has scalability and universality.

[0143] As Figure 6 shown, when the orthographic projections of the connection parts located in the first wiring area 31 on the substrate 10 do not overlap, one end of each connection part is correspondingly connected to the display terminal 41, and the other end is connected to the connection part of the second wiring area 32 through its respective via hole. In this structure, the first via hole K1, the second via hole K2, and the third via hole K3 are arranged in sequence in the second direction. That is, the other end of the first connection part 3411 is connected to the fourth connection part 3414 through the first via hole K1, the other end of the second connection part 3422 is connected to the fifth connection part 3425 through the second via hole K2, and the other end of the third connection part 3433 is connected to the sixth connection part 3436 through the third via hole K3. The first connection part 3411, the second connection part 3422, and the third connection part 3433 in the second outgoing line group 34B all adopt the same connection setting as the first connection. In this structure, the display terminal 41, each connection part, and each via hole are arranged in sequence according to the order.

[0144] For the second wiring area 32, in the first outgoing line group 34A, the fourth connection part 3414 is connected to the first connection part 3411 through the first via hole K1, the fifth connection part 3425 is connected to the second connection part 3422 through the second via hole K2, and the sixth connection part 3436 is connected to the third connection part 3433 through the third via hole K3. The fourth connection part 3414, the fifth connection part 3425, and the sixth connection part 3436 in the second outgoing line group 34B are all connected in the same way. Therefore, before the two fourth connection parts 3414 overlap, the fourth connection part 3414 further includes a first sub-connection part connected to the first via hole K1. Similarly, the fifth connection part 3425 of the first outgoing line group 34A, the sixth connection part 3436 of the first outgoing line group 34A, and each connection part in the second outgoing line group 34B all have this structure, and each first sub-connection part is used to connect the signal lines in the overlapping area and the corresponding via holes.

[0145] As Figure 6As shown, the other ends of the respective connection parts in the second wiring area 32 are connected to the corresponding connection parts in the third wiring area 33 through corresponding vias. Similar to the design principle of the first wiring area 31, for example, after the two fourth connection parts 3414 overlap, the fourth connection part 3414 further includes a second sub-connection part connected to the fourth via K4. Similarly, the fifth connection part 3425, the sixth connection part 3436 of the first fan-out line group 34A, and each connection part in the second fan-out line group 34B all have this structure. Each second sub-connection part is used to connect the signal lines in the overlapping area and the corresponding vias.

[0146] In the second wiring area 32, the fourth connection parts 3414 of the two first fan-out lines 341 in the two fan-out line groups 34 form a first overlapping area S1, the fifth connection parts 3425 of the two second fan-out lines 342 form a second overlapping area S2, and the sixth connection parts 3436 of the two third fan-out lines 343 form a third overlapping area S3. And the two connection parts at the overlapping area are located on different conductive layers, which not only ensures the connection performance but also can realize the overlapping design to reduce the coupling offset of the common electrode.

[0147] In an optional embodiment, when the orthographic projections of the respective connection parts located in the third wiring area 33 on the substrate 10 do not overlap, for example, in this structure, the design of the respective connection parts in the third wiring area 33 is similar to the design principle of the first wiring area 31. In the third wiring area 33, for the first fan-out line group 34A, the seventh connection part 3417, the eighth connection part 3428, and the eighth connection part 3439 are arranged in parallel in the projection on the substrate 10. For the second fan-out line group 34B, the projections of the respective connection parts on the substrate 10 are also arranged in parallel. At this time, no overlapping area is formed between the respective connection parts, that is to say, even if the respective connection parts are arranged on the same layer, no interference of the wiring will be formed.

[0148] Therefore, in the third wiring area 33 of this embodiment, the positions of the respective connection parts are not limited either. On the one hand, the positions of the same type of connection parts in different fan-out line groups 34 are not restricted. For example, in the first fan-out line group 34A, the seventh connection part 3417 can be arranged on either the first conductive layer 35 or the second conductive layer 37. In the second fan-out line group 34B, the seventh connection part 3417 can also be arranged on either the first conductive layer 35 or the second conductive layer 37.

[0149] On the other hand, the positions of different types of connection parts in the same fan-shaped lead-out group 34 are not restricted. Exemplarily, in the first fan-shaped lead-out group 34A, the seventh connection part 3417 can be arranged on either the first conductive layer 35 or the second conductive layer 37. In this fan-shaped lead-out group 34, the eighth connection part 3428 can also be arranged on either the first conductive layer 35 or the second conductive layer 37. Similarly, in the first wiring area 31, the connection between each connection part and the metal layer of the display terminal 41 is not restricted. In this structure, the bonding terminals, each connection part, and each via hole are arranged in sequence, that is Figure 6 As shown, the fourth via hole K4, the fifth via hole K5, and the sixth via hole K6 are arranged in sequence in the second direction. Therefore, the fan-shaped lead-out arrangement design of this embodiment has scalability and universality.

[0150] In a specific example, in the related art, the layer structure design in the second wiring area 32 is as Figure 15a and the layer structure at the cross-section EE Figure 15b As shown. As Figure 15a and Figure 15b shown, the arrangement of each fan-shaped lead-out of the fan-shaped lead-out group 34 is the first fan-shaped lead-out 341 with positive polarity of the first fan-shaped lead-out group 34A, the second fan-shaped lead-out 342 with negative polarity of the first fan-shaped lead-out group 34A, and the third fan-shaped lead-out 343 of the first fan-shaped lead-out group 34A. In the second wiring area 32, the first fan-shaped lead-out 341 with positive polarity and the second fan-shaped lead-out 342 with negative polarity of the first fan-shaped lead-out group 34A overlap, the third fan-shaped lead-out 343 and the first fan-shaped lead-out 341 with positive polarity of the second fan-shaped lead-out group 34B overlap, and the second fan-shaped lead-out 342 with negative polarity of the second fan-shaped lead-out group 34B and the third fan-shaped lead-out 343 overlap.

[0151] That is to say, in the related art, under the design of double-layer wiring, on the basis of realizing the cooperative arrangement of the signal lines between the display terminal 41 and the bonding terminal 21, different signal lines are overlapped to reduce the space occupied by the wiring. This makes the capacitance at the overlapping area formed by different fan-shaped lead-outs relatively large, and has a greater influence on the coupling offset of the common electrode.

[0152] Exemplarily, since the polarities of the first outgoing line 341 and the second outgoing line 342 are opposite, when signals are written to the first outgoing line 341 and the second outgoing line 342, the voltage changes of the first outgoing line 341 and the second outgoing line 342 are opposite. This leads to changes at both ends of the capacitor between the first outgoing line 341 and the second outgoing line 342, and the changes at both ends of the capacitor are opposite. Based on the foregoing, this change will cause the coupling capacitor of the common electrode to deviate from the original set value. At high refresh rates, the coupling capacitor of the severely deflected common electrode will not recover in time, but signals will be rewritten at the deflected position, resulting in a gradual increase in the deviation degree of the coupling capacitor of the common electrode and causing visible display unevenness.

[0153] In a specific example, such as Figure 16 shown, the coupling capacitance between the outgoing lines of each layer structure in the figure is calculated with a unit length of 100 μm as an example. Figure 15b For the coupling capacitance between the outgoing lines of each layer structure, the third outgoing line 343 of the first outgoing line group 34A and the third outgoing line 343 of the second outgoing line group 34B have the same potential and there is no coupling capacitance. The coupling capacitance between the third outgoing line 343 and the positive-polarity first outgoing line 341 of the second outgoing line group 34B is 19.51 fF. The coupling capacitance between the third outgoing line 343 of the first outgoing line group 34A and the positive-polarity first outgoing line 341 of the same first outgoing line group 34A is 1.65 fF. The coupling capacitance between the third outgoing line 343 and the negative-polarity second outgoing line 342 of the same first outgoing line group 34A is 0.81 fF. The coupling capacitance between the third outgoing line 343 and the negative-polarity second outgoing line 342 of the second first outgoing line group 34B is 1.65 fF. It can be calculated that the total capacitance of the third outgoing line 343 is 23.62 fF, and the overlapping capacitance between the third outgoing line 343 and the positive-polarity first outgoing line 341 of the second first outgoing line group 34B is the main influencing factor.

[0154] In this embodiment, the design of forming the first overlapping region S1 with the same type of first outgoing line 341, the second overlapping region S2 with the same type of second outgoing line 342, and the third overlapping region S3 with the same type of third outgoing line 343 as described above can effectively reduce the coupling capacitance between each outgoing line.

[0155] In a specific example, in this embodiment, the same type of outgoing lines are overlapped in the double-layer layout design. Figure 17 Shown as Figure 13The coupling capacitance between each fan-out line of the overlapping design layer structure shown. In the figure, the trace coupling capacitance is also calculated with a unit length of 100 μm as an example. In this embodiment, still taking the third fan-out line 343 in the first fan-out line group 34A as an example, under the overlapping design of the same type of fan-out signal lines, the polarities of the same type of fan-out signal lines are the same, the written signals are the same, and there is no coupling capacitance. The coupling capacitance between the third fan-out line 343 and the first fan-out line 341 with positive polarity in the first fan-out line group 34A is 1.65 fF, the coupling capacitance between the third fan-out line 343 and the second fan-out line 342 with negative polarity in the same first fan-out line group 34A is 0.81 fF, the coupling capacitance between the third fan-out line 343 and the first fan-out line 341 with positive polarity in the second fan-out line group 34B is 0.81 fF, and the coupling capacitance between the third fan-out line 343 and the second fan-out line 342 with negative polarity in the second fan-out line group 34B is 1.65 fF. From the calculation, the total capacitance of the third fan-out line 343 is 4.92 fF, about Figure 16 1 / 5 of the trace design in Figure 16 , which can effectively reduce the Touch block Mura defect under the heavy load screen.

[0156] In a specific example, calculate the power P of the embodiment of the present invention according to the power consumption of the capacitor charging and discharging with a square wave: P = (1 / 2)fCV2, where V is the applied voltage, f is the refresh frequency, and C is the capacitance.

[0157] As can be seen from the above, under the same screen, the power consumption of the fan-out trace area 30 in this embodiment is reduced to Figure 16 1 / 5 of the trace design. Exemplarily, taking a 6.58-inch display device as an example, the power consumption of the monochromatic screen (R / G / B) at 120 Hz is reduced from the original 230 mW to 215 mW, a reduction of about 6.5%. In a specific example, as Figure 18 shown, the uniformity of the display screen of the display device is greatly improved, compared with Figure 1 the visible non-uniformity in Figure 1 has been greatly improved. Therefore, the solution of the embodiment of the invention has a wide application prospect.

[0158] The layout design of the fan-out trace area 30 in this embodiment is not limited to Figure 6 shown. Based on Figure 8 and Figure 11 the trace design shown, there are other design solutions for the fan-out trace area 30 in this embodiment.

[0159] In another alternative embodiment, as Figure 19As shown, in the two fan-out line groups 34 located in the first routing area 31, when any two of the first connection part 3411, the second connection part 3422, and the third connection part 3433 form a fourth overlapping area S4 in the orthographic projection on the substrate 10, among the two connection parts forming the fourth overlapping area S4, one connection part is located in the first conductive layer 35 or the second conductive layer 37, and the other connection part is located in the second conductive layer 37 or the first conductive layer 35. In this embodiment, by arranging the two connection parts forming the fourth overlapping area S4 in different layers, the insulating layer is used to avoid signal interference. In a specific example, as Figure 19 shown, the first connection part 3411 of the second fan-out line group 34B respectively forms two fourth overlapping areas with the second connection part 3422 of the first fan-out line group 34A and with the third connection part 3433 of the first fan-out line group 34A. Then, the second connection part 3422 of the first fan-out line group 34A and the first connection part 3411 of the second fan-out line group 34B are designed in different layers, and the third connection part 3433 of the first fan-out line group 34A and the first connection part 3411 of the second fan-out line group 34B are designed in different layers. Exemplarily, the second connection part 3422 of the first fan-out line group 34A and the third connection part 3433 of the first fan-out line group 34A are arranged in the second conductive layer 37, and the first connection part 3411 of the second fan-out line group 34B is arranged in the first conductive layer 35. The insulating layer between the first conductive layer 35 and the second conductive layer 37 is used to keep the signals independent and avoid signal interference.

[0160] In an alternative embodiment, in the two fan-out line groups 34 located in the first routing area 31, the first vias K1 corresponding to the first connection part 3411 of one of the fan-out line groups 34 and the first vias K1 corresponding to the first connection part 3411 of the other fan-out line group 34 are arranged adjacent to each other, the second vias K2 corresponding to the second connection part 3422 of one of the fan-out line groups 34 and the second vias K2 corresponding to the second connection part 3422 of the other fan-out line group 34 are arranged adjacent to each other, and the third vias K3 corresponding to the third connection part 3433 of one of the fan-out line groups 34 and the third vias K3 corresponding to the third connection part 3433 of the other fan-out line group 34 are arranged adjacent to each other.

[0161] Exemplarily, the arrangement pattern of the bonding terminals 21 at the driving chip end is an SST arrangement period. The AA area is for matching the arrangement pattern of the bonding terminals 21, and the rule for the display terminals 41 to lead out is also SST. In this embodiment, the fan-out lines of the same type are designed to overlap, which will move the positions of the fan-out lines of the fan-out line groups 34 in other periods. Therefore, under the condition of ensuring the arrangement rule of the bonding terminals 21, a jumper design is required to both achieve the overlapping design of the fan-out lines of the same type in the second routing area 32 and make the arrangement rules of the display terminals 41 and the bonding terminals 21 the same.

[0162] Exemplarily, in this embodiment, a jumper design is carried out through the vias in each first routing area 31. For example Figure 19 As shown, when the first fan-out line 341 of the second fan-out line group 34B is led out to the side of the first fan-out line 341 of the first fan-out line group 34A to achieve an overlapping routing design, in this structure, the first via K1 corresponding to the first connection portion 3411 of the first fan-out line group 34A and the first via K1 corresponding to the first connection portion 3411 of the second fan-out line group 34B are arranged adjacent to each other. Similarly, the second via K2 corresponding to the second connection portion 3422 of the first fan-out line group 34A and the second via K2 corresponding to the second connection portion 3422 of the second fan-out line group 34B are arranged adjacent to each other, and the third via K3 corresponding to the third connection portion 3433 of the first fan-out line group 34A and the third via K3 corresponding to the third connection portion 3433 of the second fan-out line group 34B are arranged adjacent to each other. That is, in this structure, the arrangement order of each via is: the first via K1 of the first fan-out line group 34A, the first via K1 of the second fan-out line group 34B, the second via K2 of the first fan-out line group 34A, the second via K2 of the second fan-out line group 34B, the third via K3 of the first fan-out line group 34A, and the third via K3 of the second fan-out line group 34B, so as to design the fan-out line arrangement when the fourth overlapping area S4 is formed in the first routing area 31.

[0163] In an alternative embodiment, for example Figure 19 As shown, among the two fan-out line groups 34 in the third routing area 33, when any two of the seventh connection portion 3417, the eighth connection portion 3428, and the eighth connection portion 3439 form a fifth overlapping area S5 in the orthographic projection on the substrate 10, among the two connection portions forming the fifth overlapping area S5, one connection portion is located in the first conductive layer 35 or the second conductive layer 37, and the other connection portion is located in the second conductive layer 37 or the first conductive layer 35. In this embodiment, by arranging the two connection portions forming the fifth overlapping area S5 in different layers, the insulating layer is used to avoid signal interference.

[0164] The principle of the fan-out line arrangement design when the third routing area 33 forms an overlap can refer to the principle of the fan-out line arrangement design when the first routing area 31 forms an overlap.

[0165] In a specific example, for example Figure 19As shown, the seventh connection part 3417 of the second outgoing line group 34B forms two fifth overlapping regions with the eighth connection part 3428 of the first outgoing line group 34A and with the eighth connection part 3439 of the first outgoing line group 34A respectively. Then, the seventh connection part 3417 of the second outgoing line group 34B and the eighth connection part 3428 of the first outgoing line group 34A are of different layer design, and the seventh connection part 3417 of the second outgoing line group 34B and the eighth connection part 3439 of the first outgoing line group 34A are of different layer design. Exemplarily, the eighth connection part 3428 of the first outgoing line group 34A and the eighth connection part 3439 of the first outgoing line group 34A are arranged on the first conductive layer 35, and the seventh connection part 3417 of the second outgoing line group 34B is arranged on the second conductive layer 37. The insulating layer between the first conductive layer 35 and the second conductive layer 37 is used to keep the signals independent and avoid signal interference.

[0166] In an optional embodiment, among the two outgoing line groups 34 located in the third routing area 33, the fourth vias K4 corresponding to the seventh connection parts 3417 of one of the outgoing line groups 34 are arranged adjacent to the fourth vias K4 corresponding to the seventh connection parts 3417 of the other outgoing line group 34; the fifth vias K5 corresponding to the eighth connection parts 3428 of one of the outgoing line groups 34 are arranged adjacent to the fifth vias K5 corresponding to the eighth connection parts 3428 of the other outgoing line group 34; the sixth vias K6 corresponding to the eighth connection parts 3439 of one of the outgoing line groups 34 are arranged adjacent to the sixth vias K6 corresponding to the eighth connection parts 3439 of the other outgoing line group 34; when the orthographic projections of any two of the seventh connection part 3417, the eighth connection part 3428 and the eighth connection part 3439 on the substrate 10 form an overlapping region, among the two connection parts forming the overlapping region, one connection part is located on the first conductive layer 35 or the second conductive layer 37, and the other is located on the second conductive layer 37 or the first conductive layer 35.

[0167] The layout design principle of the outgoing line when the third routing area 33 forms an overlap can refer to the layout design principle of the outgoing line when the first routing area 31 forms an overlap as described above.

[0168] Exemplarily, in this embodiment, a jumper design is carried out through the vias in each third routing area 33, such as Figure 19As shown, when the first outgoing wire 341 of the second outgoing wire group 34B is led out to the side of the first outgoing wire 341 of the first outgoing wire group 34A to achieve the design of overlapping wire routing, in this structure, the fourth via hole K4 corresponding to the seventh connection part 3417 of the first outgoing wire group 34A and the fourth via hole K4 corresponding to the seventh connection part 3417 of the second outgoing wire group 34B are adjacent to each other. Similarly, the fifth via hole K5 corresponding to the eighth connection part 3428 of the first outgoing wire group 34A and the fifth via hole K5 corresponding to the eighth connection part 3428 of the second outgoing wire group 34B are adjacent to each other, and the sixth via hole K6 corresponding to the eighth connection part 3439 of the first outgoing wire group 34A and the sixth via hole K6 corresponding to the eighth connection part 3439 of the second outgoing wire group 34B are adjacent to each other. That is to say, in this structure, the arrangement order of each via hole is as follows: the fourth via hole K4 of the first outgoing wire group 34A, the fourth via hole K4 of the second outgoing wire group 34B, the fifth via hole K5 of the first outgoing wire group 34A, the fifth via hole K5 of the second outgoing wire group 34B, the sixth via hole K6 of the first outgoing wire group 34A, and the sixth via hole K6 of the second outgoing wire group 34B, so as to form the arrangement design of the outgoing wires when forming the fifth overlapping area S5 for the first wire routing area 31.

[0169] Exemplarily, although the jumper design is carried out using each via hole to form an overlapping design of the same type of outgoing wires in the second wire routing area 32, one end of the third wire routing area 33 of the present embodiment connected to the bonding terminal 21 is still arranged according to the SST rule, which not only realizes the overlapping design of the same type of outgoing wires in the second wire routing area 32, but also makes the arrangement rules of the display terminal 41 and the bonding terminal 21 the same.

[0170] In an alternative embodiment, as Figure 20 shown, the display area AA includes a driving thin film transistor 42 located on the substrate 10, and the driving thin film transistor includes:

[0171] an active layer 421 disposed on the substrate 10;

[0172] an interlayer dielectric layer 422 covering the active layer 421;

[0173] a gate 423 disposed on the interlayer dielectric layer 422;

[0174] a gate insulating layer 424 covering the gate 423; and

[0175] a source-drain electrode layer 425 located on the gate insulating layer 424;

[0176] Among them, the first conductive layer 35 is disposed on the same layer as the gate electrode 424, the second conductive layer 37 is disposed on the same layer as the source-drain electrode layer 426, and the first insulating layer 36 is disposed on the same layer as the gate insulating layer 425.

[0177] Therefore, each fan-out line in the non-display area NA of this embodiment can be disposed on the same layer as each metal layer in the display area AA. That is, when manufacturing the driving thin-film transistor, the first conductive layer 35, the second conductive layer 37, and the first insulating layer 36 of this embodiment can be formed simultaneously by the same process, thereby improving the manufacturing efficiency.

[0178] Another embodiment of the present invention provides a display device, which is characterized by including the array substrate of the above embodiment of the present invention.

[0179] Based on the same inventive concept, an embodiment of the present application also provides a display device. The display device includes the array substrate provided in any embodiment of the present application, and may further include structures such as a backlight module, which will not be elaborated here. In this embodiment, the display device may be a mobile phone. In other alternative embodiments of the present invention, the display device may also be any display function-equipped device such as a tablet computer, a notebook, a monitor, etc.

[0180] It should also be noted that in the description of the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0181] Obviously, the above embodiments of the present invention are merely examples for clearly explaining the present invention, rather than limiting the embodiments of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the embodiments here. Any obvious changes or modifications derived from the technical solutions of the present invention still fall within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, Comprising: A substrate, a display area disposed on the substrate, and a non-display area at least partially surrounding the display area, the non-display area including a bonding area and a fan-out routing area disposed between the bonding area and the display area; The fan-out routing area includes: a first routing area, a second routing area, and a third routing area arranged in sequence along a first direction perpendicular to the second direction, the first routing area being located on the side close to the display area; The fan-out routing area further includes a plurality of fan-out line groups arranged in an array along the second direction, one end of each fan-out line group is connected to the display area, sequentially passing through the first routing area, the second routing area, and the third routing area, and the other end is connected to the bonding area; Wherein, each fan-out line group includes a first fan-out line, a second fan-out line, and a third fan-out line arranged in sequence along the second direction, Two first fan-out lines in two of the fan-out line groups located in the second routing area overlap at least partially in the projection on the substrate to form a first overlapping area, and the two first fan-out lines at the first overlapping area are disposed on different layers; Two second fan-out lines in two of the fan-out line groups located in the second routing area overlap at least partially in the projection on the substrate to form a second overlapping area, and the two second fan-out lines at the formed first overlapping area are disposed on different layers; Two third fan-out lines in two of the fan-out line groups located in the second routing area overlap at least partially in the projection on the substrate to form a third overlapping area, and the two third fan-out lines at the third overlapping area are disposed on different layers.

2. The array substrate according to claim 1, wherein The array substrate further includes a first conductive layer formed on the substrate, a first insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the first insulating layer, At the first overlapping area, one of the first fan-out lines is located on the first conductive layer or the second conductive layer, and the other first fan-out line is located on the second conductive layer or the first conductive layer, At the second overlapping area, one of the second fan-out lines is located on the first conductive layer or the second conductive layer, and the other second fan-out line is located on the second conductive layer or the first conductive layer, At the third overlapping area, one of the third fan-out lines is located on the first conductive layer or the second conductive layer, and the other third fan-out line is located on the second conductive layer or the first conductive layer.

3. The array substrate according to claim 2, wherein The display area includes a plurality of display terminals disposed at the location surrounded by the non-display area, and the display terminals are arranged along the second direction; The first fan-out line includes a first connection portion located in the first routing area and connecting the display terminal, the second fan-out line includes a second connection portion located in the first routing area and connecting the display terminal, and the third fan-out line includes a third connection portion located in the first routing area and connecting the display terminal, When two connection portions in two fan-out line groups located in the first routing area form a fourth overlapping area in the orthographic projection on the substrate, the two connection portions at the fourth overlapping area are located on different layers.

4. The array substrate according to claim 3, wherein The bonding area is provided with a plurality of bonding terminals arranged along the second direction, The first fan-shaped outgoing line further includes a seventh connecting portion located in the third wiring region and connecting the bonding terminal, the second fan-shaped outgoing line further includes an eighth connecting portion located in the third wiring region and connecting the bonding terminal, and the third fan-shaped outgoing line further includes a ninth connecting portion located in the third wiring region and connecting the bonding terminal. When any two fan-shaped outgoing lines in the two fan-shaped outgoing line groups located in the third wiring region form a fifth overlapping region in the orthographic projection on the substrate, the two connecting portions at the fifth overlapping region are located on different layers.

5. The array substrate according to claim 4, wherein The first fan-shaped outgoing line further includes a fourth connecting portion located in the second wiring region. The fourth connecting portion includes the first fan-shaped outgoing line corresponding to the first overlapping region. The fourth connecting portion is connected to the first connecting portion through a first via hole and is connected to the seventh connecting portion through a fourth via hole. The second fan-shaped outgoing line further includes a fifth connecting portion located in the second wiring region. The fifth connecting portion includes the second fan-shaped outgoing line corresponding to the second overlapping region. The fifth connecting portion is connected to the second connecting portion through a second via hole and is connected to the eighth connecting portion through a fifth via hole. The third fan-shaped outgoing line further includes a sixth connecting portion located in the second wiring region. The sixth connecting portion further includes the third fan-shaped outgoing line corresponding to the third overlapping region. The sixth connecting portion is connected to the third connecting portion through a third via hole and is connected to the ninth connecting portion through a sixth via hole.

6. The array substrate according to claim 5, wherein When the orthographic projections of the respective connecting portions located in the first wiring region on the substrate do not overlap The first connecting portion, the second connecting portion, and the third connecting portion are located in the first conductive layer or the second conductive layer. The first via hole, the second via hole, and the third via hole are arranged in sequence in the second direction.

7. The array substrate according to claim 5, wherein When the orthographic projections of the respective connecting portions located in the third wiring region on the substrate do not overlap The respective connecting portions located in the third wiring region are located in the first conductive layer or the second conductive layer. The fourth via hole, the fifth via hole, and the sixth via hole are arranged in sequence in the second direction.

8. The array substrate according to claim 5, wherein When any two of the first connecting portion, the second connecting portion, and the third connecting portion in the two fan-shaped outgoing line groups located in the first wiring region form a fourth overlapping region in the orthographic projection on the substrate, among the two connecting portions forming the fourth overlapping region, one connecting portion is located in the first conductive layer or the second conductive layer, and the other connecting portion is located in the second conductive layer or the first conductive layer.

9. The array substrate according to claim 8, wherein In the two fan-shaped outgoing line groups located in the first wiring region The first via hole corresponding to the first connecting portion of one fan-shaped outgoing line group and the first via hole corresponding to the first connecting portion of the other fan-shaped outgoing line group are arranged adjacent to each other. The second via hole corresponding to the second connecting portion of one fan-shaped outgoing line group and the second via hole corresponding to the second connecting portion of the other fan-shaped outgoing line group are arranged adjacent to each other. The third via hole corresponding to the third connecting portion of one fan-shaped outgoing line group and the third via hole corresponding to the third connecting portion of the other fan-shaped outgoing line group are arranged adjacent to each other.

10. The array substrate according to claim 5, wherein in two fan-out line groups located in the third wiring region, when a fifth overlapping region is formed by the orthographic projection of any two of the seventh connection portion, the eighth connection portion, and the ninth connection portion on the substrate, among the two connection portions forming the fifth overlapping region, one connection portion is located in the first conductive layer or the second conductive layer, and the other connection portion is located in the second conductive layer or the first conductive layer.

11. The array substrate according to claim 10, wherein in two fan-out line groups located in the third wiring region, the fourth vias corresponding to the seventh connection portions of one of the fan-out line groups and the fourth vias corresponding to the seventh connection portions of the other fan-out line group are arranged adjacent to each other; the fifth vias corresponding to the eighth connection portions of one of the fan-out line groups and the fifth vias corresponding to the eighth connection portions of the other fan-out line group are arranged adjacent to each other; the sixth vias corresponding to the ninth connection portions of one of the fan-out line groups and the sixth vias corresponding to the ninth connection portions of the other fan-out line group are arranged adjacent to each other; when an overlapping region is formed by the orthographic projection of any two of the seventh connection portion, the eighth connection portion, and the ninth connection portion on the substrate, among the two connection portions forming the overlapping region, one connection portion is located in the first conductive layer or the second conductive layer, and the other is located in the second conductive layer or the first conductive layer.

12. The array substrate according to claim 2, wherein the display region includes driving thin-film transistors located on the substrate, and the driving thin-film transistors include: a gate electrode, a gate insulating layer covering the gate electrode; and a source-drain electrode layer located on the gate electrode; wherein, the first conductive layer is arranged on the same layer as the gate electrode, the second conductive layer is arranged on the same layer as the source-drain electrode layer, and the first insulating layer is arranged on the same layer as the gate insulating layer.

13. The array substrate according to claim 1, wherein The central axes of the two first fan-out lines at the first overlapping region coincide with each other in the orthographic projection on the substrate, the central axes of the two second fan-out lines at the second overlapping region coincide with each other in the orthographic projection on the substrate, and the central axes of the two third fan-out lines at the third overlapping region coincide with each other in the orthographic projection on the substrate.

14. The array substrate according to claim 1, wherein The first fan-out line and the second fan-out line are data signal lines, the polarities of the first fan-out line and the second fan-out line are opposite, and the third fan-out line is a touch signal line.

15. A display device, characterized in that, including the array substrate according to any one of claims 1 to 14.

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