6° beveled GOS substrate, short-wave infrared focal plane pixel and its fabrication method

Abstract

This invention relates to a 6° beveled GOS substrate, a short-wave infrared focal plane pixel, and a method for fabricating the same. The 6° beveled GOS substrate comprises SiN0 from bottom to top. x The structure consists of a layer, a doped polycrystalline silicon layer, a sapphire substrate, a dielectric stack layer, and a 6° beveled germanium layer, where x≠0. This invention solves the problems of large lattice mismatch and high thermal mismatch in the epitaxial growth of III-V materials, improves the quality of III-V epitaxial materials and the responsivity of devices such as short-wave infrared focal plane arrays based on them, and reduces the dark current of the devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a 6° obliquely cut GOS substrate, a short-wave infrared focal plane pixel, and a method for fabricating the same. Background Technology

[0002] Short-wave infrared focal plane arrays based on III-V group short-wave infrared materials possess characteristics such as high sensitivity, high uniformity, and high stability, with a response band covering the range of 0.9–3.0 μm. However, commercially available III-V group short-wave infrared focal plane arrays face drawbacks such as small wafer size, high manufacturing cost, and small array size. Replacing high-cost small-size substrates with low-cost, large-size substrates is an inevitable trend. Sapphire substrates not only possess the advantages of large size and mature manufacturing processes but also low cost. Therefore, realizing high-performance III-V group short-wave infrared focal plane arrays on sapphire substrates is one of the important technical approaches supporting the development of low-cost short-wave infrared imaging technology. The technical challenge lies in the large lattice mismatch and high thermal mismatch issues encountered when directly epitaxially growing III-V group short-wave infrared materials on sapphire substrates.

[0003] Therefore, this invention is proposed. Summary of the Invention

[0004] The main objective of this invention is to provide a method for preparing a 6° beveled GOS substrate, a short-wave infrared focal plane pixel, and both. This method solves the problems of large lattice mismatch and high thermal mismatch in the epitaxial growth of III-V materials, improves the quality of III-V epitaxial materials and the responsivity of devices such as short-wave infrared focal plane pixels based on them, and reduces the dark current of the devices.

[0005] To achieve the above objectives, the present invention provides the following technical solutions.

[0006] A first aspect of the present invention provides a 6° beveled GOS substrate comprising, from bottom to top, SiN x The structure consists of a layer, a doped polycrystalline silicon layer, a sapphire substrate, a dielectric stack layer, and a 6° beveled germanium layer, where x ≠ 0.

[0007] Compared to both ordinary GOI substrates and III-V-OI substrates, the 6° beveled GOS substrate provided by this invention, due to its 6° bevel angle and high crystal quality, can improve the quality of III-V group materials epitaxially grown on it, reduce defect density, and avoid problems such as large lattice mismatch and high thermal mismatch.

[0008] In addition, the present invention can also achieve the following effects due to the specific stacked structure described above:

[0009] On the one hand, the dielectric stacked layer in the obliquely cut GOS substrate provided by the present invention has a resonant cavity effect, which can significantly improve the responsivity when used for short-wave infrared focal plane pixels;

[0010] On the other hand, adding a doped polycrystalline silicon layer to a sapphire substrate can give it optical and electrical properties similar to those of a silicon wafer. These properties can be recognized by device fabrication equipment that uses a silicon wafer as a substrate, thus avoiding incompatibility issues with the fabrication equipment.

[0011] On the other hand, since semiconductor devices such as short-wave infrared focal plane pixels involve wet etching or other corrosion steps during processing, this corrosion can easily damage the doped polysilicon layer. This invention adds SiN... x The layer can avoid the above-mentioned damage problems and improve the quality and reliability of the device.

[0012] The dielectric stack layer in this invention can be a stack of multiple dielectric materials, or a multi-layer stack of the same dielectric material.

[0013] For example, in some embodiments, the dielectric stack is a stack of multiple silicon oxide layers, or a cross stack of silicon oxide and aluminum oxide, or a stack of multiple aluminum oxide layers.

[0014] In some embodiments, the dielectric stack layer includes a silicon oxide layer and an aluminum oxide layer, with the silicon oxide layer close to the sapphire substrate.

[0015] In some embodiments, the thickness of the 6° beveled germanium layer is 100–500 nm, which has a lower defect density.

[0016] In some embodiments, the thickness of the doped polysilicon layer is 2000 nm or more, and the resistivity is preferably 0.001 to 1000 Ohm·cm. This property of the polysilicon layer can be accurately identified by existing wafer fabrication equipment.

[0017] In some embodiments, the SiN x The layer has a thickness of 50–500 nm, which can fully protect the doped polysilicon from corrosion.

[0018] A second aspect of the present invention provides a method for preparing a 6° beveled GOS substrate, comprising:

[0019] Provides 6° beveled silicon substrates;

[0020] A low-temperature germanium layer and a high-temperature germanium layer are sequentially formed on the 6° beveled silicon substrate;

[0021] A first dielectric layer is formed on the high-temperature germanium layer to obtain a sacrificial substrate;

[0022] Provide sapphire substrates;

[0023] A doped polycrystalline silicon layer and a SiN layer are sequentially formed from bottom to top on the front side of the sapphire substrate. x A second dielectric layer is formed on the back side of the sapphire substrate to obtain a support substrate;

[0024] Using the first dielectric layer and the second dielectric layer as bonding surfaces, the sacrificial substrate and the supporting substrate are bonded together;

[0025] Then, the obliquely cut silicon substrate and the low-temperature germanium layer are removed sequentially.

[0026] Optionally, the surface of the high-temperature germanium layer may be subjected to CMP treatment.

[0027] The above method uses a 6° beveled silicon substrate with the same bevel angle as a template or guiding substrate to grow a high-quality beveled high-temperature germanium layer, and then transfers it to a sapphire substrate by bonding. This can greatly improve the quality of the beveled high-temperature germanium layer and greatly reduce the defect density.

[0028] As mentioned above, this process also has the following advantages: it is compatible with silicon wafer processing equipment and the doped polycrystalline silicon layer is not easily corroded.

[0029] In some embodiments, the first dielectric layer and the second dielectric layer are each independently made of at least one of silicon oxide, aluminum oxide, or TEOS;

[0030] And / or, the second dielectric layer is a stacked layer of multilayer materials.

[0031] All of the above-mentioned dielectric stacking layers have good resonant cavity effects.

[0032] The second dielectric layer also adopts a multilayer material stacking form, which can further reduce the adverse effects of bonding on the obliquely cut high-temperature germanium layer, while improving the resonant cavity effect.

[0033] In some embodiments, the first dielectric layer is formed using the ALD method; for example, alumina is formed using the ALD method as the first dielectric layer.

[0034] And / or, the second dielectric layer is formed using at least one of thermal oxidation and CVD methods. When the second dielectric layer is a multilayer material stack, silicon can be grown on a sapphire substrate first, then a silicon oxide layer can be formed using thermal oxidation, and then a silicon oxide or other material layer can be formed using CVD.

[0035] In some embodiments, the 6° beveled silicon substrate is removed by grinding or dry etching;

[0036] And / or, the low-temperature germanium layer is removed using the TMAH etching method.

[0037] The above embodiments employ appropriate methods for removing different materials, which helps to reduce adverse effects on the substrate and improve process efficiency.

[0038] In some embodiments, high-temperature annealing or cyclic annealing is also performed during the formation of the high-temperature germanium layer. The high-temperature annealing temperature is 820°C, the annealing time is 10 min, and the annealing atmosphere is H2. This approach can further improve the crystal quality of the obliquely cut germanium layer.

[0039] In some embodiments, the growth temperature of the high-temperature germanium layer is 550-750°C, and the growth temperature of the low-temperature germanium layer is 350-450°C.

[0040] A third aspect of the present invention provides a short-wave infrared focal plane pixel, comprising:

[0041] The 6° beveled GOS substrate mentioned above;

[0042] A GaAs buffer layer located on the substrate;

[0043] A PIN stack structure located above the GaAs buffer layer, wherein the PIN stack structure is made of a III-V group material, and the PIN stack structure mainly includes: N + -InGaAs / I-InGaAs / P + -InGaAs, N + -InP / I-InGaAs / P + -InP,P + -GaAsSb / I-InGaAs / N + -InP,N + -GaAs / I-AlGaAs / InGaAs multiple quantum well / P + -GaAs, N + -GaAs / I-AlGaAs / InGaAs multiple quantum dots / P + -GaAs, etc.;

[0044] And N-type contact structures and P-type contact structures that respectively achieve ohmic contact with the N-layer and P-layer in the PIN stack structure.

[0045] The short-wave infrared focal plane array uses a 6° beveled GOS substrate as described above. Therefore, the grown III-V group PIN stacked structure inevitably has high quality, without problems such as large lattice mismatch and high thermal mismatch, resulting in improved responsivity and reduced dark current. Furthermore, GaAs is used as a buffer layer in this scheme, further improving crystal quality.

[0046] In some embodiments, the PIN stacking structure is a vertical stacking structure.

[0047] Of course, the present invention does not exclude horizontally stacked PIN structures.

[0048] In addition, the order of the PIN vertical stacking structure can be PIN from bottom to top, or NIP.

[0049] A fourth aspect of the present invention provides a method for preparing the above-mentioned short-wave infrared focal plane pixel, comprising:

[0050] First, a 6° oblique-cut GOS substrate is obtained using the above-described method for preparing a 6° oblique-cut GOS substrate.

[0051] A GaAs buffer layer is formed on the 6° beveled GOS substrate;

[0052] A PIN stack structure is formed on the GaAs buffer layer;

[0053] The N-type contact structure and the P-type contact structure are formed respectively.

[0054] In some embodiments, a three-step method of low temperature-medium temperature-high temperature is used to form the GaAs buffer layer, and the ranges of low temperature, medium temperature and high temperature are 390~410℃, 580~610℃ and 660~680℃, respectively. The preferred ranges of low temperature, medium temperature and high temperature are 400℃, 600℃ and 670℃.

[0055] In some embodiments, after forming the N-type contact structure and the P-type contact structure, the method further includes forming a two-dimensional crystal. The two-dimensional crystal can improve susceptibility.

[0056] In some embodiments, prior to forming the N-type and P-type contact structures, the process further includes: patterning the PIN stack structure to form mesas; the mesas expose layers in the PIN stack structure adjacent to the GaAs buffer layer. This structure simplifies the device patterning process, eliminating the need to etch contact holes and other structures prone to defects.

[0057] In summary, compared with the prior art, the present invention achieves the following technical effects: on the one hand, a high-quality 6° beveled GOS substrate is obtained; on the other hand, based on this substrate, high-quality epitaxial III-V group short-wave infrared focal plane pixels are obtained, which have high responsivity and lower dark current; furthermore, all process flows and structures are compatible with existing semiconductor process equipment, and have advantages such as low cost. Attached Figure Description

[0058] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0059] Figure 1-11 Schematic diagrams of the structures obtained by each step of the preparation method of the 6° beveled GOS substrate provided by the present invention;

[0060] Figure 12-16 The diagram shows the structural results obtained from each step of the method for preparing shortwave infrared focal plane pixels provided by this invention. Detailed Implementation

[0061] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0062] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0063] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0064] Existing III-V group short-wave infrared focal plane pixels are limited by the quality of the substrate crystal and cannot avoid problems such as large lattice mismatch and high thermal mismatch, resulting in poor key indicators such as device responsivity and dark current.

[0065] Therefore, the present invention provides a 6° obliquely cut GOS substrate and its preparation method, as well as a short-wave infrared focal plane pixel based on the substrate and its preparation method.

[0066] The key structural features of the 6° beveled GOS substrate provided by this invention are the "bevel angle" and the crystal quality of the germanium layer, which includes SiN from bottom to top. xThe structure consists of a polycrystalline silicon layer, a sapphire substrate, a dielectric stack layer, and a 6° beveled germanium layer. Where x≠0, the ratio of silicon to nitrogen is not particularly limited, but a nitrogen-silicon ratio that provides good shielding for the polycrystalline silicon is preferred.

[0067] To obtain the high-quality 6° beveled GOS substrate, the fabrication process provided by this invention mainly includes four key stages: fabrication of a sacrificial substrate, fabrication of a support substrate, bonding, and removal of excess layers, as detailed below.

[0068] I. Fabrication of Sacrificial Substrates

[0069] First, a 6° beveled silicon substrate is provided.

[0070] Then, a low-temperature germanium layer and a high-temperature germanium layer are sequentially formed on the 6° beveled silicon substrate. In this step, the growth temperatures of the low-temperature germanium layer and the high-temperature germanium layer can be within the ranges of 350-450℃ and 550-750℃, respectively. Furthermore, adding high-temperature annealing or cyclic annealing can further improve the crystal quality. Annealing can be performed after the formation of the subsequent first dielectric layer. The annealing temperature is appropriately controlled at 820℃, the annealing time is 10 minutes, and the annealing atmosphere is H2.

[0071] Additionally, a compositionally graded germanium-silicon buffer layer can be added before forming the germanium layer. Using a compositionally graded germanium-silicon buffer layer can further improve the crystal quality of the obliquely cut germanium layer.

[0072] Next, a first dielectric layer is formed on the high-temperature germanium layer to obtain a sacrificial substrate. The first dielectric layer can be an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer, or a stack of these layers. When selecting its material, the resonant cavity effect, as well as the ease and stability of bonding to the supporting substrate, must be considered. Therefore, aluminum oxide is preferably used in this invention.

[0073] II. Fabrication of the Support Substrate

[0074] First, sapphire substrates are provided. Sapphire substrates have the characteristics of large size and mature manufacturing process, and also have advantages such as high resistivity, low radio frequency (RF) loss, strong crosstalk suppression capability, and strong radiation resistance.

[0075] Then, from bottom to top, a doped polycrystalline silicon layer and a SiN layer are sequentially formed on the front side of the sapphire substrate. x A second dielectric layer is formed on the back side of the sapphire substrate to obtain a supporting substrate.

[0076] In the fabrication of the sacrificial substrate and the support substrate described above, the methods for forming each dielectric layer include, but are not limited to, CVD, ALD, PCVD, PECVD, thermal oxidation, etc.

[0077] III. Bonding

[0078] The sacrificial substrate and the supporting substrate are bonded using the first dielectric layer and the second dielectric layer as bonding surfaces. Fusion bonding is typically used.

[0079] IV. Removing excess layers

[0080] The 6° beveled silicon substrate and the low-temperature germanium layer are removed sequentially. Removal methods include, but are not limited to, CMP, dry etching, wet etching, or a combination of these methods. Preferably, different methods are used for different materials; for example, grinding or dry etching is used to remove the beveled silicon substrate, and TMAH etching is used to remove the low-temperature germanium layer.

[0081] The surface of the high-temperature germanium layer can then be planarized to reduce roughness, typically using CMP (chemical mechanical polishing).

[0082] When fabricating short-wave infrared focal plane pixels on the 6° obliquely cut GOS substrate obtained above, the subsequent process also includes the following main steps:

[0083] First, a GaAs buffer layer is formed on the 6° beveled GOS substrate. The GaAs buffer layer is preferably formed using a three-step method of low-temperature-medium-high-temperature, with the low-temperature, medium-temperature, and high-temperature ranges being 390–410°C, 580–610°C, and 660–680°C, respectively. The preferred ranges for the low-temperature, medium-temperature, and high-temperature ranges are 400°C, 600°C, and 670°C, respectively.

[0084] Then, a PIN stack structure is formed on the GaAs buffer layer. This stack structure can be horizontal or vertical, and the order of the P-type and N-type layers is arbitrary. Furthermore, the PIN stack structure of this invention uses a III-V group material.

[0085] The N-type contact structure and the P-type contact structure are then formed respectively. The contact structure is an ohmic contact, which can take the form of a mesa or a contact hole, with a mesa being preferred.

[0086] Finally, a two-dimensional crystal can be formed by any choice.

[0087] Based on the core of the solution described above, the present invention also provides the following preferred embodiments.

[0088] Example 1: Fabrication of a 6° beveled GOS substrate

[0089] Sacrificial substrate fabrication stage:

[0090] Step S1: Form a 6° angled low-temperature germanium buffer layer 2 on a 6° angled silicon substrate 1, such as... Figure 1 As shown, a 6° beveled high-temperature germanium buffer layer 3 is then formed, as... Figure 2As shown. The growth temperatures for low temperature and high temperature are 350-450℃ and 550-750℃, respectively.

[0091] Step S2: An aluminum oxide layer 4 is formed on a 6° beveled high-temperature germanium buffer layer 3 using the ALD method to obtain a sacrificial substrate, as shown below. Figure 3 As shown.

[0092] Substrate fabrication stage:

[0093] Step S3: A polycrystalline silicon layer is formed on the front side of the sapphire substrate 5, and then it is doped to form a doped polycrystalline silicon layer 6, as shown below. Figure 4 The doping concentration, depth, and type are not limited, as long as their electrical and optical properties allow for recognition by silicon wafer processing. The doping type can be N-type or P-type. The thickness of the polycrystalline silicon layer can be selected to be above 2000 nm to meet the recognition requirements of most devices, and the resistivity after doping can reach 0.001–1000 Ohm·cm.

[0094] Step S4, as follows Figure 5 SiN is formed on the doped polycrystalline silicon layer 6. x Layer 7, with a thickness of 50–500 nm, is used to protect polycrystalline silicon.

[0095] Step S5: Form a silicon oxide layer on the back side of the sapphire substrate 5. This can be achieved by first depositing a silicon 8 layer, such as... Figure 6 Then, a silicon oxide layer 9 is formed using a thermal oxidation method, such as... Figure 7 As shown.

[0096] Step S6: A TEOS layer 10 is formed on the silicon oxide layer 9 using the TEOS method to obtain a supporting substrate, as shown below. Figure 8 As shown.

[0097] Bonding and removing redundant layers:

[0098] Step S7: Using the alumina layer 4 and the TEOS layer 10 as bonding surfaces, the sacrificial substrate and the support substrate are fused and bonded, as follows: Figure 9 As shown.

[0099] Step S8, then grinding or dry etching is used to remove the 6° beveled silicon substrate 1, as shown. Figure 10 As shown.

[0100] Step S9, then remove the 6° beveled low-temperature germanium buffer layer 2 using the TMAH etching method, as shown. Figure 11 As shown;

[0101] Step S10 involves CMP treatment of the surface of the 6° beveled high-temperature germanium buffer layer 3 until the thickness reaches 100–500 nm, at which point the defect density can be as low as 10. 7 cm -2Magnitude.

[0102] Example 2: Fabrication of shortwave infrared focal plane pixels

[0103] The first step is to form a GaAs buffer layer 11 on the 6° beveled GOS substrate obtained in Example 1, as follows: Figure 12 As shown; the formation method is a three-step process of low temperature (400℃) - medium temperature (600℃) - high temperature (670℃).

[0104] The second step is to form a PIN stack structure on the GaAs buffer layer 11: from bottom to top, it consists of: a P-type III-V material layer 12, a III-V short-wave infrared absorption layer 13, and an N-type III-V material layer 14, as shown in Figure 13.

[0105] The third step is to graphically process the PIN stack structure to form a shape like... Figure 14 As shown.

[0106] The fourth step involves surface passivation of the formed PIN stack structure, with a passivation layer thickness of 15. Figure 15 As shown.

[0107] Fifth step, forming the N-type contact structure and P-type contact structure respectively: etching contact holes in the passivation layer, thereby depositing metals 16 and 17 at the exposed areas of the P-type III-V material layer 12 and the N-type III-V material layer 14, as shown. Figure 16 As shown.

[0108] The sixth step is to form a two-dimensional crystal, which is not shown in the figure. Adjustments should be made as needed.

[0109] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for preparing a 6° beveled GOS substrate, characterized in that, include: Provides 6° beveled silicon substrates; A low-temperature germanium layer and a high-temperature germanium layer are sequentially formed on the 6° beveled silicon substrate; The growth temperature of the high-temperature germanium layer is 550–750°C, and the growth temperature of the low-temperature germanium layer is 350–450°C. A first dielectric layer is formed on the high-temperature germanium layer to obtain a sacrificial substrate; Provide sapphire substrates; A doped polycrystalline silicon layer and a SiN layer are sequentially formed from bottom to top on the front side of the sapphire substrate. x A second dielectric layer is formed on the back side of the sapphire substrate to obtain a supporting substrate; the SiN x The thickness of the layer is 50–500 nm; Using the first dielectric layer and the second dielectric layer as bonding surfaces, the sacrificial substrate and the supporting substrate are bonded together; Then, the 6° beveled silicon substrate and the low-temperature germanium layer are removed sequentially to obtain the 6° beveled germanium layer, the thickness of which is 100-500 nm. The surface of the high-temperature germanium layer is subjected to CMP treatment.

2. The preparation method according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer are each independently made of at least one of silicon oxide, aluminum oxide, or TEOS; And / or, the second dielectric layer is a stacked layer of multilayer materials.

3. The preparation method according to claim 1, characterized in that, The first dielectric layer is formed using the ALD method; And / or, the second dielectric layer is formed using at least one of thermal oxidation and CVD methods.

4. The preparation method according to claim 1, characterized in that, The 6° beveled silicon substrate was removed by grinding or dry etching. And / or, the low-temperature germanium layer is removed using the TMAH etching method.

5. The preparation method according to claim 1, characterized in that, During the formation of the high-temperature germanium layer, a high-temperature annealing or cyclic annealing process is also performed. The high-temperature annealing temperature is 820°C, the annealing time is 10 min, and the annealing atmosphere is H2.

6. A 6° beveled GOS substrate, characterized in that, The substrate is prepared by the method described in any one of claims 1 to 5, and the substrate comprises SiN from bottom to top. x The structure consists of a layer, a doped polycrystalline silicon layer, a sapphire substrate, a dielectric stack layer, and a 6° beveled germanium layer, where x ≠ 0. The SiN x The thickness of the layer is 50–500 nm; The thickness of the 6° beveled germanium layer is 100–500 nm.

7. The 6° beveled GOS substrate according to claim 6, characterized in that, The dielectric stack is a stack of multiple silicon oxide layers, or a cross stack of silicon oxide and aluminum oxide, or a stack of multiple aluminum oxide layers.

8. The 6° beveled GOS substrate according to claim 7, characterized in that, The dielectric stack layer includes a silicon oxide layer and an aluminum oxide layer, with the silicon oxide layer close to the sapphire substrate.

9. The 6° beveled GOS substrate according to claim 6, characterized in that, The thickness of the doped polycrystalline silicon layer is above 2000 nm, and the resistance reaches 0.001 to 1000 Ohm·cm.

10. A short-wave infrared focal plane pixel, characterized in that, include: A 6° beveled GOS substrate as described in any one of claims 6-9; A GaAs buffer layer located on the 6° GOS substrate; A PIN stack structure located above the GaAs buffer layer, wherein the PIN stack structure is made of a III-V group material, and the PIN stack structure is as follows: N + -InGaAs / I-InGaAs / P + -InGaAs,N + -InP / I-InGaAs / P + -InP,P + -GaAsSb / I-InGaAs / N + -InP,N + -GaAs / I-AlGaAs / InGaAs multi-quantum well / P + -GaAs,N + -GaAs / I-AlGaAs / InGaAs multi-quantum dots / P + -GaAs; And N-type contact structures and P-type contact structures that respectively achieve ohmic contact with the N-layer and P-layer in the PIN stack structure.

11. The shortwave infrared focal plane pixel according to claim 10, characterized in that, The PIN stacking structure is a vertical stacking structure.

12. A method for preparing a shortwave infrared focal plane pixel as described in claim 10 or 11, characterized in that, include: A 6° beveled GOS substrate was obtained using the preparation method described in any one of claims 1-5; A GaAs buffer layer is formed on the 6° beveled GOS substrate; A PIN stack structure is formed on the GaAs buffer layer; The N-type contact structure and the P-type contact structure are formed respectively.

13. The preparation method according to claim 12, characterized in that, A GaAs buffer layer was formed using a three-step method of low temperature-medium temperature-high temperature, with the low temperature, medium temperature and high temperature ranges being 390~410℃, 580~610℃ and 660~680℃, respectively.

14. The preparation method according to claim 13, characterized in that, The low temperature, medium temperature, and high temperature are 400℃, 600℃, and 670℃, respectively.

15. The preparation method according to claim 12, characterized in that, After forming the N-type contact structure and the P-type contact structure, the process further includes: forming a two-dimensional crystal.

16. The preparation method according to claim 12, characterized in that, Before forming the N-type contact structure and the P-type contact structure, the method further includes: patterning the PIN stack structure to form a mesa; the mesa exposes the layer in the PIN stack structure that is close to the GaAs buffer layer.

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