A method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode.

Abstract

This invention provides a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. A barrier layer is formed on a drift layer of a silicon carbide substrate, and vias are etched into the barrier layer. Ion implantation is performed through the vias to form a first base region, a second base region, a third base region, and a fourth base region, forming a source region. The barrier layer is then reformed and etched again to form vias. Oxidation is performed through the vias to form a first gate dielectric isolation layer and a second gate dielectric isolation layer. The barrier layer is reformed again and etched again to form vias. A first source metal layer, a second source metal layer, a first gate metal layer, a second gate metal layer, and a source heterojunction are deposited through the vias. All barrier layers are removed, and metal is deposited on the silicon carbide substrate to form a drain metal layer. This method distributes the MOSFET current across the left and right sides of the device, avoiding current concentration, reducing thermal management issues, and improving device reliability.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Background Technology

[0002] Silicon carbide (SiC) materials have attracted widespread attention and research due to their superior physical properties. Their high-temperature, high-power electronic devices possess advantages such as high input impedance, fast switching speed, high operating frequency, and resistance to high temperatures and pressures, leading to their widespread application in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] However, due to the superior material properties of SiC, the current density of devices is increasing, which places new demands on the internal heat distribution of the devices. This requires a more uniform current channel distribution, less heat concentration, and faster heat dissipation. At the same time, parasitic body diode losses in MOSFETs are an unavoidable problem for vertical devices. How to reduce the body diode forward voltage drop and suppress the bipolar effect is an urgent problem to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode, so that the current of the MOSFET is distributed on the left and right sides of the device, avoiding current concentration, reducing device thermal management problems, and improving device reliability.

[0005] This invention is achieved as follows: a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode, specifically including the following steps:

[0006] Step 1: Form a barrier layer on the drift layer of the silicon carbide substrate, and etch the barrier layer to form vias. Perform ion implantation on the drift layer through the vias to form the first base region, the second base region, the third base region and the fourth base region.

[0007] Step 2: Re-form a barrier layer on the drift layer, and etch the barrier layer to form vias. Ion implantation is performed on the first base region, the second base region, the third base region, and the fourth base region through the vias to form source regions.

[0008] Step 3: Reform the barrier layer and etch the barrier layer to form vias. Oxidize the vias to form the first gate dielectric isolation layer and the second gate dielectric isolation layer.

[0009] Step 4: Reform the barrier layer and etch the barrier layer to form vias. Deposit metal on the source region through the vias to form the first source metal layer and the second source metal layer.

[0010] Step 5: Reform the barrier layer and etch the barrier layer to form vias. Deposit metal on the gate dielectric isolation layer through the vias to form the first gate metal layer and the second gate metal layer.

[0011] Step 6: Reform the barrier layer and etch the barrier layer to form vias. Deposit through the vias to form the source heterojunction.

[0012] Step 7: Remove all barrier layers and deposit metal on the silicon carbide substrate to form a drain metal layer.

[0013] Furthermore, the first base region, the second base region, the third base region, and the fourth base region are all P-type.

[0014] The advantages of this invention are:

[0015] First, it adopts a symmetrical cell structure, with two gates in each cell and two sources in each gate. The two gates can form two conductive channels, so that the current of the MOSFET is distributed on the left and right sides of the device, avoiding current concentration, reducing device thermal management problems, and improving device reliability.

[0016] Second, there is a heterojunction in the middle of the two gate structures. This heterojunction structure becomes a source-to-drain heterojunction diode, which can reduce the on-state voltage drop of the SiC body diode and reduce the on-state conduction loss of the body diode. Moreover, this heterojunction diode has only one type of charge carrier, eliminating the bipolar degradation effect of traditional MOSFETs. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Figure 1 This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 1 .

[0019] Figure 2 This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 2 .

[0020] Figure 3 This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 3 .

[0021] Figure 4 This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 4 .

[0022] Figure 5This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 5 .

[0023] Figure 6 This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 6 .

[0024] Figure 7 This invention relates to a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. Figure 7 .

[0025] Figure 8 This is a schematic diagram of the principle of a planar gate silicon carbide MOSFET with integrated heterojunction diode according to the present invention. Figure 1 .

[0026] Figure 9 This is a cross-section of a planar gate silicon carbide MOSFET with integrated heterojunction diode according to the present invention. Figure 1 .

[0027] Figure 10 This is a cross-section of a planar gate silicon carbide MOSFET with integrated heterojunction diode according to the present invention. Figure 2 . Detailed Implementation

[0028] like Figures 1 to 10 As shown, the present invention discloses a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode, which specifically includes the following steps:

[0029] Step 1: Form a barrier layer a on the drift layer 2 of the silicon carbide substrate 1, and etch a through-hole to form a barrier layer a. Perform ion implantation on the drift layer 2 through the through-hole to form a first base region 21, a second base region 22, a third base region 23 and a fourth base region 24. The first base region 21, the second base region 22, the third base region 23 and the fourth base region 24 are all P-type.

[0030] Step 2: Re-form the barrier layer a on the drift layer 2, and etch the barrier layer to form a via. Ion implantation is performed on the first base region 21, the second base region 22, the third base region 23 and the fourth base region 24 through the via to form the source region 25.

[0031] Step 3: Reform the barrier layer a, and etch the barrier layer a to form a via. Oxidize the via to form the first gate dielectric isolation layer 6 and the second gate dielectric isolation layer 7.

[0032] Step 4: Reform the barrier layer a, and etch the barrier layer a to form a via. Deposit metal on the source region through the via to form the first source metal layer 3 and the second source metal layer 4.

[0033] Step 5: Reform the barrier layer a, and etch the barrier layer to form a via. Deposit metal on the gate dielectric isolation layer through the via to form the first gate metal layer 8 and the second gate metal layer 9.

[0034] Step 6: Reform the barrier layer a, and etch the barrier layer to form a via. Deposit through the via to form the source heterojunction 5.

[0035] Step 7: Remove all barrier layers a and deposit metal on silicon carbide substrate 1 to form drain metal layer 10.

[0036] like Figures 8 to 10 As shown, the MOSFET obtained by the above manufacturing method includes:

[0037] Silicon carbide substrate 1,

[0038] A drift layer 2 is disposed on the upper side of the silicon carbide substrate 1. The drift layer 2 has a first base region 21, a second base region 22, a third base region 23 and a fourth base region 24. A source region 25 is disposed in each of the first base region 21, the second base region 22, the third base region 23 and the fourth base region 24. The first base region 21, the second base region 22, the third base region 23 and the fourth base region 24 are all P-type.

[0039] The first source metal layer 3 is connected to the source region 25 of the first base region 21 and the second base region 22;

[0040] The second source metal layer 4 is connected to the source region 25 of the third base region 23 and the fourth base region 24;

[0041] Source heterojunction 5, which is connected to drift layer 2, second base region 22 and third base region 23;

[0042] A first gate dielectric isolation layer 6 is connected to the drift layer 2;

[0043] The second gate dielectric isolation layer 7 is connected to the drift layer 2;

[0044] A first gate metal layer 8 is connected to the first gate isolation layer 6;

[0045] The second gate metal layer 9 is connected to the second gate isolation layer 7;

[0046] And a drain metal layer 10, which is connected to the lower side of the silicon carbide substrate 1.

[0047] The MOSFET adopts a symmetrical cell structure. Each cell structure has a first gate metal layer 8 and a second gate metal layer 9. The first gate metal layer 8 is matched with the first source metal layer 3, and the second gate metal layer 9 is matched with the second source metal layer 4.

[0048] The first gate metal layer 8 and the second gate metal layer 9 can respectively form two conductive channels, so that the current of the MOSFET is distributed on the left and right sides of the device, avoiding current concentration, reducing device thermal management problems, and improving device reliability.

[0049] In this structure, when the current in the first source metal layer 3 and the second source metal layer 4 is concentrated in the channel below the first gate metal layer 8 and the second gate metal layer 9, the lateral current is evenly distributed on the source surface of the device, which can effectively reduce the current concentration effect of the device and reduce the degradation of device performance.

[0050] There is a source heterojunction 5 between the first gate metal layer 8 and the second gate metal layer 9. This source heterojunction 5 constitutes a heterojunction diode, which can reduce the on-state voltage drop of the body diode made of silicon carbide itself and reduce the on-state conduction loss of the body diode. The conductive channel of this source heterojunction diode does not coincide with the normal conductive channel of the MOSFET and is located in the middle of the device. Since the conduction time of the device body diode is short and the freewheeling requirement is low, its position distribution has the least impact on the thermal distribution of the device.

[0051] This heterojunction diode has only one type of charge carrier, which matches the unipolar conductivity of a MOSFET. Since there are no two types of charge carriers participating in conduction, it eliminates the bipolar degradation effect of traditional MOSFETs.

[0052] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode, characterized in that, Specifically, the steps include the following: Step 1: Form a barrier layer on the drift layer of the silicon carbide substrate, and etch the barrier layer to form vias. Perform ion implantation on the drift layer through the vias to form the first base region, the second base region, the third base region and the fourth base region. Step 2: Re-form a barrier layer on the drift layer, and etch the barrier layer to form vias. Then, perform ion implantation on the first base region, the second base region, the third base region, and the fourth base region through the vias to form source regions. Step 3: Reform the barrier layer and etch the barrier layer to form vias. Oxidize the vias to form the first gate dielectric isolation layer and the second gate dielectric isolation layer. Step 4: Reform the barrier layer and etch the barrier layer to form vias. Deposit metal on the source region through the vias to form the first source metal layer and the second source metal layer. Step 5: Reform the barrier layer and etch the barrier layer to form vias. Deposit metal on the gate dielectric isolation layer through the vias to form the first gate metal layer and the second gate metal layer. Step 6: Reform the barrier layer and etch the barrier layer to form vias. Deposit through the vias to form the source heterojunction. Step 7: Remove all barrier layers and deposit metal on the silicon carbide substrate to form a drain metal layer; A drift layer is disposed on the upper side of the silicon carbide substrate. The drift layer contains a first base region, a second base region, a third base region, and a fourth base region. Each of the first base region, the second base region, the third base region, and the fourth base region contains a source region. Each of the first base region, the second base region, the third base region, and the fourth base region is a P-type. The first source metal layer is connected to the source region of the first base region and the second base region; The second source metal layer is connected to the source regions of the third and fourth base regions; The source heterojunction is connected to the drift layer, the second base region, and the third base region; The first gate dielectric isolation layer is connected to the drift layer; The second gate dielectric isolation layer is connected to the drift layer; The first gate metal layer is connected to the first gate isolation layer; The second gate metal layer is connected to the second gate isolation layer.

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