Gate structure in semiconductor devices and method of forming the same

Abstract

This disclosure relates to gate structures in semiconductor devices and methods for forming the same. One method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are located in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively; forming a fluorine-containing layer, the fluorine-containing layer including a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer; removing the second portion of the fluorine-containing layer; performing an annealing process to diffuse fluorine from the first portion of the fluorine-containing layer into the first gate dielectric layer; and after the annealing process, forming a first work function layer and a second work function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to gate structures in semiconductor devices and methods for forming them. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given chip area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] A first aspect of this disclosure relates to a method comprising: removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench, wherein the first dummy gate stack and the second dummy gate stack are located in a first device region and a second device region, respectively; depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively; forming a fluorine-containing layer, the fluorine-containing layer comprising a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer; removing the second portion of the fluorine-containing layer; performing an annealing process to diffuse fluorine in the first portion of the fluorine-containing layer into the first gate dielectric layer; and after the annealing process, forming a first work function layer and a second work function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

[0005] A second aspect of this disclosure relates to a method comprising: forming a first dummy gate stack on a top surface and sidewalls of a first multilayer stack, wherein the first multilayer stack includes alternating first plurality of sacrificial layers and first plurality of nanostructures; forming a second dummy gate stack on a top surface and sidewalls of a second multilayer stack, wherein the second multilayer stack includes alternating second plurality of sacrificial layers and second plurality of nanostructures; removing the first dummy gate stack and the second dummy gate stack to form a first recess and a second recess in a dielectric layer, respectively; removing the first plurality of sacrificial layers and the second plurality of sacrificial layers; depositing a first gate dielectric surrounding the first plurality of nanostructures; depositing a second gate dielectric surrounding the second plurality of nanostructures; depositing a first protective layer and a second protective layer on the first gate dielectric and the second gate dielectric, respectively; forming a first fluorinated layer and a second fluorinated layer on the first protective layer and the second protective layer, respectively; removing the second fluorinated layer; performing an annealing process after removing the second fluorinated layer, wherein the first fluorinated layer is subjected to the annealing process; and removing the first fluorinated layer after the annealing process.

[0006] A third aspect of this disclosure relates to a method comprising: forming a first nanostructure in a first trench, wherein a first gate spacer is included in a portion on an opposite side of the first trench; forming a second nanostructure in a second trench, wherein a second gate spacer is included in a portion on an opposite side of the second trench; depositing a first gate dielectric extending into the first trench to surround the first nanostructure; depositing a second gate dielectric extending into the second trench to surround the second nanostructure; and, after forming the first gate dielectric and the second gate dielectric, adding fluorine to the first gate dielectric, wherein when fluorine is added to the first gate dielectric, the fluorine in the second gate dielectric remains substantially unchanged. Attached Figure Description

[0007] When with attachment Figure 1 When reading this document, the various aspects of this disclosure can be best understood from the following detailed description. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0008] Figure 1-45A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 14-15, 16A, 16B, 17, 18, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 24C, 24D, and 24E illustrate intermediate stages in forming a gate all-around (GAA) transistor according to some embodiments.

[0009] Figure 25-27 The distribution of fluorine atom percentages according to some embodiments is shown.

[0010] Figure 28 A process flow for forming a GAA transistor according to some embodiments is shown.

[0011] Figure 29 An example of a FinFET is shown, with a three-dimensional view according to some embodiments.

[0012] Figures 30-35 36A, 36B, 37A, 37B, 38A, 38B, 38C, 38D, 39A, 39B, 40A, 40B, 41A, 41B, 42A, 42B, 42C, 43, 44, 45, 46, 47, 48, 50A, 50B, 51A, 51B, 52A, and 52B illustrate intermediate stages in the formation of a FinFET according to some embodiments.

[0013] Figure 49 A flowchart illustrating a method for forming a layer for replacing a gate, according to some embodiments, is shown.

[0014] Figure 53 An example of a GAA transistor is shown, according to a three-dimensional view of some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatial relative terms such as “below,” “under,” “lower than,” “overlapping,” “higher than,” etc., may be used here to easily describe the relationship between one element or feature and another, as shown in the figure. Besides the orientation depicted in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0017] A method for selectively incorporating fluorine into a gate dielectric of a replacement gate stack, and a corresponding transistor, are provided. According to some embodiments, a dummy gate stack is removed from a first device region and a second device region, exposing a nanostructure. A first gate dielectric and a second gate dielectric are formed around the nanostructure. A protective layer can be formed on the gate dielectric, followed by deposition of a fluorine-containing layer. The fluorine-containing layer is removed from the second device region and remains in the first device region. An annealing process is then performed to diffuse fluorine into the first gate dielectric. The fluorine-containing layer in the first device region can then be removed. A function layer can then be formed on the first and second gate dielectrics.

[0018] According to some embodiments, fluorine treatment is applied to one or more gate dielectric layers of the gate structure, and a dipole dopant material is diffused into the gate dielectric layer, thereby adjusting the work function (and thus the threshold voltage) of the subsequently formed transistor. These aspects can also be implemented in various combinations, with or without an additional work function adjustment layer in the gate structure for adjusting the threshold voltage. In some embodiments, the work function of the transistor can be adjusted by dipole doping, thereby omitting the work function adjustment layer from the gate structure and allowing the gate structure to be formed to a smaller size. Therefore, the threshold voltage of the subsequently formed transistor can be adjusted by controlling the concentration of the dipole dopant material in the gate dielectric layer without negatively impacting the corresponding spacing of the transistor's gate structure. Introducing dipole dopant material into the gate dielectric layer can lead to charge accumulation in the gate dielectric layer, resulting in leakage paths and reliability issues in the transistor. Charge accumulation can be reduced by additionally diffusing fluorine into the gate dielectric layer.

[0019] In the description of this disclosure, gate-all-around (GAA) transistors (also known as nanostructures, such as nanosheets, nanowires, etc., field-effect transistors (NSFETs)) and fin field-effect transistors (FinFETs) are discussed to explain the concepts of this disclosure. Embodiments of this disclosure can also be applied to other types of transistors, such as planar transistors.

[0020] The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0021] Figure 1-4 Tables 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 14-15, 16A, 16B, 17, 18, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 24C, 24D, and 24E illustrate various views of intermediate stages in forming a GAA transistor according to some embodiments of the present disclosure. The corresponding processes are also schematically reflected in... Figure 28 The process flow shown is as follows.

[0022] refer to Figure 1 The image shows a perspective view of wafer 10. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate or a silicon-germanium (SiGe) substrate, etc., while other substrates and / or structures such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, etc., may be used. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0023] According to some embodiments, the multilayer stack 22 is formed through a series of deposition processes for depositing alternating materials. The corresponding processes are described in... Figure 28 The process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0024] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is achieved through epitaxial growth, and the corresponding deposition method can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed in approximately... and approximately The first thickness is within the range between [specific thicknesses]. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0025] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or combinations thereof, which differs from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B can be formed of silicon, and vice versa. It is understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0026] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, the second layer 22B may be formed, for example, to a thickness of approximately... and approximately The second thickness within the range between.

[0027] Once the second layer 22B is formed on top of the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 has been formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as sacrificial layer 22A throughout the description. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0028] According to some embodiments, a number of pad oxide layers and hard mask layers (not shown) are formed on top of the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0029] refer to Figure 2 In one or more etching processes, a portion of the multilayer stack 22 and the underlying substrate 20 is patterned to form trenches 23. The corresponding process is... Figure 28 The process flow 200 shown is indicated as process 204. Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', a portion of substrate 20 is left and is hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. hereinafter, semiconductor layer 22A is alternatively referred to as sacrificial layer, and semiconductor layer 22B is alternatively referred to as nanostructure. The portion of multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0030] In the above embodiments, the GAA transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0031] Figure 3 The formation of isolation zone 26 is shown; throughout this embodiment, isolation zone 26 is also referred to as a shallow trench isolation (STI) zone. The corresponding process is described in... Figure 28 The process flow 200 shown is designated as process 206. The STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), or CVD. The STI region 26 may also include a dielectric material on top of the liner oxide, which may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to planarize the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes the STI region 26.

[0032] The STI region 26 is then recessed such that the top of the semiconductor strip 24 protrudes above the top surface 26T of the remainder of the STI region 26 to form a protruding fin 28. The protruding fin 28 comprises the top of the multilayer stack 22' and the substrate strip 20'. The recess of the STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon gas may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed by a wet etching process. For example, the etching chemicals may include HF.

[0033] refer to Figure 4 A dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is described in... Figure 28 The process flow 200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on top of the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, polycrystalline silicon or amorphous silicon may be used to form the dummy gate electrode 34, and other materials such as amorphous carbon may also be used.

[0034] Each dummy gate stack 30 may further include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span over one or more protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers by one or more patterning processes.

[0035] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, followed by performing an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layers constitutes the gate spacers 38.

[0036] Figure 5A and5B It shows Figure 4 Cross-sectional view of the structure shown. Figure 5A It shows Figure 4 The reference cross-section A1-A1 is shown, which passes through the portion of the protruding fin 28 not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the gate-length direction. The fin spacer 38 is also shown on the sidewall of the protruding fin 28. Figure 5B It shows Figure 4 The reference cross section BB is parallel to the longitudinal direction of the protruding fin 28.

[0037] refer to Figure 6A and 6B The portion of the protruding fin 28 that is not directly beneath the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is... Figure 28 The process flow 200 shown is referred to as process 210. For example, a dry etching process can be performed using the following to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20': C2F6; CF4; SO2; a mixture of HBr, Cl2, and O2; or a mixture of HBr, Cl2, O2, and CH2F2, etc. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower than the bottom of the multilayer semiconductor stack 22' (e.g., ...). Figure 6B (As shown). Etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0038] refer to Figure 7A and 7B The sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed relative to the edges of the corresponding upper and lower nanostructures 22B. The corresponding process is performed in... Figure 28The process flow 200 shown is illustrated as process 212. Lateral recesses in the sacrificial semiconductor layer 22A can be achieved using a wet etching process with an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon-germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using immersion processes or spraying processes, and can be performed using any suitable process temperature (e.g., between approximately 400°C and approximately 600°C) and suitable process time (e.g., between approximately 100 seconds and approximately 1000 seconds). According to an alternative embodiment, lateral recesses in the sacrificial semiconductor layer 22A can be performed using an isotropic dry etching process or a combination of dry and wet etching processes.

[0039] Figure 8A and 8B The formation of the inner spacer 44 is shown. The corresponding process is as follows: Figure 28 The process flow 200 shown is illustrated as process 214. The forming process includes depositing a spacer layer extending into the recess 41 and performing an etching process to remove the portion of the inner spacer layer outside the recess 41, thereby leaving an inner spacer 44 in the recess 41. The inner spacer 44 may be formed of or comprised of SiOCN, SiON, SiOC, or SiCN, etc. The inner spacers 44 may also be porous, such that they have a low k value below, for example, about 3.5. According to some embodiments, the etching of the spacer layer may be performed by a wet etching process, wherein the etching chemicals may include H2SO4, diluted HF, ammonia solution (NH4OH, ammonia in water), etc., or combinations thereof.

[0040] refer to Figure 9A and 9B An epitaxial source / drain region 48 is formed in the recess 42. The corresponding process is as follows: Figure 28 The process flow 200 is shown as process 216. According to some embodiments, the source / drain region 48 can apply stress to the nanostructure 22B, which serves as the channel for the corresponding GAA transistor, thereby improving performance. According to some embodiments, the corresponding transistor is n-type, and the epitaxial source / drain region 48 is correspondingly topologically n-type by doping with an n-type dopant. For example, silicon-phosphorus (SiP) or silicon-carbon-phosphorus (SiCP) can be grown to form the epitaxial source / drain region 48. After filling the recess 42 with the epitaxial region 48, further epitaxial growth of the epitaxial region 48 causes the epitaxial region 48 to expand horizontally and can form a small facet. Further growth of the epitaxial region 48 may also cause adjacent epitaxial regions 48 to merge with each other.

[0041] Following the epitaxial process, the epitaxial region 48 can be further implanted with n-type impurities to form source and drain regions, which are also indicated by reference numeral 48. According to an alternative embodiment of this disclosure, the implantation process is skipped when the epitaxial region 48 is in-situ doped with n-type impurities during epitaxy, and the epitaxial region 48 is also the source / drain region.

[0042] Figure 10A , 10B Figures 10C and 10C show cross-sectional views of the structure after the formation of the contact etch stop layer (CESL) 50 and the interlayer dielectric (ILD) 52. (The last two lines appear to be incomplete and require further context.) Figure 4 The same cross-sections A2-A2, BB, and A1-A1 are obtained. Figure 10A , 10B And 10C. The corresponding process is in Figure 28 The process flow 200 shown is referred to as process 218. CESL 50 can be formed from silicon oxide, silicon nitride, or silicon carbonitride, and can be formed using CVD, ALD, etc. ILD 52 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0043] In subsequent processes, a replacement gate stack is formed to replace the dummy gate stack 30. (See reference...) Figure 11A and 11B A planarization process, such as CMP or mechanical polishing, is performed to flatten the top surface of the ILD 52. The corresponding process is... Figure 28 The process flow 200 shown is referred to as process 220. According to some embodiments, the planarization process can remove the hard mask 36 to expose the dummy gate electrode 34, such as… Figure 11B As shown. According to an alternative embodiment, the planarization process may expose the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surface of the dummy gate electrode 34 (or hard mask 36), the top surface of the gate spacer 38, and the top surface of the ILD 52 are flush with each other within a process variation.

[0044] Next, the dummy gate electrode 34 (and hard mask 36, if any) is removed in one or more etching processes to form the recess 58, as shown. Figure 12A , 12B As shown in Figure 12C. The corresponding process is... Figure 28 The process flow 200 shown is referred to as process 222. Figure 12C A three-dimensional view of the structure is shown, and Figure 12A and 12B They are shown respectively Figure 12C The cross sections 12A-12A and 12B-12B are shown in the image. The portion of the dummy gate dielectric 32 within the recess 58 is also removed. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by a dry etching process. For example, the etching process can be performed using a reactive gas that selectively etches the dummy gate electrode 34 at a faster rate than etching the ILD 52. Each recess 58 exposes and / or covers a portion of the multilayer stack 22' including the future channel region in the subsequently completed nanoFET. Respective portions of the multilayer stack 22' are located between adjacent pairs of epitaxial source / drain regions 48.

[0045] The sacrificial layer 22A is then removed to extend the recesses 58 between the nanostructures 22B, and the resulting structure is... Figure 13A and 13B The corresponding process is shown in [the diagram]. Figure 28 The process flow 200 shown is referred to as process 224. The sacrificial layer 22A can be removed by performing an isotropic etching process, such as a wet etching process, using an etchant selective for the material of the sacrificial layer 22A. Compared to the sacrificial layer 22A, the nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched. According to some embodiments where the sacrificial layer 22A comprises, for example, SiGe and the nanostructure 22B comprises, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), or ammonium hydroxide (NH4OH), etc., can be used to remove the sacrificial layer 22A. It should be understood that, although... Figure 13A The accompanying figures show the cross-section of nanostructure 22B as rectangular, but nanostructure 22B can have rounded corners, such as... Figure 13A As shown by the dashed line in the image.

[0046] The aforementioned process can be used to form various types of GAA transistors. In the subsequent discussion, two device regions are shown, each used to form a transistor. For example, Figure 14 Two device regions 59-1 and 59-2 are shown, where the illustrated structure is formed using the process discussed in the preceding paragraphs. Each of device regions 59-1 and 59-2 may include any combination of n-type transistor regions or p-type transistor regions. For example, device regions 59-1 and 59-2 may be an n-type transistor region and a p-type transistor region, respectively, or they may be a p-type transistor region and an n-type transistor region, respectively. Alternatively, device regions 59-1 and 59-2 may both be n-type transistor regions, or both device regions 59-1 and 59-2 may both be p-type transistor regions.

[0047] refer to Figure 15 This forms the gate dielectric 62. The corresponding process is as follows: Figure 28 The process flow 200 is shown as process 226. According to some embodiments, each gate dielectric 62 includes an interface layer 62A and a high-k dielectric layer 62B on the interface layer 62A. The interface layer 62A may be formed of or comprise silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. According to an alternative embodiment, the interface layer 62A is formed by thermal oxidation. When the STI region 26 is formed by thermal oxidation, a portion of the interface layer 62A on the top surface of the STI region 26 will not be formed. According to some embodiments, the high-k dielectric layer 62B includes one or more dielectric layers. For example, the high-k dielectric layer(s) 62B may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0048] refer to Figure 16A A protective layer 64 is conformally deposited on the gate dielectric 62. The corresponding process is as follows: Figure 28 The process flow 200 shown is illustrated as process 228. According to some embodiments, the protective layer 64 includes titanium nitride, tantalum nitride, or titanium silicon nitride (TiSiN), etc. The protective layer 64 can be deposited by a conformal deposition process such as CVD or ALD, such that the protective layer 64 includes a portion surrounding each gate dielectric 62.

[0049] The thickness of the protective layer 64 affects the outcome and is therefore controlled within a selected range. If the thickness is too small, the protective layer 64 may not form a complete monolayer completely surrounding the gate dielectric 62 and will fail to protect it. If the thickness is too large, fluorine will have difficulty diffusing through it to the gate dielectric layer 62 within a short annealing time and at a low annealing temperature. Furthermore, by controlling the protective layer 64 to be not too thick and completing the subsequent annealing within a short timeframe, metal elements in the subsequently deposited fluorine-containing layer 66 (which diffuse more slowly than fluorine) will advantageously not diffuse significantly through the protective layer 64 and into the gate dielectric 62.

[0050] Further reference Figure 16A A fluorine-containing layer 66 is formed on the gate dielectric 62. The corresponding process is as follows: Figure 28The process flow 200 shown is designated as process 230. According to some embodiments, the formation process includes a deposition process, including CVD or ALD, etc. The precursor used in the deposition process may include a fluorinated precursor and a reducing agent. The fluorinated precursor may include WF6, and the reducing agent may include SiH4, B2H6, H2, etc., or combinations thereof. A protective layer 64 may protect the gate dielectric 62 during the deposition process and may prevent the precursor (e.g., the fluorinated precursor) from etching the gate dielectric 62. The fluorinated layer 66 may be deposited at a temperature ranging from about 250°C to about 475°C. The pressure of the corresponding chamber may range from about 0.5 Torr to about 400 Torr. According to some embodiments, when the deposition of the fluorinated layer 66 is completed, the atomic percentage of fluorine in the deposited fluorinated layer 66 may range from about 3.5% to about 40%. It should be understood that although the fluorinated layer 66 may be a continuous layer completely surrounding the corresponding protective layer 64, according to alternative embodiments, the fluorinated layer 66 may be formed as a discontinuous layer.

[0051] According to alternative embodiments, such as Figure 16B As shown, instead of forming a fluorine-containing layer on the protective layer 64, fluorine is doped into the protective layer 64 through an immersion process. In the immersion process, the exposed protective layer 64 is immersed in a fluorine-containing gas. As a result of the immersion process, the surface (or entirety) of the protective layer 64 has a high percentage of fluorine atoms, thus forming a fluorine-containing layer 66. The corresponding process is described in... Figure 28 The process flow 200 shown is again referred to as process 230. The corresponding fluorinated gas may include WF6, NF3, CF4, CaF2, CrF6, MoF6, or combinations thereof. Some molecules of the fluorinated gas may remain intact as they diffuse to the surface portion of the protective layer 64, while some other molecules of the fluorinated precursor may at least partially dissociate, in which case the fluorine diffuses deeper into the protective layer 64, while metallic elements such as tungsten may remain on the surface of the protective layer 64.

[0052] The immersion process can be carried out at a temperature ranging from about 250°C to about 475°C and a pressure ranging from about 0.5 Torr to about 50 Torr, for a duration ranging from about 0.1 seconds to about 1 hour. According to some embodiments, at the completion of the immersion process, the percentage of fluorine atoms in the fluorine-containing layer 66 can be ranging from about 1.5% to about 55%.

[0053] Figure 25 The distribution of fluorine in wafer 10 immediately following the formation of fluorine-containing layer 66 is schematically shown. Fluorine has the highest atomic percentage in fluorine-containing layer 66, which is either a deposited layer or a surface layer of the original protective layer 64. The atomic percentage of fluorine decreases towards nanostructure 22B.

[0054] Figure 17The formation of an etching mask 68 is illustrated. The etching mask 68 is used to remove portions of the fluorine-containing layer 66 and the protective layer 64 in device region 59-2. The etching mask 68 may include a photoresist and may be a single-layer mask, a three-layer mask, or a four-layer mask, etc. The etching mask 68 is patterned and removed from device region 59-2, while a portion remains in device region 59-1. Then, the portions of the fluorine-containing layer 66 and the protective layer 64 in device region 59-2 are removed by an etching process. The corresponding process is described in... Figure 28 The process flow 200 shown is illustrated as process 232. The etching process may include a wet etching process. For example, the etching solution may include HCl, H2O2, NH4OH, H2O, etc., or combinations thereof. According to some embodiments, the etching solution includes HCl, H2O2, and H2O. According to an alternative embodiment, the etching solution includes H2O2 and H2O. According to yet another alternative embodiment, the etching solution includes NH4OH and H2O2. The etching time may be in the range of about 15 seconds to about 600 seconds. After the etching process, the etching mask 68 is removed, resulting in the structure shown below. Figure 18 As shown.

[0055] According to an alternative embodiment, after etching the fluorine-containing layer 66 in device region 59-2, a portion of the protective layer 64 in device region 59-2 is exposed, but this portion is not removed at this stage. Instead, it is removed after a subsequent annealing process.

[0056] Figure 19A and 19B arrive Figure 24A and 24B Subsequent figure numbers in the figure may be followed by the letter A or B, and corresponding numbers. The letter A indicates that the corresponding figure shows a cross-section and... Figure 4 The cross-sections A2-A2 in the diagram are the same, and the letter B indicates that the corresponding reference cross-section shown in the diagram is the same as... Figure 4 The reference cross section BB is the same.

[0057] exist Figure 19A and 19B In this process, annealing process 72 is performed to diffuse fluorine from the fluorine-containing layer 66 into the protective layer 64 and the gate dielectric 62. The corresponding process is as follows: Figure 28The process flow 200 is shown as process 234. Some fluorine can fill the vacancies or micropores in the gate dielectric 62, and some fluorine can adhere to the dangling silicon bonds at the interface between the interface layer 62A and the nanostructure 22B. This improves the reliability of the resulting device. Time-dependent dielectric breakdown (TDDB) of the gate dielectric 62 can be advantageously reduced. The annealing process 72 can be performed at a temperature ranging from about 150°C to about 750°C. The annealing duration can range from about 0.5 seconds to about 60 seconds.

[0058] As a result of the annealing process, the gate dielectric 62 in device region 59-1 has an increased percentage of fluorine atoms, FAP1, which is also higher than the percentage of fluorine atoms, FAP2, in the gate dielectric 62 in device region 59-2. According to some embodiments, the percentage of fluorine atoms, FAP1, is in the range of about 0.5% to about 20%. Furthermore, the difference between (FAP1 and FAP2) can be greater than about 0.5 atomic percentages and can be in the range of about 0.5% to about 20%.

[0059] After the annealing process, the remaining portions of the protective layer 64 and the fluorine-containing layer 66 are removed from device region 59-1 by etching process 73, resulting in the structure shown below. Figure 20A and 20B As shown. The corresponding process is in Figure 28 The process flow 200 shown is designated as process 236. The etching process can also be performed using either a wet etching process or a dry etching process. The etching chemicals can be selected from those suitable for use in [specific applications]. Figure 17 Candidate chemicals for the process shown. For example, the etching process may include a wet etching process and may use HCl, H2O2, NH4OH, H2O, etc., or combinations thereof.

[0060] According to an alternative embodiment, where the portion of the protective layer 64 in device region 59-2 was not removed in the previous process, the portion of the protective layer 64 in device region 59-2 can be removed simultaneously when the portions of the fluorine-containing layer 66 and the protective layer 64 in device region 59-1 are removed.

[0061] In the above embodiment, the fluorine-containing layer 66 is formed on the protective layer 64 and separated from the high-k dielectric layer 62B by the protective layer 64. According to an alternative embodiment, the formation of the protective layer 64 is skipped, and the fluorine-containing layer 66 is deposited directly on the high-k dielectric layer 62B. When the fluorine-containing layer 66 is formed by deposition, as described above, a precursor such as WF6 may etch a portion of the surface of the high-k dielectric layer 62B before the newly deposited fluorine-containing layer 66 serves as a protective layer to prevent further etching of the high-k dielectric layer 62B.

[0062] Before the newly deposited fluorine-containing layer 66 is thick enough to protect the high-k dielectric layer 62B, the thickness of the high-k dielectric layer 62B may have been reduced by up to [amount missing]. The value of . On the other hand, if the fluorine-containing layer 66 is formed using an immersion process, the percentage of fluorine atoms in the surface (or overall) of the high-k dielectric layer 62B increases, thus transforming it into a fluorine-containing layer 66. According to these embodiments, after the annealing process 72, the fluorine-containing layer 66 can be removed or left to remain, as it is part of the original high-k dielectric layer 62B.

[0063] According to yet another alternative embodiment, in such Figure 20A and 20B In the etching process shown, the fluorine-containing layer 66 is etched (rather than etching both the fluorine-containing layer 66 and the protective layer 64), while the protective layer 64 is retained as part of the final structure. For example, when device region 59-1 is a p-type transistor region, the protective layer 64 can be used as the lower part or the entirety of the work function layer of the resulting GAA transistor 92-1. Figure 24A and 24B Alternatively, when device region 59-1 is an n-type transistor region, protective layer 64 can be used as a capping layer located below the n-type work function layer of the resulting GAA transistor 92-1. Figure 24A and 24B Therefore, the thickness of the protective layer 64 can be adjusted in the preceding processes to the desired thickness suitable for its function.

[0064] refer to Figure 21A and 21B This forms a stacked conductive layer 76 and a filler metal 78. The corresponding process is as follows: Figure 28 The process flow 200 shown is illustrated as process 238. According to some embodiments, the conductive layer 76 and fill metal 78 in device regions 59-1 and 59-2 are formed in a common process and using a common material. According to alternative embodiments, the conductive layer 76 and fill metal 78 are formed by separate processes and can be formed from the same or different materials. For example, when the transistors formed in device regions 59-1 and 59-2 have opposite conductivity types, the work function layers in device regions 59-1 and 59-2 are formed from different materials and in separate processes. According to alternative embodiments, the transistors formed in device regions 59-1 and 59-2 have the same conductivity type (both p-type or both n-type) but different performance requirements, such as different threshold voltages. Therefore, the stacked conductive layer 76 in device regions 59-1 and 59-2 can also be formed by different processes and / or different materials.

[0065] The conductive layer 76 may include a work function layer and may or may not include other layers, such as a capping layer or a barrier layer. For example, when one or both of device regions 59-1 and 59-2 are p-type transistor regions, the corresponding work function layer may include TiN, TaN, TiSiN, WCN, MOCN, or combinations thereof. When one or both of device regions 59-1 and 59-2 are n-type transistor regions, the corresponding work function layer may include TiAlC, TiAlN, TaAlC, TaAlN, or combinations thereof. The stacked conductive layer 76 may or may not include a capping layer, such as a TiN layer or a TiSiN layer, formed between the work function layer and the gate dielectric 62. The stacked conductive layer 76 may or may not include a barrier layer, such as a TiN layer, above the work function layer. If the remaining recesses 58 are not completely filled, a filler metal 78 may be formed to fill them. The filler metal 78 may include a metallic material, such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof.

[0066] refer to Figure 22A and 22B After filling the recess 58, a planarization process, such as CMP or mechanical polishing, is performed to remove excess material from the gate dielectric and gate electrode 80 that protrudes above the top surface of the ILD 52. The remaining portion of the conductive layer 76 and the remaining portion of the fill metal 78 form the gate electrode 80. The gate electrode 80 and the gate dielectric 62 are collectively referred to as the gate stack 82.

[0067] Next, as Figure 23A and 23B As shown, the gate stack 82 is recessed, thereby forming a recess directly on the gate stack 82 and between the opposing portions of the gate spacer 38. Each recess is filled with a gate mask 84 comprising one or more layers of dielectric material (such as silicon nitride or silicon oxynitride), and then a planarization process is performed to remove excess dielectric material extending over the ILD 52. The corresponding process is as follows: Figure 28 The process flow 200 shown is referred to as process 240.

[0068] like Figure 23A and 23B As further shown, ILD 86 is deposited on top of ILD 52 and gate mask 84. The corresponding process is as follows: Figure 28 The process flow 200 shown is designated as process 242. An etch stop layer (not shown) may be deposited before the formation of ILD 86 or may not be deposited. According to some embodiments, ILD 86 is formed by FCVD, CVD, or PECVD, etc. ILD 86 is formed of a dielectric material, which may be selected from silicon oxide, PSG, BSG, BPSG, USG, etc.

[0069] exist Figure 24A and 24B In this process, ILD 86, ILD 52, CESL 50, and gate mask 84 are etched to form recesses (occupied by contact plugs 88A and 88B) that expose the surfaces of the epitaxial source / drain regions 48 and / or gate stack 82. The recesses can be formed by etching using anisotropic etching processes such as RIE, NBE, etc. According to some embodiments, the recesses can be formed by etching through ILD 86 and ILD 52 using a first etching process, etching through gate mask 84 using a second etching process, and possibly etching through CESL 50 using a third etching process.

[0070] After the recess is formed, a silicide region 90 is formed on top of the epitaxial source / drain region 48. Figure 24B The corresponding processes are in Figure 28 The process flow 200 shown is referred to as process 244. According to some embodiments, the silicide region 90 is formed by first depositing a metal layer (not shown) capable of reacting with the underlying epitaxial source / drain region 48 (e.g., silicon, silicon-germanium, germanium) to form a silicide and / or germanide region, and then performing a thermal annealing process to form the silicide region 90. The metal may include nickel, cobalt, titanium, tantalum, platinum, or tungsten, etc. Unreacted portions of the deposited metal are then removed, for example, by an etching process.

[0071] Then, a contact plug 88B is formed over the silicide region 90. Furthermore, a contact plug 88A (also referred to as a gate contact plug) is also formed in the recess, and it is over and contacts the gate electrode 80. The corresponding process is as follows: Figure 28 The process flow 200 shown is referred to as process 246. Although Figure 24B The diagram shows contact plugs 88A and 88B in the same cross-section, but in various embodiments, contact plugs 88A and 88B may be formed in different cross-sections, thereby reducing the risk of short-circuiting each other.

[0072] Contact plugs 88A and 88B may each comprise one or more layers, such as a barrier layer, a diffusion barrier layer, and a filler material, and are electrically coupled to an underlying conductive feature (e.g., gate stack 82 or silicide region 90 in the illustrated embodiment). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the ILD 86. GAA transistors 92-1 and 92-2 are thus formed in device regions 59-1 and 59-2, respectively.

[0073] Figure 24C It shows Figure 24Aand 24B A three-dimensional diagram of the structure shown, in which Figure 24A and 24B The cross-sectional views shown are obtained from cross-sections 24A-24A and 24B-24B in Figure 24, respectively. Figure 24D and 24E It shows Figure 24A , 24B The horizontal cross-sectional views of the structures shown in Figure 24C are respectively from... Figure 24B The horizontal planes 24D-24D and 24E-24E in the middle are obtained.

[0074] Figure 26 The percentage of fluorine atoms in the gate stack 82 according to some embodiments is shown, where the X-axis represents Figure 24B The distance in the direction of the middle arrow 94 (in device region 59-1). Due to the removal of... Figure 25 The protective layer 64 and the fluorine-containing layer 66 in the formation of such Figure 26 Before the conductive layer 76 and the fill metal 78 shown, the peak fluorine atom percentage will be at the outer surface of the gate dielectric 62, as... Figure 25 Position 95 is shown in the diagram. During the subsequent annealing process and due to other thermal budgets, fluorine will diffuse outwards. However, the peak fluorine atomic percentage can be maintained at or near the interface between the gate dielectric 62 and the conductive layer 76.

[0075] Figure 27 The percentage of fluorine atoms in the gate stack 82 according to an alternative embodiment is shown. In these embodiments, the protective layer 64 is not removed. Therefore, the peak percentage of fluorine atoms can be inside the protective layer 64, which can be part of the work function layer or as a capping layer below the work function layer.

[0076] The following figures illustrate some alternative embodiments. Figure 29 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes a fin 352 on a substrate 350 (e.g., a semiconductor substrate). Isolation regions 356 are disposed in the substrate 350, and the fin 352 extends over and from adjacent isolation regions 356. Although the isolation regions 356 are described / shown as separate from the substrate 350, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Furthermore, although the fin 352 is shown as a single continuous material like the substrate 350, the fin 352 and / or the substrate 350 may comprise a single material or multiple materials. In this context, the fin 352 refers to the portion extending between adjacent isolation regions 356.

[0077] A gate dielectric layer 392 runs along the sidewall of fin 352 and is above its top surface, and a gate electrode 394 is above the gate dielectric layer 392. Source / drain regions 382 are disposed on opposite sides of fin 352 with respect to the gate dielectric layer 392 and the gate electrode 394. Figure 29 The reference cross sections used in the following figures are further illustrated. Cross section CC is along the longitudinal axis of the gate electrode 394 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 382 of the FinFET. Cross section DD is perpendicular to cross section CC and along the longitudinal axis of the fin 352 and in a direction, for example, the current flow direction between the source / drain regions 382 of the FinFET. Cross section EE is parallel to cross section CC and extends through the source / drain regions of the FinFET. These reference cross sections are referenced in the subsequent figures for clarity.

[0078] Some embodiments discussed herein are presented in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments consider aspects for use in planar devices, such as planar FETs, gate-all-around field-effect transistors (GAAFETs), etc.

[0079] exist Figure 30 The substrate 350 is provided. The substrate 350 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 350 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 350 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0080] The substrate 350 has an n-type region 350N and a p-type region 350P. The n-type region 350N can be used to form an n-type device, such as an NMOS transistor, or an n-type FinFET. The p-type region 350P can be used to form a p-type device, such as a PMOS transistor, or a p-type FinFET. The n-type region 350N can be physically separated from the p-type region 350P (as shown by separator 351), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between the n-type region 350N and the p-type region 350P.

[0081] exist Figure 31 In this embodiment, fins 352 are formed in substrate 350. Fins 352 are semiconductor strips. In some embodiments, fins 352 can be formed in substrate 350 by etching trenches in substrate 350. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0082] The fin can be patterned using any suitable method. For example, the fin 352 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fin can then be patterned using the remaining spacers. In some embodiments, a mask (or other layer) may be retained on the fin 352.

[0083] exist Figure 32 In this embodiment, an insulating material 354 is formed on the substrate 350 and between adjacent fins 352. The insulating material 354 can be an oxide, such as silicon oxide, nitrides, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing CVD-based materials in a remote plasma system and post-curing them to transform them into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 354 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material 354 is formed such that excess insulating material 354 covers the fins 352. Although the insulating material 354 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 350 and the fins 352. Subsequently, filler materials such as those described above may be formed on the liner.

[0084] exist Figure 33In this process, a removal process is applied to the insulating material 354 to remove excess insulating material 354 from the fin 352. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, or combinations thereof, can be used. The planarization process exposes the fin 352 such that the top surface of the fin 352 is flush with the top surface of the insulating material 354 after the planarization process is completed. In embodiments where the mask remains on the fin 352, the planarization process may expose or remove the mask such that the mask or the fin 352 is flush with the top surface of the insulating material 354 after the planarization process is completed.

[0085] exist Figure 34 In this process, insulating material 354 is recessed to form shallow trench isolation (STI) regions 356. The recessing of insulating material 354 causes fins 352 to protrude from between adjacent STI regions 356 at their upper portions in the n-type region 350N and p-type region 350P. Furthermore, the top surface of the STI region 356 can have a flat surface, a convex surface, a concave surface (e.g., pits), or a combination thereof, as shown. The top surface of the STI region 356 can be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess the STI region 356, such as selective etching processes for the material of insulating material 354 (e.g., etching the material of insulating material 354 at a faster rate than etching the material of fins 352). For example, it can be removed using an oxide, such as dilute hydrofluoric acid (dHF).

[0086] about Figures 30 to 34 The described process is merely one example of how fin 352 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of substrate 350, and trenches can be etched through the dielectric layer to expose the underlying substrate 350. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes relative to the dielectric layer to form the fin. Furthermore, in some embodiments, heteroethelic structures can be used for fin 352. For example, Figure 33 The fin 352 may be recessed, and a material different from the fin 352 may be epitaxially grown on the recessed fin 352. In such an embodiment, the fin 352 includes a recessed material and an epitaxially grown material disposed on the recessed material.

[0087] In a further embodiment, a dielectric layer can be formed above the top surface of the substrate 350, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from that of the substrate 350, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes relative to the dielectric layer to form fins 352. In some embodiments of homoepitaxial or heteroepitaxial structure epitaxial growth, the material for epitaxial growth can be in-situ doped during growth, which avoids prior and subsequent implantation, but in-situ and implantation doping can be used together.

[0088] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 350N (e.g., NMOS region) than in the p-type region 350P (e.g., PMOS region). In various embodiments, the upper portion of the fin 352 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0089] Further in Figure 34 In this process, suitable wells (not shown) may be formed in fin 352 and / or substrate 350. In some embodiments, a P-well may be formed in n-type region 350N and an N-well may be formed in p-type region 350P. In some embodiments, a P-well or an N-well is formed in both n-type region 350N and p-type region 350P.

[0090] In embodiments with different well types, different implantation steps for the n-type region 350N and the p-type region 350P can be implemented using photoresist and / or other masks (not shown). For example, photoresist can be formed over the fins 352 and STI regions 356 in the n-type region 350N. The photoresist is patterned to expose the p-type region 350P of the substrate 350. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 350P, and the photoresist can be used as a mask to substantially prevent n-type impurity implantation into the n-type region 350N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 Peace Treaty 10 18 cm -3Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0091] Following implantation in the p-type region 350P, a photoresist is formed over the fins 352 and STI region 356 within the p-type region 350P. The photoresist is patterned to expose the n-type region 350N of the substrate 350. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 350N, and the photoresist can be used as a mask to substantially prevent p-type impurity implantation into the p-type region 350P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in this region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 Peace Treaty 10 18 cm -3 Between. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0092] After implantation in the n-type region 350N and the p-type region 350P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ and implantation doping can be used together.

[0093] exist Figure 35 In this configuration, a dummy dielectric layer 360 is formed on fin 352. The dummy dielectric layer 360 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 362 is formed on the dummy dielectric layer 360, and a mask layer 364 is formed on the dummy gate layer 362. The dummy gate layer 362 can be deposited on the dummy dielectric layer 360 and then planarized, for example, by CMP. The mask layer 364 can be deposited on the dummy gate layer 362. The dummy gate layer 362 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals.

[0094] The dummy gate layer 362 can be deposited using physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 362 can be made of other materials with high etch selectivity for etching isolation regions (e.g., STI region 356 and / or dummy dielectric layer 360). The mask layer 364 can comprise one or more layers, such as silicon nitride or silicon oxynitride. In this example, a single dummy gate layer 362 and a single mask layer 364 are formed across the n-type region 350N and the p-type region 350P.

[0095] Note that, for illustrative purposes only, the dummy dielectric layer 360 is shown to cover only the fin 352. In some embodiments, the dummy dielectric layer 360 may be deposited such that the dummy dielectric layer 360 covers the STI region 356 and extends over the STI region and between the dummy gate layer 362 and the STI region 356.

[0096] Figures 36A to 48 Figures 50A to 52B illustrate various additional steps in manufacturing the devices of the embodiments. Figures 36A to 48 Figures 50A to 52B illustrate features in either the n-type region 350N or the p-type region 350P. For example, Figures 36A to 48 The structures shown in 50A to 52B are applicable to both n-type region 350N and p-type region 350P. The differences (if any) between the structures of n-type region 350N and p-type region 350P are described in the accompanying text for each figure.

[0097] exist Figure 36A and 36B In this process, acceptable photolithography and etching techniques can be used to process mask layer 364 (see...). Figure 35 The mask 374 is patterned to form a mask 374. The pattern of the mask 374 can then be transferred to the dummy gate layer 362. In some embodiments (not shown), the pattern of the mask 374 can also be transferred to the dummy dielectric layer 360 using an acceptable etching technique to form the dummy gate 372. The dummy gate 372 covers the corresponding channel region 358 of the fin 352. The pattern of the mask 374 can be used to separate each of the dummy gates 372 from the adjacent dummy gate entity. The dummy gate 372 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the respective epitaxial fin 352.

[0098] Further in Figure 36A and 36B In this process, a gate sealing spacer 380 can be formed on the exposed surfaces of the dummy gate 372, mask 374, and / or fin 352. The gate sealing spacer 380 can be formed by thermal oxidation or deposition following anisotropic etching. The gate sealing spacer 380 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0099] After the gate sealing spacer 380 is formed, implantation for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different device types, similar to the above... Figure 34 The implantation discussed herein involves forming a mask, such as a photoresist, over the n-type region 350N, while simultaneously exposing the p-type region 350P. An appropriate type of impurity (e.g., p-type) can then be implanted into the exposed fins 352 within the p-type region 350P. The mask can then be removed.

[0100] Subsequently, a mask, such as a photoresist, can be formed on top of the p-type region 350P while exposing the n-type region 350N, and an appropriate type of impurity (e.g., n-type) can be implanted into the exposed fins 352 in the n-type region 350N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed above, and the p-type impurity can be any p-type impurity discussed above. The lightly doped source / drain regions can have a doping density of approximately 10. 15 cm -3 To about 10 19 cm -3 The concentration of impurities. Annealing can be used to repair implantation damage and reactivate the implanted impurities.

[0101] exist Figure 37A and 37B In this configuration, a gate spacer 386 is formed on the gate sealing spacer 380 along the sidewalls of the dummy gate 372 and the mask 374. The gate spacer 386 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 386 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0102] Note that the above disclosure broadly describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and steps in a different sequence can be used (e.g., the gate seal spacer 380 may not be etched before forming the gate spacer 386 to create an "L-shaped" gate seal spacer; spacers can be formed and removed, etc.). Furthermore, n-type and p-type devices can be formed using different structures and steps. For example, the LDD region of an n-type device can be formed before forming the gate seal spacer 380, while the LDD region of a p-type device can be formed after forming the gate seal spacer 380.

[0103] exist Figure 38A and 38BIn this configuration, epitaxial source / drain regions 382 are formed within fins 352. The epitaxial source / drain regions 382 are formed within fins 352 such that each dummy gate 372 is disposed between adjacent pairs of corresponding epitaxial source / drain regions 382. In some embodiments, the epitaxial source / drain regions 382 may extend into or penetrate the fins 352. In some embodiments, gate spacers 386 are used to separate the epitaxial source / drain regions 382 from the dummy gates 372 by an appropriate lateral distance, such that the epitaxial source / drain regions 382 do not short-circuit the gate of the subsequently formed FinFET. The material of the epitaxial source / drain regions 382 can be selected to apply stress in the respective channel regions 358, thereby improving performance.

[0104] The epitaxial source / drain region 382 in the n-type region 350N can be formed by masking the p-type region 350P and etching the source / drain region of the fin 352 in the n-type region 350N to form a recess in the fin 352. The epitaxial source / drain region 382 in the n-type region 350N is then epitaxially grown in the recess. The epitaxial source / drain region 382 can include any acceptable material, such as materials suitable for n-type FinFETs. For example, if the fin 352 is silicon, the epitaxial source / drain region 382 in the n-type region 350N can include a material to which tensile strain is applied in the channel region 358, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 382 in the n-type region 350N can have a surface protruding from the corresponding surface of the fin 352 and can have a small facet.

[0105] The epitaxial source / drain region 382 in the p-type region 350P can be formed by masking the n-type region 350N and etching the source / drain region of the fin 352 in the p-type region 350P to form a recess in the fin 352. The epitaxial source / drain region 382 in the p-type region 350P is then epitaxially grown in the recess. The epitaxial source / drain region 382 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 352 is silicon, the epitaxial source / drain region 382 in the p-type region 350P can include a material to which compressive strain is applied in the channel region 358, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 382 in the p-type region 350P can have a surface protruding from the corresponding surface of the fin 352 and can have a small facet.

[0106] Epitaxial source / drain regions 382 and / or fins 352 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 To about 10 21 cm -3Between. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 382 can be doped in situ during growth.

[0107] As a result of the epitaxial process used to form the epitaxial source / drain regions 382 in the n-type region 350N and the p-type region 350P, the upper surface of the epitaxial source / drain regions has small facets that extend laterally outward beyond the sidewalls of the fins 352. In some embodiments, these small facets cause adjacent source / drain regions 382 of the same FinFET to merge, such as... Figure 38C As shown. In other embodiments, adjacent source / drain regions 382 remain separated after the epitaxial process is completed, as... Figure 38D As shown. In Figure 38C and 38D In the illustrated embodiment, the gate spacer 386 is formed to cover a portion of the sidewall of the fin 352 that extends above the STI region 356, thereby preventing epitaxial growth. In some other embodiments, the spacer etching used to form the gate spacer 386 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 356.

[0108] exist Figure 39A and 39B In the middle, the first interlayer dielectric (ILD) 388 is deposited in Figure 38A and 38B The structure shown is above the first ILD 388. The first ILD 388 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 387 is disposed between the first ILD 388 and the epitaxial source / drain region 382, ​​mask 374, and gate spacer 386. The CESL 387 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., with an etch rate lower than that of the material of the first ILD 388 above.

[0109] exist Figure 40A and 40BIn this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 388 flush with the top surface of the dummy gate 372 or the top surface of the mask 374. The planarization process may also remove the mask 374 on the dummy gate 372, as well as portions of the gate sealing spacers 380 and 386 along the sidewalls of the mask 374. After the planarization process, the top surfaces of the dummy gate 372, the gate sealing spacers 380, the gate spacers 386, and the first ILD 388 are flush. Therefore, the top surface of the dummy gate 372 is exposed through the first ILD 388. In some embodiments, the mask 374 may be retained, in which case the planarization process makes the top surface of the first ILD 388 flush with the top surface of the mask 374.

[0110] exist Figure 41A and 41B In this process, the dummy gate 372 and mask 374 (if present) are removed in one or more etching steps to form the recess 390. A portion of the dummy dielectric layer 360 within the recess 390 may also be removed. In some embodiments, only the dummy gate 372 is removed, and the dummy dielectric layer 360 remains and is exposed by the recess 390. In some embodiments, the dummy dielectric layer 360 is removed from the recess 390 in a first region of the die (e.g., a core logic region) and remains in the recess 390 in a second region of the die (e.g., an input / output region).

[0111] In some embodiments, the dummy gate 372 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 372 while little or no etching of the first ILD 388 or gate spacer 386. Each recess 390 exposes and / or covers the channel region 358 of the corresponding fin 352. Each channel region 358 is disposed between adjacent pairs of epitaxial source / drain regions 382. During removal, the dummy dielectric layer 360 may be used as an etch stop layer as the dummy gate 372 is etched. The dummy dielectric layer 360 may then be optionally removed after the removal of the dummy gate 372.

[0112] exist Figure 42A and 42B In this recess 390, a gate dielectric layer 392 and a gate electrode layer 394 are formed to replace the gate. The gate dielectric layer 392 is formed in the recess 390, and the gate electrode layer 394 is formed on the gate dielectric layer 392. Figure 42C It shows Figure 42B A detailed view of region 389, showing additional details of the gate dielectric layer 392 and the gate electrode layer 394.

[0113] The gate dielectric layer 392 includes one or more layers deposited in the recess 390, such as on the top surface and sidewalls of the fin 352 and on the sidewalls of the gate sealing spacer 380 / gate spacer 386. In some embodiments, the gate dielectric layer 392 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, as Figure 42C As shown, in some embodiments, the gate dielectric layer 92 includes an interface layer 392A of silicon oxide formed by thermal oxidation or chemical oxidation and a high-k dielectric layer 392B of a high-k dielectric material (e.g., metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof). In some embodiments, the high-k dielectric layer 392B includes hafnium oxide. The gate dielectric layer 392 may include a dielectric layer with a k value greater than about 7.0.

[0114] Gate electrode layer 394 is deposited over gate dielectric layer 392 and fills the remainder of recess 390. Gate electrode 394 may include a metallic material, such as titanium nitride, titanium oxide, titanium aluminum, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although Figure 42B The diagram shows a single-layer gate electrode layer 394, but the gate electrode layer 394 may include any number of liner layers 394A, any number of work function adjustment layers 394B, and filler material 394C, such as... Figure 42C As shown.

[0115] The formation of the gate dielectric layer 392 in the n-type region 350N and the p-type region 350P can occur simultaneously, such that the gate dielectric layer 392 in each region is formed of the same material, and the formation of the gate electrode layer 394 can occur simultaneously, such that the gate electrode layer 394 in each region is formed of the same material.

[0116] In some embodiments, the gate dielectric layer 392 in each region can be formed using different processes, such that the gate dielectric layer 392 can be made of different materials, and / or the gate electrode layer 394 in each region can be formed using different processes, such that the gate electrode layer 394 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions. In the following description, at least some portions of the gate dielectric layer 392 in the n-type region 350N and the gate dielectric layer 392 in the p-type region 350P are formed separately.

[0117] Figures 43 to 48 The process for forming the replacement gate layer is shown. As will be described in more detail later, a gate dielectric layer 392 and a gate electrode layer 394 are formed in the recess 390. Fluorine treatment 610 (see...) Figure 44A fluorine dopant is applied to the gate dielectric layer 392, causing fluorine to diffuse into the gate dielectric layer 392. The dipole dopant material also diffuses into the gate dielectric layer 392 (see [link]). Figures 45-47 By controlling the concentration of the dipole dopant material in the gate dielectric layer 392, the threshold voltage of the subsequently formed transistor can be adjusted without negatively impacting the corresponding spacing of the transistor's gate. These aspects can be further implemented in various combinations, with or without an additional work function adjustment layer in the gate (see below). Figure 48 This is used to adjust the threshold voltage.

[0118] Dipole dopant material introduced into the gate dielectric layer 392 (see below), Figures 45-47 This can lead to charge accumulation within the gate dielectric layer 392, which may cause leakage paths and reliability issues in the transistor. Diffused fluorine in the gate dielectric layer 392 can combine with the diffused dipole dopant in the gate dielectric layer 392 and reduce charge accumulation within the gate dielectric layer 392, which further reduces leakage paths and reliability issues.

[0119] exist Figure 43 In the recess 390, a gate dielectric layer 392 (including an interface layer 392A and a high-k dielectric layer 392B) is deposited. The gate dielectric layer 392 may also be deposited on the top surface of the first ILD 388 (see [reference]). Figure 42B Methods for forming the gate dielectric layer 392 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where some portions of the dummy gate dielectric 361 remain in the recess 390, the gate dielectric layer 392 comprises the material of the dummy gate dielectric 361 (e.g., silicon oxide).

[0120] exist Figure 44 In this process, a fluorine treatment 610 is applied to the high-k dielectric layer 392B. In some embodiments, the fluorine treatment 610 is a chemical immersion in which a fluorine-containing precursor flows over the surface of the high-k dielectric layer 392B. In some embodiments, the fluorine-containing precursor may be WF. x NF x TiF x TaF x HfF x And so on, where x is an integer in the range of 1 to 6. For example, in some embodiments, the fluorinated precursor is WF6 and / or NF3. When the fluorinated precursor reaches the high-k dielectric layer 392B, fluorine atoms 612 dissociate from the fluorinated precursor and diffuse through the high-k dielectric layer 392B to the interface between the high-k dielectric layer 392B and the interface layer 392A. Some fluorine atoms 612 further diffuse through the interface layer 392A to the interface between the interface layer 392A and the channel region 358.

[0121] Fluorine atoms 612 can bond with atoms in the high-k dielectric layer 392B, the interface layer 392A, and the channel region 358, for example, at the interface between the high-k dielectric layer 392B and the interface layer 392A, and at the interface between the interface layer 392A and the channel region 358. For example, in some embodiments where the high-k dielectric layer 392B comprises hafnium dioxide, the interface layer 392A comprises silicon oxide or silicon dioxide, and the channel region comprises silicon, fluorine atoms 612 form strong hafnium fluoride (Hf-F) and silicon fluoride (Si-F) bonds at the respective interfaces of the high-k dielectric layer 392B, the interface layer 392A, and the channel region 358. The dopants subsequently introduced into the gate dielectric layer 392 (see below) Figures 45-47 This can lead to charge accumulation in the gate dielectric layer 392. As will be described in more detail later, diffused fluorine atoms 612 help reduce this charge accumulation and improve transistor performance.

[0122] In some embodiments, the fluorine treatment 610 is performed at a temperature in the range of 250°C to 550°C (e.g., by immersing the gate dielectric layer 392 in a fluorine-containing precursor at such a temperature), which can facilitate sufficient fluorine diffusion into the gate dielectric layer 392 to reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. It has been observed that when the temperature of the fluorine treatment 610 is below 250°C, the fluorine-containing precursor does not properly dissociate and affect the desired changes in the high-k dielectric layer 392B and / or the layers beneath it. It has been observed that when the temperature of the fluorine treatment 610 is above 550°C, the amount of fluorine dissociated from the fluorine-containing precursor may be too large to be precisely controlled.

[0123] In some embodiments, the fluorine treatment 610 is performed at a pressure ranging from 0.5 Torr to 40 Torr (e.g., by immersing the gate dielectric layer 392 in a fluorine-containing precursor at such pressure), which can facilitate sufficient fluorine diffusion into the gate dielectric layer 392 to reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. It has been observed that when the pressure of the fluorine treatment 610 is less than 0.5 Torr, the fluorine-containing precursor does not properly dissociate and affect the desired changes in the high-k dielectric layer 392B and / or its underlying layers. It has been observed that when the pressure of the fluorine treatment 610 is greater than 40 Torr, the amount of fluorine dissociated from the fluorine-containing precursor may be too large to be precisely controlled.

[0124] In some embodiments, the fluorine treatment 610 is performed at a flow rate of 100 standard cubic centimeters per minute (sccm) to 6000 sccm (e.g., by allowing the fluorine-containing precursor to flow over the gate dielectric layer 392 at such a flow rate). This may facilitate sufficient fluorine diffusion into the gate dielectric layer 392 to reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. It has been observed that when the fluorine treatment 610 is performed at a flow rate less than 100 sccm, the process may be insufficient to adjust the threshold voltage of the resulting transistor. It has been observed that when the fluorine treatment 610 is performed at a flow rate greater than 6000 sccm, excess fluorine may be introduced into the device, negatively impacting the threshold voltage of the resulting transistor.

[0125] In some embodiments, the fluorine treatment 610 is performed for a duration ranging from 0.5 seconds to 60 minutes (e.g., by immersing the gate dielectric layer 392 in a fluorine-containing precursor for such a duration), which can facilitate sufficient fluorine diffusion into the gate dielectric layer 392 to reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. It has been observed that when the fluorine treatment 610 is performed for less than 0.5 seconds, the process may be insufficient to adjust the threshold voltage of the resulting transistor. It has been observed that when the fluorine treatment 610 is performed for more than 60 minutes, excessive fluorine may be introduced into the device, negatively impacting the threshold voltage of the resulting transistor.

[0126] In some embodiments, the concentration of fluorine atoms 612 at the interface between the high-k dielectric layer 392B and the interface layer 392A is 2 × 10⁻⁶. 3 atoms / cm 2 Up to 5×10 7 atoms / cm 2 Within this range, this may help reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. The concentration of fluorine atom 612 at the interface between the high-k dielectric layer 392B and the interface layer 392A is less than 2 × 10⁻⁶. 3 atoms / cm 2 This could be detrimental, as it leads to increased leakage paths and reliability weaknesses. The concentration of fluorine atom 612 at the interface between the high-k dielectric layer 392B and the interface layer 392A is greater than 5 × 10⁻⁶. 7 atoms / cm 2 This could be detrimental because it negatively impacts the threshold voltage of the resulting transistor.

[0127] In some embodiments, the diffused fluorine atoms 612 have a density gradient from the top surface of the high-k dielectric layer 392B to the bottom surface of the high-k dielectric layer 392B, ranging from 2 × 10⁻⁶. 3 atoms / cm 2 / nm to 5×10 7atoms / cm 2 / nm, which may help reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. The density gradient from the top surface of the high-k dielectric layer 392B to the bottom surface of the high-k dielectric layer 392B is less than 2×10 3 atoms / cm 2 / nm may be disadvantageous because it leads to increased leakage paths and reliability weaknesses. The density gradient from the top surface of the high-k dielectric layer 392B to the bottom surface of the high-k dielectric layer 392B is greater than 5 × 10⁻⁶. 7 atoms / cm 2 / nm may be detrimental because it negatively impacts the threshold voltage of the resulting transistor.

[0128] In some embodiments, the concentration of fluorine atoms 612 at the interface between the interface layer 392A and the channel region 358 is 2 × 10⁻⁶. 3 atoms / cm 2 Up to 5×10 7 atoms / cm 2 Within this range, this may help reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. The concentration of fluorine atoms 612 at the interface between interface layer 392A and channel region 358 is less than 2 × 10⁻⁶. 3 atoms / cm 2 This could be detrimental, as it leads to increased leakage paths and reliability vulnerabilities. The concentration of fluorine atoms 612 at the interface between interface layer 92A and channel region 358 is greater than 5 × 10⁻⁶. 7 atoms / cm 2 This could be detrimental because it negatively impacts the threshold voltage of the resulting transistor.

[0129] In some embodiments, the diffused fluorine atoms 612 have a distance of 2 × 10 from the top surface of the interface layer 392A to the bottom surface of the interface layer 392A. 3 atoms / cm 2 / nm to 5×10 7 atoms / cm 2 The density gradient within this range may help reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. The density gradient from the top surface of interface layer 392A to the bottom surface of interface layer 392A is less than 2 × 10⁻⁶. 3 atoms / cm 2 / nm may be disadvantageous because it leads to increased leakage paths and reliability weaknesses. The density gradient from the top surface of interface layer 392A to the bottom surface of interface layer 392A is greater than 5 × 10⁻⁶. 7 atoms / cm 2 / nm may be disadvantageous because it negatively affects the threshold voltage of the resulting transistor.

[0130] exist Figure 45 In this process, a dipole layer 620 is formed over a high-k dielectric layer 392B. The dipole layer 620 then serves as a source of dipole dopant material to dope the gate dielectric layer 392 in order to adjust the threshold voltage of the subsequently formed transistor. The dipole dopant material of the dipole layer 620 may include aluminum (Al), lanthanum (La), zinc (Zn), gallium (Ga), or combinations thereof; the dipole layer 620 may be formed from its oxide, its nitride, or its carbide, etc. Different dipole layers 620 may be formed in the n-type region 350N and the p-type region 350P. In some embodiments, the dipole layer 620 in the p-type region 350P is formed of a material including a p-type dipole dopant, such as zinc oxide. In some embodiments, the dipole layer 620 in the n-type region 350N is formed of a material including an n-type dipole dopant, such as lanthanum oxide.

[0131] In some embodiments, the dipole layer 620 is formed by atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD) processes. The formation of the dipole layer 620 can be performed at temperatures ranging from 250°C to 550°C and pressures ranging from 0.5 Torr to 40 Torr. The process may include cyclically pulsed a first process gas, purging the first process gas (e.g., using nitrogen (N2)), pulsed a second process gas, and purging the second process gas (e.g., using nitrogen (N2)).

[0132] The first process gas is a doped gas containing the desired dipole dopant. Suitable doped gases include aluminum-containing gases such as trimethylaluminum (TMA) (Al2(CH3)6), lanthanum-containing gases such as tris(isopropylcyclopentadienyl)lanthanum (La(iPrCp)3), zinc-containing gases such as diethylzinc (Zn(C2H5)2), and gallium-containing gases such as tris(dimethylamino)gallium(III) (Ga2[N(CH3)2]6), etc. The second process gas is a gas of material capable of reacting with the first process gas to form the dipole layer 620.

[0133] The second process gas may include oxygen-containing gases such as oxygen (O2 and / or O3) and / or water (H2O), as well as other gases such as nitrogen (N2), hydrogen (H2), argon, helium, krypton, xenon and / or similar gases, or combinations thereof. The duration of each pulse and essence cycle may range from 0.1 seconds to 20 seconds.

[0134] exist Figure 46In this process, annealing 630 is performed to drive (e.g., diffuse) dipole dopant material from dipole layer 620 into gate dielectric layer 392 (e.g., high-k dielectric layer 392B and / or interface layer 392A). The diffused dipole dopant material can modulate the threshold voltage of the subsequently formed transistor. The diffused dipole dopant material can introduce energy states into gate dielectric layer 392 close to the conduction band edge of gate dielectric layer 392, which can make the conductivity of gate dielectric layer 392 closer to the conductivity of semiconductor material. This increased conductivity of gate dielectric layer 392 may cause charge (e.g., electrons released by oxygen vacancies along the interface of gate dielectric layer 392 (e.g., the interface between high-k dielectric layer 392B, interface layer 392A, and channel region 358 of fin 352)) to accumulate along the interface of gate dielectric layer 392. This charge accumulation along the interface of gate dielectric layer 392 may lead to leakage paths and reliability problems. Diffused fluorine atoms 612 (see above, Figure 44 Electrons can be located by filling oxygen vacancies, reducing the charge along the interface, and thus reducing leakage paths and reliability weaknesses.

[0135] In some embodiments, the diffused fluorine atoms 612 combine with the diffused dipole dopant material to form a combined fluorine-dipole material, which includes fluorine atoms combined with the dipole dopant material. For example, the combined fluorine-dipole material may include F-Al-O materials, Al-OF materials, F-La-O materials, La-OF materials, etc. These combined fluorine-dipole materials can further reduce the charge along the interface.

[0136] In some embodiments, annealing 630 is a rapid thermal annealing or other thermal process that can be performed in a temperature range from 500°C to 1000°C and for a duration ranging from 1 second to 20 seconds. Annealing 630 may have a temperature and / or duration sufficient to drive (e.g., diffuse) one or more dipole dopant materials into the gate dielectric layer 392 to achieve a desired dipole dopant concentration (see below). Figure 48 ).

[0137] exist Figure 47 In this process, one or more material-selective etching processes are used to remove the dipole layer 620. The etching processes may include wet etching or dry etching. In some embodiments, the dipole layer 620 is removed using a wet etching process employing, for example, SC-1, SC-2, dilute hydrofluoric acid, ammonium hydroxide, or combinations thereof. In some embodiments, the dipole layer 620 is removed using a dry etching process employing, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. However, any suitable removal process can be used to remove the dipole layer 620.

[0138] exist Figure 48 In this configuration, the gate electrode layer 394 is deposited on the gate dielectric layer 392. As described above, the gate electrode layer 394 may include any number of liner layers 394A, any number of work function adjustment layers 394B, and filler material 394C. The liner layer 394A is formed of any acceptable material to promote adhesion and prevent diffusion. For example, the liner layer 394A may be formed of a metal or a metal nitride, such as titanium nitride, titanium aluminum nitride, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, etc., which can be deposited by ALD, CVD, PVD, etc.

[0139] The work function adjustment layer 394B is formed of any acceptable material to adjust the work function of the device to the amount required for a given application of the device to be formed. In some embodiments, the work function adjustment layer 394B in the p-type region 350P is formed of a p-type work function metal (P-WFM), such as titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof, which can be deposited by ALD, CVD, or PVD. In some embodiments, the work function adjustment layer 394B in the n-type region 350N is formed of an n-type work function metal (N-WFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), or combinations thereof, which can be deposited by ALD, CVD, or PVD.

[0140] The filler material 394C includes any acceptable low-resistivity material. For example, the filler material 394C can be formed from metals such as tungsten, aluminum, cobalt, ruthenium, combinations thereof, etc., which can be deposited by ALD, CVD, or PVD, etc. The filler material 394C fills the remaining portion of the recess 390.

[0141] In some embodiments, the concentration of fluorine atoms 612 at the interface between the high-k dielectric layer 392B and the gate electrode layer 394 is 2 × 10⁻⁶. 3 atoms / cm 2 Up to 5×10 7 atoms / cm 2 Within this range, this may help reduce leakage paths and reliability weaknesses caused by the subsequent introduction of dipole dopants. The concentration of fluorine atoms 612 at the interface between the high-k dielectric layer 392B and the gate electrode layer 394 is less than 2 × 10⁻⁶. 3 atoms / cm 2 This could be detrimental, as it leads to increased leakage paths and reliability weaknesses. The concentration of fluorine atoms 612 at the interface between the high-k dielectric layer 392B and the gate electrode layer 394 is greater than 5 × 10⁻⁶. 7 atoms / cm 2 This could be detrimental because it negatively impacts the threshold voltage of the resulting transistor.

[0142] Figure 49 A flowchart of a method 1000 for forming a replacement gate layer is shown, as follows: Figures 43 to 48 As shown. In step 1010, a gate dielectric layer 392 is formed, as described above regarding... Figure 43 As described above. In step 1020, a fluorine treatment 610 is performed on the gate dielectric layer 392, as described above. Figure 44 As described above. In step 1030, a dipole layer 620 is formed on the gate dielectric layer 392, as described above. Figure 45 As described above. In step 1040, the dipole dopant material is driven from the dipole layer 620 into the gate dielectric layer 392, as described above. Figure 46 As described above. In step 1050, the dipole layer 620 is removed, as per the above description. Figure 47 As described above. In step 1060, a gate electrode layer 394 is formed on the gate dielectric layer 392, as described above. Figure 48 As stated above.

[0143] exist Figure 50A and 50B In this process, a removal process is performed to remove excess portions of the gate dielectric layer 392 and the gate electrode layer 394, thereby forming a gate dielectric 402 and a gate electrode 404, the excess portions of which are above the top surface of the ILD 388. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be used. The remaining portion of the gate electrode layer 394 in the recess forms the gate electrode 404. The remaining portion of the gate dielectric layer 392 in the recess forms the gate dielectric 402. The gate dielectric 402 and the gate electrode 404 thus form the replacement gate of the resulting FinFET. The gate electrode 404 and the gate dielectric 402 may be collectively referred to as the “gate structure”. The gate and the gate structure may extend along the sidewalls of the channel region 358 of the fin 352.

[0144] The gate dielectric 402 has diffused dipole dopant material useful for adjusting the threshold voltage of the formed FinFET, and the diffused fluorine atoms are useful for reducing leakage and reliability issues (which the presence of dipole dopant material can cause in other cases). Due to the presence of dipole dopant material in the gate dielectric 402, the work function adjustment layer 394B (see...) Figure 48 The thickness of the gate electrode 404 can be smaller, which allows for a smaller spacing between adjacent gate electrodes 404. In some embodiments, the gate electrode 404 does not have a work function adjustment layer because the threshold voltage of the gate can be adjusted by a dipole dopant material in the gate dielectric layer 104.

[0145] In some embodiments, after forming the gate dielectric 402, the high-k dielectric layer 392B (see...) Figure 48The concentration of the dipole dopant in ) is 2×10 3 cm -3 Up to 5×10 7 cm -3 Within this range, it may be advantageous for adjusting the threshold voltage of the subsequently formed gate. The dipole dopant concentration in the high-k dielectric layer 392B is less than 2 × 10⁻⁶. 3 cm -3 This could be disadvantageous because the threshold voltage of the subsequently formed gate cannot be adequately adjusted. The dipole dopant concentration in the high-k dielectric layer 392B is greater than 5 × 10⁻⁶. 7 cm -3 This could be detrimental because it increases leakage paths and reliability weaknesses.

[0146] In some embodiments, after the gate dielectric 402 is formed, the interface layer 392A (see...) Figure 48 The concentration of the dipole dopant in ) is 2×10 3 cm -3 Up to 5×10 7 cm -3 Within this range, it can be beneficial to adjust the threshold voltage of the subsequently formed gate. The dipole dopant concentration in interface layer 392A is less than 2 × 10⁻⁶. 3 cm -3 This could be disadvantageous because the threshold voltage of the subsequently formed gate cannot be adequately adjusted. The dipole dopant concentration in interface layer 392A is greater than 5 × 10⁻⁶. 7 cm -3 This could be disadvantageous because it increases leakage paths and reliability vulnerabilities. In some embodiments, the dipole dopant concentration in the high-k dielectric layer 392B is greater than the dipole dopant concentration in the interface layer 392A.

[0147] exist Figure 51A and 51B In this embodiment, a gate mask 396 is formed over a gate structure (including a gate dielectric 402 and a corresponding gate electrode 404), and the gate mask 396 may be disposed between opposing portions of a gate spacer 386. In some embodiments, forming the gate mask 396 includes recessing the gate structure, thereby forming a recess directly over the gate structure and between opposing portions of the gate spacer 386. The recess is filled with the gate mask 396 comprising one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride), followed by a planarization process to remove excess portions of the dielectric material extending above the first ILD 388. The gate mask 396 is optional and may be omitted in some embodiments. In such embodiments, the gate structure may remain flush with the top surface of the first ILD 388.

[0148] Similarly, Figure 51A and51B As shown, the second ILD 408 is deposited on top of the first ILD 388. In some embodiments, the second ILD 408 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 408 is formed of a dielectric material such as PSG, BSG, BPSG, or USG, and can be deposited by any suitable method such as CVD and PECVD. The gate contact 410 is subsequently formed (see below). Figure 52A and 52B It passes through the second ILD 408 and the gate mask 396 (if present) to contact the top surface of the recessed gate electrode 404.

[0149] exist Figure 52A and 52B In some embodiments, gate contacts 410 and source / drain contacts 412 are formed through the second ILD 408 and the first ILD 388. Openings for the source / drain contacts 412 are formed through the first ILD 388 and the second ILD 408, and openings for the gate contacts 410 are formed through the second ILD 408 and the gate mask 396 (if present). Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown), such as a diffusion barrier layer or adhesion layer, and conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the ILD 408. The remaining liner and conductive material form the source / drain contacts 412 and the gate contacts 410 in the openings.

[0150] An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 382 and the source / drain contact 412. The source / drain contact 412 is physically and electrically coupled to the epitaxial source / drain region 382, ​​and the gate contact 410 is physically and electrically coupled to the gate electrode 404. The source / drain contact 412 and the gate contact 410 can be formed in different processes or in the same process. Although each of the source / drain contact 412 and the gate contact 410 is shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 412 and the gate contact 410 can be formed in different cross-sections, which avoids short circuits in the contacts.

[0151] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as gate-all-around (GAAFET) field-effect transistors (e.g., nanostructures, nanosheets, or nanowires). See above for reference. Figure 1-24EThe GAA device is formed as described.

[0152] Figure 53 An example of a GAAFET according to some embodiments is shown in three-dimensional view. The GAAFET includes a nanostructure 355 (e.g., nanosheet or nanowire, etc.) on fins 366 on a substrate 350 (e.g., a semiconductor substrate), wherein the nanostructure 355 serves as the channel region of the GAAFET. The nanostructure 355 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 356 are disposed between adjacent fins 366, and the fins 366 may protrude from and protrude above these isolation regions 356. Although the bottom of the fins 366 is shown as being a single, continuous material with the substrate 350, the bottom of the fins 366 and / or the substrate 350 may include a single material or multiple materials. In this document, fin 366 refers to the portion extending between adjacent isolation regions 368.

[0153] The gate dielectric 402 is located above the top surface of the fin 366 and along the top, sidewalls, and bottom surfaces of the nanostructure 355. The formation of the gate dielectric 402 is similar to that described above. Figure 42A-50B The difference lies in the formation of the gate dielectric 402 in a GAAFET (e.g., as referenced above). Figure 15 In the context of (as described above). For example, the gate dielectric 402 may be included on the top surface of the fin 366 and along the interface layer 392A of the top surface, sidewalls and bottom surface of the nanostructure 355 (see above, Figure 48 ) and a high-k dielectric layer 392B along the top, sidewalls and bottom surfaces of interface layer 392A (see above, Figure 48 The gate electrode 404 is on the gate dielectric 402. The epitaxial source / drain region 382 is disposed on the fin 366 on the opposite side of the gate dielectric 402 and the gate electrode 404.

[0154] The embodiments of this disclosure have several advantageous features. Dipole dopant material diffuses into one or more gate dielectric layers to adjust the threshold voltage of the subsequently formed transistor without negatively impacting the corresponding spacing of the transistor's gates. Dipole doping of one or more gate dielectric layers can lead to leakage paths and reliability issues, such as charge accumulation at the interface between one or more gate dielectric layers or the underlying channel region.

[0155] Furthermore, by forming a fluorine-containing layer and then diffusing fluorine into the underlying gate dielectric to locate electrons, leakage path problems can be reduced and the reliability of the resulting transistor can be improved. Additionally, diffusing fluorine has the effect of adjusting the threshold voltage of the resulting transistor, which can be used in embodiments of this application to adjust the threshold voltage. Furthermore, by selectively doping fluorine into selected transistors, the performance of the transistor can be selectively adjusted.

[0156] According to some embodiments of this disclosure, a method includes: removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench, wherein the first dummy gate stack and the second dummy gate stack are located in a first device region and a second device region, respectively; depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively; forming a fluorine-containing layer, the fluorine-containing layer including a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer; removing the second portion of the fluorine-containing layer; performing an annealing process to diffuse fluorine in the first portion of the fluorine-containing layer into the first gate dielectric layer; and after the annealing process, forming a first work function layer and a second work function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

[0157] In one embodiment, forming the fluorine-containing layer includes depositing the fluorine-containing layer using a fluorine-containing precursor. In another embodiment, the fluorine-containing precursor includes WF6. In yet another embodiment, the deposition of the fluorine-containing layer is performed using an additional precursor containing a silane. In another embodiment, forming the fluorine-containing layer includes immersing a corresponding wafer comprising the first gate dielectric layer and the second gate dielectric layer in a silicon-containing process gas. In yet another embodiment, the immersion results in an increased percentage of fluorine atoms on the surface portion of the first gate dielectric layer in contact with the silicon-containing process gas, thus forming the fluorine-containing layer.

[0158] In an embodiment, the silicon-containing process gas is selected from NF3, WF6, or a combination thereof. In an embodiment, the method further includes depositing protective layers comprising a first portion and a second portion on the first gate dielectric layer and the second gate dielectric layer, respectively, before forming the fluorine-containing layer. In an embodiment, in the step of removing the second portion of the fluorine-containing layer, a portion of the protective layer is further removed from over the second gate dielectric layer. In an embodiment, the method further includes removing an additional portion of the protective layer from over the first gate dielectric layer after the annealing process. In an embodiment, the method further includes forming a first source / drain region on one side of the first work function layer and a second source / drain region on one side of the second work function layer, wherein the first source / drain region and the second source / drain region have opposite conductivity types.

[0159] In one embodiment, the method further includes forming a first source / drain region on one side of the first work function layer and a second source / drain region on one side of the second work function layer, wherein the first source / drain region and the second source / drain region have the same conductivity type. In another embodiment, the first dummy gate stack is formed on the top surface and sidewalls of a multilayer stack, and wherein the multilayer stack includes alternating sacrificial layers and multiple nanostructures.

[0160] According to some embodiments of this disclosure, a method includes: forming a first dummy gate stack on the top surface and sidewalls of a first multilayer stack, wherein the first multilayer stack includes alternating first plurality of sacrificial layers and first plurality of nanostructures; forming a second dummy gate stack on the top surface and sidewalls of a second multilayer stack, wherein the second multilayer stack includes alternating second plurality of sacrificial layers and second plurality of nanostructures; removing the first dummy gate stack and the second dummy gate stack, and forming a first recess and a second recess in a dielectric layer, respectively; removing the first plurality of sacrificial layers and the second plurality of sacrificial layers; depositing a first gate dielectric surrounding the first plurality of nanostructures; depositing a second gate dielectric surrounding the second plurality of nanostructures; depositing a first protective layer and a second protective layer on the first gate dielectric and the second gate dielectric, respectively; forming a first fluorinated layer and a second fluorinated layer on the first protective layer and the second protective layer, respectively; removing the second fluorinated layer; performing an annealing process after removing the second fluorinated layer, wherein the first fluorinated layer is subjected to the annealing process; and removing the first fluorinated layer after the annealing process.

[0161] In one embodiment, the method further includes: removing the first protective layer and the second protective layer; and forming a work function layer in the space left by the removed first and second protective layers. In another embodiment, the method further includes forming a first work function layer and a second work function layer on the first protective layer and the second protective layer, respectively. In yet another embodiment, forming the first fluorinated layer and the second fluorinated layer includes a deposition process or an immersion process.

[0162] According to some embodiments of the present disclosure, a method includes: forming a first nanostructure in a first trench, wherein a first gate spacer includes portions on opposite sides of the first trench; forming a second nanostructure in a second trench, wherein a second gate spacer includes portions on opposite sides of the second trench; depositing a first gate dielectric extending into the first trench to surround the first nanostructure; depositing a second gate dielectric extending into the second trench to surround the second nanostructure; and after forming the first gate dielectric and the second gate dielectric, adding fluorine to the first gate dielectric, wherein when fluorine is added to the first gate dielectric, the fluorine in the second gate dielectric remains substantially unchanged.

[0163] In one embodiment, the addition of fluorine includes: forming a fluorine-containing layer on the first gate dielectric; and performing an annealing process to drive the fluorine from the fluorine-containing layer into the first gate dielectric. In another embodiment, the fluorine-containing layer is further formed to extend on the second gate dielectric, and the method further includes removing the fluorine-containing layer from the second trench prior to the annealing process.

[0164] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

[0165] Example 1. A method comprising:

[0166] Remove the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench, wherein the first dummy gate stack and the second dummy gate stack are located in the first device region and the second device region, respectively;

[0167] The deposition extends to the first gate dielectric layer and the second gate dielectric layer in the first trench and the second trench, respectively;

[0168] A fluorine-containing layer is formed, the fluorine-containing layer comprising a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer;

[0169] Remove the second portion of the fluorine-containing layer;

[0170] An annealing process is performed to diffuse fluorine from the first portion of the fluorine-containing layer into the first gate dielectric layer; and

[0171] After the annealing process, a first work function layer and a second work function layer are formed on the first gate dielectric layer and the second gate dielectric layer, respectively.

[0172] Example 2. The method according to Example 1, wherein forming the fluorinated layer includes depositing the fluorinated layer using a fluorinated precursor.

[0173] Example 3. The method according to Example 2, wherein the fluorinated precursor comprises WF6.

[0174] Example 4. The method according to Example 3, wherein the deposition of the fluorine-containing layer is performed using an additional precursor including a silane.

[0175] Example 5. The method according to Example 1, wherein forming the fluorine-containing layer includes immersing a corresponding wafer including the first gate dielectric layer and the second gate dielectric layer in a silicon-containing process gas.

[0176] Example 6. The method according to Example 5, wherein the immersion causes the surface portion of the first gate dielectric layer in contact with the silicon-containing process gas to have an increased percentage of fluorine atoms and causes the fluorine-containing layer to form on the surface portion.

[0177] Example 7. The method according to Example 5, wherein the silicon-containing process gas is selected from NF3, WF6, or a combination thereof.

[0178] Example 8. The method described in Example 1 further includes:

[0179] Before forming the fluorine-containing layer, protective layers comprising a first portion and a second portion are deposited on the first gate dielectric layer and the second gate dielectric layer, respectively.

[0180] Example 9. The method according to Example 8, wherein, in the step of removing the second portion of the fluorine-containing layer, a portion of the protective layer is also removed from the second gate dielectric layer.

[0181] Example 10. The method according to Example 9 further includes removing an additional portion of the protective layer from above the first gate dielectric layer after the annealing process.

[0182] Example 11. The method according to Example 1 further includes forming a first source / drain region on one side of the first work function layer and forming a second source / drain region on one side of the second work function layer, wherein the first source / drain region and the second source / drain region have opposite conductivity types.

[0183] Example 12. The method according to Example 1 further includes forming a first source / drain region on one side of the first work function layer and forming a second source / drain region on one side of the second work function layer, wherein the first source / drain region and the second source / drain region have the same conductivity type.

[0184] Example 13. The method according to Example 1, wherein the first dummy gate stack is formed on the top surface and sidewalls of a multilayer stack, and wherein the multilayer stack includes a plurality of sacrificial layers and a plurality of nanostructures arranged alternately.

[0185] Example 14. A method comprising:

[0186] A first dummy gate stack is formed on the top surface and sidewalls of a first multilayer stack, wherein the first multilayer stack includes a first plurality of sacrificial layers and a first plurality of nanostructures arranged alternately;

[0187] A second dummy gate stack is formed on the top surface and sidewalls of the second multilayer stack, wherein the second multilayer stack includes alternating second sacrificial layers and second nanostructures;

[0188] Remove the first dummy gate stack and the second dummy gate stack to form a first recess and a second recess in the dielectric layer, respectively;

[0189] Remove the first plurality of sacrificial layers and the second plurality of sacrificial layers;

[0190] Deposit a first gate dielectric surrounding the first plurality of nanostructures;

[0191] A second gate dielectric is deposited around the second plurality of nanostructures;

[0192] A first protective layer and a second protective layer are deposited on the first gate dielectric and the second gate dielectric, respectively;

[0193] A first fluorine-containing layer and a second fluorine-containing layer are formed on the first protective layer and the second protective layer, respectively;

[0194] Remove the second fluorine-containing layer;

[0195] After removing the second fluorinated layer, an annealing process is performed, wherein the first fluorinated layer undergoes the annealing process; and

[0196] After the annealing process, the first fluorine-containing layer is removed.

[0197] Example 15. The method according to Example 14 further includes:

[0198] Remove the first protective layer and the second protective layer; and

[0199] A function layer is formed in the space left by the removal of the first and second protective layers.

[0200] Example 16. The method according to Example 14 further includes forming a first work function layer and a second work function layer on the first protection layer and the second protection layer, respectively.

[0201] Example 17. The method according to Example 14, wherein forming the first fluorinated layer and the second fluorinated layer includes a deposition process or an immersion process.

[0202] Example 18. A method comprising:

[0203] A first nanostructure is formed in a first trench, wherein a first gate spacer is included in a portion on opposite sides of the first trench;

[0204] A second nanostructure is formed in a second trench, wherein a second gate spacer is included in a portion on the opposite side of the second trench;

[0205] The deposition extends into the first trench to surround the first gate dielectric of the first nanostructure;

[0206] The deposition extends into the second trench to surround the second gate dielectric of the second nanostructure; and

[0207] After the first gate dielectric and the second gate dielectric are formed, fluorine is added to the first gate dielectric, wherein when fluorine is added to the first gate dielectric, the fluorine in the second gate dielectric remains substantially unchanged.

[0208] Example 19. The method according to Example 18, wherein the addition of fluorine comprises:

[0209] A fluorine-containing layer is formed on the first gate dielectric; and

[0210] An annealing process is performed to drive the fluorine in the fluorine-containing layer into the first gate dielectric.

[0211] Example 20. The method according to Example 19, wherein the fluorine-containing layer is further formed to extend over the second gate dielectric, and the method further includes removing the fluorine-containing layer from the second trench prior to the annealing process.

Claims

1. A method comprising: Remove the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench, wherein the first dummy gate stack and the second dummy gate stack are located in the first device region and the second device region, respectively; The deposition extends to the first gate dielectric layer and the second gate dielectric layer in the first trench and the second trench, respectively; A fluorine-containing layer is formed, the fluorine-containing layer comprising a first portion over the first gate dielectric layer and a second portion over the second gate dielectric layer; Remove the second portion of the fluorine-containing layer; An annealing process is performed to diffuse fluorine from the first portion of the fluorine-containing layer into the first gate dielectric layer; and After the annealing process, a first work function layer and a second work function layer are formed on the first gate dielectric layer and the second gate dielectric layer, respectively. The method further includes: after performing the annealing process, diffusing a dipole dopant material into the first gate dielectric layer, and forming a bonded fluorine-dipole material in the first gate dielectric layer.

2. The method according to claim 1, wherein, Forming the fluorine-containing layer includes depositing the fluorine-containing layer using a fluorine-containing precursor.

3. The method according to claim 2, wherein, The fluorine-containing precursor includes WF6.

4. The method according to claim 3, wherein, The deposition of the fluorine-containing layer is performed using additional chemicals, including silanes.

5. The method according to claim 1, wherein, Forming the fluorine-containing layer involves immersing a corresponding wafer, including the first gate dielectric layer and the second gate dielectric layer, in a fluorine-containing process gas.

6. The method according to claim 5, wherein, The immersion causes an increased percentage of fluorine atoms on the surface portion of the first gate dielectric layer that is in contact with the fluorine-containing process gas, resulting in the formation of the fluorine-containing layer on that surface portion.

7. The method according to claim 5, wherein, The fluorine-containing process gas is selected from NF3, WF6, or a combination thereof.

8. The method according to claim 1, further comprising: Before forming the fluorine-containing layer, protective layers comprising a first portion and a second portion are deposited on the first gate dielectric layer and the second gate dielectric layer, respectively.

9. The method according to claim 8, wherein, In the second step of removing the fluorine-containing layer, a portion of the protective layer is also removed from the second gate dielectric layer.

10. The method of claim 9, further comprising, after the annealing process, removing an additional portion of the protective layer over the first gate dielectric layer.

11. The method according to claim 1, further comprising forming a first source / drain region on one side of the first work function layer and forming a second source / drain region on one side of the second work function layer, wherein, The first source / drain region and the second source / drain region have opposite conductivity types.

12. The method according to claim 1, further comprising forming a first source / drain region on one side of the first work function layer and forming a second source / drain region on one side of the second work function layer, wherein, The first source / drain region and the second source / drain region have the same conductivity type.

13. The method according to claim 1, wherein, The first dummy gate stack is formed on the top surface and sidewalls of a multilayer stack, wherein the multilayer stack includes a plurality of sacrificial layers and a plurality of nanostructures arranged alternately.

14. A method comprising: A first dummy gate stack is formed on the top surface and sidewalls of a first multilayer stack, wherein the first multilayer stack includes a first plurality of sacrificial layers and a first plurality of nanostructures arranged alternately; A second dummy gate stack is formed on the top surface and sidewalls of the second multilayer stack, wherein the second multilayer stack includes alternating second sacrificial layers and second nanostructures; Remove the first dummy gate stack and the second dummy gate stack to form a first recess and a second recess in the dielectric layer, respectively; Remove the first plurality of sacrificial layers and the second plurality of sacrificial layers; Deposit a first gate dielectric surrounding the first plurality of nanostructures; A second gate dielectric is deposited around the second plurality of nanostructures; A first protective layer and a second protective layer are deposited on the first gate dielectric and the second gate dielectric, respectively; A first fluorine-containing layer and a second fluorine-containing layer are formed on the first protective layer and the second protective layer, respectively; Remove the second fluorine-containing layer; After removing the second fluorinated layer, an annealing process is performed, wherein the first fluorinated layer undergoes the annealing process; and After the annealing process, the first fluorine-containing layer is removed. The method further includes: after performing the annealing process, diffusing a dipole dopant material into the first gate dielectric, and forming a bonded fluorine-dipole material in the first gate dielectric.

15. The method of claim 14, further comprising: Remove the first protective layer and the second protective layer; as well as A function layer is formed in the space left by the removal of the first and second protective layers.

16. The method of claim 14, further comprising forming a first work function layer and a second work function layer on the first protective layer and the second gate dielectric layer, respectively.

17. The method of claim 14, wherein, The formation of the first fluorine-containing layer and the second fluorine-containing layer includes a deposition process or an immersion process.

18. A method comprising: A first nanostructure is formed in a first trench, wherein a first gate spacer is included in a portion on opposite sides of the first trench; A second nanostructure is formed in a second trench, wherein a second gate spacer is included in a portion on the opposite side of the second trench; The deposition extends into the first trench to surround the first gate dielectric of the first nanostructure; The deposition extends into the second trench to surround the second gate dielectric of the second nanostructure; and After forming the first gate dielectric and the second gate dielectric, fluorine is added to the first gate dielectric, wherein when fluorine is added to the first gate dielectric, the fluorine in the second gate dielectric remains substantially unchanged. The method further includes: after fluorine is added to the first gate dielectric, diffusing a dipole dopant material into the first gate dielectric, and forming a bonded fluorine-dipole material in the first gate dielectric.

19. The method according to claim 18, wherein, The added fluorine includes: A fluorine-containing layer is formed on the first gate dielectric; and An annealing process is performed to drive the fluorine in the fluorine-containing layer into the first gate dielectric.

20. The method according to claim 19, wherein, The fluorine-containing layer is further formed to extend over the second gate dielectric, and the method further includes removing the fluorine-containing layer from the second trench prior to the annealing process.

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