Fabrication methods of MOS devices
By forming an asymmetric sidewall structure during the fabrication of MOS devices, the problem of low drain breakdown voltage of MOS devices has been solved, expanding their application range in high-power fields.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-29
- Publication Date
- 2026-04-03
AI Technical Summary
The low drain breakdown voltage of symmetrical MOS devices in the prior art limits their application in high-power fields.
In the fabrication process of MOS devices, an asymmetric sidewall structure is formed by first forming a first isolation layer on the inside of the gate and then forming an outer wall on the outside, thereby improving the fabrication process and enhancing the applicability of the device.
By forming an asymmetric sidewall structure, the breakdown voltage of MOS devices is improved, expanding their application range in high-power fields.
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Figure CN115360144B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to a method for fabricating a MOS device. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to as "MOS" in this application) are electronic devices used in analog and digital circuits. (Reference) Figure 1 It shows a cross-sectional schematic diagram of a MOS device provided in the related art, such as Figure 1 As shown:
[0003] The MOS device is formed on a substrate 110, in which a shallow trench isolation (STI) structure 111 is formed. The area surrounded by the STI structure 111 is the active area (AA) of the MOS device, which includes an active area 101 of a first type of MOS device and an active area 102 of a second type of MOS device (if the first type of MOS device is a P-type MOS device, then the second type of MOS device is an N-type MOS device; if the first type of MOS device is an NMOS device, then the second type of MOS device is a PMOS device). A first gate 121 of the first type of MOS device is formed in the active area 101, and a second gate 122 of the second type of MOS device is formed in the active area 102. A gate dielectric layer is formed between the first gate 121, the second gate 122, and the substrate 110. Figure 1 (Not shown in the image), sidewalls 130 are formed on both sides of the first gate 121 and the second gate 122.
[0004] like Figure 1 As shown, the MOS devices (first type MOS devices and second type MOS devices) provided in the related technologies have a symmetrical structure, with symmetrical sidewalls of the same morphology on both sides of the gate (first gate 121 and second gate 122), and the sidewalls on both sides of the gate have the same thickness. However, symmetrical MOS devices are not suitable for high-power operating environments, and their low breakdown voltage (brake voltage, BV) at the output drain limits their application in high-power fields. Summary of the Invention
[0005] The present application provides a method for manufacturing a MOS device, which can solve the problem in the related art that the symmetric MOS device has a narrow application range due to the low breakdown voltage at its drain end. The method includes:
[0006] Remove the polysilicon layer and the first oxide layer in the first target area. The polysilicon layer is formed on the first oxide layer, and the first oxide layer is formed on the substrate.
[0007] Form a second oxide layer, which covers the exposed surfaces of the polysilicon layer, the first oxide layer, and the substrate.
[0008] Remove the second oxide layer on the top of the polysilicon layer and in a predetermined area of the first target area. The remaining second oxide layer forms a first isolation layer on the side surfaces of the polysilicon layer and the first oxide layer.
[0009] Remove the polysilicon layer and the first oxide layer in the second target area. The remaining polysilicon layer forms the gate of the MOS device, and the remaining first oxide layer forms the gate dielectric layer of the MOS device. The second target area and the first target area do not have overlapping areas.
[0010] Form a third oxide layer, which covers the exposed surfaces of the gate, the gate dielectric layer, the first isolation layer, and the substrate.
[0011] Remove the third oxide layer on the top of the gate and in a predetermined area of the first target area and the second target area. The remaining third oxide layer forms the outer sidewall of the gate on one side of the gate, and the remaining third oxide layer forms a second isolation layer on the other side of the gate. The first isolation layer and the second isolation layer form the inner sidewall of the gate.
[0012] In some embodiments, a surrounding STI structure is formed in the substrate. From a top view, the gate is formed in the area surrounded by the STI structure.
[0013] In some embodiments, from a top view, the gate is in a loop shape, the inner sidewall is formed inside the loop shape, and the outer sidewall is formed outside the loop shape.
[0014] In some embodiments, the removing the polysilicon layer and the first oxide layer in the first target area includes:
[0015] Cover a photoresist on the polysilicon layer through a lithography process to expose the first target area.
[0016] Perform etching to remove the polysilicon layer and the first oxide layer in the first target area.
[0017] Remove the photoresist.
[0018] In some embodiments, removing the polysilicon layer and the first oxide layer from the second target region includes:
[0019] Photoresist is applied using a photolithography process, covering the polysilicon layer, the first isolation layer, and the exposed surface of the substrate, thereby exposing the polysilicon layer of the second target region.
[0020] Etching is performed to remove the polysilicon layer and the first oxide layer in the second target region;
[0021] Remove light resistance.
[0022] In some embodiments, removing the second oxide layer from the top of the polysilicon layer and a predetermined area in the first target region includes:
[0023] The second oxide layer on top of the polysilicon layer and in a predetermined area of the first target region is removed by a dry etching process.
[0024] In some embodiments, removing the third oxide layer from the top of the gate and a predetermined area in the first target region and the second target region includes:
[0025] The third oxide layer in the top of the gate and the predetermined areas in the first and second target regions is removed by a dry etching process.
[0026] The technical solution of this application has at least the following advantages:
[0027] By forming a first isolation layer inside the gate during the fabrication process of a MOS device, and then simultaneously forming an outer wall on the outside of the gate and a second isolation layer on the inside of the gate, with the second isolation layer and the outer wall having the same thickness, and the second isolation layer and the first isolation layer forming an inner sidewall, the fabrication process of the MOS device is simplified, making it an asymmetric sidewall structure, thus improving the applicability of the device. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 This is a cross-sectional schematic diagram of a MOS device provided in related technologies;
[0030] Figure 2This is a flowchart of a method for fabricating a MOS device according to an exemplary embodiment of this application;
[0031] Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 This is a top view schematic diagram of the formation process of a MOS device provided in an exemplary embodiment of this application;
[0032] Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 This is a cross-sectional schematic diagram of the formation process of a MOS device provided in an exemplary embodiment of this application. Detailed Implementation
[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0036] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0037] refer to Figure 2 It illustrates a flowchart of a method for fabricating a MOS device according to an exemplary embodiment of this application, such as... Figure 2 As shown, the method includes:
[0038] Step S1: Remove the polysilicon layer and the first oxide layer in the first target region. The polysilicon layer is formed on the first oxide layer, and the first oxide layer is formed on the substrate.
[0039] For example, step S1 includes, but is not limited to: covering a photoresist layer on a polysilicon layer using a photolithography process to expose a first target region; performing etching to remove the polysilicon layer and the first oxide layer of the first target region; and removing the photoresist.
[0040] refer to Figure 3 It shows a top view schematic diagram of photoresist covering a polycrystalline silicon layer; Reference Figure 4 It shows a schematic cross-sectional view along the AA' direction after photoresist is coated on a polycrystalline silicon layer; Reference Figure 5 It shows a top view schematic diagram after removing the polysilicon layer and the first oxide layer in the first target region; Reference Figure 6 It shows a cross-sectional view along the AA' direction after the polysilicon layer and the first oxide layer of the first target region have been removed.
[0041] For example, such as Figure 3 and Figure 4 As shown, photoresist 400 can be applied to the polysilicon layer 320 using photolithography to expose the first target region. The polysilicon layer 320 is formed on the first oxide layer. Figure 3 and Figure 4 On a substrate 310 (not shown), a first oxide layer is formed, and a shallow trench isolation (STI) structure 311 is formed in the substrate 310. The shallow trench isolation structure 311, viewed from a top view, is a surrounding structure, and the surrounding area is the active area (AA) of the device. The first target region is located within the active area, and its area is smaller than the area of the active area. Figure 5 and Figure 6 As shown, etching is performed until the substrate 310 of the first target region is exposed, and the photoresist is removed.
[0042] Step S2: A second oxide layer is formed, which covers the polysilicon layer, the first oxide layer, and the exposed surface of the substrate.
[0043] refer to Figure 7 It shows a top view schematic diagram of the formation of the second oxide layer; Reference Figure 8 It shows a schematic cross-sectional view along the AA' direction after the formation of the second oxide layer.
[0044] For example, such as Figure 7 and Figure 8 As shown, a second oxide layer 330 can be formed by depositing silicon oxide (e.g., silicon dioxide (SiO2)) through a chemical vapor deposition (CVD) process (e.g., through a high-density plasma chemical vapor deposition (HDP CVD) process and / or a sub-atmospheric pressure chemical vapor deposition (SACVD) process).
[0045] Step S3: Remove the second oxide layer from the top of the polysilicon layer and a predetermined area in the first target region, and the remaining second oxide layer forms a first isolation layer on the side surface of the polysilicon layer and the first oxide layer.
[0046] refer to Figure 9 It shows a top view schematic diagram of the formation of the first isolation layer; Reference Figure 10 It shows a cross-sectional view along the AA' direction after the formation of the first isolation layer.
[0047] For example, such as Figure 9 and Figure 10 As shown, the top of the polysilicon layer 320 and the second oxide layer 330 in a predetermined area of the first target region can be removed by dry etching, and the remaining second oxide layer 330 forms a first isolation layer on the side surface of the polysilicon layer 320 and the first oxide layer.
[0048] Step S4: Remove the polysilicon layer and the first oxide layer of the second target region. The remaining polysilicon layer forms the gate of the MOS device, and the remaining first oxide layer forms the gate dielectric layer of the MOS device. The second target region and the first target region do not have overlapping regions.
[0049] For example, step S4 includes, but is not limited to: covering photoresist by photolithography, the photoresist covering the polysilicon layer, the first isolation layer and the exposed surface of the substrate, exposing the polysilicon layer of the second target region; performing etching to remove the polysilicon layer and the first oxide layer of the second target region; and removing the photoresist.
[0050] refer to Figure 11 It shows a top view of the photoresist layer after photolithography; Reference Figure 12 It shows a schematic cross-sectional view along the AA' direction after photoresist has been applied using a photolithography process; Reference Figure 13 , which shows a top view schematic diagram after removing the polysilicon layer and the first oxide layer of the second target area; refer to Figure 14 , which shows a cross-sectional schematic diagram along the AA' direction after removing the polysilicon layer and the first oxide layer of the second target area.
[0051] Exemplarily, as Figure 11 and Figure 12 shown, the photoresist 400 can be covered through a photolithography process to expose the polysilicon layer 320 of the second target area; as Figure 13 and Figure 14 shown, the formed gate 320 is in a loop shape. Observed from the top view, the gate 320 is formed in the area surrounded by the STI structure 311. The first target area is the area surrounded by the inner periphery of the gate 320, and the second target area is the area surrounded by the outer periphery of the gate 320.
[0052] Step S5, form a third oxide layer, and the third oxide layer covers the exposed surfaces of the gate, the gate dielectric layer, the first isolation layer, and the substrate.
[0053] Refer to Figure 15 , which shows a top view schematic diagram of forming the third oxide layer; refer to Figure 16 , which shows a cross-sectional schematic diagram along the AA' direction after forming the third oxide layer.
[0054] Exemplarily, as Figure 15 and Figure 16 shown, the third oxide layer 350 can be deposited by a CVD process (for example, by a HDP CVD process and / or a SACVD process) to form the third oxide layer 350, and the third oxide layer 350 covers the exposed surfaces of the gate 320, the gate dielectric layer, the first isolation layer 330, and the substrate 310.
[0055] Step S6, remove the third oxide layer on the top of the gate and in the predetermined areas of the first target area and the second target area. The remaining third oxide layer forms the outer sidewall of the gate on one side of the gate, and the remaining third oxide layer forms the second isolation layer on the other side of the gate. The first isolation layer and the second isolation layer form the inner sidewall of the gate.
[0056] Refer to Figure 17 , which shows a top view schematic diagram of forming the third oxide layer; refer to Figure 18 , which shows a cross-sectional schematic diagram along the AA' direction after forming the third oxide layer.
[0057] Exemplarily, as Figure 17 and Figure 18As shown, the third oxide layer 350 in the top of the gate 320 and a predetermined area in the first target region and the second target region can be removed by a dry etching process. The remaining third oxide layer 350 forms an outer wall on one side of the gate 320, and the remaining third oxide layer 350 forms a second isolation layer on the other side of the gate 320. The first isolation layer 330 and the second isolation layer 350 form the inner wall of the gate 320. Since the thickness of the inner wall is greater than the thickness of the outer wall, an asymmetric sidewall structure is formed.
[0058] In summary, in the embodiments of this application, by forming a first isolation layer inside the gate during the fabrication process of the MOS device, and then simultaneously forming an outer wall on the outside of the gate and a second isolation layer inside the gate, with the second isolation layer and the outer wall having the same thickness, and the second isolation layer and the first isolation layer forming an inner sidewall, the fabrication process of the MOS device is simplified, making it an asymmetric sidewall structure, thus improving the applicability of the device.
[0059] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a MOS device, characterized in that, Including: Removing the polysilicon layer and the first oxide layer in the first target region, where the polysilicon layer is formed on the first oxide layer, and the first oxide layer is formed on the substrate; Forming a second oxide layer that covers the exposed surfaces of the polysilicon layer, the first oxide layer, and the substrate; Removing the second oxide layer on the top of the polysilicon layer and in a predetermined region in the first target region, and the remaining second oxide layer forms a first isolation layer on the side surfaces of the polysilicon layer and the first oxide layer; Removing the polysilicon layer and the first oxide layer in the second target region, where the remaining polysilicon layer forms the gate of the MOS device, and the remaining first oxide layer forms the gate dielectric layer of the MOS device, and there is no overlapping region between the second target region and the first target region; Forming a third oxide layer that covers the exposed surfaces of the gate, the gate dielectric layer, the first isolation layer, and the substrate; Removing the third oxide layer on the top of the gate and in predetermined regions in the first target region and the second target region, and the remaining third oxide layer forms the outer sidewall of the gate on one side of the gate, and the remaining third oxide layer forms a second isolation layer on the other side of the gate, and the first isolation layer and the second isolation layer form the inner sidewall of the gate.
2. The method according to claim 1, characterized in that, A surrounding STI structure is formed in the substrate, and from a top view, the gate is formed in the region surrounded by the STI structure.
3. The method according to claim 2, characterized in that, From a top view, the gate is in a return shape, the inner sidewall is formed inside the return shape, and the outer sidewall is formed outside the return shape.
4. The method according to claim 3, characterized in that, The removing of the polysilicon layer and the first oxide layer in the first target region includes: Covering a photoresist on the polysilicon layer through a lithography process to expose the first target region; Performing etching to remove the polysilicon layer and the first oxide layer in the first target region; Removing the photoresist.
5. The method according to claim 4, characterized in that, The removing of the polysilicon layer and the first oxide layer in the second target region includes: Covering a photoresist through a lithography process, where the photoresist covers the exposed surfaces of the polysilicon layer, the first isolation layer, and the substrate to expose the polysilicon layer in the second target region; Performing etching to remove the polysilicon layer and the first oxide layer in the second target region; Removing the photoresist.
6. The method according to any one of claims 1 to 5, characterized in that, The removing of the second oxide layer on the top of the polysilicon layer and in a predetermined region in the first target region includes: Removing the second oxide layer on the top of the polysilicon layer and in a predetermined region in the first target region through a dry etching process.
7. The method according to claim 6, characterized in that, The removing of the third oxide layer on the top of the gate and in predetermined regions in the first target region and the second target region includes: Removing the third oxide layer on the top of the gate and in predetermined regions in the first target region and the second target region through a dry etching process.
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