Signal processing circuit, method, device and storage medium

Abstract

The present application discloses a signal processing circuit, method, device, and storage medium. The circuit includes: a test module, which is used to obtain a primary signal and obtain a reference secondary signal and a secondary signal to be tested based on the primary signal, and then obtain a clock signal based on the reference secondary signal; a signal recovery module, which is connected to the test module and is used to obtain the secondary signal to be tested and the clock signal, and recover the secondary signal to be tested based on the clock signal to obtain a target secondary signal. In an embodiment of the present application, the test module obtains a reference secondary signal and a secondary signal to be tested based on the primary signal, and obtains a clock signal based on the reference secondary signal and the secondary signal to be tested; the signal recovery module compensates and recovers the distorted secondary signal to be tested based on the clock signal to obtain a target secondary signal, which is used to improve the user's Internet access quality.

Description

Technical Field

[0001] The present application belongs to the field of signal processing technology, and in particular relates to a signal processing circuit, method, device and storage medium. Background Art

[0002] According to the negotiation and training mechanism of xDSL, the signal-to-noise ratio (SNR) directly affects the bit error rate (BER) of the xDSL system, and thus the training rate. As a low-power, small-signal transmission device in this circuit, the signal transformer must have high conversion efficiency and low signal distortion.

[0003] However, the leakage inductance L in the current signal transformer is i The existence of leakage inductance will reduce the conversion efficiency. The leakage inductance is the equivalent of energy loss caused by the incomplete coupling of the magnetic flux between the primary and secondary coils of the signal transformer. While the signal transmission power is partially lost, the information transmitted on the link is also partially lost, resulting in a slight impedance mismatch. It is also the main parasitic parameter that affects the signal transformer in the high-frequency environment and the decrease in the downstream line rate. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, one object of the present application is to provide a signal processing circuit, method, device and storage medium.

[0005] In order to solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0006] A signal processing circuit, comprising:

[0007] A testing module, the testing module being configured to obtain a primary signal, and obtain a reference secondary signal and a secondary signal to be tested based on the primary signal, and then obtain a clock signal based on the reference secondary signal;

[0008] A signal recovery module is connected to the test module, and is used to obtain the secondary signal to be tested and the clock signal, and recover the secondary signal to be tested according to the clock signal to obtain the target secondary signal.

[0009] Optionally, a processing chip is further included, wherein the input end of the processing chip is connected to the test module, and the output end of the processing chip is connected to the signal recovery module;

[0010] The processing chip is used to obtain the secondary signal to be tested and send the secondary signal to be tested to the signal recovery module.

[0011] Optionally, the test module includes a signal transformer to be tested, a first primary coil of the signal transformer to be tested is connected to a data interface, and a first secondary coil of the signal transformer to be tested is connected to an input terminal of the processing chip;

[0012] The signal transformer to be tested is used to obtain the primary signal, obtain the secondary signal to be tested according to the primary signal, and then send the secondary signal to be tested to the input end of the processing chip.

[0013] Optionally, the test module includes an isolation module;

[0014] The isolation module is connected to the signal transformer to be tested;

[0015] The isolation module is used to obtain the primary signal and the secondary signal to be tested, and obtain the reference secondary signal according to the primary signal.

[0016] Optionally, the isolation module includes a first load-effect isolation element;

[0017] The input end of the first load isolation element is connected to the input end of the processing chip and the first secondary winding of the signal transformer to be tested respectively;

[0018] The first load effect isolation element is used to obtain the secondary signal to be tested and process the signal to be tested.

[0019] Optionally, the first load effect isolation element includes a first operational amplifier, and the first operational amplifier is used to collect the secondary signal to be tested and amplify the secondary signal to be tested.

[0020] Optionally, the isolation module further includes a second load effect isolation element;

[0021] The input end of the second load effect isolation element is connected to the first primary coil of the signal transformer to be tested and the data interface respectively;

[0022] The second load-effect isolation element is used to obtain the primary signal and obtain the reference secondary signal according to the primary signal.

[0023] Optionally, the second load-effect isolation element includes a second operational amplifier, and the second operational amplifier is used to collect the primary signal and amplify the primary signal.

[0024] Optionally, the output end of the second load effect isolation element is connected to the second primary coil of the reference signal transformer;

[0025] The reference signal transformer is used to obtain the primary signal and obtain the reference secondary signal according to the primary signal.

[0026] Optionally, the test module further includes a digital signal processing element;

[0027] The input end of the digital signal processing element is connected to the second secondary winding of the reference signal transformer and the output end of the second load effect isolation element respectively; the output end of the digital signal processing element is connected to the signal recovery module;

[0028] The digital signal processing component is configured to obtain the reference secondary signal sent by the second secondary coil of the reference signal transformer and the secondary signal to be tested sent by the output end of the second load effect isolation component, and compare the reference secondary signal and the secondary signal to be tested to obtain a data loss rate of the secondary signal to be tested;

[0029] The digital signal processing component compares the data loss rate with a data loss rate threshold to obtain a comparison result, and processes the reference secondary signal according to the comparison result.

[0030] Optionally, the test module further includes a clock recovery element provided between the digital signal processing element and the signal recovery module;

[0031] The input end of the clock recovery element is connected to the output end of the digital signal processing element; the output end of the clock recovery element is connected to the input end of the signal recovery module;

[0032] The clock recovery element is used to obtain the reference secondary signal, obtain the clock signal according to the reference secondary signal, and then send the clock signal to the signal recovery module.

[0033] Optionally, the signal recovery module is provided with a data comparison element, and the input end of the data comparison element is respectively connected to the output end of the signal transformer to be tested and the clock recovery element;

[0034] The data comparison element is used to obtain the clock signal and the secondary signal to be tested, and compare the clock signal and the digital signal to be tested to obtain the data to be compensated.

[0035] An embodiment of the present application further provides a signal processing method, applied to the circuit as described above, comprising: a connected test module and a signal recovery module;

[0036] Based on the test module, a primary signal is acquired, and a reference secondary signal and a secondary signal to be tested are acquired according to the primary signal, and then a clock signal is acquired according to the reference secondary signal;

[0037] Based on the signal recovery module, the secondary signal to be tested and the clock signal are acquired, and the secondary signal to be tested is recovered according to the clock signal to obtain a target secondary signal.

[0038] An embodiment of the present application further provides an electronic device, characterized in that it includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above-mentioned method when executing the computer program.

[0039] An embodiment of the present application further provides a computer-readable storage medium, characterized in that the computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the method described above.

[0040] The embodiments of this application have the following technical effects:

[0041] In the above technical solution of the present application, the signal of the xDSL system passes through the data interface to obtain a primary signal. The primary signal enters the test module from the input end of the test module. The test module obtains a reference secondary signal and a secondary signal to be tested based on the primary signal, and obtains a clock signal based on the reference secondary signal and the secondary signal to be tested. The clock signal is then sent to the signal recovery module. The signal recovery module compensates and recovers the severely distorted secondary signal to be tested based on the clock signal to obtain a target secondary signal, and transmits the target secondary signal to improve the user's Internet access quality.

[0042] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a structural diagram of an equivalent circuit of a signal transformer provided in an embodiment of the present application;

[0044] Figure 2 is a structural diagram of a signal processing circuit provided in an embodiment of the present application;

[0045] Figure 3 This is a schematic diagram of an example structure of a signal processing circuit provided in an embodiment of the present application;

[0046] Figure 4Schematic diagram of the structure of the processing chip and signal recovery module provided in the embodiment of the present application;

[0047] Figure 5 This is a schematic structural diagram of a load effect isolation element provided in an embodiment of the present application;

[0048] Figure 6 is a structural diagram of a clock recovery element provided in an embodiment of the present application;

[0049] Figure 7 It is a flowchart of a signal processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0051] In order to facilitate the understanding of the embodiments by those skilled in the art, some terms are explained:

[0052] (1) RJ11: Four-connector interface.

[0053] (2)ADC: Analog to Digital Converter.

[0054] (3)DAC: Digital-to-Analog Converter.

[0055] (4)CPU: Central Processing Unit, central processing unit.

[0056] (5)I2C: Inter-Integrated Circuit, two-wire serial bus.

[0057] (6)Clock: clock.

[0058] (7)LNA: Low Noise Amplifier, low noise amplifier.

[0059] (8) LD: Line Driver, whose main function is signal amplification.

[0060] (9) wifi: wireless network communication technology.

[0061] (10) CDR: Clock and Data Recovery, clock and data recovery circuit.

[0062] like Figure 1 As shown, an embodiment of the present application provides an equivalent circuit of a signal transformer; specifically, the equivalent circuit uses passive network theory to equate the signal transformer to a two-port network. For ease of explanation, the magnetic core is regarded as an ideal linear state. Figure 1 In, R a is the line impedance at the input, R b is the load impedance, n represents the turns ratio of the primary and secondary coils of the signal transformer, L K represents the leakage inductance of the primary and secondary coils of the signal transformer, ω is the resonant frequency, and C p / C s are the distributed capacitances of the primary and secondary coils, C WW is the interleaving capacitor, R p 、R s are the copper loss resistance of the primary coil and the secondary coil respectively, R p / R c is the iron loss resistance of the primary coil, L m is the magnetizing inductance of the primary coil.

[0063] Leakage inductance L k The corresponding insertion loss can be calculated based on the following formula:

[0064]

[0065] Based on the above formula, we can know that the leakage inductance L of the signal transformer is k The corresponding insertion loss is related to the resonant frequency ω and leakage inductance L k related;

[0066] Specifically, when the frequency is high or the leakage inductance value is large, the corresponding insertion loss is also large. At this time, it will affect the complete transmission of the xDSL system signal and cause signal distortion. Or when the frequency is high and the leakage inductance value is large, the corresponding insertion loss is also large. At this time, it will also affect the complete transmission of the xDSL system signal and cause signal distortion.

[0067] In combination with the above equivalent circuit and formula, in order to reduce the bit error rate of the xDSL system caused by the insertion loss generated by the leakage inductance of the signal transformer and thereby improve the quality of signal transmission, the embodiments of the present application provide the following technical solutions:

[0068] like Figure 2 As shown, an embodiment of the present application provides a signal processing circuit, including:

[0069] A testing module, the testing module being configured to obtain a primary signal, and obtain a reference secondary signal and a secondary signal to be tested based on the primary signal, and then obtain a clock signal based on the reference secondary signal;

[0070] A signal recovery module is connected to the test module, and is used to obtain the secondary signal to be tested and the clock signal, and recover the secondary signal to be tested according to the clock signal to obtain the target secondary signal.

[0071] In an embodiment of the present application, the input end of the test module is connected to the data interface, and is used to obtain the primary signal based on the data interface; wherein the data interface can be implemented based on the RJ11 interface;

[0072] The output end of the signal recovery module can be connected to a network, such as a wireless network module.

[0073] Specifically, the xDSL system signal passes through the data interface to obtain a primary signal. The primary signal enters the test module from the input end. The test module obtains a reference secondary signal based on the primary signal, and obtains a clock signal based on the reference secondary signal. The clock signal is then sent to the signal recovery module. The signal recovery module compensates and recovers the severely distorted secondary signal to be tested based on the clock signal to obtain a target secondary signal, and transmits the target secondary signal to improve the user's Internet access quality.

[0074] like Figure 3 As shown, an optional embodiment of the present application further includes a processing chip, wherein the input end of the processing chip is connected to the test module, and the output end of the processing chip is connected to the signal recovery module;

[0075] The processing chip is used to obtain the secondary signal to be tested and send the secondary signal to be tested to the signal recovery module.

[0076] In the embodiment of the present application, the processing chip realizes transmission of the secondary signal to be tested to the signal recovery module.

[0077] like Figure 4 As shown, in the embodiment of the present application, the processing chip can be implemented based on an xDSL chip;

[0078] Specifically, the processing chip may include a filter, an LNA, and an LD;

[0079] The input of the filter is connected to the output of the LNA; the input of the LNA is connected to the output of the signal transformer to be tested.

[0080] The signal recovery module may include an ADC and a DAC, wherein the input of the ADC is connected to the output of the filter, the output of the DAC is connected to the input of the LD; the output of the LD is connected to the input of the signal transformer to be tested; the signal recovery module may be implemented based on a CPU;

[0081] The signal transformer sends the secondary signal to be tested to the input of the LNA of the processing chip. The LNA amplifies the acquired secondary signal to be tested and then sends it to the filter for filtering. The filtered secondary signal to be tested is sent to the input of the ADC by the output of the filter. The ADC performs analog-to-digital conversion on the acquired secondary signal to obtain data of the secondary signal to be tested.

[0082] Furthermore, the data of the signal recovery module can be converted from digital to analog through the DAC, and output to the input of the LD through the output of the DAC, amplified by the LD, and enter the signal transformer to be tested, and then the data is transmitted to the data interface, such as RJ11, through the signal transformer to be tested.

[0083] In addition, the signal recovery module and the processing chip are provided with an I2C circuit and a Clock circuit.

[0084] For example, taking the downstream signal as an example, the xDSL signal generated by the central office is transmitted through the twisted pair cable and input from the RJ11 port. After passing through the signal transformer to be tested, it enters the xDSL chip for amplification and filtering. The xDSL chip transmits the amplified signal to the CPU for analog-to-digital conversion. The CPU then transmits this digital signal to the Wi-Fi module, thus enabling the user to access the Internet.

[0085] Taking the uplink signal as an example, the data of the signal recovery module can be converted from digital to analog by the DAC, and output to the input of the LD through the output of the DAC, amplified by the LD, and enter the signal transformer to be tested, and then the data is transmitted to the data interface through the signal transformer to be tested;

[0086] In the embodiment of the present application, the structure of the processing chip and the signal recovery module realizes coupling separation, filtering, driving amplification, etc. of the uplink and downlink signals of the xDSL system.

[0087] like Figure 3 As shown, in an optional embodiment of the present application, the test module includes a signal transformer to be tested, the first primary coil of the signal transformer to be tested is connected to the data interface, and the first secondary coil of the signal transformer to be tested is connected to the input terminal of the processing chip;

[0088] The signal transformer to be tested is used to obtain the primary signal, obtain the secondary signal to be tested according to the primary signal, and then send the secondary signal to be tested to the input end of the processing chip.

[0089] In an embodiment of the present application, the first primary coil of the signal transformer to be tested obtains a primary signal based on a data interface, wherein the primary signal may specifically be a pulse signal. The primary signal is transmitted or converted to a first secondary coil via the first primary coil, and then the first secondary coil outputs a secondary signal to be tested.

[0090] Specifically, in the embodiment of the present application, the turns ratio of the first primary coil and the first secondary coil may be 2.7:1, and the turns ratio may be adjusted according to actual needs.

[0091] In an optional embodiment of the present application, the test module includes an isolation module;

[0092] The isolation module is connected to the signal transformer to be tested;

[0093] The isolation module is used to obtain the primary signal and the secondary signal to be tested, and obtain the reference secondary signal according to the primary signal.

[0094] In the embodiment of the present application, the isolation module is used to implement load effect isolation of the primary signal, and is also used to implement load effect isolation of the secondary signal to be tested, so as to reduce the influence of the load effect of the test module on signal transmission.

[0095] like Figure 3 As shown, in an optional embodiment of the present application, the isolation module includes a first load effect isolation element;

[0096] The input end of the first load isolation element is connected to the input end of the processing chip and the first secondary winding of the signal transformer to be tested respectively;

[0097] The first load effect isolation element is used to obtain the secondary signal to be tested and process the signal to be tested.

[0098] In an optional embodiment of the present application, the first load effect isolation element includes a first operational amplifier, and the first operational amplifier is used to collect the secondary signal to be tested and amplify the secondary signal to be tested.

[0099] like Figure 5 As shown, in an optional embodiment of the present application, the first load effect isolation element includes a first operational amplifier, and the first operational amplifier is used to collect the secondary signal to be tested and amplify the secondary signal to be tested.

[0100] The first load-effect isolation element further includes a first resistor R1 , a second resistor R2 , a third resistor R3 , a fourth resistor R4 , a fifth resistor R5 , a first capacitor C1 , and a second capacitor C2 .

[0101] The input end of the first resistor R1 is connected to the input end of the second resistor R2, the input end of the first capacitor C1, the non-inverting input end of the operational amplifier, and the input voltage U i connect;

[0102] The output end of the second resistor R2 is connected to the input end of the third resistor R3 and the output end of the first capacitor C1 respectively;

[0103] The output end of the second resistor R2 is grounded, the input end of the third resistor R3 is grounded, and the output end of the first capacitor C1 is grounded;

[0104] The output end of the first capacitor C1 is connected to the input end of the third resistor R3;

[0105] The output end of the third resistor R3 is connected to the inverting input end of the first operational amplifier and the input end of the fourth resistor R4 respectively;

[0106] The non-inverting input terminal of the first operational amplifier is connected to a power supply (for example, the power supply voltage may be 3.3V), and the inverting output terminal of the first operational amplifier is grounded;

[0107] The output end of the first operational amplifier is connected to the input end of the fifth resistor R5 and the output end of the fourth resistor R4 respectively;

[0108] The input end of the fifth resistor R5 is connected to the output end of the fourth resistor R4;

[0109] The output terminals of the fifth resistor R5 are connected to the output voltage U o and an input terminal of a second capacitor C2;

[0110] The input terminal of the second capacitor C2 is connected to the output voltage U o The output terminal of the second capacitor C2 is grounded.

[0111] The first resistor R1 and the second resistor R2 are used for voltage division to prevent damage to subsequent stages caused by excessive input voltage. The xDSL system signal passes through the first capacitor C1 of the first load-effect isolation element and is filtered before entering the first operational amplifier. Specifically, the first capacitor C1 can also serve as a decoupling capacitor to reduce power supply noise and increase the stability of the first operational amplifier. Its capacitance is generally 0.1uF. In actual application, the capacitance of the first capacitor C1 can be adjusted according to actual needs.

[0112] The third resistor R3 and the fourth resistor R4 play an amplifying role. Specifically, the amplification ratio of the third resistor R3 and the fourth resistor R4 can be calculated based on the following formula:

[0113]

[0114] The fifth resistor R5 and the second capacitor C2 form a low-pass filter for filtering out harmonics generated in the signal of the xDSL system.

[0115] In an embodiment of the present application, a load effect of a secondary signal to be tested is isolated based on a first load effect isolation element;

[0116] Specifically, since the interior of the first operational amplifier is composed of a field-effect transistor, which is a voltage-controlled element, there is basically no current between the gate G and the source S of an ideal field-effect transistor, only a control voltage, and G and S are insulated, so the resistance is large and the input impedance is also high. Therefore, the first operational amplifier of the embodiment of the present application has a very high input impedance.

[0117] In the embodiment of the present application, the first operational amplifier may firstly be used to collect and amplify the secondary signal to be tested;

[0118] Secondly, assuming that the input impedance of the first operational amplifier is very small, some current will flow through the operational amplifier, causing loss and affecting signal transmission on the original transmission path. Therefore, when the first operational amplifier has a very large input impedance, no current will flow through the first operational amplifier, and no loss will be caused, thereby minimizing the load effect.

[0119] Therefore, when the input end of the first load effect isolation element is connected to the first secondary coil of the signal transformer to be tested, the first load effect isolation element isolates the influence of the load effect on the transmission of the secondary signal to be tested, thereby ensuring that the transmission of the secondary signal to be tested in the transmission path of the test module is not affected, thereby ensuring the accuracy of the test of the insertion loss caused by the leakage inductance of the signal transformer to be tested.

[0120] like Figure 3 As shown, in an optional embodiment of the present application, the isolation module further includes a second load effect isolation element;

[0121] The input end of the second load effect isolation element is connected to the first primary coil of the signal transformer to be tested and the data interface respectively;

[0122] The second load-effect isolation element is used to obtain the primary signal and obtain the reference secondary signal according to the primary signal.

[0123] In an optional embodiment of the present application, the second load-effect isolation element includes a second operational amplifier, and the second operational amplifier is used to collect the primary signal and amplify the primary signal.

[0124] In an optional embodiment of the present application, the second load-effect isolation element includes a second operational amplifier, and the second operational amplifier is used to collect the primary signal and amplify the primary signal.

[0125] Specifically, the circuit structure of the second load-effect isolation element is the same as the circuit structure of the first load-effect isolation element. Therefore, the second load-effect isolation element can also be implemented based on the above-mentioned first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, first capacitor C1, second capacitor C2 and second operational amplifier (the structure is the same as the first operational amplifier).

[0126] In the embodiment of the present application, the second operational amplifier may firstly be used to collect and amplify the primary signal;

[0127] Secondly, for the same reason, when the second operational amplifier has a large input impedance, the loading effect can also be minimized.

[0128] Therefore, when the input end of the second load effect isolation element is connected to the first primary coil of the signal transformer to be tested and the data interface, the first load effect isolation element isolates the transmission influence of the load effect on the primary signal, thereby making the transmission of the primary signal in the transmission path of the test module unaffected, thereby ensuring the accuracy of the test of the insertion loss caused by the leakage inductance of the signal transformer to be tested.

[0129] In an optional embodiment of the present application, the output end of the second load-effect isolation element is connected to the second primary coil of the reference signal transformer;

[0130] The reference signal transformer is used to obtain the primary signal and obtain the reference secondary signal according to the primary signal.

[0131] Specifically, the output end of the second load effect isolation element is connected to the reference signal transformer, and the output end of the second load effect isolation element sends the primary signal to the second primary coil of the reference signal transformer. The primary signal passes through the second secondary coil to obtain a reference secondary signal.

[0132] In an embodiment of the present application, the reference signal transformer and the signal transformer to be tested have the same primary-secondary coil turns ratio. For example, when the turns ratio of the first primary coil to the first secondary coil is 2.7:1, the turns ratio of the second primary coil to the second secondary coil is also 2.7:1, and the reference signal transformer has better operating parameters such as DC resistance, total harmonic distortion, and leakage inductance.

[0133] That is, after the second primary coil obtains the primary signal, it transmits the primary signal to the second secondary coil to obtain a reference secondary signal. In this process, since the leakage inductance parameters of the reference signal transformer are better, that is, the insertion loss is small, the impact on signal transmission is also small, and will not affect the user's normal Internet access. For the convenience of subsequent testing, it can even be ignored.

[0134] Therefore, in the embodiment of the present application, the data loss rate of the reference secondary signal data is smaller than that of the primary signal, and can even be ignored for the convenience of subsequent calculations. Therefore, in the embodiment of the present application, the data loss rate of the data of the secondary signal to be tested is determined by comparing the data of the reference secondary signal with the data of the secondary signal to be tested, and then the leakage inductance of the signal transformer to be tested and the insertion loss of the signal transformer to be tested can be evaluated. According to the value of the data loss rate, it is determined whether the data of the secondary signal to be tested needs to be restored, that is, whether the degree of signal distortion is acceptable, so as to avoid the problem that the data loss rate of the secondary signal to be tested is too large, resulting in a poor Internet experience for users.

[0135] like Figure 3 As shown, in an optional embodiment of the present application, the test module further includes a digital signal processing element;

[0136] The input end of the digital signal processing element is connected to the second secondary winding of the reference signal transformer and the output end of the second load effect isolation element respectively; the output end of the digital signal processing element is connected to the signal recovery module;

[0137] The digital signal processing component is used to obtain the reference secondary signal sent by the second secondary coil of the reference signal transformer and the secondary signal to be tested sent by the output end of the second load effect isolation component, and compare the reference secondary signal and the secondary signal to be tested to obtain a data loss rate of the secondary signal to be tested;

[0138] The digital signal processing component compares the data loss rate with a data loss rate threshold to obtain a comparison result, and processes the reference secondary signal according to the comparison result.

[0139] In an embodiment of the present application, the second secondary coil of the reference signal transformer inputs the reference secondary signal to the input terminal of the digital signal processing component, and at the same time, the output terminal of the first load effect isolation component sends the secondary signal to be tested to the input terminal of the data signal processing component;

[0140] The digital signal processing component is provided with an ADC, and performs analog-to-digital conversion on the reference secondary signal and the secondary signal to be tested based on the ADC, converting the analog signals into digital signals, thereby obtaining a reference digital signal of the reference secondary signal and a digital signal to be tested respectively;

[0141] After obtaining the reference digital signal and the digital signal to be tested, the digital signal processing component performs word alignment on the reference digital signal and the digital signal to be tested, thereby determining the data loss rate of the digital signal to be tested relative to the reference digital signal.

[0142] Furthermore, in the embodiments of the present application, a data loss rate threshold may be preset based on actual needs (for example, the user's acceptance of the degree of signal distortion. Specifically, the greater the user's acceptance of the degree of signal distortion, the greater the data loss rate threshold, and so on). The data loss rate threshold is then compared with the actually calculated data loss rate to obtain a comparison result.

[0143] If the comparison result shows that the data loss rate is greater than the data loss rate threshold, it indicates that the signal transformer under test has a large insertion loss due to a large leakage inductance during signal transmission, thereby affecting the normal transmission of the signal and causing serious signal distortion. In this case, the digital signal processing unit processes the reference digital signal.

[0144] Or if the comparison result shows that the data loss rate is less than or equal to the data loss rate threshold, it indicates that during the signal transmission process, the signal transformer to be tested has a small leakage inductance, resulting in a small insertion loss and a low degree of signal distortion, which will not affect the normal transmission of the signal; at this time, the digital signal processing unit does not process the reference digital signal.

[0145] like Figure 3 As shown, in an optional embodiment of the present application, the test module further includes a clock recovery element provided between the digital signal processing element and the signal recovery module;

[0146] The input end of the clock recovery element is connected to the output end of the digital signal processing element; the output end of the clock recovery element is connected to the input end of the signal recovery module;

[0147] The clock recovery element is used to obtain the reference secondary signal, obtain the clock signal according to the reference secondary signal, and then send the clock signal to the signal recovery module.

[0148] In the embodiment of the present application, when the comparison result shows that the data loss rate is greater than the data loss rate threshold, it indicates that the signal transformer to be tested has a large insertion loss during signal transmission due to a large leakage inductance, thereby affecting the normal transmission of the signal;

[0149] Therefore, the digital signal processing element sends the reference digital signal to the clock recovery element, and the clock recovery element obtains a clock signal corresponding to the reference digital signal based on the reference digital signal, and sends the clock signal to the signal recovery module.

[0150] An optional embodiment of the present application is as follows: Figure 6 As shown, the clock recovery element can be implemented based on CDR; specifically, the clock recovery element includes a phase detector PD, a loop filter LF, and a voltage-controlled oscillator VCO, etc., which are connected in sequence.

[0151] Specifically, the input end of the phase detector PD is connected to the output end of the digital signal processing element, and the phase detector is used to obtain the reference digital signal V of the reference secondary signal output from the output end of the digital signal processing element. i At the same time, the input end of the phase detector PD is also connected to the output end of the voltage controlled oscillator VCO. The input end of the phase detector PD is used to obtain the signal V sent by the output end of the voltage controlled oscillator VCO. o Perform phase comparison, if the reference digital signal V i With V o If there is a frequency difference, a phase difference will be generated. The phase detector compares the phase error and converts it into a corresponding error voltage. The error voltage is filtered by the loop filter LF to generate a control signal for the voltage-controlled oscillator VCO, thereby adjusting the output clock frequency of the voltage-controlled oscillator VCO.

[0152] Repeat the above steps, through repeated phase detection and adjustment, the output signal V of the voltage controlled oscillator VCO is finally o frequency and the input digital signal V i The frequency of the reference digital signal is equal to that of the reference digital signal, thereby extracting the clock signal from the reference digital signal, and the clock recovery element enters the locked state.

[0153] Generally, the loop filter LF is usually a low-pass filter, and the input of the loop filter LF is the output voltage V of the phase detector. d , the loop filter LF filters out the voltage V d The high frequency components and noise in the image are averaged and the average component V is taken out. c To control the frequency of the voltage controlled oscillator VCO.

[0154] Therefore, the loop filter LF can improve the spectrum purity of the control voltage and thus enhance the stability of the circuit.

[0155] In an optional embodiment of the present application, the signal recovery module is provided with a data comparison element, and the input end of the data comparison element is respectively connected to the output end of the signal transformer to be tested and the clock recovery element;

[0156] The data comparison element is used to obtain the clock signal and the secondary signal to be tested, and compare the clock signal and the digital signal to be tested to obtain the data to be compensated.

[0157] In an embodiment of the present application, the data comparison component performs data bit alignment on the secondary signal to be tested according to the clock signal, and then performs word alignment to determine the data to be compensated;

[0158] Supplementing the secondary signal to be tested based on the data to be compensated to obtain a target secondary signal;

[0159] After obtaining the target secondary signal, the signal recovery module performs analog-to-digital conversion on the target secondary signal based on its built-in ADC to obtain the target secondary signal, and sends the target secondary signal to a wireless network module, such as a Wi-Fi module, thereby enabling users to access the Internet with high quality.

[0160] like Figure 7 As shown, the embodiment of the present application also provides a signal processing method, which is applied to Figure 2 The circuit shown includes: a connected test module and a signal recovery module;

[0161] Step S61: Based on the test module, a primary signal is acquired, and a reference secondary signal and a secondary signal to be tested are acquired according to the primary signal, and then a clock signal is acquired according to the reference secondary signal;

[0162] Specifically, based on the signal transformer to be tested of the test module, the primary signal is acquired, and the secondary signal to be tested is obtained according to the primary signal, and then the secondary signal to be tested is sent to the input end of the processing chip.

[0163] The isolation module based on the test module obtains the primary signal and the secondary signal to be tested, and obtains the reference secondary signal according to the primary signal; wherein the signal transformer to be tested is connected to the isolation module.

[0164] Further, based on the first load effect isolation element of the isolation module, the secondary signal to be tested is obtained, and the signal to be tested is processed;

[0165] Wherein, the input end of the first load effect isolation element is connected to the first secondary winding of the signal transformer to be tested;

[0166] The primary signal is acquired based on the second load-effect isolation element of the isolation module, and the reference secondary signal is obtained according to the primary signal.

[0167] The input end of the second load-effect isolation element is connected to the second primary coil of the reference signal transformer and the data interface respectively.

[0168] Furthermore, based on the digital signal processing element of the test module, the reference secondary signal sent by the second secondary coil of the reference signal transformer and the secondary signal to be tested sent by the output end of the second load effect isolation element are obtained, and the reference secondary signal and the secondary signal to be tested are compared to obtain a data loss rate of the secondary signal to be tested;

[0169] The digital signal processing component compares the data loss rate with a data loss rate threshold to obtain a comparison result, and processes the reference secondary signal according to the comparison result.

[0170] Based on the clock recovery element of the test module, the reference secondary signal is acquired, the clock signal is obtained according to the reference secondary signal, and then the clock signal is sent to the signal recovery module.

[0171] The input end of the digital signal processing element is connected to the output end of the first load effect isolation element and the second secondary winding of the reference signal transformer respectively;

[0172] The output end of the digital signal processing element is connected to the input end of the clock recovery element, and the output end of the clock recovery element is connected to the input end of the signal recovery module.

[0173] Step S62: Based on the signal recovery module, the secondary signal to be tested and the clock signal are acquired, and the secondary signal to be tested is recovered according to the clock signal to obtain a target secondary signal.

[0174] Specifically, based on the data comparison element of the signal recovery module, the clock signal and the secondary signal to be tested are acquired, and the clock signal and the digital signal to be tested are compared to obtain the data to be compensated.

[0175] After obtaining the target secondary signal, the signal recovery module performs analog-to-digital conversion on the target secondary signal based on its built-in ADC to obtain the target secondary signal, and sends the target secondary signal to the wireless network module.

[0176] An embodiment of the present application further provides an electronic device, characterized in that it includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above-mentioned method when executing the computer program.

[0177] An embodiment of the present application further provides a computer-readable storage medium, characterized in that the computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the method described above.

[0178] In addition, other structures and functions of the device in the embodiment of the present application are known to those skilled in the art and will not be described here to reduce redundancy.

[0179] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0180] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0181] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0182] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0183] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0184] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0185] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0186] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A signal processing circuit, characterized in that: include: A testing module, the testing module being configured to obtain a primary signal, and obtain a reference secondary signal and a secondary signal to be tested based on the primary signal, and then obtain a clock signal based on the reference secondary signal; a signal recovery module, the signal recovery module being connected to the test module, and being used to obtain the secondary signal to be tested and a clock signal, and recover the secondary signal to be tested according to the clock signal to obtain a target secondary signal; It also includes a processing chip, wherein the input end of the processing chip is connected to the test module, and the output end of the processing chip is connected to the signal recovery module; The processing chip is used to obtain the secondary signal to be tested and send the secondary signal to be tested to the signal recovery module; The test module includes a signal transformer to be tested, a first primary coil of the signal transformer to be tested is connected to the data interface, and a first secondary coil of the signal transformer to be tested is connected to the input end of the processing chip; The signal transformer to be tested is used to obtain the primary signal, obtain the secondary signal to be tested according to the primary signal, and then send the secondary signal to be tested to the input end of the processing chip.

2. The circuit according to claim 1, wherein: The test module includes an isolation module; The isolation module is connected to the signal transformer to be tested; The isolation module is used to obtain the primary signal and the secondary signal to be tested, and obtain the reference secondary signal according to the primary signal.

3. The circuit according to claim 2, characterized in that The isolation module includes a first load-effect isolation element; The input end of the first load effect isolation element is connected to the input end of the processing chip and the first secondary winding of the signal transformer to be tested respectively; The first load effect isolation element is used to obtain the secondary signal to be tested and process the signal to be tested.

4. The circuit according to claim 3, characterized in that The first load-effect isolation element includes a first operational amplifier, which is used to collect the secondary signal to be tested and amplify the secondary signal to be tested.

5. The circuit according to claim 2, characterized in that The isolation module further includes a second load effect isolation element; The input end of the second load effect isolation element is connected to the first primary coil of the signal transformer to be tested and the data interface respectively; The second load-effect isolation element is used to obtain the primary signal and obtain the reference secondary signal according to the primary signal.

6. The circuit according to claim 5, characterized in that The second load-effect isolation element includes a second operational amplifier, and the second operational amplifier is used to collect the primary signal and amplify the primary signal.

7. The circuit according to claim 5, characterized in that The output end of the second load effect isolation element is connected to the second primary coil of the reference signal transformer; The reference signal transformer is used to obtain the primary signal and obtain the reference secondary signal according to the primary signal.

8. The circuit according to claim 7, characterized in that The test module also includes a digital signal processing element; The input end of the digital signal processing element is connected to the second secondary winding of the reference signal transformer and the output end of the second load effect isolation element respectively; the output end of the digital signal processing element is connected to the signal recovery module; The digital signal processing component is configured to obtain the reference secondary signal sent by the second secondary coil of the reference signal transformer and the secondary signal to be tested sent by the output end of the second load effect isolation component, and compare the reference secondary signal and the secondary signal to be tested to obtain a data loss rate of the secondary signal to be tested; The digital signal processing component compares the data loss rate with a data loss rate threshold to obtain a comparison result, and processes the reference secondary signal according to the comparison result.

9. The circuit according to claim 8, characterized in that The test module further includes a clock recovery element disposed between the digital signal processing element and the signal recovery module; The input end of the clock recovery element is connected to the output end of the digital signal processing element; the output end of the clock recovery element is connected to the input end of the signal recovery module; The clock recovery element is used to obtain the reference secondary signal, obtain the clock signal according to the reference secondary signal, and then send the clock signal to the signal recovery module.

10. The circuit according to claim 9, characterized in that The signal recovery module is provided with a data comparison element, the input end of the data comparison element is respectively connected to the output end of the signal transformer to be tested and the clock recovery element; The data comparison element is used to obtain the clock signal and the secondary signal to be tested, and compare the clock signal and the digital signal to be tested to obtain the data to be compensated.

11. A signal processing method, characterized in that: As used in the circuit according to any one of claims 1 to 10, comprising: a connected test module and a signal recovery module; Based on the test module, a primary signal is acquired, and a reference secondary signal and a secondary signal to be tested are acquired according to the primary signal, and then a clock signal is acquired according to the reference secondary signal; Based on the signal recovery module, the secondary signal to be tested and the clock signal are acquired, and the secondary signal to be tested is recovered according to the clock signal to obtain a target secondary signal.

12. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor implements the method according to claim 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to claim 11.

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