A method, device, equipment and medium for synchronizing clock

Abstract

The present application discloses a method, device, equipment and medium for synchronizing clocks, and relates to the field of clock technology. The method is applied to a multi-processor architecture containing a master processor and a slave processor, and includes: receiving a clock synchronization signal according to a clock synchronization request and sending the signal to the slave processor; recording the first master timestamp of receiving the signal and the first slave timestamp of receiving the signal from the slave processor; sending a data packet containing the first master timestamp to the slave processor to facilitate parsing of the data packet containing the first master timestamp, and obtaining a second slave timestamp when the parsing is completed; determining the transmission delay according to the first slave timestamp and the second slave timestamp; compensating according to the transmission delay to complete clock synchronization. Introducing the second slave timestamp that has been parsed by the slave processor, which represents the lag of the slave processor, into the process of determining the transmission delay avoids inaccurate transmission delays and achieves the accuracy of the synchronized clock.

Description

Technical Field

[0001] The present application relates to the field of clock technology, and in particular to a method, device, equipment and medium for synchronizing clocks. Background Art

[0002] Currently, most VR / AR wearable devices use a multi-processor architecture. Figure 1 A schematic diagram of a multi-processor architecture provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, it can be understood that one master processor is connected to one or more slave processors, and peripheral devices (such as cameras or IMUs, etc.) are connected to the slave processors. In order for the master processor and the slave processor to receive data synchronously, it is necessary to synchronize the clocks of the master processor and the slave processor. The existing method of synchronizing the clocks is to send the timestamp of the master processor directly to the slave processor through the data bus (such as SPI or I2C). When the slave processor receives the timestamp sent by the master processor, the clock is synchronized based on the timestamp. However, since the clock sources used by the master processor and the slave processor are different, when the master processor sends the timestamp to the slave processor, even if the transmission time through the data bus can be ignored, the slave processor needs to parse the data sent by the master processor to obtain the timestamp. This process still takes a certain amount of time. After this process, the clock synchronized by the slave processor is a delayed timestamp, and the synchronized clock is still inaccurate at this time.

[0003] In view of the above problems, finding out how to accurately synchronize the clocks between the master processor and the slave processor is a problem that those skilled in the art are trying their best to solve. Summary of the invention

[0004] The purpose of the present application is to provide a method, apparatus, device and medium for synchronizing clocks, which are used to accurately synchronize the clocks between a master processor and a slave processor.

[0005] In order to solve the above technical problems, the present application provides a method for synchronizing clocks, which is applied to a multi-processor architecture including a master processor and a slave processor, comprising:

[0006] receiving a clock synchronization signal and sending the clock synchronization signal to a slave processor according to a clock synchronization request;

[0007] Recording a first master timestamp of receiving a clock synchronization signal and a first slave timestamp of receiving a clock synchronization signal from a processor;

[0008] Sending a data packet containing a first master timestamp to a slave processor so that the slave processor can parse the data packet containing the first master timestamp and obtain a second slave timestamp when the slave processor completes parsing;

[0009] Determine a transmission delay according to the first slave timestamp and the second slave timestamp;

[0010] Compensation is performed based on the transmission delay to facilitate clock synchronization between the master processor and the slave processor.

[0011] Preferably, after recording the first master timestamp of receiving the clock synchronization signal and the first slave timestamp of receiving the clock synchronization signal from the slave processor, and before sending the data packet containing the first master timestamp to the slave processor, the method further includes:

[0012] When the first preset time is reached, the second master timestamp is recorded and a data packet containing the second master timestamp is sent to the slave processor, so that the slave processor can parse the data packet containing the second master timestamp, and obtain the second slave timestamp when the slave processor completes the parsing, and determine the transmission delay based on the first slave timestamp, the second slave timestamp, and the first preset time.

[0013] Preferably, after compensating according to the transmission delay, the method further includes:

[0014] determining a calibration transmission delay based on the second master timestamp;

[0015] The transmission deviation is obtained according to the transmission delay and the calibrated transmission delay;

[0016] determining whether the transmission deviation exceeds a transmission deviation threshold;

[0017] If yes, return to the step of receiving the clock synchronization signal and sending the clock synchronization signal to the slave processor according to the clock synchronization request;

[0018] If not, the clock synchronization of the master processor and the slave processor is completed according to the transmission delay.

[0019] Preferably, determining the calibration transmission delay according to the second master timestamp comprises:

[0020] When the second preset time is reached, the third master timestamp is recorded and a data packet containing the third master timestamp is sent to the slave processor, so that the slave processor can parse the data packet containing the third master timestamp and obtain the third slave timestamp when the slave processor completes the parsing;

[0021] A calibrated transmission delay of the slave processor is determined based on the third master timestamp and the third slave timestamp.

[0022] Preferably, obtaining the transmission deviation according to the transmission delay and the calibrated transmission delay includes:

[0023] The transmission delay is subtracted from the calibrated transmission delay to obtain the transmission deviation.

[0024] Preferably, setting the transmission deviation threshold includes:

[0025] Select the coefficient of deviation;

[0026] The transmission delay is divided by the deviation coefficient to obtain the transmission deviation threshold.

[0027] Preferably, receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to a slave processor comprises:

[0028] Receives clock synchronization signals through GPIO and sends clock synchronization signals to slave processors.

[0029] In order to solve the above technical problems, the present application also provides a device for synchronizing clocks, including:

[0030] A first receiving and sending module, configured to receive a clock synchronization signal and send the clock synchronization signal to a slave processor according to a clock synchronization request;

[0031] A first recording module, used for recording a first master timestamp of receiving a clock synchronization signal and a first slave timestamp of receiving a clock synchronization signal from a processor;

[0032] A sending module, used for sending a data packet containing a first master timestamp to a slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain a second slave timestamp when the slave processor completes parsing;

[0033] A first determining module, configured to determine a transmission delay according to a first slave timestamp and a second slave timestamp;

[0034] The compensation module is used to compensate according to the transmission delay so as to facilitate the master processor and the slave processor to complete the clock synchronization.

[0035] In addition, the device also includes the following modules:

[0036] After recording the first master timestamp of the received clock synchronization signal and the first slave timestamp of the clock synchronization signal received by the slave processor, and before sending the data packet containing the first master timestamp to the slave processor, the method further includes:

[0037] The second recording module is used to record the second master timestamp and send a data packet containing the second master timestamp to the slave processor when the first preset time is reached, so that the slave processor can parse the data packet containing the second master timestamp and obtain the second slave timestamp when the slave processor completes the parsing, and determine the transmission delay based on the first slave timestamp, the second slave timestamp and the first preset time.

[0038] After compensating for the transmission delay, it also includes:

[0039] A second determination module, configured to determine a calibration transmission delay according to a second master timestamp;

[0040] An obtaining module, used for obtaining a transmission deviation according to a transmission delay and a calibration transmission delay;

[0041] A judgment module, used to judge whether the transmission deviation exceeds the transmission deviation threshold;

[0042] If yes, trigger the first receiving and sending module;

[0043] If not, the clock synchronization module is triggered to complete the clock synchronization of the master processor and the slave processor according to the transmission delay.

[0044] Determining the calibration transmission delay according to the second master timestamp includes:

[0045] A third recording module, used for recording a third master timestamp and sending a data packet containing the third master timestamp to the slave processor when a second preset time is reached, so that the slave processor can parse the data packet containing the third master timestamp and obtain the third slave timestamp when the slave processor completes the parsing;

[0046] The third determination module is used to determine the calibration transmission delay of the slave processor according to the third master timestamp and the third slave timestamp.

[0047] The transmission deviation obtained based on the transmission delay and the calibrated transmission delay includes:

[0048] The difference module is used to subtract the transmission delay from the calibration transmission delay to obtain the transmission deviation.

[0049] Setting the transmission deviation threshold includes:

[0050] A selection module is used to select a deviation coefficient;

[0051] The quotient module is used to calculate the quotient of the transmission delay and the deviation coefficient to obtain the transmission deviation threshold.

[0052] Receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to a slave processor comprises:

[0053] The second receiving and sending module is used to receive the clock synchronization signal through the GPIO and send the clock synchronization signal to the slave processor.

[0054] In order to solve the above technical problems, the present application also provides a device for synchronizing clocks, including:

[0055] Memory for storing computer programs;

[0056] The processor is used to direct the computer program to implement the steps of the method for synchronizing clocks.

[0057] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned method for synchronizing clocks are implemented.

[0058] A method for synchronizing clocks provided by the present application is applied to a multi-processor architecture containing a master processor and a slave processor, including: receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to the slave processor; recording the first master timestamp of receiving the clock synchronization signal and the first slave timestamp of receiving the clock synchronization signal from the slave processor; sending a data packet containing the first master timestamp to the slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain the second slave timestamp when the slave processor completes the parsing; determining the transmission delay according to the first slave timestamp and the second slave timestamp; compensating according to the transmission delay, so that the master processor and the slave processor can complete the clock synchronization. It can be seen from this that the time parsed by the slave processor is represented by the second slave timestamp, so that the second slave timestamp that lags behind the slave processor is introduced into the process of determining the transmission delay, avoiding the inaccurate transmission delay caused by the lagging second slave timestamp, thereby achieving the accuracy of the synchronized clock.

[0059] The present application also provides a device, equipment and medium for synchronizing a clock, with the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0061] Figure 1 A schematic diagram of a multi-processor architecture provided in an embodiment of the present application;

[0062] Figure 2 A flow chart of a first clock synchronization method provided in an embodiment of the present application;

[0063] Figure 3 A connection diagram of a master processor and a slave processor in a multi-processor architecture provided in an embodiment of the present application;

[0064] Figure 4 A flow chart of a second clock synchronization method provided in an embodiment of the present application;

[0065] Figure 5 A structural diagram of a clock synchronization device provided in an embodiment of the present application;

[0066] Figure 6A structural diagram of a device for synchronizing a clock provided in an embodiment of the present application;

[0067] Figure 7 A flow chart of a third method for synchronizing clocks provided in an embodiment of the present application.

[0068] Among them, 10 is a master processor and 11 is a slave processor. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0070] The core of the present application is to provide a method, apparatus, device and medium for synchronizing clocks, which can accurately synchronize the clocks between a master processor and a slave processor.

[0071] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0072] Figure 1 A schematic diagram of a multi-processor architecture provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the number of slave processors 11 can be 1 or more; similarly, the number of peripheral devices can also be 1 or more. In this application, there is no limitation on the number, model, etc. of slave processors and peripheral devices involved in the multi-processor architecture, and the implementation method can be determined according to the specific implementation scenario. However, it should be noted that in this multi-processor architecture, the number of main processors 10 can only be 1. It should be noted that the execution subject of the method for synchronizing clocks provided in the present application is the main processor.

[0073] Figure 2 This is a flow chart of the first method for synchronizing clocks provided in the embodiment of the present application. Figure 2 As shown, the method for synchronizing clocks is applied to a multi-processor architecture including a master processor and a slave processor, and includes:

[0074] S20: Receive a clock synchronization signal according to the clock synchronization request and send the clock synchronization signal to the slave processor.

[0075] Figure 3 This is a connection diagram of a master processor and a slave processor in a multi-processor architecture provided by an embodiment of the present application. Figure 3The following understanding is made: the main processor transmits the clock synchronization request to the clock synchronization module in the main processor, and the clock synchronization module generates a clock synchronization signal according to the clock synchronization request. It can be understood that the main processor can be regarded as a CPU. When the method is applicable to the CPU, the process of generating the clock synchronization signal can be performed at the application layer. Of course, the CPU is only one of many embodiments, and its implementation method can be determined according to the specific implementation scenario.

[0076] S21: Recording a first master timestamp of receiving a clock synchronization signal and a first slave timestamp of receiving the clock synchronization signal from a processor.

[0077] It should also be noted that when the method is applied to a CPU, the main processor receives the transmitted clock synchronization signal from the application layer, and the transmission process can be performed at the kernel layer.

[0078] The above process can be understood as follows: the main processor is provided with multiple interfaces, in this application, one of which is used to send a clock synchronization signal generated at the application layer according to a clock synchronization request, and send the clock synchronization signal to another interface used at the kernel layer and an interface of the slave processor that receives the clock synchronization signal. In addition, in this application, it is required to receive the clock synchronization signal through GPIO and send the clock synchronization signal to the slave processor.

[0079] S22: Send the data packet containing the first master timestamp to the slave processor.

[0080] This is so that the slave processor can parse the data packet containing the first master timestamp and obtain the second slave timestamp when the slave processor completes the parsing.

[0081] S23: Determine a transmission delay according to the first slave timestamp and the second slave timestamp.

[0082] S24: Compensation is performed according to the transmission delay so as to facilitate clock synchronization between the master processor and the slave processor.

[0083] Among them, the first master timestamp is recorded as Ta1, the first slave timestamp is recorded as Tm1, and the transmission delay is recorded as △T. At this time, the transmission delay can be calculated according to the formula △T=Tm2-Tm1. Further, the timing time Tm of the slave processor after compensation for the transmission delay is calculated by Tm=Ta1+△T.

[0084] A method for synchronizing clocks provided by the present application is applied to a multi-processor architecture containing a master processor and a slave processor, including: receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to the slave processor; recording the first master timestamp of receiving the clock synchronization signal and the first slave timestamp of receiving the clock synchronization signal from the slave processor; sending a data packet containing the first master timestamp to the slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain the second slave timestamp when the slave processor completes the parsing; determining the transmission delay according to the first slave timestamp and the second slave timestamp; compensating according to the transmission delay, so that the master processor and the slave processor can complete the clock synchronization. It can be seen from this that the time parsed by the slave processor is represented by the second slave timestamp, so that the second slave timestamp that lags behind the slave processor is introduced into the process of determining the transmission delay, avoiding the inaccurate transmission delay caused by the lagging second slave timestamp, thereby achieving the accuracy of the synchronized clock.

[0085] Figure 4 A flow chart of a second method for synchronizing clocks provided in an embodiment of the present application. Based on the above embodiment, as a more preferred embodiment, Figure 4 As shown, after recording the first master timestamp of the received clock synchronization signal and the first slave timestamp of the clock synchronization signal received by the slave processor, and before sending the data packet containing the first master timestamp to the slave processor, it also includes:

[0086] S40: When the first preset time is reached, record the second master timestamp and send a data packet containing the second master timestamp to the slave processor.

[0087] This is so that the slave processor can parse the data packet containing the second master timestamp, obtain the second slave timestamp when the slave processor completes the parsing, and determine the transmission delay according to the first slave timestamp, the second slave timestamp, and the first preset time.

[0088] Assuming that the interface of the master processor for receiving the clock synchronization signal does not receive the clock synchronization signal at the same time as the interface of the slave processor, the first master timestamp and the first slave timestamp will not be equal. At this time, there will generally be two situations: first, the first master timestamp is marked with the first slave timestamp first. At this time, the first slave timestamp used in the transmission delay is later than the receiving time, resulting in a smaller transmission delay, which is still inaccurate after compensation; second, the first master timestamp is marked later than the first slave timestamp. At this time, the first slave timestamp used in the transmission delay is earlier than the receiving time, resulting in a larger transmission delay, which is still inaccurate after compensation. In order to avoid the situation where the interface of the master processor for receiving the clock synchronization signal and the interface of the slave processor cannot receive the clock synchronization signal at the same time, a first preset time is set. After the first preset time, the master processor and the slave processor are marked with timestamps at the same time, which are the first master timestamp and the first slave timestamp respectively. At this time, the first master timestamp is the first slave timestamp. At the same time, it lays the foundation for the subsequent determination of accurate transmission delay. The second master timestamp is recorded as Ta2, the second slave timestamp is recorded as Tm2, ​​and the first preset time is recorded as t1. At this time, the transmission delay can be calculated according to the formula △T=Tm2-Tm1-t1. Furthermore, after compensation for the transmission delay, the timing time Tm of the slave processor is calculated by Tm=Ta2+△T.

[0089] Based on the above embodiments, as a more preferred embodiment, Figure 4 As shown, after compensation according to the transmission delay, it also includes:

[0090] S41: Determine and calibrate the transmission delay according to the second master timestamp.

[0091] Wherein, determining the calibration transmission delay according to the second master timestamp includes:

[0092] When the second preset time is reached, the third master timestamp is recorded and a data packet containing the third master timestamp is sent to the slave processor, so that the slave processor can parse the data packet containing the third master timestamp and obtain the third slave timestamp when the slave processor completes the parsing;

[0093] A calibrated transmission delay of the slave processor is determined based on the third master timestamp and the third slave timestamp.

[0094] S42: Obtaining a transmission deviation according to the transmission delay and the calibration transmission delay;

[0095] S43: Determine whether the transmission deviation exceeds the transmission deviation threshold;

[0096] If yes, the process returns to step S20: receiving a clock synchronization signal according to the clock synchronization request and sending the clock synchronization signal to the slave processor.

[0097] If not, proceed to step S44: complete the clock synchronization of the master processor and the slave processor according to the transmission delay.

[0098] In order to ensure that the transmission delay is always in an accurate state, it is necessary to mark the third timestamp again every second preset time to further obtain the transmission deviation. According to the relationship between the transmission deviation and the transmission deviation threshold, it is determined whether the clock synchronization of the master processor and the slave processor can be completed according to the transmission delay.

[0099] It should be noted that the second preset time is recorded as t2, the third main time stamp is recorded as Ta3, the third main time stamp is recorded as Tm3, the calibration transmission delay is recorded as △T', the transmission deviation is recorded as Tp, and the transmission deviation threshold is recorded as Tthreshold. The transmission delay is subtracted from the calibration transmission delay to obtain the transmission deviation, which can be expressed as: Tp = △T-△T'. At the same time, by selecting the deviation coefficient k; the transmission delay is divided by the deviation coefficient to obtain the transmission deviation threshold, which can be expressed as: Tthreshold = △T / k. The deviation coefficient is a natural number, and its specific value is not limited.

[0100] In the above embodiments, the method for synchronizing clocks is described in detail, and the present application also provides embodiments corresponding to the apparatus for synchronizing clocks. It should be noted that the present application describes the embodiments of the apparatus part from two perspectives, one is based on the perspective of functional modules, and the other is based on the perspective of hardware.

[0101] Figure 5 This is a structural diagram of a device for synchronizing a clock provided in an embodiment of the present application. Figure 5 As shown, the present application also provides a device for synchronizing a clock, including:

[0102] A first receiving and sending module 50, configured to receive a clock synchronization signal and send the clock synchronization signal to a slave processor according to a clock synchronization request;

[0103] A first recording module 51, used for recording a first master timestamp of receiving a clock synchronization signal and a first slave timestamp of receiving a clock synchronization signal from a processor;

[0104] The sending module 52 is used to send the data packet containing the first master timestamp to the slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain the second slave timestamp when the slave processor completes the parsing;

[0105] A first determining module 53, configured to determine a transmission delay according to a first slave timestamp and a second slave timestamp;

[0106] The compensation module 55 is used to compensate according to the transmission delay so as to facilitate the master processor and the slave processor to complete clock synchronization.

[0107] In addition, the device also includes the following modules:

[0108] After recording the first master timestamp of the received clock synchronization signal and the first slave timestamp of the clock synchronization signal received by the slave processor, and before sending the data packet containing the first master timestamp to the slave processor, the method further includes:

[0109] The second recording module is used to record the second master timestamp and send a data packet containing the second master timestamp to the slave processor when the first preset time is reached, so that the slave processor can parse the data packet containing the second master timestamp and obtain the second slave timestamp when the slave processor completes the parsing, and determine the transmission delay based on the first slave timestamp, the second slave timestamp and the first preset time.

[0110] After compensating for the transmission delay, it also includes:

[0111] A second determination module, configured to determine a calibration transmission delay according to a second master timestamp;

[0112] An obtaining module, used for obtaining a transmission deviation according to a transmission delay and a calibration transmission delay;

[0113] A judgment module, used to judge whether the transmission deviation exceeds the transmission deviation threshold;

[0114] If yes, trigger the first receiving and sending module;

[0115] If not, the clock synchronization module is triggered to complete the clock synchronization of the master processor and the slave processor according to the transmission delay.

[0116] Determining the calibration transmission delay according to the second master timestamp includes:

[0117] A third recording module, used for recording a third master timestamp and sending a data packet containing the third master timestamp to the slave processor when a second preset time is reached, so that the slave processor can parse the data packet containing the third master timestamp and obtain the third slave timestamp when the slave processor completes the parsing;

[0118] The third determination module is used to determine the calibration transmission delay of the slave processor according to the third master timestamp and the third slave timestamp.

[0119] The transmission deviation obtained based on the transmission delay and the calibrated transmission delay includes:

[0120] The difference module is used to subtract the transmission delay from the calibration transmission delay to obtain the transmission deviation.

[0121] Setting the transmission deviation threshold includes:

[0122] A selection module is used to select a deviation coefficient;

[0123] The quotient module is used to calculate the quotient of the transmission delay and the deviation coefficient to obtain the transmission deviation threshold.

[0124] Receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to a slave processor comprises:

[0125] The second receiving and sending module is used to receive the clock synchronization signal through the GPIO and send the clock synchronization signal to the slave processor.

[0126] A method for synchronizing clocks provided by the present application is applied to a multi-processor architecture containing a master processor and a slave processor, including: receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to the slave processor; recording the first master timestamp of receiving the clock synchronization signal and the first slave timestamp of receiving the clock synchronization signal from the slave processor; sending a data packet containing the first master timestamp to the slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain the second slave timestamp when the slave processor completes the parsing; determining the transmission delay according to the first slave timestamp and the second slave timestamp; compensating according to the transmission delay, so that the master processor and the slave processor can complete the clock synchronization. It can be seen from this that the time parsed by the slave processor is represented by the second slave timestamp, so that the second slave timestamp that lags behind the slave processor is introduced into the process of determining the transmission delay, avoiding the inaccurate transmission delay caused by the lagging second slave timestamp, thereby achieving the accuracy of the synchronized clock.

[0127] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0128] Figure 6 A device structure diagram of a synchronous clock provided in an embodiment of the present application, such as Figure 6 As shown, the devices for synchronizing clocks include:

[0129] A memory 60, for storing computer programs;

[0130] The processor 61 is configured to implement the steps of the clock synchronization method mentioned in the above embodiment when executing a computer program.

[0131] The clock synchronization device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0132] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0133] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor 61, the relevant steps of the method for synchronizing the clock disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 60 may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, a method for synchronizing the clock, etc.

[0134] In some embodiments, the clock synchronization device may further include a display screen, an input and output interface, a communication interface, a power supply, and a communication bus.

[0135] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation on the device for synchronizing clocks, and may include more or less components than those shown in the figure.

[0136] The clock synchronization device provided in the embodiment of the present application includes a memory 60 and a processor 61. When the processor 61 executes the program stored in the memory 60, the method for synchronizing the clock can be implemented.

[0137] In addition, the present application also provides a practical application of a step clock method. Figure 7 A flow chart of a third method for synchronizing clocks provided in an embodiment of the present application is shown in FIG. Figure 7 The operation in the whole process can be clearly understood from the figure, which can be further understood in combination with the above-mentioned embodiment in which the execution subject is the main processor and the execution subject is the slave processor, and will not be repeated here.

[0138] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, the steps recorded in the above method embodiment (which may be a method corresponding to a master processor, a method corresponding to a slave processor, or a method corresponding to both a master processor and a slave processor) are implemented.

[0139] When the executor of the clock synchronization method is a slave processor, it receives a clock synchronization signal and records the first slave timestamp corresponding to it, and at the same time obtains and records the first master timestamp of the main processor receiving the clock synchronization signal; receives and parses the data packet containing the first master timestamp, and obtains the second slave timestamp after the parsing is completed; and transmits the transmission delay determined according to the first slave timestamp and the second slave timestamp to the main processor, so that the main processor can compensate according to the transmission delay and complete clock synchronization.

[0140] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory), ROM, random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program code.

[0141] The above is a detailed introduction to a method, device, equipment and medium for synchronizing a clock provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0142] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A method for synchronizing a clock, characterized in that: Applications include: receiving a clock synchronization signal and sending the clock synchronization signal to a slave processor according to a clock synchronization request; Recording a first master timestamp of receiving the clock synchronization signal and a first slave timestamp of receiving the clock synchronization signal by the slave processor; Sending the data packet containing the first master timestamp to the slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain a second slave timestamp when the slave processor completes parsing; Determine a transmission delay according to the first slave timestamp and the second slave timestamp; Compensating according to the transmission delay so as to facilitate clock synchronization between the master processor and the slave processor; After recording the first master timestamp of receiving the clock synchronization signal and the first slave timestamp of receiving the clock synchronization signal by the slave processor, and before sending the data packet containing the first master timestamp to the slave processor, the method further includes: When the first preset time is reached, a second master timestamp is recorded and a data packet containing the second master timestamp is sent to the slave processor, so that the slave processor parses the data packet containing the second master timestamp, and obtains the second slave timestamp when the slave processor completes the parsing, and determines the transmission delay according to the first slave timestamp, the second slave timestamp, and the first preset time; After compensating according to the transmission delay, the method further includes: determining a calibration transmission delay according to the second master timestamp; Obtaining a transmission deviation according to the transmission delay and the calibrated transmission delay; Determining whether the transmission deviation exceeds a transmission deviation threshold; If yes, return to the step of receiving the clock synchronization signal according to the clock synchronization request and sending the clock synchronization signal to the slave processor; If not, the clock synchronization of the master processor and the slave processor is completed according to the transmission delay.

2. The method for synchronizing clocks according to claim 1, characterized in that: Determining the calibration transmission delay according to the second master timestamp includes: When the second preset time is reached, a third master timestamp is recorded and a data packet containing the third master timestamp is sent to the slave processor, so that the slave processor can parse the data packet containing the third master timestamp and obtain the third slave timestamp when the slave processor completes the parsing; A calibrated transmission delay of the slave processor is determined based on the third master timestamp and the third slave timestamp.

3. The method for synchronizing clocks according to claim 1, characterized in that: The obtaining of the transmission deviation according to the transmission delay and the calibrated transmission delay comprises: The transmission deviation is obtained by subtracting the transmission delay from the calibrated transmission delay.

4. The method for synchronizing clocks according to claim 1, characterized in that: Setting the transmission deviation threshold includes: Select the coefficient of deviation; The transmission delay is divided by the deviation coefficient to obtain the transmission deviation threshold.

5. The method for synchronizing clocks according to claim 1, characterized in that: The receiving a clock synchronization signal according to a clock synchronization request and sending the clock synchronization signal to the slave processor comprises: The clock synchronization signal is received through GPIO and sent to the slave processor.

6. A device for synchronizing a clock, characterized in that: include: A first receiving and sending module, configured to receive a clock synchronization signal and send the clock synchronization signal to a slave processor according to a clock synchronization request; A first recording module, used for recording a first master timestamp of receiving the clock synchronization signal and a first slave timestamp of receiving the clock synchronization signal by the slave processor; a sending module, configured to send the data packet containing the first master timestamp to the slave processor, so that the slave processor can parse the data packet containing the first master timestamp and obtain a second slave timestamp when the slave processor completes parsing; A first determining module, configured to determine a transmission delay according to the first slave timestamp and the second slave timestamp; A compensation module, used for compensating according to the transmission delay so as to facilitate clock synchronization between the master processor and the slave processor; In addition, the device also includes the following modules: After recording the first master timestamp of the received clock synchronization signal and the first slave timestamp of the clock synchronization signal received by the slave processor, and before sending the data packet containing the first master timestamp to the slave processor, the method further includes: A second recording module is used to record a second master timestamp and send a data packet containing the second master timestamp to a slave processor when the first preset time is reached, so that the slave processor can parse the data packet containing the second master timestamp, obtain the second slave timestamp when the slave processor completes the parsing, and determine the transmission delay according to the first slave timestamp, the second slave timestamp, and the first preset time; After compensating for the transmission delay, it also includes: A second determination module, configured to determine a calibration transmission delay according to a second master timestamp; An obtaining module, used for obtaining a transmission deviation according to a transmission delay and a calibration transmission delay; A judgment module, used to judge whether the transmission deviation exceeds the transmission deviation threshold; If yes, trigger the first receiving and sending module; If not, the clock synchronization module is triggered to complete the clock synchronization of the master processor and the slave processor according to the transmission delay.

7. A device for synchronizing a clock, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the method for synchronizing clocks as described in any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for synchronizing clocks as described in any one of claims 1 to 5 are implemented.

Images