Package including a substrate having interconnect routing lines over a solder mask layer

Abstract

A package includes a substrate and an integrated device coupled to the substrate. The substrate includes: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects include pads located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located above the at least one dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein at least one routing interconnect is located above the outer dielectric layer, wherein at least one routing interconnect is located below the bottom metal layer of the substrate; and (v) a cover dielectric layer located above the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pads located on the bottom metal layer of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. non-provisional application No. 16 / 840,752, filed on April 6, 2020, entitled “PACKAGE COMPRISING ASUBSTRATE WITH INTERCONNECT ROUTING OVER SOLDER RESIST LAYER,” which application has been assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] Various features are directed to packages including integrated devices, but more particularly to packages including integrated devices, substrates, and interconnects over solder resist layers. Background Art

[0004] Figure 1 A package 100 is shown, which includes a substrate 102, an integrated device 104, and an encapsulation layer 108. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. The encapsulation layer 108 encapsulates the integrated device 104 and the plurality of solder interconnects 144. It may be challenging to manufacture a small package including a substrate with a high density of interconnects. There has always been a need to provide a more compact package that can accommodate high density interconnects and / or high pin counts. Summary of the invention

[0005] Various features are directed to packages including integrated devices, but more particularly to packages including integrated devices, substrates, and interconnects over solder resist layers.

[0006] One example provides a package that includes a substrate and an integrated device coupled to the substrate. The substrate includes: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects include pads located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located above the at least one inner dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein at least one routing interconnect is located above the outer dielectric layer, wherein at least one routing interconnect is located above the bottom metal layer of the substrate; and (v) a cover dielectric layer located above the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pads located on the bottom metal layer of the substrate.

[0007] Another example provides a package including a substrate and an integrated device coupled to the substrate. The substrate includes: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects include pads located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located above the at least one inner dielectric layer; (iv) a component for routing interconnects coupled to the plurality of interconnects, wherein the component for routing interconnects is located above the outer dielectric layer, wherein the component for routing interconnects is located above the bottom metal layer of the substrate; and (v) a cover dielectric layer located above the outer dielectric layer and the component for routing interconnects. The package includes a solder interconnect coupled to the pads located on the bottom metal layer of the substrate.

[0008] Yet another example provides a method for manufacturing a package. The method provides a substrate. The substrate includes: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects include pads located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located above the at least one inner dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein at least one routing interconnect is located above the outer dielectric layer, wherein at least one routing interconnect is located above the bottom metal layer of the substrate; and (v) a capping dielectric layer located above the outer dielectric layer and the at least one routing interconnect. The method couples an integrated device to the substrate. The method couples a solder interconnect to a pad located on the bottom metal layer of the substrate.

[0009] Yet another example provides a package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises: (i) at least one inner dielectric layer; (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects comprise pads located on a bottom metal layer of the substrate; (iii) an outer dielectric layer located above the at least one inner dielectric layer; (iv) a cover dielectric layer located above the at least one inner dielectric layer; (v) at least one routing interconnect coupled to the plurality of interconnects, wherein at least one routing interconnect is located above the cover dielectric layer, wherein at least one routing interconnect is located above the bottom metal layer of the substrate; and (vi) a second outer dielectric layer located above the cover dielectric layer and the at least one routing interconnect. The package comprises a solder interconnect coupled to the pads located on the bottom metal layer of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various features, properties and advantages will become apparent from the detailed description set forth below when considered in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0011] Figure 1 A cross-sectional view of a package including an integrated device and a substrate is shown.

[0012] Figure 2 A cross-sectional view of a package including a substrate with interconnects over a solder mask layer is shown.

[0013] Figure 3 A bottom plan view of a package including a substrate with interconnects over a solder mask layer is shown.

[0014] Figure 4 A cross-sectional view of a package including a substrate with interconnects over an outer dielectric layer is shown.

[0015] Figure 5 (including Figure 5A-5F ) shows an exemplary sequence for manufacturing a substrate including interconnects located above a solder mask layer.

[0016] Figure 6 (including Figure 6A-6B ) shows an exemplary sequence for fabricating a substrate including interconnects located above an outer dielectric layer.

[0017] Figure 7 An exemplary flow chart of a method for manufacturing a substrate including an interconnect over a solder mask layer is shown.

[0018] Figure 8 (including Figure 8A-B ) illustrates an exemplary sequence for manufacturing a package including a substrate having interconnects located above a solder mask layer.

[0019] Fig. 9 An exemplary flow chart of a method for manufacturing a substrate package including an interconnect over a solder mask layer is shown.

[0020] Fig.10 A package-on-package (PoP) is shown including a package including a substrate with interconnects over a solder mask layer.

[0021] Figure 11 (including Figure 11A-11C ) illustrates an exemplary sequence for manufacturing a package-on-package (PoP) comprising a package including a substrate having interconnects located above a solder mask layer.

[0022] Fig.12 Various electronic devices are shown that may integrate the dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0023] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, those of ordinary skill in the art will appreciate that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring various aspects due to unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring various aspects of the present disclosure.

[0024] The present disclosure describes a package that includes a substrate and an integrated device coupled to the substrate. The substrate includes: (i) at least one internal dielectric layer; (ii) a plurality of interconnects located at least in the at least one internal dielectric layer, wherein the plurality of interconnects include pads located on a bottom metal layer of the substrate; (iii) an external dielectric layer located above the at least one internal dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein at least one routing interconnect is located above the external dielectric layer, wherein at least one routing interconnect is located above the bottom metal layer of the substrate; and (v) a cover dielectric layer located above the external dielectric layer and at least one routing interconnect, the cover dielectric layer can be coupled to the external dielectric layer. The package includes a solder interconnect coupled to a pad located on the bottom metal layer of the substrate. The external dielectric layer can include a solder mask or a photoimageable dielectric (PID). The cover dielectric layer can include a solder mask or a photoimageable dielectric (PID). At least one routing interconnect can be located (e.g., laterally located) between a plurality of solder interconnects. The integrated device and the substrate are coupled together in such a manner that a first electrical signal to and / or from the integrated device can be configured to travel through a plurality of interconnects and at least one routing interconnect located on the outer dielectric layer substrate. Such a configuration in which at least one routing interconnect is located on the outer dielectric layer and between the solder interconnects can allow the space (e.g., lateral space) between the solder interconnects of the substrate to be used for routing lines to provide more routing line footprint without increasing the overall size and form of the substrate and / or package.

[0025] Exemplary package including a substrate having interconnects located on an outer dielectric layer

[0026] Figure 2 A cross-sectional view of a package 200 including interconnects located on an outer dielectric layer is shown. The package 200 is coupled to a board 290 (e.g., a printed circuit board (PCB)) through a plurality of solder interconnects 280. The package 200 provides a package having a compact small form factor while also having an improved routing interconnect design.

[0027] like Figure 2As shown, the package 200 includes a substrate 202 , a first integrated device 205 , a second integrated device 206 , an encapsulation layer 208 , and a plurality of solder interconnects 280 .

[0028] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one inner dielectric layer 220, a plurality of interconnects 222, a solder mask layer 224, an outer dielectric layer 230, a cover dielectric layer 240, and at least one routing interconnect 242. The plurality of interconnects 222 are at least located in and above the at least one inner dielectric layer 220. The plurality of interconnects 222 include at least one pad 222a located on the bottom metal layer of the substrate 202. The pad 222a is configured to be coupled to a solder interconnect in the plurality of solder interconnects 280. The outer dielectric layer 230 is located above the at least one dielectric layer 220. At least one routing interconnect 242 is coupled to the plurality of interconnects 222. At least one routing interconnect 242 is located above the outer dielectric layer 230. At least one routing interconnect 242 is located above (or below, depending on how top and bottom are arbitrarily defined) the bottom metal layer of the substrate 202. At least one routing interconnect 242 may be located between the plate 290 and the bottom metal layer of the substrate 202. The cover dielectric layer 240 is located above the outer dielectric layer 230 and the at least one routing interconnect 242. The at least one routing interconnect 242 may be a component for a routing interconnect. The cover dielectric layer 240 may be coupled to the outer dielectric layer 230.

[0029] As used in this disclosure, when a particular dielectric layer is "above" another dielectric layer, the particular dielectric layer may be above or below the other dielectric layer, depending on how bottom (e.g., bottom layer) or top (e.g., top layer) is arbitrarily defined. A particular dielectric layer being "above" (whether above or below) another dielectric layer may mean that the particular dielectric layer is coupled to a surface of the other dielectric layer. For example, a surface of the particular dielectric layer may be in contact with (e.g., touching) another surface of the other dielectric layer.

[0030] The outer dielectric layer 230 may be coupled to and located above (e.g., below) a bottom surface of at least one inner dielectric layer 220. The at least one routing interconnect 242 and the cover dielectric layer 240 may be coupled to and located above (e.g., below) a bottom surface of the outer dielectric layer 230. The at least one routing interconnect 242 may be laterally located between the plurality of solder interconnects 280. The at least one routing interconnect 242 may not be in direct contact with the plurality of solder interconnects 280. The at least one routing interconnect 242 may be coupled to the plurality of interconnects 222. The outer dielectric layer 230, the cover dielectric layer 240, and the at least one routing interconnect 242 may be part of the substrate 202.

[0031] The bottom metal layer of the substrate 202 may be a metal layer of the substrate 202 that includes an interconnect (such as a pad) configured to be coupled to a solder interconnect. The bottom metal layer of the substrate 202 is not necessarily the lowest metal layer of the substrate 202 or the metal layer of the substrate 202 that is closest to the board (when the substrate 202 is coupled to the board). Figure 2 In an example of the present disclosure, the bottom metal layer of the substrate 202 can be a metal layer that includes an interconnect (such as pad 222a) that is coupled (e.g., directly coupled) to the plurality of solder interconnects 280. The plurality of solder interconnects 280 are also coupled to a board 290 (e.g., a printed circuit board). The bottom metal layer of the substrate 202 can be a metal layer that is closest (e.g., vertically closest) to the plurality of solder interconnects 280 but not laterally positioned (e.g., along the X-axis and / or Y-axis) along the same plane as the plurality of solder interconnects 280. For purposes of the present disclosure, the bottom metal layer of the substrate can be defined as not including the metal layer(s) that are located to the side of the plurality of solder interconnects 280.

[0032] like Figure 2 As shown, a plurality of solder interconnects 280 are coupled to the substrate 202 (eg, coupled to a bottom metal layer of the substrate 202 ) such that at least one routing interconnect 242 is located to the side of and / or between the plurality of solder interconnects 280 .

[0033] The use of at least one routing interconnect 242 helps save space and helps reduce the overall height and footprint of the package 200, thereby utilizing space that would not otherwise be used. In addition, the use of at least one routing interconnect 242 can help reduce routing line congestion (e.g., local routing line congestion) in the substrate 202. Such a configuration in which at least one routing interconnect 242 is located between solder interconnects 280 (but may not be in direct contact with the solder interconnects) uses space that would not otherwise be used. In particular, such a configuration can allow space (e.g., lateral space) between solder interconnects 280 of the substrate 202 to be used for routing lines to provide more routing line space without increasing the overall size and form of the substrate and / or package.

[0034] Note that at least one routing interconnect 242 may also be formed over another surface (e.g., a top surface) of substrate 202. In this case, another capping dielectric layer and / or an outer dielectric may be formed over the second surface of substrate 202. Thus, in some embodiments, at least one routing interconnect, capping dielectric layer, and / or outer dielectric layer may be formed over the bottom surface and / or the top surface of substrate 202.

[0035] The outer dielectric layer 230 may include a different material than the at least one inner dielectric layer 220. The cover dielectric layer 240 may include a different material than the at least one inner dielectric layer 220. The cover dielectric layer 240 may include a different material than the at least one inner dielectric layer 220 and the outer dielectric layer 230. The cover dielectric layer 240 and the outer dielectric layer 230 may each include a different material than the at least one inner dielectric layer 220. The cover dielectric layer 240 and the outer dielectric layer 230 may include the same material.

[0036] At least one inner dielectric layer 220 may include a copper clad laminate (CCL) core, prepreg, ajinomoto build up film (ABF) and / or resin coated copper (RCC). The outer dielectric layer 230 may include a solder mask layer and / or a photoimageable dielectric (PID). The cover dielectric layer 240 may include a solder mask layer and / or a photoimageable dielectric (PID).

[0037] The first integrated device 205 is coupled to a first surface (e.g., top surface) of the substrate 202 via a plurality of interconnects 250. The plurality of interconnects 250 may include copper pillars and / or solder interconnects. The second integrated device 206 is coupled to the first surface of the substrate 202 via a plurality of interconnects 260. The plurality of interconnects 260 may include copper pillars and / or solder interconnects. The encapsulation layer 208 is located above and coupled to the first surface of the substrate 202, and may encapsulate the first integrated device 205 and the second integrated device 206. The encapsulation layer 208 may include a mold material, a resin, an epoxy resin, and / or a polymer. The encapsulation layer 208 may be a component for encapsulation.

[0038] The integrated device (e.g., 205, 206) may include a die (e.g., a bare semiconductor die). The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a GaAs-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon carbide (SiC)-based integrated device, a memory, and / or a combination thereof.

[0039] Different implementations may couple different components to substrate 202. Other components (eg, surface mounted components) that may be coupled to substrate 202 include passive devices (eg, capacitors).

[0040] Some electrical signals (e.g., first electrical signals, second electrical signals) to and from the integrated devices (e.g., 205, 206) may travel through the plurality of interconnects 222 and the at least one routing interconnect 242. For example, some signals to and / or from the integrated devices may travel through the first plurality of interconnects in the plurality of interconnects 222, the at least one routing interconnect 242, and the second plurality of interconnects in the plurality of interconnects 222. The at least one routing interconnect 242 may allow the package 200 to provide a higher I / O pin count without having to increase the size of the package 200. For example, the use of the at least one routing interconnect 242 may allow the substrate 202 to have a smaller number of metal layers, which may help reduce the overall height of the package 200. The at least one routing interconnect 242 may help reduce congestion and / or entanglement in certain areas of the substrate 202 (e.g., areas near the integrated devices) due to a higher number of pin counts and / or netlists. A netlist is an arrangement of components of a circuit and how the components are electrically coupled together.

[0041] Different embodiments may include substrates having different numbers of metal layers. In addition, different embodiments may include substrates having different shapes and / or sizes. Substrate 202 may include a core layer. Substrate 202 may be a coreless substrate. Substrate 202 may be manufactured using different manufacturing processes, including a semi-additive process (SAP) and a modified semi-additive process (mSAP). Multiple interconnects 222 and at least one routing interconnect 242 may have different shapes and / or sizes. In some embodiments, multiple interconnects 222 may include redistribution interconnects. In some embodiments, at least one routing interconnect 242 may include at least one routing redistribution interconnect. The redistribution interconnect may be manufactured using a redistribution layer (RDL) manufacturing process. An example of a method for manufacturing a substrate is described below at Figure 5A-5F and Figure 6A-6B Shown and described in.

[0042] Figure 3 An exemplary bottom plan view of package 200 is shown. Figure 3As shown, a plurality of solder interconnects 280 are coupled to the substrate 202. The substrate 202 includes an outer dielectric layer 230, at least one routing interconnect 242, and a cover dielectric layer 240. The at least one routing interconnect 242 is located above the outer dielectric layer 230. The cover dielectric layer 240 is located above the at least one routing interconnect 242 and the outer dielectric layer 230. The at least one routing interconnect 242 is located (e.g., laterally located) between the plurality of solder interconnects 280. The at least one routing interconnect 242 (which may include at least one routing pad, at least one routing trace, and / or at least one routing via) may run in and / or along a surface of the outer dielectric layer 230. The at least one routing interconnect 242 may be located (e.g., laterally located) between the plurality of solder interconnects 280.

[0043] Figure 4A package 400 including a substrate 402 is shown. Package 400 is similar to package 200 and therefore includes components similar to package 200. Substrate 402 is similar to substrate 202 and therefore includes components similar to substrate 202. Substrate 402 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). Substrate 402 includes at least one inner dielectric layer 220, a plurality of interconnects 222, a solder resist layer 224, an outer dielectric layer 230, an outer dielectric layer 430, a cover dielectric layer 240, and at least one routing interconnect 242. The plurality of interconnects 222 are at least located in and above the at least one inner dielectric layer 220. The plurality of interconnects 222 include at least one pad 222a located on the bottom metal layer of substrate 402. The pad 222a is configured to be coupled to a solder interconnect in a plurality of solder interconnects 280. At least one routing interconnect 242 is coupled to the plurality of interconnects 222. At least one routing interconnect 242 is located above the cover dielectric layer 240. At least one routing interconnect 242 is located above (or below, depending on how top and bottom are arbitrarily defined) the bottom metal layer of the substrate 402. The outer dielectric layer 230 can be located above the at least one inner dielectric layer 220. The outer dielectric layer 230 can be located laterally of the cover dielectric layer 240. The outer dielectric layer 430 is located above the cover dielectric layer 240 and the at least one routing interconnect 242. The outer dielectric layer 430 can be a second outer dielectric layer. The outer dielectric layer 430 can be considered to be part of the outer dielectric layer 230, and vice versa. Therefore, in some embodiments, the outer dielectric layer (which can include the outer dielectric layer 230 and the outer dielectric layer 430) can be located above (e.g., below) at least one inner dielectric layer 220, the cover dielectric layer 240, and the at least one routing interconnect 242. The cover dielectric laser 240 can be located between the at least one inner dielectric layer 220 and the outer dielectric layer 430. The cover dielectric laser 240 may be coupled to at least one inner dielectric layer 220 and an outer dielectric layer 430 .

[0044] As used in this disclosure, when a particular dielectric layer is "above" another dielectric layer, the particular dielectric layer may be above or below the other dielectric layer, depending on how bottom (e.g., bottom layer) or top (e.g., top layer) is arbitrarily defined. A particular dielectric layer being "above" (whether above or below) another dielectric layer may mean that the particular dielectric layer is coupled to a surface of the other dielectric layer. For example, a surface of the particular dielectric layer may be in contact with (e.g., touching) another surface of the other dielectric layer.

[0045] The outer dielectric layer 230 may be coupled to and located above (e.g., below) the bottom surface of at least one inner dielectric layer 220. The cover dielectric layer 240 may be coupled to and located above (e.g., below) the bottom surface of at least one inner dielectric layer 220. The cover dielectric layer 240 may be coplanar with the outer dielectric layer 230. At least one routing interconnect 242 may be coupled to and located above (e.g., below) the bottom surface of the cover dielectric layer 240. The outer dielectric layer 430 may be located above (e.g., below) the bottom surface of the cover dielectric layer 240 and the at least one routing interconnect 242. The at least one routing interconnect 242 may be located laterally between the plurality of solder interconnects 280. The at least one routing interconnect 242 may not be in direct contact with the plurality of solder interconnects 280. The at least one routing interconnect 242 may be coupled to the plurality of interconnects 222. The outer dielectric layer 230, the outer dielectric layer 430, the cover dielectric layer 240, and the at least one routing interconnect 242 may be part of the substrate 402.

[0046] Note that at least one routing interconnect 242 may also be formed over the first surface (e.g., top surface) of substrate 402. In this case, another cover dielectric layer and / or an outer dielectric layer may be formed over the first surface of substrate 402. Thus, in some embodiments, at least one routing interconnect, a cover dielectric layer, and / or an outer dielectric layer may be formed over the bottom surface and / or top surface of substrate 402.

[0047] The outer dielectric layer (e.g., 230, 430) may include a different material than the at least one inner dielectric layer 220. The cover dielectric layer 240 may include a different material than the at least one inner dielectric layer 220. The cover dielectric layer 240 may include a different material than the at least one inner dielectric layer 220 and the outer dielectric layer (e.g., 230, 430). The cover dielectric layer 240 and the outer dielectric layer (e.g., 230, 430) may each include a different material than the at least one inner dielectric layer 220. The cover dielectric layer 240 and the outer dielectric layer (e.g., 230, 430) may include the same material.

[0048] Having described various packages having routing interconnects, a process for fabricating a substrate having routing interconnects will now be described below.

[0049] Exemplary sequence for fabricating a substrate including routing interconnects

[0050] In some embodiments, manufacturing the substrate includes several processes. Figure 5A-5F ) shows an exemplary sequence for providing or manufacturing a substrate. In some embodiments, Figure 5A-5F The sequence can be used to provide or make Figure 2 substrate 202. However, Figure 5A-5F The process can be used to manufacture any substrate described in this disclosure.

[0051] It should be noted that Figure 5A-5F The sequence of one or more stages can be combined to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some embodiments, the order of the process can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure.

[0052] like Figure 5A As shown, stage 1 shows a state after providing a carrier 500 and forming a metal layer over the carrier 500. The metal layer may be patterned to form an interconnection 502. A plating process and an etching process may be used to form the metal layer and the interconnection.

[0053] Stage 2 shows the state after a dielectric layer 520 is formed over the carrier 500 and the interconnect 502. The dielectric layer 520 may include polyimide. However, different embodiments may use different materials for the dielectric layer. The dielectric layer 520 may be an inner dielectric layer.

[0054] Stage 3 shows a state after at least one cavity 510 is formed in the dielectric layer 520. The at least one cavity 510 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0055] Stage 4 shows the state after interconnect 512 is formed in and on dielectric layer 520. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnect. Interconnect 512 may be part of multiple interconnects 222.

[0056] Stage 5 shows the state after another dielectric layer 522 is formed on top of dielectric layer 520. Dielectric layer 522 may be the same material as dielectric layer 520. However, different embodiments may use different materials for the dielectric layer. Dielectric layer 522 may be an inner dielectric layer.

[0057] like Figure 5B As shown, stage 6 shows a state after at least one cavity 530 is formed in the dielectric layer 522. An etching process or a laser process may be used to form the at least one cavity 530.

[0058] Stage 7 shows a state after interconnect 514 is formed in and on dielectric layer 522. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnect. Interconnect 514 may be a portion of multiple interconnects 222.

[0059] Stage 8 shows the state after forming another dielectric layer 524 on top of dielectric layer 522. Dielectric layer 524 may be the same material as dielectric layer 520. However, different embodiments may use different materials for the dielectric layer. Dielectric layer 524 may be an inner dielectric layer.

[0060] Stage 9 shows a state after at least one cavity 540 is formed in the dielectric layer 524. An etching process or a laser process may be used to form the at least one cavity 540.

[0061] like Figure 5C As shown, stage 10 shows the state after interconnects 516 are formed in and on dielectric layer 524. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0062] Some or all of the interconnects 502, 512, 514, and / or 516 may define a plurality of interconnects 222 of the substrate 202. The dielectric layers 520, 522, 524 may be represented by at least one inner dielectric layer 220.

[0063] Stage 11 shows the state after the carrier 500 is decoupled (eg, removed, polished) from the at least one inner dielectric layer 220 to leave the substrate 202 .

[0064] Stage 12 shows a state after forming a solder resist layer 224 and an outer dielectric layer 230 on the substrate 202. A deposition process may be used to place the solder resist layer 224 and the outer dielectric layer 230 on the substrate 202. For example, the solder resist layer 224 may be disposed on (e.g., above) a first surface (e.g., top surface) of at least one inner dielectric layer 220, and the outer dielectric layer 230 may be disposed on (e.g., below) a second surface (e.g., bottom surface) of at least one inner dielectric layer 220. The top surface and the bottom surface may be arbitrarily defined. Different embodiments may define the top or bottom differently.

[0065] like Figure 5D As shown, stage 13 shows a state after forming a cavity 560 in the outer dielectric layer 230. A laser process and / or an etching process may be used to form the cavity 560.

[0066] Stage 14 shows the state after a mask 570 is formed over the outer dielectric layer 230 .

[0067] Stage 15 shows a state after portions of mask 570 are opened to expose portions of outer dielectric layer 230 and some of plurality of interconnects 222. An etching process may be used to open portions of mask 570.

[0068] like Figure 5E As shown, stage 16 shows a state after forming at least one routing interconnect 242 in and on the outer dielectric layer 230. For example, routing vias, routing pads, and / or routing traces may be formed. A plating process may be used to form the routing interconnect.

[0069] Stage 17 shows a state after forming a capping dielectric layer 240 over the at least one routing interconnect 242 and the outer dielectric layer 230. A deposition process may be used to dispose the capping dielectric layer 240 over the at least one routing interconnect 242 and the outer dielectric layer 230.

[0070] like Fig. 5F As shown, stage 18 shows the state after removing mask 570. An etching process may be used to remove or couple mask 570.

[0071] Stage 19 shows a state after a solder interconnect (a solder interconnect in the plurality of solder interconnects 280) is coupled to the plurality of interconnects 222. The solder interconnect 280 may be coupled to a pad 222a (which is a portion of the plurality of interconnects 222). The pad 222a may be located on a bottom metal layer of the substrate 202. Stage 19 may show the substrate 202 including at least one routing interconnect 242 located between the solder interconnects 280, such as Figure 2 As described in.

[0072] Different embodiments may use different processes to form the metal layer(s). In some embodiments, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer(s). For example, a sputtering process, a spraying process, and / or a plating process may be used to form the metal layer(s).

[0073] Exemplary sequence for fabricating a substrate including routing interconnects

[0074] In some embodiments, manufacturing the substrate includes several processes. Figure 6A-6B ) shows an exemplary sequence for providing or manufacturing a substrate. In some embodiments, Figure 6A-6B The sequence can be used to provide or make Figure 4 substrate 402. However, Figure 6A-6B The process can be used to manufacture any substrate described in this disclosure.

[0075] It should be noted that Figure 6A-6B The sequence of one or more stages can be combined to simplify and / or clarify the sequence for providing or manufacturing a substrate. In some embodiments, the order of the process can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure.

[0076] like Fig. 6A As shown, stage 1 shows a state after providing a substrate 402 including at least one inner dielectric layer 220 and a plurality of interconnects 222 . Fig. 6A The stage 1 substrate 402 may be similar to Figure 5C In some embodiments, Fig. 6A The substrate 402 of stage 1 may be as Figure 5A-5C The stages 1-11 are shown and described in the manufacture.

[0077] Stage 2 shows a state after the solder resist layer 224 and the capping dielectric layer 240 are formed over the substrate 402. A deposition process may be used to dispose the solder resist layer 224 and the capping dielectric layer 240 over the substrate 402.

[0078] Stage 3 shows a state after the portion of the capping dielectric layer 240 is removed and the cavity 640 is formed in the capping dielectric layer 240. A laser process and / or an etching process may be used to form the cavity 640 and / or remove the portion of the capping dielectric layer 240.

[0079] like Figure 6B As shown, stage 4 shows a state after at least one routing interconnect 242 is formed in and on the capping dielectric layer 240. For example, routing vias, routing pads, and / or routing traces may be formed. A plating process may be used to form the routing interconnect.

[0080] Stage 5 shows a state after the outer dielectric layer 230 is formed over the at least one routing interconnect 242 and the capping dielectric layer 240. A deposition process may be used to dispose the outer dielectric layer 230 over the at least one routing interconnect 242 and the capping dielectric layer 240. A laser process and / or an etching process may be used to form a cavity 630 in the outer dielectric layer 230.

[0081] Stage 6 shows a state after a solder interconnect (a solder interconnect in the plurality of solder interconnects 280) is coupled to the plurality of interconnects 222. The solder interconnect 280 may be coupled to a pad 222a (which is a part of the plurality of interconnects 222). The pad 222a may be located on a bottom metal layer of a substrate 402. Stage 6 may show a substrate 402 including at least one routing interconnect 242 located between the solder interconnects 280, such as Figure 4 As described in.

[0082] Different embodiments may use different processes to form the metal layer(s). In some embodiments, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the metal layer(s). For example, a sputtering process, a spraying process, and / or a plating process may be used to form the metal layer(s).

[0083] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0084] In some embodiments, manufacturing a substrate includes several processes. Figure 7 An exemplary flow chart of a method 700 for providing or manufacturing a substrate is shown. In some embodiments, Figure 7 The method 700 may be used to provide or manufacture Figure 2 For example, Figure 7 The method may be used to manufacture substrate 202 and / or substrate 402 .

[0085] It should be noted that Figure 7 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some embodiments, the order of the processes may be changed or modified.

[0086] The method provides (at 705) a carrier 500. Different embodiments may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or a carrier tape. Figure 5A Stage 1 shows the state after the carrier is provided.

[0087] The method forms (at 710) a metal layer over the carrier 500. The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and the interconnects. Figure 5A Stage 1 shows the state after the metal layer and interconnect 502 are formed.

[0088] The method forms (at 715) at least one inner dielectric layer (e.g., dielectric layer 520) over carrier 500 and interconnect 502. Dielectric layer 520 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 510) in dielectric layer 520. A deposition process may be used to form the at least one inner dielectric layer. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Figure 5A Stage 2-3 shows the formation of a dielectric layer and a cavity in the dielectric layer.

[0089] The method forms (at 720) interconnects in and on the inner dielectric layer. For example, interconnect 512 may be formed in and on dielectric layer 520. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Figure 5A Stage 4 of FIG. 1 shows an example of forming interconnects in and over the dielectric layer.

[0090] In some implementations, several inner dielectric layers (eg, 522, 524) may be formed, and several interconnects formed in and over the inner dielectric layers. Figure 5A-5C Stages 2-10 of FIG. 1 illustrate examples of forming at least one inner dielectric layer and forming a plurality of interconnects in and over the inner dielectric layer(s).

[0091] The method forms (at 725) an outer dielectric layer 230 over the at least one inner dielectric layer 220 and the plurality of interconnects 222. The outer dielectric layer 230 may include a solder mask or a photoimageable dielectric (PID). A deposition process may be used to form the outer dielectric layer 230. Forming the outer dielectric layer may also include forming a plurality of cavities (e.g., 530) in the outer dielectric layer 230. The plurality of cavities may be formed using an etching process or a laser process. Figure 5C-Figure 1 Stages 12-13 of 5D show forming an outer dielectric layer and forming a cavity in the outer dielectric layer.

[0092] The method forms (at 730) routing interconnects in and / or on the outer dielectric layer. For example, at least one routing interconnect 242 may be formed. A plating process may be used to form the routing interconnects. Forming the routing interconnects may include providing a patterned metal layer on top of the outer dielectric layer 230. Figure 5D-Figure 5E Stages 14-16 may illustrate examples of forming interconnects in and over the outer dielectric layer.

[0093] The method forms (at 735) a capping dielectric layer (e.g., 240) over the outer dielectric layer 230 and the at least one routing interconnect 242. The capping dielectric layer 240 may include a solder mask or a photoimageable dielectric (PID). A deposition process may be used to form the capping dielectric layer 240. Figure 5E-5F Stages 17-19 may illustrate an example of forming a capping dielectric layer.

[0094] As described above, the method can form the dielectric layers in different orders. For example, in some embodiments, at least one capping dielectric layer can be formed before forming at least one outer dielectric layer. Such examples are at least in 6A- Figure 6B. Different embodiments may use different processes to form the (one or more) metal layers. In some embodiments, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form the (one or more) metal layers. For example, a sputtering process, a spraying process, and / or a plating process may be used to form the (one or more) metal layers.

[0095] An exemplary sequence for manufacturing a package including a substrate having interconnects on an outer dielectric layer

[0096] Figure 8 (including Figure 8A-B ) shows an exemplary sequence for providing or manufacturing a package including a substrate. In some embodiments, Figure 8A-B The sequence can be used to provide or manufacture a Figure 2 The package 200 of the substrate 202 or any package described in the present disclosure.

[0097] It should be noted that Figure 8A-B The sequence of one or more stages can be combined to simplify and / or illustrate the sequence for providing or manufacturing a package. In some embodiments, the order of the process can be changed or modified. In some embodiments, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure. Figure 8A-B The sequence can be used to manufacture one or more packages at a time (as part of a wafer).

[0098] like Fig. 8A As shown, stage 1 shows the state after providing substrate 202. Substrate 202 can be provided or manufactured by a supplier. Figure 5A-5F A process similar to the process shown may be used to manufacture the substrate 202. However, different embodiments may use different processes to manufacture the substrate 202. Examples of processes that may be used to manufacture the substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP).

[0099] The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 includes at least one inner dielectric layer 220, a plurality of interconnects 222, a solder resist layer 224, an outer dielectric layer 230, a cover dielectric layer 240, and at least one routing interconnect 242. The plurality of interconnects 222 are at least located in and above the at least one inner dielectric layer 220. The plurality of interconnects 222 include at least one pad 222a located on the bottom metal layer of the substrate 202. The pad 222a is configured to be coupled to a solder interconnect in the plurality of solder interconnects 280. The outer dielectric layer 230 is located above the at least one inner dielectric layer 220. At least one routing interconnect 242 is coupled to the plurality of interconnects 222. At least one routing interconnect 242 is located above the outer dielectric layer 230. At least one routing interconnect 242 is located above (or below, depending on how top and bottom are arbitrarily defined) the bottom metal layer of the substrate 202. A capping dielectric layer 240 is located over the outer dielectric layer 230 and the at least one routing interconnect 242 .

[0100] Stage 2 shows a state after a plurality of solder interconnects 280 are coupled to the substrate 202. The solder interconnects 280 may be coupled to the bottom metal layer of the substrate 202. For example, the solder interconnects 280 may be coupled to the pads 222a (which are located on the bottom metal layer) of the substrate 202. A reflow process may be used to couple the solder interconnects 280 to the substrate 202.

[0101] like Figure 8B As shown, stage 3 shows a state after the first integrated device 205 is coupled to the first surface (e.g., top surface) of the substrate 202 through the plurality of interconnects 250. The plurality of interconnects 250 can be coupled to an interconnect in the plurality of interconnects 222 of the substrate 202. Stage 3 also shows a state after the second integrated device 206 is coupled to the first surface (e.g., top surface) of the substrate 202 through the plurality of interconnects 260. The plurality of interconnects 260 can be coupled to an interconnect in the plurality of interconnects 222 of the substrate 202. A reflow process can be used to couple the first integrated device 205 and / or the second integrated device 206 to the substrate 202.

[0102] Stage 4 shows a state after forming an encapsulation layer 208 on the first surface of the substrate 202 so that the encapsulation layer 208 encapsulates the first integrated device 205 and the second integrated device 206. The process of forming and / or setting the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 4 may show a package 200 including the substrate 202, the first integrated device 205, the second integrated device 206, and the encapsulation layer 208.

[0103] The packages (eg, 200 , 400 ) described in this disclosure may be fabricated one at a time, or may be fabricated together as part of one or more wafers and then singulated into individual packages.

[0104] Exemplary flow chart of a method for manufacturing a package including a substrate having an interconnect located on an outer dielectric layer

[0105] In some embodiments, manufacturing a package including a substrate includes several processes. Fig. 9 An exemplary flow chart of a method 900 for providing or manufacturing a package including a substrate is shown. In some embodiments, Fig. 9 The method 900 may be used to provide or manufacture the Figure 2 However, the method 900 may be used to provide or manufacture any package described in the present disclosure.

[0106] It should be noted that Fig. 9 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package of a substrate. In some embodiments, the order of the processes may be changed or modified.

[0107] The method (at 905) provides a substrate (e.g., 202, 402). The substrate 202 may be provided or manufactured by a supplier. The substrate 202 includes a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 202 may include at least one inner dielectric layer 220, a plurality of interconnects 222, a solder mask layer 224, an outer dielectric layer 230, a cover dielectric layer 240, and at least one routing interconnect 242. The plurality of interconnects 222 are at least located in and above the at least one inner dielectric layer 220. The plurality of interconnects 222 include at least one pad 222a located on the bottom metal layer of the substrate 202. The pad 222a is configured to be coupled to a solder interconnect in a plurality of solder interconnects 280. The outer dielectric layer 230 is located above the at least one inner dielectric layer 220. At least one routing interconnect 242 is coupled to the plurality of interconnects 222. At least one routing interconnect 242 is located above the outer dielectric layer 230. At least one routing interconnect 242 is located below the bottom metal layer of substrate 202. A capping dielectric layer 240 is located above outer dielectric layer 230 and at least one routing interconnect 242.

[0108] Different embodiments may provide different substrates. Figure 5A-5F A process similar to the process shown may be used to manufacture the substrate 202. However, different embodiments may use different processes to manufacture the substrate 202. Fig. 8A Stage 1 of the present invention shows and describes an example of providing a substrate.

[0109] The method couples (at 910) a plurality of solder interconnects (e.g., 280) to a substrate (e.g., 202). The solder interconnects 280 may be coupled to a bottom metal layer of the substrate 202. For example, the solder interconnects 280 may be coupled to pads 222a (which are located on the bottom metal layer) of the substrate 202. A reflow process may be used to couple the solder interconnects 280 to the substrate 202. Fig. 8A An example of coupling a solder interconnect to a substrate is shown and described in Stage 2 of the drawings.

[0110] The method (at 915) couples the components to the substrate (e.g., 202). For example, the method may couple the first integrated device 205 to the first surface (e.g., top surface) of the substrate 202 via the plurality of interconnects 250. The plurality of interconnects 250 may be coupled to interconnects in the plurality of interconnects 222. The method may couple the second integrated device 206 to the first surface (e.g., top surface) of the substrate 202 via the plurality of interconnects 260. The plurality of interconnects 260 may be coupled to interconnects in the plurality of interconnects 222 of the substrate 202. A reflow process may be used to couple the first integrated device 205 and / or the second integrated device 206 to the substrate 202. Figure 8BAn example of coupling a component to a substrate is shown and described in Stage 3 of the present invention.

[0111] The method forms (at 925) an encapsulation layer (e.g., 208) over a first surface of a substrate (e.g., 202). The encapsulation layer may be formed over the first surface of the substrate such that the encapsulation layer 208 encapsulates the first integrated device 205 and the second integrated device 206 (which are examples of components). The process of forming and / or providing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Figure 8B Stage 4 of FIG. 1 shows and describes an example of an encapsulation layer that is located on a substrate and encapsulates an integrated device.

[0112] An exemplary package-on-package (PoP) comprising a package including a substrate having interconnects disposed on an outer dielectric layer

[0113] Fig.10 A cross-sectional view of a package-on-package (PoP) 1000 is shown, the PoP 1000 including a package 1001 and a package 1003, the package 1001 and the package 1003 including interconnects located on an outer dielectric layer. The package 1001 is coupled to the package 1003 through a plurality of solder interconnects 1080. The package 1001 is located on the package 1003. The PoP 1000 is coupled to a board 290 (e.g., a printed circuit board (PCB)) through a plurality of solder interconnects 280 of the package 1003. The package 1003 provides a package having a compact small form factor while also having an improved routing interconnect design.

[0114] Fig.10 The package 1003 is similar to Figure 2 Package 1003 includes a plurality of vias 1088 running through encapsulation layer 208. The plurality of vias 1088 may include through mold vias (TMV). The plurality of vias 1088 are coupled to a plurality of interconnects 222. Package 1003 includes a plurality of upper routing interconnects 1042 located above encapsulation layer 208. The plurality of upper routing interconnects 1042 may be coupled to the plurality of vias 1088. An upper cover dielectric layer 1040 is located above the plurality of upper routing interconnects 1042 and encapsulation layer 208. The plurality of upper routing interconnects 1042 are located (e.g., laterally located) between the plurality of solder interconnects 1080. The plurality of routing interconnects 1042 may be components for upper routing interconnects. Encapsulation layer 1070 may be located between package 1001 and package 1003.

[0115] The package 1001 includes a substrate 1002, an integrated device 1006, and an encapsulation layer 1008. The substrate 1002 includes at least one dielectric layer 1020 and a plurality of interconnects 1022. The integrated device 1006 is coupled to the substrate 1002. The encapsulation layer 1008 is coupled to the substrate 1002 and encapsulates the integrated device 1006.

[0116] In some embodiments, package 1001 can be similar to package 200 , and thus package 1001 can include an outer dielectric layer (eg, 230 ) and / or a cover dielectric layer (eg, 240 ).

[0117] As used in this disclosure, when a particular dielectric layer is "above" another dielectric layer, the particular dielectric layer may be above or below the other dielectric layer, depending on how bottom (e.g., bottom layer) or top (e.g., top layer) is arbitrarily defined. A particular dielectric layer being "above" (whether above or below) another dielectric layer may mean that the particular dielectric layer is coupled to a surface of the other dielectric layer. For example, a surface of the particular dielectric layer may be in contact with (e.g., touching) another surface of the other dielectric layer.

[0118] An exemplary sequence for manufacturing an exemplary package-on-package (PoP) comprising a package including a substrate having an interconnect on an outer dielectric layer

[0119] Figure 11 (including Figures 11A-11C ) shows an exemplary sequence for providing or manufacturing a package-on-package (PoP). In some embodiments, Figures 11A-11C The sequence can be used to provide or make Fig.10 PoP 1000 or any PoP described in this disclosure.

[0120] It should be noted that Figure 11A-11C The sequence of one or more stages may be combined to simplify and / or clarify the sequence for providing or manufacturing a PoP. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more processes may be replaced or substituted without departing from the spirit of the present disclosure. Figure 11A-11C The sequence can be used to manufacture one PoP or several PoPs at a time (as part of a wafer).

[0121] like Fig.11A As shown, stage 1 shows a state after the package 200 is provided or manufactured. Figure 8A-B An example of providing a package is shown. The package 200 may include a substrate including at least one routing interconnect, an outer dielectric layer, and a cover dielectric layer, such as Figure 2 As described in.

[0122] Stage 2 shows a state after forming the cavity 1110 in the encapsulation layer 208 of the package 200. A laser process and / or an etching process may be used to form the cavity 1110 in the encapsulation layer 208.

[0123] Stage 3 shows a state after forming the via 1088 in the cavity 1110 of the encapsulation layer 208. A pasting process and / or a plating process may be used to form the via 1088. The via 1088 may be coupled to the plurality of interconnects 222 of the substrate 202.

[0124] like Fig. 11B As shown, stage 4 shows a state after forming a plurality of upper routing interconnects 1042 over the encapsulation layer 208. The plurality of upper routing interconnects 1042 may be coupled to the vias 1088. A plating process may be used to form the plurality of upper routing interconnects 1042.

[0125] Stage 5 shows a state after forming an upper cover dielectric layer 1040 over the plurality of upper routing interconnects 1042 and the encapsulation layer 208. A deposition process may be used to place the upper cover dielectric layer 1040 over the plurality of upper routing interconnects 1042 and the encapsulation layer 208. The upper cover dielectric layer 1040 may include a solder resist or a photoimageable dielectric (PID). Package 1003 may be manufactured from package 200.

[0126] like Fig. 11C As shown, stage 6 shows a state after the package 1001 is coupled to the package 1003 through a plurality of solder interconnects 1080. A reflow process may be used to couple the package 1001 to the package 1003. The package 1001 includes a substrate 1002, an integrated device 1006, and an encapsulation layer 1008. The substrate 1002 includes at least one dielectric layer 1020 and a plurality of interconnects 1022. The integrated device 1006 is coupled to the substrate 1002. The encapsulation layer 1008 is coupled to the substrate 1002 and encapsulates the integrated device 1006. The package 1001 may be manufactured using a process similar to that used to manufacture the package 1003.

[0127] Stage 7 shows a state after forming an encapsulation layer 1070 between the package 1001 and the package 1003. The process of forming and / or disposing the encapsulation layer 10070 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process to form the encapsulation layer 1070 between the encapsulation layer 208 and the substrate 1002. Stage 7 shows the PoP 1000 including the package 1001 and the package 1003.

[0128] Exemplary Electronic Devices

[0129] Fig.12Various electronic devices that can be integrated with any of the above-mentioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC) are shown. For example, a mobile phone device 1202, a laptop computer device 1204, a fixed location terminal device 1206, a wearable device 1208, or a motor vehicle 1210 can include a device 1200 as described herein. For example, the device 1200 can be any device and / or integrated circuit (IC) package described herein. Fig.12 The devices 1202, 1204, 1206, and 1208 and the vehicle 1210 shown are exemplary only. Other electronic devices may also feature the device 1200, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting global positioning systems (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., self-driving cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0130] Figure 2-Figure 4 , Figure 5A-5F , Figure 6A-6B , Figure 7 , Figure 8A-B , Figure 9-10 , Figure 11A-11C and / or Fig.12 One or more of the components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 2-Figure 4 , Figure 5A-5F , Figure 6A-6B , Figure 7 , Figure 8A-B , Figure 9-10 , Figures 11A-11C and / or Fig.12 and its corresponding description in this disclosure are not limited to die and / or IC. In some embodiments, Figure 2-Figure 4 , Figure 5A-5F , Figure 6A-6B , Figure 7 , Figure 8A-B , Figure 9-10, Figure 11A-11C and / or Fig.12 and corresponding descriptions thereof can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some embodiments, the device can include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0131] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits and / or transistors. In some cases, these drawings may not be drawn to scale. In some cases, for the sake of clarity, all components and / or parts may not be shown. In some cases, the positioning, location, size and / or shape of the various parts and / or components in the figures may be exemplary. In some embodiments, the various components and / or parts in the figures may be optional.

[0132] The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment or aspect described herein as "exemplary" is not necessarily to be construed as being more preferred or advantageous than other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the features, advantages or modes of operation discussed. The term "coupling" as used herein refers to a direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact. The term "electrically coupled" can mean that two objects are coupled together directly or indirectly so that an electric current (e.g., a signal, power supply, ground) can travel between the two objects. Two electrically coupled objects may or may not have an electric current flowing between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component or a fourth component. The term "encapsulate" means that an object can partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. The position of a component located at the top can be above a component located at the bottom. The top component can be considered to be a bottom component and vice versa. As described in the present disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component can be located above (e.g., above) a first surface of the second component, and the third component can be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. It should also be noted that the term "above" as used in the context of one component being located above another component in this application can be used to represent a component on and / or in (e.g., on the surface of or embedded in) another component. Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component but does not directly touch the second component; (2) the first component is on (e.g., on a surface of) the second component; and / or (3) the first component is within (e.g., embedded in) the second component. The term "about 'X value'" or "approximately X value" as used in this disclosure means within 10% of "X value". For example, a value of about 1 or approximately 1 would mean a value within the range of 0.9-1.1.

[0133] In some embodiments, an interconnect is an element or component of a device or package that allows or promotes electrical connection between two points, elements and / or components. In some embodiments, an interconnect may include a trace, a via, a pad, a column, a redistributed metal layer and / or an under bump metallization (UBM) layer. An interconnect may include one or more metal components (e.g., a seed layer+metal layer). In some embodiments, an interconnect is a conductive material that can be configured to provide an electrical path for an electric current (e.g., a data signal, ground or power supply). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different embodiments may use similar or different processes to form an interconnect. In some embodiments, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process may be used to form an interconnect. For example, a sputtering process, a spray coating and / or a plating process may be used to form an interconnect.

[0134] In addition, it should be noted that the various disclosures included herein can be described as processes depicted as flow charts, flow charts, structure diagrams, or block diagrams. Although flow charts can describe operations as sequential processes, many operations can be performed in parallel or simultaneously. In addition, the order of operations can be rearranged. A process terminates when its operations are completed.

[0135] The various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be interpreted as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, rather than limiting the scope of the claims. Therefore, this teaching can be easily applied to other types of devices, and many substitutions, modifications and changes will be clear to those skilled in the art.

[0136] Hereinafter, additional examples are described to facilitate understanding of the present invention.

[0137] In another example, a package is described that includes: a substrate that includes: (i) at least one inner dielectric layer, (ii) a plurality of interconnects in the at least one inner dielectric layer, wherein the plurality of interconnects include pads on a bottom metal layer of the substrate, (iii) an outer dielectric layer located above (e.g., above a surface of) the at least one inner dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located above (e.g., above a surface of the outer dielectric layer), wherein the at least one routing interconnect is located above the bottom metal layer of the substrate, and (v) a cover dielectric layer located above the outer dielectric layer and the at least one routing interconnect; an integrated device coupled to the substrate; and a solder interconnect coupled to the pads on the bottom metal layer of the substrate. The outer dielectric layer may include a different material than the at least one inner dielectric layer. The cover dielectric layer may include a different material than the at least one inner dielectric layer. The cover dielectric layer may include a different material than the at least one inner dielectric layer and the outer dielectric layer. In addition, the cover dielectric layer and the outer dielectric layer may each include a material different from the at least one inner dielectric layer. In addition, the cover dielectric layer and the outer dielectric layer may each include the same material. At least one inner dielectric layer may include a copper clad laminate (CCL) core, a prepreg, an Ajinomoto built-up film (ABF) and / or a resin coated copper (RCC). In addition, the outer dielectric layer and the cover dielectric layer may each include a solder mask and / or a photoimageable dielectric (PID). In addition, the first electrical signal to and / or from the integrated device may be configured to travel through at least one routing interconnect. In addition, the package may include an encapsulation layer located above the substrate; at least one via located in the encapsulation layer; at least one upper routing interconnect coupled to the at least one via, wherein the at least one upper routing interconnect is located above the encapsulation layer; and an upper cover dielectric layer located above the at least one upper routing interconnect and the encapsulation layer. The first electrical signal to and / or from the integrated device may be configured to travel through at least one upper routing interconnect. In addition, the package may be part of a package-on-package (PoP). The bottom metal layer of the substrate may be the metal layer that is vertically closest to the solder interconnection and not positioned laterally beside the solder interconnection. The package may be incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0138] In yet another example, an apparatus is described that includes: a substrate that includes: (i) at least one inner dielectric layer, (ii) a plurality of interconnects in the at least one inner dielectric layer, wherein the plurality of interconnects include pads on a bottom metal layer of the substrate, (iii) an outer dielectric layer located above the at least one inner dielectric layer, (iv) a component for routing interconnects coupled to the plurality of interconnects, wherein the component for routing interconnects is located above the outer dielectric layer, wherein the component for routing interconnects is located above the bottom metal layer of the substrate, and (v) a cover dielectric layer located above the outer dielectric layer and the component for routing interconnects; an integrated device coupled to the substrate; and a solder interconnect coupled to the pads on the bottom metal layer of the substrate. The outer dielectric layer may include a different material than the at least one inner dielectric layer. The cover dielectric layer may include a different material than the at least one inner dielectric layer. The cover dielectric layer may include a different material than the at least one inner dielectric layer and the outer dielectric layer. The cover dielectric layer and the outer dielectric layer may each include a different material than the at least one inner dielectric layer. The cover dielectric layer and the outer dielectric layer each may include the same material. A first electrical signal to and / or from the integrated device may be configured to travel through a component for routing interconnects. In addition, the apparatus may include: a component for encapsulation located above the substrate; at least one via located in the component for encapsulation; a component for upper routing interconnects coupled to the at least one via, wherein the component for upper routing interconnects is located above the component for encapsulation; and an upper cover dielectric layer located above the component for upper routing interconnects and the component for encapsulation. In addition, a first electrical signal to and / or from the integrated device may be configured to travel through a component for upper routing interconnects.

[0139] In yet another example, a method for manufacturing a package may be described, the method comprising: providing a substrate comprising: (i) at least one inner dielectric layer, (ii) a plurality of interconnects in the at least one inner dielectric layer, wherein the plurality of interconnects include pads on a bottom metal layer of the substrate, (iii) an outer dielectric layer above the at least one inner dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is above the outer dielectric layer, wherein the at least one routing interconnect is above the bottom metal layer of the substrate, and (v) a cover dielectric layer above the outer dielectric layer and the at least one routing interconnect; coupling an integrated device to the substrate; and coupling a solder interconnect to the pads on the bottom metal layer of the substrate. The method may also include: forming an encapsulation layer above the substrate; forming at least one via in the encapsulation layer; forming at least one upper routing interconnect above the encapsulation layer, wherein the at least one upper routing interconnect is coupled to the at least one via; and forming an upper cover dielectric layer above the at least one upper routing interconnect and the encapsulation layer.

[0140] In another example, a package is described that includes: a substrate that includes: (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, wherein the plurality of interconnects include pads located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located above (e.g., above a surface of) the at least one inner dielectric layer, (iv) a cover dielectric layer located above (e.g., above a surface of the at least one inner dielectric layer), (v) at least one routing interconnect coupled to the plurality of interconnects, wherein at least one routing interconnect is located above the cover dielectric layer (e.g., above the surface of the cover dielectric layer), wherein at least one routing interconnect is located above the bottom metal layer of the substrate, and (v) a second outer dielectric layer located above the cover dielectric layer and the at least one routing interconnect; an integrated device coupled to the substrate; and a solder interconnect coupled to the pads located on the bottom metal layer of the substrate.

Claims

1. A package, include: Base plate, comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects disposed in the at least one inner dielectric layer, wherein the plurality of interconnects comprises pads disposed on a bottom metal layer of the substrate; (iii) an outer dielectric layer disposed over the at least one inner dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located above the outer dielectric layer, wherein the at least one routing interconnect is located above the bottom metal layer of the substrate, and (v) a cover dielectric layer overlying the outer dielectric layer and the at least one routing interconnect; an integrated device coupled to the substrate; and A solder interconnect is coupled to the pad on the bottom metal layer of the substrate. 2 . The package of claim 1 , wherein the outer dielectric layer comprises a different material than the at least one inner dielectric layer. 3 . The package of claim 1 , wherein the cover dielectric layer comprises a different material than the at least one inner dielectric layer. 4 . The package of claim 1 , wherein the cover dielectric layer comprises a different material than the at least one inner dielectric layer and the outer dielectric layer. 5 . The package of claim 1 , wherein the cover dielectric layer and the outer dielectric layer each comprise a different material than the at least one inner dielectric layer. The package of claim 1 , wherein the cover dielectric layer and the outer dielectric layer each comprise the same material.

7. The package of claim 1, wherein the at least one inner dielectric layer comprises a copper clad laminate (CCL) core, a prepreg, an Ajinomoto built-up film (ABF), and / or a resin coated copper (RCC). 8 . The package of claim 1 , wherein the outer dielectric layer and the cover dielectric layer each comprise a solder mask layer and / or a photoimageable dielectric (PID). 9 . The package of claim 1 , wherein a first electrical signal to and / or from the integrated device is configured to travel through the at least one routing interconnect.

10. The package according to claim 1, further comprising: include: An encapsulation layer, located on the substrate; at least one via located in the encapsulation layer; at least one upper routing interconnect coupled to the at least one via, wherein the at least one upper routing interconnect is located above the encapsulation layer; an upper cover dielectric layer overlying the at least one upper routing interconnect and the encapsulation layer, wherein the outer dielectric layer is located below a bottom surface of the at least one inner dielectric layer, wherein the at least one routing interconnect is located below a bottom surface of the outer dielectric layer, and Wherein the capping dielectric layer is located below the bottom surface of the outer dielectric layer and the at least one routing interconnect. 11 . The package of claim 10 , wherein a first electrical signal to and / or from the integrated device is configured to travel through the at least one upper routing interconnect.

12. The package of claim 10, wherein the package is part of a package-on-package (PoP). 13 . The package of claim 1 , wherein the bottom metal layer of the substrate is a metal layer vertically closest to the solder interconnect and not positioned laterally beside the solder interconnect.

14. A package according to claim 1, wherein the package is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

15. A device, include: Base plate, comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects disposed in the at least one inner dielectric layer, wherein the plurality of interconnects comprises pads disposed on a bottom metal layer of the substrate; (iii) an outer dielectric layer disposed over the at least one inner dielectric layer; (iv) means for a routing interconnect coupled to the plurality of interconnects, wherein the means for routing interconnects is located above the outer dielectric layer, wherein the means for routing interconnects is located above the bottom metal layer of the substrate, and (v) a cover dielectric layer overlying the outer dielectric layer and the means for routing interconnects; an integrated device coupled to the substrate; and A solder interconnect is coupled to the pad on the bottom metal layer of the substrate.

16. The device of claim 15, wherein the outer dielectric layer comprises a different material than the at least one inner dielectric layer.

17. The device of claim 15, wherein the cover dielectric layer comprises a different material than the at least one inner dielectric layer.

18. The device of claim 15, wherein the cover dielectric layer comprises a different material than the at least one inner dielectric layer and the outer dielectric layer.

19. The device of claim 15, wherein the cover dielectric layer and the outer dielectric layer each comprise a different material than the at least one inner dielectric layer.

20. The device of claim 15, wherein the cover dielectric layer and the outer dielectric layer each comprise the same material.

21. The apparatus of claim 15, wherein a first electrical signal to and / or from the integrated device is configured to travel through the means for routing interconnects.

22. The device according to claim 15, further comprising: include: A component for encapsulation, located on the substrate; at least one via located in the component for encapsulation; a means for upper routing interconnect coupled to the at least one via, wherein the means for upper routing interconnect is located above the means for encapsulating; and An upper cover dielectric layer is located above the means for upper routing interconnects and the means for encapsulation.

23. The apparatus of claim 22, wherein a first electrical signal to and / or from the integrated device is configured to travel through the means for upper routing interconnects.

24. The device according to claim 15, wherein the outer dielectric layer (i) is coupled to the at least one inner dielectric layer and (ii) is located below the at least one inner dielectric layer, wherein the means for routing interconnects is located below the outer dielectric layer, and The capping dielectric layer is (i) coupled to the outer dielectric layer and the means for routing interconnects, and (ii) located below the outer dielectric layer.

25. A package, include: Base plate, comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects disposed in the at least one inner dielectric layer, wherein the plurality of interconnects comprises pads disposed on a bottom metal layer of the substrate; (iii) an outer dielectric layer disposed over the at least one inner dielectric layer; (iv) a cover dielectric layer disposed over the at least one inner dielectric layer; (v) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located above the capping dielectric layer, wherein the at least one routing interconnect is located above the bottom metal layer of the substrate, and (vi) a second outer dielectric layer overlying the cover dielectric layer and the at least one routing interconnect; an integrated device coupled to the substrate; and A solder interconnect is coupled to the pad on the bottom metal layer of the substrate.

26. The package of claim 25, wherein the second outer dielectric layer and the outer dielectric layer may be the same dielectric layer.

27. A method for manufacturing a package, include: A substrate is provided, the substrate comprising: (i) at least one inner dielectric layer; (ii) a plurality of interconnects disposed in the at least one inner dielectric layer, wherein the plurality of interconnects comprises pads disposed on a bottom metal layer of the substrate; (iii) an outer dielectric layer disposed over the at least one inner dielectric layer; (iv) at least one routing interconnect coupled to the plurality of interconnects, wherein the at least one routing interconnect is located above the outer dielectric layer, wherein the at least one routing interconnect is located above the bottom metal layer of the substrate, and (v) a cover dielectric layer overlying the outer dielectric layer and the at least one routing interconnect; coupling an integrated device to the substrate; and Solder interconnects are coupled to the pads on the bottom metal layer of the substrate.

28. The method according to claim 27, further comprising: include: forming an encapsulation layer on the substrate; forming at least one via in the encapsulation layer; forming at least one upper routing interconnect over the encapsulation layer, wherein the at least one upper routing interconnect is coupled to the at least one via; as well as An upper capping dielectric layer is formed over the at least one upper routing interconnect and the encapsulation layer.

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