Chip capacitor testing device and testing packaging device using the same

Abstract

The present invention provides a chip capacitor testing device and also provides a testing packaging device using the testing device, which can perform batch testing on chip capacitors with high testing efficiency. It includes a material taking station, a packaging station and a transfer mechanism, and a testing station is also arranged between the material taking station and the packaging station; a carrier box is used to store more than one chip capacitor, and the carrier box includes a hole plate and a circuit board arranged in sequence from top to bottom, and upper electrodes are evenly arranged above the circuit board, and a vacuum hole is opened on the circuit board corresponding to the position where the chip capacitor is placed, and a receiving hole for placing the chip capacitor is opened on the hole plate corresponding to the upper electrode, and the upper electrode is also connected to the lower electrode located below the circuit board through a conductive through hole; the testing station includes an upper probe card and a lower probe card, and the upper probe card and the lower probe card are respectively provided with more than one probe, and the probe of the upper probe card is used to press on the chip capacitor, and the probe of the lower probe card is used to press on the lower electrode.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitor testing devices, in particular to a chip capacitor testing device and a testing packaging device using the testing device. Background Art

[0002] Chip capacitors, also known as single-layer capacitors, are micro capacitors with capacitor electrodes made on two planes of a thinner planar dielectric. In actual production, the capacitor needs to be removed from the blue film used for dicing, and the capacitor needs to be subjected to four electrical performance tests, including a withstand voltage test (need to be applied with a specified voltage for more than 5 seconds), an insulation resistance test (a certain charging time is required for accurate testing), a capacity test, and a loss test. Then, the electrode appearance is inspected, and capacitors with unqualified performance and appearance are removed. Finally, the capacitor is placed in another blue film or packaging box. All of these operations must be performed as little as possible to avoid damaging the entire surface and corner appearance of the capacitor.

[0003] The prior art only uses the vibration plate feeding device, rotary multi-station test and appearance inspection device, and boxing or taping device commonly used in conventional electronic components to form an integrated machine for the capacitors in the aliasing pile. Moreover, the rotary multi-station test and appearance inspection device used in the prior art is in a continuous rotation and transposition state when working, charging and measuring each capacitor in turn. The charging time allocated to each capacitor is very short, far less than 1 second, so that it is impossible to perform accurate insulation resistance testing, and it can only be estimated by prediction method. What is more serious is that the voltage application duration of the withstand voltage test project usually takes several seconds, for example, more than 5 seconds. If this common method stays at each station for more than 5 seconds for each capacitor, the efficiency will be extremely low and the cost will become extremely high, which cannot meet the requirements of high efficiency and low cost for mass production. Summary of the invention

[0004] In view of the problem that the existing testing device has low testing efficiency and cannot perform batch testing on chip capacitors, the present invention provides a chip capacitor testing device, which can perform batch testing on chip capacitors with high testing efficiency, and also provides a test packaging device using the testing device.

[0005] The technical solution is as follows: a chip capacitor testing device, which includes a probe card, characterized in that: the probe card includes an upper probe card and a lower probe card, the upper probe card and the lower probe card are respectively provided with more than one probe, a carrier box is provided between the upper probe card and the lower probe card, the carrier box is used to store more than one chip capacitor, the carrier box includes a hole plate and a circuit board arranged in sequence up and down, upper electrodes are evenly arranged above the circuit board, the circuit board is provided with a vacuum hole corresponding to the position where the chip capacitor is placed, the vacuum hole is used to connect with the vacuum mechanism, the hole plate is provided with a receiving hole for positioning the chip capacitor corresponding to the upper electrode, the upper electrode is also connected to the lower electrode located below the circuit board through a conductive through hole, the probe of the upper probe card is used to press on the chip capacitor, and the probe of the lower probe card is used to press on the lower electrode.

[0006] It is further characterized by:

[0007] The carrier box also includes a vacuum bottom plate located below the circuit board, a vacuum groove is provided on the vacuum bottom plate, the vacuum hole is connected to the vacuum groove, and the vacuum hole is connected to the vacuum mechanism through the vacuum bottom plate; an avoidance groove is provided on the vacuum bottom plate at a position corresponding to the lower electrode, and the avoidance groove is used to avoid the lower probe.

[0008] A chip capacitor testing and packaging device comprises a material picking station, a packaging station and a transfer mechanism, and is characterized in that: a test station is also provided between the material picking station and the packaging station, the test station is provided with the above-mentioned chip capacitor testing device, the material picking station is used to place the chip capacitor in a carrier box, the packaging station is used to take the chip capacitor out of the carrier box and place it on a blue film or into a packaging box, and the carrier box is transferred among the material picking station, the packaging station and the testing station through the transfer mechanism.

[0009] It is further characterized by:

[0010] The material picking station includes a material picking robot arm and a blue film lower ejector pin, the material picking robot arm is equipped with a suction head, the blue film lower ejector pin is used to eject the chip capacitor from the blue film, and the material picking robot arm absorbs the chip capacitor through the suction head and places it into the carrier box; the packaging station includes a material unloading robot arm and a loading position, the material unloading robot arm is equipped with a suction head, and the loading position is placed with a blue film or a packaging box;

[0011] The test station includes a capacitor withstand voltage / insulation resistance test bench and a capacity loss test bench, and the capacitor withstand voltage / insulation resistance test bench and the capacity loss test bench are respectively provided with the chip capacitance test device;

[0012] The test station also includes a chip capacitor upper surface appearance inspection table, and a camera is installed on the chip capacitor upper surface appearance inspection table;

[0013] The capacitor withstand voltage / insulation resistance test bench and the capacity loss test bench are respectively equipped with the vacuum pumping mechanism; the capacitor withstand voltage / insulation resistance test bench comprises a DC upper probe card and a DC lower probe card, and the probes on the DC upper probe card and the probes on the DC lower probe card are respectively connected to the withstand voltage / insulation resistance test circuit; the capacity loss test bench comprises an AC upper probe card and an AC lower probe card, and the probes of the AC upper probe card and the probes of the AC lower probe card are connected to the capacitor test meter;

[0014] The AC upper probe card or the AC lower probe card is provided with a multi-way switch channel device, and the probes of the AC upper probe card and the probes of the AC lower probe card are connected to a capacitance test meter through the multi-way switch channel device.

[0015] After adopting such a structure, a carrier box has multiple chip capacitors, and the lower electrode of the chip capacitor contacts the upper electrode of the circuit board, so that the lower electrode of the chip capacitor can be connected to the lower electrode of the circuit board, and multiple probes on the upper probe card are pressed on the upper electrode of the chip capacitor at the same time, and multiple probes on the lower probe card are pressed on the lower electrode of the carrier box at the same time, so that the chip capacitor can be connected to the pressure test circuit for voltage application and testing, and multiple capacitors can be pressure tested at one time, so that batch testing of chip capacitors can be realized, and the testing efficiency is high. When in use, the chip capacitor can be removed from the blue film and placed in the carrier box through the material taking station, and then the carrier box is moved to the test station through the transfer mechanism, and tested by the test device of the test station. After the test is completed, it is moved to the packaging station through the transfer mechanism, and the qualified capacitor is placed on the blue film or put into the packaging box for packaging, and the unqualified capacitor is removed, thereby completing the chip capacitor test packaging process, and the whole process is efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a top view of a carrier box;

[0017] Figure 2 It is an enlarged schematic diagram of the carrier box viewed from above;

[0018] Figure 3 This is a schematic diagram of the carrier box viewed from above;

[0019] Figure 4 This is an enlarged schematic diagram of the carrier box viewed from above;

[0020] Figure 5 This is a schematic diagram of a capacitor withstand voltage / insulation resistance test bench;

[0021] Figure 6 Schematic diagram of the capacity loss test bench. DETAILED DESCRIPTION

[0022] A chip capacitor testing and packaging device includes a material picking station, a packaging station and a transfer mechanism. The material picking station is used to place the chip capacitor in a carrier box. The packaging station is used to take the chip capacitor out of the carrier box and place it on a blue film or into a packaging box. A test station is also provided between the material picking station and the packaging station. The carrier box is transferred between the material picking station, the packaging station and the test station through the transfer mechanism. Specifically, the chip capacitor is generally on the blue film before entering the device. The chip capacitor on the blue film is taken out and placed in the carrier box through the material picking station. The material picking station can be manually operated, but in order to realize automated testing, as a preferred embodiment, the material picking station includes a material picking robot arm that can move up and down and rotate and a blue film lower ejector pin. A suction head is installed on the material picking robot arm. The blue film lower ejector pin is used to eject the chip capacitor from the blue film. The material picking robot arm absorbs the ejected chip capacitor through the suction head and places it in the carrier box. The transfer mechanism can be manually realized, but in order to improve automation, an automatic transfer mechanism can also be used, that is, by placing the carrier box on an electric track and performing the transfer via the electric track. Transfer, but it should be noted that an opening needs to be opened in the middle of the track to avoid the lower probe. Of course, the edge of the carrier box can be connected to the lifting rope and lifted to the test station through a lifting mechanism, and the carrier box can also be clamped to the test station by a robotic arm; the packaging station can also rely on manual labor to take the chip capacitor out of the carrier box and place it in a blue film or a packaging box, but in order to improve the degree of automation, as a preferred embodiment, the packaging station includes a unloading robotic arm and a loading position that can move up and down and rotate, the unloading robotic arm is equipped with a suction head, and a blue film or a packaging box is placed on the loading position, and the chip capacitor is taken out of the carrier box and placed on the blue film or in the packaging box by the suction head of the unloading robotic arm.

[0023] like Figure 1 , 2As shown in Figures 3 and 4, the carrier box 1 is used to store more than one chip capacitor 100. The carrier box 1 includes a perforated plate 11 and a circuit board 12 which are arranged in sequence from top to bottom. The perforated plate 11 is only used to position the capacitor and can be replaced by other structures with positioning holes. An array of independent, planar upper electrodes 121 is evenly arranged above the circuit board 12. The circuit board 12 is provided with a vacuum hole 122 corresponding to the position where the chip capacitor is placed. The vacuum hole 122 is used to connect with a vacuum mechanism (such as a vacuum pump, etc.). The perforated plate 11 is made of insulating material and a receiving hole 111 for placing the chip capacitor 100 is provided thereon corresponding to the upper electrode 121. The upper electrode 121 is also connected to a lower electrode 124 located below the circuit board 12 through a conductive through hole 123. The lower electrode 124 is used to contact with a lower probe. The vacuum mechanism can be directly connected to the vacuum hole 122 through a pipeline to adsorb the capacitor. It should be noted that the vacuum hole 122 and the conductive through hole 123 avoid each other to ensure normal operation. The vacuum hole 122 can be directly opened in the center of the upper electrode 121, and the upper electrode 121 can be connected to the conductive through hole on one side through a circuit. The above structure is complicated because each vacuum hole 122 needs to be provided with a corresponding vacuum pipe. Preferably, in order to simplify the structure, the carrier box 1 also includes a vacuum bottom plate 13 located below the circuit board, and a vacuum groove is provided on the vacuum bottom plate 13. The vacuum hole 131 is connected to the vacuum groove, and the vacuum hole 131 is connected to the vacuum mechanism through the vacuum bottom plate 13; an avoidance groove 131 is provided on the vacuum bottom plate 13 at a position corresponding to the lower electrode 124, and the avoidance groove 131 is used to avoid the lower probe and expose the lower electrode 124. With the above structure, the vacuum holes 131 can be collected into the vacuum groove by providing a vacuum groove on the vacuum bottom plate 13, and then the vacuum groove is connected to the vacuum pump through a pipeline. At the same time, the vacuum groove needs to be separated from the avoidance groove 131 to avoid affecting the vacuuming, so that the structure can be simplified. At the same time, in order to increase the sealing performance, a sealing structure (sealing ring, sealant, etc.) can be provided between the vacuum bottom plate 13 and the circuit board 12 to prevent the gap between the two plates from affecting the vacuuming.

[0024] Combination Figure 5 , Figure 6 As shown, the test device of the test station includes an upper probe card 2 and a lower probe card 3, and more than one probe 4 is respectively provided on the upper probe card 2 and the lower probe card 3. The probe 4 of the upper probe card 2 is used to press on the chip capacitor 100, and the probe 4 of the lower probe card 3 is used to press on the lower electrode 124. Specifically, the test station may include a capacitor withstand voltage / insulation resistance test bench, a capacity loss test bench, and a chip capacitor upper surface appearance inspection bench, and a camera is installed on the chip capacitor upper surface appearance inspection bench.

[0025] The capacitor withstand voltage / insulation resistance test bench and the capacity loss test bench are respectively equipped with vacuum mechanisms; the capacitor withstand voltage / insulation resistance test bench includes a DC upper probe card and a DC lower probe card, and the probes on the DC upper probe card and the probes on the DC lower probe card are respectively connected to the withstand voltage / insulation resistance test circuit; the capacity loss test bench includes an AC upper probe card and an AC lower probe card, and the probes of the AC upper probe card and the probes of the AC lower probe card are connected to a capacitor test meter; preferably, the AC upper probe card or the AC lower probe card is provided with a multi-way switch switching channel device, and the probes of the AC upper probe card and the probes of the AC lower probe card are connected to a capacitor test meter through the multi-way switch switching channel device, and the array plane probes are pressed in a static manner on the surface of multiple chip capacitors in the carrier box to perform withstand voltage, insulation resistance, capacity, and loss parameter tests, and then the chip capacitors in the carrier box are visually inspected with a camera at another workstation.

[0026] When the preferred solution of the device is used to test the chip capacitor, when the material picking robot arm moves the suction head to the top of the chip capacitor on the blue film, the ejector pin slightly lifts a chip capacitor from the blue film to separate the chip capacitor from the blue film as much as possible, the material picking robot arm descends to bring the suction head close to the chip capacitor, and then the suction head sucks up the chip capacitor, and then the material picking robot arm rises and rotates to the loading position of the chip capacitor test carrier box, and the material picking robot arm descends to load the capacitor on the suction head into the carrier box. The material picking robot arm rises again and rotates back to the top of the blue film to suck up the next chip capacitor. The carrier box shifts one capacitor slot, and uses an empty slot to prepare to receive the next chip capacitor to be loaded into the box.

[0027] After the carrier box is loaded, it is transferred to the test station through the automatic transfer mechanism, which is the capacitor withstand voltage / insulation resistance test bench, the capacity loss test bench, and the chip capacitor upper surface appearance inspection bench. The first two test benches are equipped with a vacuum workpiece table with a vacuum pipe on it, which is connected to the end of the bottom vacuum groove of the capacitor carrier box placed on it. It will pass through the vacuum groove in the vacuum bottom plate at the bottom of the carrier box, and generate negative pressure at all the vacuum holes 122 in the upper part of the carrier box, so that the chip capacitor placed on the upper electrode 121 is adsorbed on the upper electrode; the upper and lower DC probe cards and DC lower probe cards are respectively provided above and below the capacitor withstand voltage / insulation resistance test bench, where the diameter of the lower probe on the lower probe card 3 is smaller than the diameter of the avoidance groove 131 on the vacuum bottom plate 13 of the carrier box. When the lower probe passes through the avoidance groove 131 and contacts the lower electrode 124, the probe 4 will not touch the hole wall of the avoidance groove 131. In this way, the lower probe is connected to the lower electrode of the chip capacitor through the probe contact electrode. Before the lower probe card rises to contact the lower electrode at the bottom of the carrier box, the upper probe card has moved downward first, so that the probe is pressed on the upward surface of each chip capacitor in the carrier box. At this point, all capacitors in the carrier box can start the withstand voltage test first, and load the voltage required for the withstand voltage test on multiple capacitors at the same time for the required time, such as 5 seconds or longer, and then load the charging voltage required for the insulation resistance test on all capacitors until they are basically full, and then start testing the insulation resistance of each chip capacitor in the carrier box one by one. The test speed that can be achieved by this method will be much higher than the speed of the aforementioned existing test method.

[0028] The upper and lower AC probe cards installed in the capacity loss test bench have a multi-way switch channel switching device inside the probe card, which is connected to a capacitance test meter that can measure capacity / loss. In this way, when the upper and lower probe arrays are connected to the chip capacitors in the carrier box, the test meter will test the capacity and loss of each chip capacitor in the carrier box in sequence. Because each chip capacitor in the carrier box is sucked onto the capacitor contact electrode of the carrier box by negative pressure on the vacuum workpiece table, when the test is completed and the probe rises, the chip capacitor will not be stuck to the probe and taken away from the carrier box.

[0029] When the carrier box is moved to the chip capacitor upper surface appearance inspection table, a camera that can move in a two-dimensional plane is provided above the carrier box. The camera will observe and inspect the upward surface of each chip capacitor in the carrier box one by one.

[0030] After that, the test is completed and the carrier box is moved to the packaging station, which includes multiple chip classification packaging stations. Each packaging station has a material unloading robot arm and a loading position, on which a blue film or packaging box is placed. The carrier box will be moved to each packaging station. According to the agreed category of this packaging station, the unloading robot arm will pick up the chip capacitors of this category from the carrier box one by one, move them to the corresponding loading position, and place them on the blue film or in the packaging box. Unqualified capacitors will be removed and put into the defective product collection box.

[0031] The chip capacitor testing and packaging machine made using this solution can complete the material removal from the blue film, the withstand voltage and insulation resistance test that requires more than 5 seconds to charge, the capacity loss test, the appearance inspection and the classification packaging at a relatively high speed without damaging the surface electrodes of the chip capacitor. It is relatively easy to achieve a medium-speed test and packaging equipment of 3 to 4 chip capacitors per second, and it can also achieve a high-speed equipment of 6 to 8 chip capacitors per second, which is far superior to the same functional equipment using existing technology, achieves higher performance at a reasonable cost, and better meets the actual production needs.

[0032] The above are only preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by anyone familiar with the technology within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip capacitance testing device, comprising a probe card, characterized in that: The probe card comprises an upper probe card and a lower probe card, wherein the upper probe card and the lower probe card are respectively provided with more than one probe, a carrier box is provided between the upper probe card and the lower probe card, and the carrier box is used to store more than one chip capacitor, and the carrier box comprises an orifice plate and a circuit board which are sequentially arranged up and down, upper electrodes are evenly arranged above the circuit board, and a vacuum hole is provided on the circuit board corresponding to the position where the chip capacitor is placed, and the vacuum hole is used to be connected to the vacuum mechanism, and a receiving hole for positioning the chip capacitor is provided on the orifice plate corresponding to the upper electrode, and the upper electrode is also connected to the lower electrode located below the circuit board through a conductive through hole, and the probe of the upper probe card is used to be pressed on the chip capacitor, and the probe of the lower probe card is used to be pressed on the lower electrode; The chip capacitor to be tested is a micro capacitor with capacitor electrodes made on two planes of a thin planar dielectric; The upper electrodes are independent of each other and are planar; The carrier box also includes a vacuum bottom plate located below the circuit board, a vacuum groove is provided on the vacuum bottom plate, the vacuum hole is connected to the vacuum groove, and the vacuum hole is connected to the vacuum mechanism through the vacuum bottom plate; an avoidance groove is provided on the vacuum bottom plate at a position corresponding to the lower electrode, and the avoidance groove is used to avoid the lower probe and expose the lower electrode; the vacuum groove needs to be separated from the avoidance groove to avoid affecting the vacuum pumping; The vacuum hole is directly opened in the center of the upper electrode; the vacuum hole and the conductive through hole avoid each other; The diameter of the lower probe on the lower probe card is smaller than the diameter of the avoidance groove on the vacuum bottom plate of the carrier box; The lower probe is connected to the lower electrode of the chip capacitor through the probe contact electrode. Before the lower probe card rises to contact the lower electrode at the bottom of the carrier box, the upper probe card moves downward so that the probe is pressed against the upward surface of each chip capacitor in the carrier box. Each chip capacitor in the carrier is sucked onto the capacitor contact electrode of the carrier by negative pressure on the vacuum worktable. When the test is completed and the probe rises, the chip capacitor will not be stuck to the probe and taken away from the carrier.

2. A chip capacitor test packaging device, which includes a material taking station, a packaging station and a transfer mechanism, and is characterized by: A testing station is also provided between the material picking station and the packaging station, and the testing station is provided with the chip capacitor testing device according to claim 1. The material picking station is used to place the chip capacitor in a carrier box, and the packaging station is used to take the chip capacitor out of the carrier box and place it on a blue film or put it into a packaging box. The carrier box is transferred between the material picking station, the packaging station and the testing station through the transfer mechanism.

3. The chip capacitor test packaging device according to claim 2, characterized in that: The material picking station includes a material picking robot arm and a blue film lower ejector pin, the material picking robot arm is equipped with a suction head, the blue film lower ejector pin is used to eject the chip capacitor from the blue film, and the material picking robot arm absorbs the chip capacitor through the suction head and places it into the carrier box; the packaging station includes a material unloading robot arm and a loading position, the material unloading robot arm is equipped with a suction head, and the blue film or packaging box is placed on the loading position.

4. The chip capacitor test packaging device according to claim 2, characterized in that: The test station comprises a capacitor withstand voltage / insulation resistance test bench and a capacity loss test bench, and the capacitor withstand voltage / insulation resistance test bench and the capacity loss test bench are respectively provided with the chip capacitance test device.

5. The chip capacitor test packaging device according to claim 4, characterized in that: The testing station also includes a chip capacitor upper surface appearance inspection table, and a camera is installed on the chip capacitor upper surface appearance inspection table.

6. The chip capacitor test packaging device according to claim 4, characterized in that: The capacitor withstand voltage / insulation resistance test bench and the capacity loss test bench are respectively equipped with the vacuum pumping mechanism; the capacitor withstand voltage / insulation resistance test bench includes a DC upper probe card and a DC lower probe card, and the probes on the DC upper probe card and the probes on the DC lower probe card are respectively connected to the withstand voltage / insulation resistance test circuit; the capacity loss test bench includes an AC upper probe card and an AC lower probe card, and the probes of the AC upper probe card and the probes of the AC lower probe card are connected to the capacitor test meter.

7. The chip capacitor test packaging device according to claim 6, characterized in that: The AC upper probe card or the AC lower probe card is provided with a multi-way switch channel device, and the probes of the AC upper probe card and the probes of the AC lower probe card are connected to the capacitance test meter through the multi-way switch channel device.

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