Array coherent balanced photoelectric detection component and manufacturing method

Abstract

The present invention provides an array coherent balanced photodetection component and manufacturing method. The component includes: a package housing, an array balanced readout integrated circuit, two photodetector array units, and a package substrate. The top surface of the package housing includes a filter plate. Inside the package housing, two photodetector array units are disposed on the top surface of the array balanced readout integrated circuit and connected to the array balanced readout integrated circuit. The top surface of the array balanced readout integrated circuit is the side facing the filter plate. The package substrate is disposed on the bottom surface of the array balanced readout integrated circuit and connected to the array balanced readout integrated circuit. The above-mentioned array coherent balanced photodetection component can integrate the two photodetector array units, thereby realizing high-sensitivity laser signal array detection based on laser signal coherent detection and integrated array photoelectric signal processing, thereby improving detection sensitivity.

Description

Technical Field

[0001] The present invention relates to the field of photoelectric detection technology, and in particular to an array coherent balanced photoelectric detection component and a manufacturing method thereof. Background Art

[0002] In the field of weak laser signal detection, there are two main detection systems from a technical perspective: direct detection and coherent detection. Direct detection directly measures the intensity of the optical echo. Coherent detection measures the frequency and phase of the optical echo signal by heterodyning the local oscillator light and the echo light.

[0003] At present, the main detection devices of the direct detection system are mainly single-point photodetector solutions. For example, the single-point photodetector can be a PIN (positive-intrinsic-negative) photodiode, APD (avalanche photo diode), SPAD (Single Photon Avalanche Diode), SiPM (Silicon photomultiplier), etc.

[0004] Direct detection systems for weak laser signals are relatively mature. Signals are often amplitude modulated, for example, using pulses or continuous waves. Detection sensitivity is limited by optical and electrical noise levels, and due to the nature of the detection system, detection sensitivity is relatively low.

[0005] Coherent detection systems can improve detection sensitivity through laser signal modulation and optical heterodyne demodulation. However, direct and coherent detection systems require the integration of array detectors for wide-field detection and imaging. Current array photodetectors are only suitable for direct detection systems. This means that current balanced photodetectors lack integration potential, exhibit poor interference resistance, and are unable to improve detection sensitivity. Therefore, improving detection sensitivity is a critical issue currently under investigation in the industry. Summary of the Invention

[0006] The present invention provides an array coherent balanced photoelectric detection component and a manufacturing method thereof, which are used to solve the defect of low detection sensitivity in the prior art and improve the detection sensitivity.

[0007] The present invention provides an array coherent balanced photoelectric detection component, which comprises: a packaging shell, an array balanced readout integrated circuit, two photodetector array units and a packaging substrate, wherein the top surface of the packaging shell comprises a filter plate;

[0008] Inside the package housing, the two photodetector array units are disposed on a top surface of the array-balanced readout integrated circuit and connected to the array-balanced readout integrated circuit, wherein the top surface of the array-balanced readout integrated circuit is a surface facing the filter plate;

[0009] The packaging substrate is disposed on the bottom surface of the array-balanced readout integrated circuit and is connected to the array-balanced readout integrated circuit.

[0010] Optionally, the array-balanced readout integrated circuit includes a plurality of unit circuits, the two photodetector array units are a first photodetector array unit and a second photodetector array unit, the first photodetector array unit includes a plurality of first photodetectors, and the second photodetector array unit includes a plurality of second photodetectors, wherein the number of the unit circuits, the number of the first photodetectors, and the number of the second photodetectors are equal;

[0011] Each of the unit circuits is respectively connected to a first photodetector and a second photodetector, and the first photodetectors and second photodetectors connected to the multiple unit circuits are different from each other, wherein the unit circuit is used to receive and process the current signal input by the corresponding first photodetector and the current signal input by the second photodetector.

[0012] Optionally, the unit circuit includes: a conversion unit and an amplification unit;

[0013] The conversion unit is connected to the first photodetector and the second photodetector corresponding to the unit circuit, and the amplification unit is connected to the conversion unit, wherein the conversion unit is used to convert the current signal input by the first photodetector and the current signal input by the second photodetector received into a voltage signal, and the amplification unit is used to amplify the voltage signal.

[0014] Optionally, the array balanced readout integrated circuit further includes: a logic control circuit and an output circuit;

[0015] The logic control circuit is respectively connected to the output circuit and the plurality of unit circuits;

[0016] The logic control circuit is used to determine a target control logic and, according to the target control logic, input signals output by at least one unit circuit into the output circuit in groups.

[0017] Optionally, the photodetector array unit further includes: a first microlens array and a second microlens array, wherein the first microlens array includes a plurality of first microlenses, and the second microlens array includes a plurality of second microlenses;

[0018] The first microlens is attached to a side of the first photodetector facing the filter plate, wherein the first microlens array is used to process incident light;

[0019] The second microlens is attached to a side of the second photodetector facing the filter plate, wherein the second microlens array is used to process incident light.

[0020] Optionally, the component further comprises: a semiconductor refrigerator;

[0021] The semiconductor cooler is arranged between the packaging substrate and the bottom surface of the packaging shell, and the semiconductor cooler is connected to the packaging substrate and the packaging shell respectively; wherein the bottom surface of the packaging shell is a side of the packaging shell facing the filter plate.

[0022] Optionally, the component further includes: a temperature sensor;

[0023] The temperature sensor is connected to at least one of the photodetector array unit, the array balance readout integrated circuit, and the package substrate; or

[0024] The temperature sensor is integrated into the photodetector array unit.

[0025] The present invention also provides a method for manufacturing an array coherent balanced photoelectric detection component, the method comprising:

[0026] An array-balanced readout integrated circuit, two photodetector array units, and a package substrate are arranged inside the package shell, wherein the top surface of the package shell includes a filter plate;

[0027] Two photodetector array units are arranged on the top surface of the array-balanced readout integrated circuit, and the two photodetector array units are connected to the array-balanced readout integrated circuit, wherein the top surface of the array-balanced readout integrated circuit is a surface facing the filter plate;

[0028] The packaging substrate is mounted on the bottom surface of the array balance readout integrated circuit.

[0029] Optionally, the step of providing two photodetector array units on the top surface of the array-balanced readout integrated circuit includes:

[0030] In a preset area on the top surface of the array-balanced readout integrated circuit, a plurality of first photodetectors are arranged to form a first photodetector array unit, and a plurality of second photodetectors are arranged to form a second photodetector array unit;

[0031] A plurality of unit circuits are arranged around the periphery of the preset area, wherein the number of the unit circuits, the number of the first photodetectors, and the number of the second photodetectors are equal, each of the unit circuits is respectively connected to a first photodetector and a second photodetector, and the first photodetectors and second photodetectors connected to the plurality of unit circuits are different from each other.

[0032] Optionally, the step of mounting the packaging substrate on the bottom surface of the array balance readout integrated circuit includes:

[0033] The input end and the output end of the array balanced readout integrated circuit are connected to the packaging substrate, and the packaging substrate is arranged on the bottom surface of the array balanced readout integrated circuit.

[0034] The present invention provides an array coherent balanced photodetection component and manufacturing method. The component includes: a package housing, an array balanced readout integrated circuit, two photodetector array units, and a package substrate. The top surface of the package housing includes a filter plate. Inside the package housing, two photodetector array units are disposed on the top surface of the array balanced readout integrated circuit and connected to the array balanced readout integrated circuit. The top surface of the array balanced readout integrated circuit is the side facing the filter plate. The package substrate is disposed on the bottom surface of the array balanced readout integrated circuit and connected to the array balanced readout integrated circuit. The above-mentioned array coherent balanced photodetection component can integrate the two photodetector array units, thereby realizing high-sensitivity laser signal array detection based on laser signal coherent detection and integrated array photoelectric signal processing, thereby improving detection sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 This is one of the structural diagrams of an array coherent balanced photoelectric detection component provided by the present invention;

[0037] Figure 2 This is the second structural diagram of an array coherent balanced photoelectric detection component provided by the present invention;

[0038] Figure 3 It is a schematic diagram of the unit circuit and photoelectric detection provided by the present invention;

[0039] Figure 4This is the third structural diagram of an array coherent balanced photoelectric detection component provided by the present invention;

[0040] Figure 5 This is the fourth structural diagram of an array coherent balanced photoelectric detection component provided by the present invention;

[0041] Figure 6 This is the fifth structural diagram of an array coherent balanced photoelectric detection component provided by the present invention;

[0042] Figure 7 This is the sixth structural diagram of an array coherent balanced photoelectric detection component provided by the present invention;

[0043] Figure 8 It is a flow chart of a method for manufacturing an array coherent balanced photoelectric detection component provided by the present invention.

[0044] Reference numerals:

[0045] 101: Package housing; 102: Array balanced readout integrated circuit; 103: First photodetector array unit; 104: First photodetector array unit; 105: Package substrate; 106: Filter plate; 201: Unit circuit; 202: First photodetector; 203: Second photodetector; 204: Unit circuit; 205: First photodetector; 206: Second photodetector; 401: First photodetector; 402: Second photodetector; 403: Conversion unit; 404: Amplification unit; 501: Logic control circuit; 502: Output circuit; 601: First microlens array; 602: Second microlens array; 603: First photodetector array; 604: Second photodetector array. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0047] In order to improve detection sensitivity, the present invention provides an array coherent balanced photoelectric detection component and a manufacturing method. The following first introduces an array coherent balanced photoelectric detection component provided by the present invention.

[0048] like Figure 1As shown, the present invention discloses an array coherent balanced photodetection component, which may include: a packaging shell 101, an array balanced readout integrated circuit 102, two photodetector array units, namely a first photodetector array unit 103 and a second photodetector array unit 104, and a packaging substrate 105.

[0049] The top surface of the package housing 101 includes a filter plate 106. In other words, the surface on which the filter plate 106 is located constitutes the top surface of the package housing 101. The filter plate 106 may be a filter glass cover plate. Light of a specific wavelength band can pass through the filter plate 106, while light of non-specific wavelength bands cannot pass through the filter plate 106, thereby filtering external incident light. The package housing 101 may be a sealed structure.

[0050] Inside the package housing 101 , two photodetector array units are disposed on the top surface of the array-balanced readout integrated circuit 102 and connected to the array-balanced readout integrated circuit 102 , wherein the top surface of the array-balanced readout integrated circuit 102 faces the filter plate 106 .

[0051] That is, the first photodetector array unit 103 and the second photodetector array unit 104 are disposed on the top surface of the array-balanced readout integrated circuit 102 , and the first photodetector array unit 103 and the second photodetector array unit 104 are connected to the array-balanced readout integrated circuit 102 .

[0052] In this way, the laser light can pass through the filter 106 and enter the first photodetector array unit 103 and the second photodetector array unit 104. The first photodetector array unit 103 and the second photodetector array unit 104 can convert the optical signal into an electrical signal. Then, the array-balanced readout integrated circuit 102 can receive the electrical signal input by the first photodetector array unit 103 and the second photodetector array unit 104.

[0053] The package substrate 105 is disposed on the bottom surface of the array-balanced readout integrated circuit 102 and is connected to the array-balanced readout integrated circuit 102. The bottom surface of the array-balanced readout integrated circuit 102 is opposite to the top surface of the array-balanced readout integrated circuit 102. In other words, the bottom surface of the array-balanced readout integrated circuit 102 faces the bottom surface of the package housing 101. The bottom surface of the package housing 101 is the surface opposite to the filter plate 106.

[0054] It can be seen that the array coherent balanced photoelectric detection component disclosed in the present invention can integrate two photodetector array units, thereby realizing high-sensitivity laser signal array detection based on laser signal coherent detection and integrated array photoelectric signal processing, thereby improving detection sensitivity.

[0055] As an embodiment of the present invention, the above-mentioned array-balanced readout integrated circuit may include multiple unit circuits, and the two photodetector array units are a first photodetector array unit and a second photodetector array unit, wherein the photodetector arrays included in the first photodetector array unit and the second photodetector array unit have the same scale, and the sizes of the individual photodetectors (pixels) included therein are also the same.

[0056] The first photodetector array unit may include a plurality of first photodetectors, and the second photodetector array unit may include a plurality of second photodetectors, wherein the number of unit circuits, the number of first photodetectors, and the number of second photodetectors are equal.

[0057] The number of unit circuits, the number of first photodetectors, and the number of second photodetectors can be set according to the actual requirements of the array coherent balanced photodetection component. For example, the number can be 16, 25, or 100, which are all reasonable and are not specifically limited here.

[0058] The spacing between the individual photodetectors can be set based on the actual requirements of the array coherent balanced photodetection assembly, and the spacing between the individual unit circuits can be set based on the actual requirements of the array coherent balanced photodetection assembly. The top surface of the array balanced readout integrated circuit includes multiple pads, where the pads can include two types: bonding pads suitable for wire bonding and bump pads suitable for flip-chip bonding.

[0059] For example, Figure 2 , which is a top view of the array-balanced readout integrated circuit 102 connected to the first photodetector array unit 103 and the second photodetector array unit 104. The array-balanced readout integrated circuit 102 includes 16 unit circuits and multiple pads. The first photodetector array unit 103 includes a 4x4 photodetector array, i.e., 16 first photodetectors. The second photodetector array unit 104 includes a 4x4 photodetector array, i.e., 16 second photodetectors.

[0060] Each unit circuit is connected to a first photodetector and a second photodetector respectively, and the first photodetectors and second photodetectors connected to the multiple unit circuits are different from each other.

[0061] For example, Figure 2As shown, unit circuit 201 is connected to first photodetector 202, unit circuit 201 is also connected to second photodetector 203, unit circuit 204 is connected to first photodetector 205, and unit circuit 204 is also connected to second photodetector 206. That is, the photodetectors corresponding to unit circuit 201 are first photodetector 202 and second photodetector 203. The photodetectors corresponding to unit circuit 204 are first photodetector 205 and second photodetector 206.

[0062] The unit circuit is used to receive the current signal inputted by the corresponding first photodetector and the current signal inputted by the corresponding second photodetector, and perform processing such as addition, conversion, and amplification.

[0063] In order to more clearly illustrate the connection relationship between the unit circuit and the first photodetector and the second photodetector, Figure 3 The connection relationship between the unit circuit and the first photodetector and the second photodetector is illustrated by way of example:

[0064] The array-balanced readout integrated circuit includes m*n unit circuits (pixels). The first row includes unit circuit U11, unit circuit U12, ..., unit circuit U1n, for a total of n unit circuits. The second row includes unit circuit U21, unit circuit U22, ..., unit circuit U2n, for a total of n unit circuits. ... The mth row includes unit circuit Um1, unit circuit Um2, ..., unit circuit Umn, for a total of n unit circuits.

[0065] The first photodetector array unit includes an m*n photodetector array, i.e., m*n first photodetectors (pixels). The first row includes first photodetector Pa11, first photodetector Pa12, ..., first photodetector Pa1n, for a total of n first photodetectors. The second row includes first photodetector Pa21, first photodetector Pa22, ..., first photodetector Pa2n, for a total of n first photodetectors. ... The mth row includes first photodetector Pam1, first photodetector Pam2, ..., first photodetector Pamn, for a total of n first photodetectors.

[0066] The second photodetector array unit includes an m*n photodetector array, i.e., m*n second photodetectors (pixels). The first row includes second photodetector Pb11, second photodetector Pb12, ..., second photodetector Pb1n, for a total of n second photodetectors. The second row includes second photodetector Pb21, second photodetector Pb22, ..., second photodetector Pb2n, for a total of n second photodetectors. ... The mth row includes second photodetector Pbm1, second photodetector Pbm2, ..., second photodetector Pbmn, for a total of n second photodetectors.

[0067] The connection relationship between the unit circuits and the first photodetector and the second photodetector is as follows: unit circuit U11 is connected to the first photodetector Pa11 and the second photodetector Pb11, unit circuit U12 is connected to the first photodetector Pa12 and the second photodetector Pb12...unit circuit Umn is connected to the first photodetector Pamn and the second photodetector Pbmn.

[0068] As an embodiment of the present invention, the unit circuit may include: a conversion unit and an amplification unit. The conversion unit is connected to the first photodetector and the second photodetector corresponding to the unit circuit, and the amplification unit is connected to the conversion unit.

[0069] The conversion unit is used to convert the received current signal inputted by the first photodetector and the received current signal inputted by the second photodetector into a voltage signal, and the amplification unit is used to amplify the voltage signal.

[0070] In one embodiment, the conversion unit may be a trans-impedance amplifier (TIA), and the specific structure may include but is not limited to a resistive feedback structure, a common-gate structure, an adjustable common-gate common-source structure, etc. The conversion unit may include but is not limited to single-ended input, differential input single-ended use, etc. The conversion unit may include but is not limited to fixed gain configuration, controllable gain configuration, and other gain configurations. All of these are reasonable and are not specifically limited here.

[0071] As an embodiment, the amplification unit may be an amplifier stage gain, which may specifically include but is not limited to fixed gain configuration, controllable gain configuration, and other gain configuration modes. The gain may be set to be greater than 1 or may be set to be no greater than 1. The amplification unit may include but is not limited to single-ended input, differential input single-ended use, and other modes, which are all reasonable and are not specifically limited here.

[0072] For example, Figure 4As shown, the unit circuit may include a conversion unit 403 and an amplification unit 404 . The conversion unit 403 is connected to the first photodetector 401 . The conversion unit 403 is also connected to the second photodetector 402 . The amplification unit 404 is connected to the conversion unit 403 .

[0073] In this way, after the first photodetector 401 and the second photodetector 402 convert the light signal into a current signal, the first photodetector 401 and the second photodetector 402 can input the current signal into the conversion unit 403. The conversion unit 403 can convert the received current signal input from the first photodetector 401 and the current signal input from the second photodetector 402 into a voltage signal, and then input the voltage signal into the amplification unit 404. The amplification unit 404 can amplify the voltage signal and output the amplified voltage signal.

[0074] It can be seen that each unit circuit can realize the addition operation of the current signal input by the first photodetector and the current signal input by the second photodetector, that is, the two current signals, and then realize the conversion and amplification of the current signal into a voltage signal.

[0075] As an embodiment of the present invention, the array-balanced readout integrated circuit may further include a logic control circuit and an output circuit, wherein the logic control circuit is connected to the output circuit and the plurality of unit circuits respectively.

[0076] The logic control circuit is used to determine the target control logic and, based on the target control logic, input the signals output by at least one unit circuit into the output circuit in groups. In other words, the logic control circuit can input specific signals from the voltage signals output by each unit circuit into the output circuit.

[0077] In one embodiment, the output circuit can have a parallel output structure, and the number of output circuit channels can be no greater than the number of unit circuits. The output circuit has output drive capability, and specific structures include but are not limited to emitter-follower structures, common-collector amplifier structures, and the like. As an embodiment, the logic control circuit can implement one or more control logics as needed.

[0078] For example, Figure 5As shown, the number of unit circuits (pixels) is x*y. The first row includes unit circuit U11, unit circuit U12, ..., unit circuit U1x, for a total of x unit circuits. The second row includes unit circuit U21, unit circuit U22, ..., unit circuit U2x, for a total of x unit circuits. ... The yth row includes unit circuit Uy1, unit circuit Uy2, ..., unit circuit Uyx, for a total of x unit circuits. Each unit circuit is connected to a logic control circuit 501, and an output circuit 502 is also connected to the logic control circuit 501.

[0079] Each unit circuit inputs the amplified voltage signal to the logic control circuit 501. The logic control circuit 501 can implement one or more logic controls according to actual needs, and then group the signals output by at least one unit circuit and input them into the output circuit 502. The number of parallel output interfaces provided by the output circuit 502 is not greater than x*y.

[0080] For another example, if the number of unit circuits is 100, the target control logic can be determined based on the logic control circuit, and according to the target control logic, the signals output by the 10 unit circuits are grouped and input into the output circuit to achieve the output of specific signals.

[0081] It can be seen that the array-balanced readout integrated circuit disclosed in the present invention includes multiple unit circuits, logic control circuits, and output circuits. The logic control circuits and output circuits are set according to actual usage requirements to achieve grouped signal output.

[0082] As one embodiment of the present invention, the photodetector array unit may further include a first microlens array and a second microlens array. The first microlens array may include multiple first microlenses, and the second microlens array may include multiple second microlenses. The microlens array can spatially divide a complete laser wavefront into many tiny segments, each of which is focused onto a focal plane by a corresponding lenslet. A series of microlenses can produce a plane consisting of a series of focal points.

[0083] The first microlens is attached to the side of the first photodetector facing the filter plate, wherein the first microlens array is used to process incident light. The second microlens is attached to the side of the second photodetector facing the filter plate, wherein the second microlens array is used to process incident light, thereby improving optical efficiency.

[0084] In one embodiment, after the laser passes through the filter, it can be incident on the first microlens array and the second microlens array, so that the first microlens array and the second microlens array can perform light focusing, light shaping and other processing on the incident light, thereby improving optical efficiency.

[0085] For example, Figure 6 As shown (schematically), a first microlens array 601 is attached to a side of a first photodetector array 603 facing the filter plate, i.e., the first microlens array 601 is focused on the top surface of the first photodetector array 603. A second microlens array 602 is attached to a side of a second photodetector array 604 facing the filter plate, i.e., the second microlens array 602 is focused on the top surface of the second photodetector array 604. Specifically, the first microlens is attached to a side of the first photodetector facing the filter plate (not shown in the figure), and the second microlens is attached to a side of the second photodetector facing the filter plate (not shown in the figure).

[0086] It can be seen that the photodetector array unit disclosed in the present invention includes a photodetector and a microlens array, which can improve optical efficiency so as to effectively expand the laser detection field of view and improve the three-dimensional imaging resolution.

[0087] As an embodiment of the present invention, the above-mentioned assembly may further include a semiconductor cooler (TEC). The TEC may be disposed between the package substrate and the bottom surface of the package housing, and the TEC is connected to the package substrate and the package housing, respectively. The bottom surface of the package housing is the side of the package housing that faces the filter plate.

[0088] like Figure 7 As shown, the TEC may be packaged between the substrate 105 and the bottom surface of the package housing 101 .

[0089] As an implementation of the embodiment of the present invention, the above-mentioned component may further include: a temperature sensor.

[0090] In one embodiment, the temperature sensor can be connected to at least one of the photodetector array unit, the array-balanced readout integrated circuit, and the package substrate, as needed. In other words, the temperature sensor can be connected to one or more structures included in the array coherent balanced photodetection assembly.

[0091] For example, the temperature sensor can be connected to the photodetector array unit, the array balanced readout integrated circuit, or the packaging substrate. It can also be connected to the photodetector array unit and the array balanced readout integrated circuit at the same time. It can also be connected to the photodetector array unit, the array balanced readout integrated circuit, and the packaging substrate at the same time. This is all reasonable and is not specifically limited here.

[0092] In another embodiment, the temperature sensor may be integrated into the photodetector array unit. For example, the temperature sensor may be integrated into the first photodetector array unit or the second photodetector array unit. For another example, the temperature sensor may be integrated into the first microlens array or the second microlens array. Both are reasonable and are not specifically limited herein.

[0093] It can be seen that the array coherent balanced photoelectric detection component disclosed in the present invention can include a semiconductor cooler and a temperature sensor, which can ensure that the array coherent balanced photoelectric detection component operates in a reasonable temperature range.

[0094] As an embodiment of the present invention, the photodetector array included in the photodetector array unit can be in the form of a single point, a linear array, or a planar array, which is all reasonable.

[0095] As an embodiment of the present invention, the above-mentioned photodetector can be PIN, APD, SPAD, SiPM, etc., which is reasonable.

[0096] As an embodiment of the present invention, the photodetector can be made of silicon (Si), indium gallium arsenide (InGaAs), germanium (Ge), or the like, all of which are reasonable. The photodetector can correspond to a wavelength of 905 nm to 1550 nm, and can be adjusted based on actual needs, without specific limitation herein.

[0097] As an embodiment of the present invention, the array balanced readout integrated circuit may adopt DC coupling or AC coupling, which is reasonable.

[0098] As an embodiment of the present invention, the array coherent balanced photoelectric detection component disclosed in the present invention can adopt ceramic packaging, PGA (Pin Grid Array Package, pin grid array packaging technology), BGA (Ball Grid Array, ball pin grid array packaging technology), etc., which are all reasonable.

[0099] Corresponding to the above-mentioned array coherent balanced photoelectric detection component, the present invention discloses a method for manufacturing the array coherent balanced photoelectric detection component. The manufacturing method of the array coherent balanced photoelectric detection component disclosed by the present invention is introduced below.

[0100] like Figure 8 As shown, the present invention discloses a method for manufacturing an array coherent balanced photoelectric detection component, which may include:

[0101] S801 , placing an array-balanced readout integrated circuit, two photodetector array units, and a packaging substrate inside the packaging shell.

[0102] The top surface of the package shell includes a filter plate. The array balanced readout integrated circuit is a chip.

[0103] S802: two photodetector array units are arranged on the top surface of the array-balanced readout integrated circuit, and the two photodetector array units are connected to the array-balanced readout integrated circuit.

[0104] The top surface of the array-balanced readout integrated circuit is the side facing the filter plate.

[0105] In one embodiment, a flip chip bending process can be used to place two photodetector array units on the top surface (at the location corresponding to the bump pad) of an array-balanced readout integrated circuit, wherein interconnection lines can be implemented on the array-balanced readout integrated circuit.

[0106] As an implementation, the two photodetector array units may be connected to the array balanced readout integrated circuit by a flip-chip bonding process.

[0107] S803 , installing the packaging substrate on the bottom surface of the array balance readout integrated circuit.

[0108] The bottom surface of the array-balanced readout integrated circuit is a surface facing opposite to the top surface of the array-balanced readout integrated circuit.

[0109] It can be seen that the manufacturing method of an array coherent balanced photoelectric detection component disclosed in the present invention has a high degree of integration. Compared with the traditional method of individually packaging each photodetector to form a component-based balanced detector, it can save material usage. Since the traditional method of packaging photodetectors is device-level packaging, the photodetectors have a large volume and area, poor parasitic parameters, low integration, and poor performance. The manufacturing method of an array coherent balanced photoelectric detection component disclosed in the present invention is chip-level packaging, which has a higher degree of integration and higher detection sensitivity than the traditional packaging method.

[0110] As an embodiment of the present invention, the step of providing two photodetector array units on the top surface of the array-balanced readout integrated circuit may include:

[0111] In a preset area on the top surface of the array-balanced readout integrated circuit, a plurality of first photodetectors are arranged to form a first photodetector array unit, and a plurality of second photodetectors are arranged to form a second photodetector array unit.

[0112] A plurality of unit circuits are arranged on the periphery of the preset area.

[0113] The number of the unit circuits, the number of the first photodetectors and the number of the second photodetectors are equal, each of the unit circuits is connected to a first photodetector and a second photodetector respectively, and the first photodetectors and second photodetectors connected to the multiple unit circuits are different from each other.

[0114] In one embodiment, the predetermined region may be an area corresponding to a predetermined range on either side of the center point of the top surface of the array-balanced readout integrated circuit (chip). Furthermore, a first photodetector array unit and a second photodetector array unit may be disposed on either side of the center point of the top surface of the array-balanced readout integrated circuit, respectively. A plurality of unit circuits may be disposed around the region where the first and second photodetector array units overlap with the array-balanced readout integrated circuit.

[0115] The preset area can be selected according to actual needs, and the unit circuit can also be adjusted according to actual needs. This is all reasonable.

[0116] As an embodiment of the present invention, the step of mounting the package substrate on the bottom surface of the array-balanced readout integrated circuit may include:

[0117] The input end and the output end of the array balanced readout integrated circuit are connected to the packaging substrate, and the packaging substrate is arranged on the bottom surface of the array balanced readout integrated circuit.

[0118] In one embodiment, the input and output terminals of the array-balanced readout integrated circuit may be connected to the package substrate through wires.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An array coherent balanced photoelectric detection component, characterized in that: The assembly comprises: a package housing, an array balanced readout integrated circuit, two photodetector array units and a package substrate, wherein the top surface of the package housing comprises a filter plate; Inside the package housing, the two photodetector array units are disposed on a top surface of the array-balanced readout integrated circuit and connected to the array-balanced readout integrated circuit, wherein the top surface of the array-balanced readout integrated circuit is a surface facing the filter plate; The packaging substrate is disposed on the bottom surface of the array balanced readout integrated circuit and is connected to the array balanced readout integrated circuit; One of the two photodetector array units includes a plurality of first photodetectors, and the other photodetector array unit includes a plurality of second photodetectors. The plurality of array-balanced readout integrated circuits include a plurality of unit circuits, each of the unit circuits is respectively connected to a first photodetector and a second photodetector, and the first photodetectors and second photodetectors connected to the plurality of unit circuits are different from each other. The unit circuits are used to receive current signals input from the corresponding first photodetectors and current signals input from the second photodetectors, and perform addition, conversion, and amplification processing. The unit circuit includes: a conversion unit, which is used to convert the current signal input by the first photodetector and the current signal input by the second photodetector into a voltage signal.

2. The assembly according to claim 1, characterized in that The array-balanced readout integrated circuit includes a plurality of unit circuits, the two photodetector array units are a first photodetector array unit and a second photodetector array unit, the first photodetector array unit includes a plurality of first photodetectors, and the second photodetector array unit includes a plurality of second photodetectors, wherein the number of the unit circuits, the number of the first photodetectors, and the number of the second photodetectors are equal; Each of the unit circuits is respectively connected to a first photodetector and a second photodetector, and the first photodetectors and second photodetectors connected to the multiple unit circuits are different from each other, wherein the unit circuit is used to receive and process the current signal input by the corresponding first photodetector and the current signal input by the second photodetector.

3. The assembly according to claim 2, characterized in that The unit circuit includes: a conversion unit and an amplification unit; The conversion unit is connected to the first photodetector and the second photodetector corresponding to the unit circuit, and the amplification unit is connected to the conversion unit, wherein the conversion unit is used to convert the current signal input by the first photodetector and the current signal input by the second photodetector received into a voltage signal, and the amplification unit is used to amplify the voltage signal.

4. The assembly according to claim 2, characterized in that The array balanced readout integrated circuit further includes: a logic control circuit and an output circuit; The logic control circuit is respectively connected to the output circuit and the plurality of unit circuits; The logic control circuit is used to determine a target control logic and, according to the target control logic, input signals output by at least one unit circuit into the output circuit in groups.

5. The assembly according to claim 2, characterized in that The photodetector array unit further includes: a first microlens array and a second microlens array, wherein the first microlens array includes a plurality of first microlenses and the second microlens array includes a plurality of second microlenses; The first microlens is attached to a side of the first photodetector facing the filter plate, wherein the first microlens array is used to process incident light; The second microlens is attached to a side of the second photodetector facing the filter plate, wherein the second microlens array is used to process incident light.

6. The assembly according to any one of claims 1 to 5, characterized in that The assembly further comprises: a semiconductor refrigerator; The semiconductor cooler is arranged between the packaging substrate and the bottom surface of the packaging shell, and the semiconductor cooler is connected to the packaging substrate and the packaging shell respectively; wherein the bottom surface of the packaging shell is a side of the packaging shell facing the filter plate.

7. The assembly according to any one of claims 1 to 5, characterized in that The assembly further includes: a temperature sensor; The temperature sensor is connected to at least one of the photodetector array unit, the array balance readout integrated circuit, and the package substrate; or The temperature sensor is integrated into the photodetector array unit.

8. A method for manufacturing an array coherent balanced photoelectric detection component, characterized in that: The method comprises: An array-balanced readout integrated circuit, two photodetector array units, and a package substrate are arranged inside the package shell, wherein the top surface of the package shell includes a filter plate; Two photodetector array units are provided on the top surface of the array-balanced readout integrated circuit, and the two photodetector array units are connected to the array-balanced readout integrated circuit, wherein the top surface of the array-balanced readout integrated circuit is the side facing the filter plate; one of the two photodetector array units includes a plurality of first photodetectors, and the other photodetector array unit includes a plurality of second photodetectors; the plurality of array-balanced readout integrated circuits include a plurality of unit circuits, each of the unit circuits is respectively connected to a first photodetector and a second photodetector, and the first photodetectors and second photodetectors connected to the plurality of unit circuits are different from each other, wherein the unit circuits are used to receive current signals inputted by the corresponding first photodetector and current signals inputted by the second photodetector, and perform addition, conversion, and amplification processing; the unit circuits include: a conversion unit, wherein the conversion unit is used to convert the received current signals inputted by the first photodetector and the received current signals inputted by the second photodetector into a voltage signal; The packaging substrate is mounted on the bottom surface of the array balance readout integrated circuit.

9. The method according to claim 8, characterized in that The step of arranging two photodetector array units on the top surface of the array balanced readout integrated circuit comprises: In a preset area on the top surface of the array-balanced readout integrated circuit, a plurality of first photodetectors are arranged to form a first photodetector array unit, and a plurality of second photodetectors are arranged to form a second photodetector array unit; A plurality of unit circuits are arranged around the periphery of the preset area, wherein the number of the unit circuits, the number of the first photodetectors, and the number of the second photodetectors are equal, each of the unit circuits is respectively connected to a first photodetector and a second photodetector, and the first photodetectors and second photodetectors connected to the plurality of unit circuits are different from each other.

10. The method according to claim 8 or 9, characterized in that The step of mounting the package substrate on the bottom surface of the array balance readout integrated circuit comprises: The input end and the output end of the array balanced readout integrated circuit are connected to the packaging substrate, and the packaging substrate is arranged on the bottom surface of the array balanced readout integrated circuit.

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