Power failure protection system for solid state drive

Abstract

A power fail protection system for a solid state drive is provided. In an embodiment, the system includes a plurality of power converters, a backup power converter, a power switch array including power switch pairs, and a power control complex programmable logic device. The power control complex programmable logic device monitors power failures of the plurality of power converters, configures a power level of the backup power converter when a power failure of a certain power converter is detected, the configured power level corresponding to the failed power converter, and controls a target power switch pair corresponding to the failed power converter such that an operating voltage generated by the backup power converter is applied to an internal component.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a power system for a data storage device. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with storage devices, i.e., data storage devices. Data storage devices serve as either the main memory or secondary memory devices in portable electronic devices.

[0003] Data storage devices such as solid-state drives (SSDs) may include power systems. Summary of the Invention

[0004] Aspects of the present invention include a power failure protection system for a data storage device such as a solid-state drive.

[0005] In one aspect of the invention, a power failure protection system for a solid-state drive includes: a plurality of power converters, each power converter providing a predetermined operating voltage to internal components of the solid-state drive; a backup power converter configured to provide a backup operating voltage to the internal components; a power switch array including a plurality of power switch pairs, each power switch pair including a first power switch connected between the power converter and the internal components and a second power switch connected between the backup power converter and the internal components; and a power control complex programmable logic device. The power control complex programmable logic device is configured to: monitor power failures of the plurality of power converters; when a power failure is detected in one of the plurality of power converters, configure a power level of the backup power converter, the configured power level corresponding to the failed power converter; and control a target power switch pair corresponding to the failed power converter such that the operating voltage generated by the backup power converter is applied to the internal components through the second power switch of the target power switch pair.

[0006] In another aspect of the invention, a solid-state drive includes: an internal component including a memory device, a buffer memory, and a memory controller interconnected with each other; and a power failure protection system configured to receive power from a host, generate one or more different operating voltages, and provide one of the operating voltages to the internal component. The power failure protection system includes: a plurality of power converters, each power converter providing a predetermined operating voltage to the internal component; a backup power converter configured to provide a backup operating voltage to the internal component; a power switch array including a plurality of power switch pairs, each power switch pair including a first power switch connected between the power converter and the internal component and a second power switch connected between the backup power converter and the internal component; and a power control complex programmable logic device configured to: monitor power failures of the plurality of power converters; when a power failure of one of the plurality of power converters is detected, configure a power level of the backup power converter corresponding to the failed power converter; and control a target power switch pair corresponding to the failed power converter such that the operating voltage generated by the backup power converter is applied to the internal component through the second power switch of the target power switch pair.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example of a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a diagram illustrating an example of the power supply of a storage device according to an embodiment of the present invention.

[0010] Figure 3A This is a diagram illustrating an example of providing an internal power supply for a solid-state drive according to an embodiment of the present invention.

[0011] Figure 3B This is a diagram illustrating another example of providing an internal power supply for a solid-state drive according to an embodiment of the present invention.

[0012] Figure 4 This is a diagram illustrating a power protection system according to an embodiment of the present invention.

[0013] Figure 5 This is a diagram illustrating an example of a power protection system according to an embodiment of the present invention.

[0014] Figure 6 This is a diagram illustrating another example of a power protection system according to an embodiment of the present invention.

[0015] Figure 7This is a flowchart illustrating the operation method of a power protection system according to an embodiment of the present invention.

[0016] Figure 8A and Figure 8B This is a diagram illustrating an example of a power supply voltage conversion process according to an embodiment of the present invention.

[0017] Figure 9 This is a flowchart illustrating the post-check operation of a power protection system according to an embodiment of the present invention. Detailed Implementation

[0018] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references to “embodiment,” “another embodiment,” etc., herein are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0019] This invention can be embodied in a variety of ways, including as a process; an apparatus; a system; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by memory linked to a processor. In this specification, these embodiments or any other form in which the invention may take may be referred to as technology. Generally, the order of steps of the disclosed process can be varied within the scope of this invention. Unless otherwise stated, components described as suitable for performing tasks, such as processors or memory, may be implemented as general components temporarily configured to perform tasks at a given time or manufactured as specific components for performing tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores adapted to process data such as computer program instructions.

[0020] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating aspects of the invention. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is defined only by the claims. The invention covers many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes only, and the invention may be practiced according to the claims without requiring some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0021] Figure 1 This is a block diagram illustrating an example of a data processing system 10 according to an embodiment of the present invention.

[0022] Reference Figure 1 The data processing system 10 may include a host device 50 and a storage device (which may be implemented as a memory system) 100. The storage device 100 may receive requests from the host device 50 and operate in response to the received requests. For example, the storage device 100 may store data to be accessed by the host device 50.

[0023] The host device 50 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 50 may include electronic devices such as: desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, and / or digital video recorders and digital video players. In various embodiments, the host device 50 may include portable electronic devices such as: mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and / or portable game consoles.

[0024] Storage device 100 may include internal components and a power supply 130. Internal components may include a memory controller 110, a buffer memory 115, and a memory device 120. In some embodiments, the buffer memory 115 may be included within the memory controller 110. Internal components, such as the memory controller 110, may exchange signals SGL (which may represent multiple signals) with the host device 50 via a signal connector SC. Signals SGL may include commands, addresses, and data. Depending on the interface scheme between the host device 50 and storage device 100, the signal connector SC may be configured as any of a variety of connector types.

[0025] The memory controller 110 can control all operations of the memory device 120 in response to the signal SGL from the host device 50. For example, the memory controller 110 can control the memory device 120 to perform one or more erase operations, programming operations, and read operations.

[0026] The memory device 120 can be coupled to the memory controller 110 via one or more channels. The memory device 120 can be implemented using multiple non-volatile memory devices. The memory controller 110 and the memory device 120 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards.

[0027] Buffer memory 115 can be configured to store system data used in storage device 100. For example, buffer memory 115 can store a mapping table and can temporarily store data transferred between host device 50 and storage device 100, the mapping table being mapping information of addresses used in host device 50. Buffer memory 115 can be configured with volatile memory cells to achieve fast operating speed. For example, volatile memory cells can be configured with dynamic random access memory (DRAM) or static random access memory (SRAM). In some embodiments, buffer memory 115 can be implemented using a double data rate (DDR) SDRAM buffer.

[0028] Power supply 130 can supply power PWR, which is input from host device 50 via power connector PC, to the components in storage device 100.

[0029] Figure 2 This is a diagram illustrating an example of a power supply 130 of a storage device 100 according to an embodiment of the present invention.

[0030] Reference Figure 2 The power supply 130 may include multiple capacitors C1 to Cn, a boost regulator RU, and a buck regulator RD. Although in Figure 1 Not shown in the text, but as Figure 2 As shown, the storage device 100 may further include a power switch 140 and a power controller 150 connected to the power supply 130.

[0031] Power switch 140 can provide a normal power delivery path or a power loss protection (PLP) delivery path under the control of power controller 150. In the normal power delivery path, power supplied from host device 50 is delivered to multiple capacitors C1 to Cn via power switch 140, power controller 150, and boost regulator RU. Boost regulator RU can convert a low input voltage from host device 50 to a high voltage (e.g., 35V or higher). The high voltage can be used to charge the multiple capacitors C1 to Cn. Power supply 130 can include a first path (i.e., V_High_Bus) for delivering power (i.e., high voltage) between voltage regulators RU, RD and multiple capacitors C1 to Cn, and a second path (i.e., V_Low_Bus) for delivering power (i.e., low voltage) between voltage regulators RU, RD and host device 50 via power switch 140. Furthermore, power supply 130 can include a third path for delivering signals from power controller 150 to voltage regulators RU, RD.

[0032] When power is interrupted or cut off from host device 50 to storage device 100, multiple capacitors C1 to Cn can discharge, and the energy stored in the multiple capacitors C1 to Cn can be transferred through a PLP transfer path including buck regulator RD, power switch 140, power controller 150, and internal power regulator. Storage device 100 can use the multiple capacitors as a power source to back up data from the internal memory (e.g., volatile memory) of memory controller 110 to memory device 120 (e.g., NAND flash memory device).

[0033] In this way, multiple capacitors C1 to Cn can form a capacitor array to provide sufficient energy to maintain the power rail voltage for backing up data from memory controller 110 to memory device 120. The capacitor array or large-capacity capacitors can be used as power loss protection (PLP) capacitors for memory device 100. The boost regulator RU can be implemented using a voltage regulator that typically includes switching components (e.g., FETs) for high power conversion efficiency. The boost regulator RU can be connected to the PLP capacitors via power path V_High_Bus. Power paths V_High_Bus and V_Low_Bus can be implemented on the printed circuit board (PCB) of memory device 100 (e.g., a solid-state drive (SSD)) using one or more power planes or layers.

[0034] Return to reference Figure 1Unlike hard disk drives (HDDs), storage devices such as solid-state drives (SSDs) 100 require protection of data in buffer memory 115 (e.g., a DDR buffer) from power failures. This protection is crucial because the data in buffer memory 115 contains address mapping information for user data stored in storage device 120 (e.g., NAND flash memory). The location of the data is dynamically changed through specific mechanisms, such as write leveling, to even out the use of storage device 120 (e.g., NAND flash memory) and extend its lifespan. Without address mapping information, user data becomes unrecoverable from storage device 100. When a mains power failure from host device 50 is detected, storage device 100 can switch to using internal power from internal power supply 130 (e.g., ...). Figure 2 The power loss protection (PLP) capacitor provides power as a short-term temporary energy source to move necessary data from the buffer memory 115 to the memory device 120 (e.g., NAND flash memory).

[0035] Power from the PLP capacitor in the host device 50 or power supply 130 can be converted into the internal power supply of the storage device 100 by multiple power converters (e.g., DC-DC converters). Figure 3A and Figure 3B An example of a device for providing internal power to an SSD is shown. Figure 3A and Figure 3B The device can be connected to Figure 2 The power controller 150. Optionally, Figure 3A and Figure 3B The device can be implemented inside the power supply 130. Figure 3A and Figure 3B The device can receive power supply VIN from the PLP capacitor of the host device 50 or power supply 130 as input power supply and generate various operating voltages with different voltage levels.

[0036] exist Figure 3AIn an SSD, the internal power supply is converted by multiple DC-DC converters implemented in a power management integrated circuit (PMIC). SSDs have evolved to utilize a single PMIC for all internal power supplies. A single PMIC includes multiple DC-DC converters and has multiple output channels (e.g., n channels CH1 to CHn) corresponding to the multiple DC-DC converters. The converters have different maximum voltage and maximum current limits for the SSD. Furthermore, the PMIC may include hardware-configurable ROM and registers. The hardware-configurable ROM can be configured to meet specific SSD power design requirements and can be controlled by hardware code pre-programmed into the ROM. An internal integrated circuit (I2C) bus can connect between the system-on-chip (SoC) controller and the PMIC's registers. Therefore, the controller's firmware (FW) can read or write various miscellaneous configuration registers to perform special tasks such as PLP capacitor health checks and to obtain the operating status of all internal DC-DC converters. Additionally, the PMIC can output special control signals to the SoC controller, such as hardware reset, power failure interrupt, PLP capacitor power warning, etc. The PMIC also receives control signals, such as interrupts, from the SoC controller to indicate whether clearing data from buffer memory 115 to memory device 120 is complete.

[0037] exist Figure 3B In an SSD, the internal power supply is converted by multiple discrete DC-DC converters. These discrete DC-DC converters can be hardwired and are not programmable to achieve flexibility such as power sequence adjustments. There is no communication between the DC-DC converters and the SoC controller.

[0038] Various operating voltages of the SSD can be supplied to internal components such as the memory controller (e.g., a system-on-chip (SoC) controller) 110, buffer memory 115, memory device 120, and miscellaneous devices. Figure 3A and Figure 3B In the example shown, and without any restrictions, the SSD can use a variety of operating voltages (e.g., 8 voltages) as shown and defined in Listing 1:

[0039] List 1:

[0040]

[0041] As shown in Listing 1, the operating voltage of the SSD may include the voltage of the memory controller 110 (i.e., SoC_Core, SoC_IO_AON), the voltage of the buffer memory 115 (i.e., DDR_Core_IO, DDR_VPP), the voltage of the memory device 120 (i.e., NAND_Core, NAND_IO, NAND_VPP), and the voltage of the miscellaneous device (i.e., Power_n).

[0042] SSDs do not have power protection components to prevent power supply (i.e., DC-DC converter) failures. Any internal power supply failure can cause the SSD to stop operating and result in the loss of internal data, such as the loss of address mapping information in cache memory 115. Therefore, user data stored in memory device 120 cannot be recovered. Thus, it is necessary to protect the SSD's internal power supply from internal power supply failures.

[0043] The embodiments provide systems and methods for internal power failure protection of storage devices (e.g., SSDs). In some embodiments, when the system detects a power failure of the faulty power supply, the SSD's internal power protection system can immediately switch the internal power supply from the faulty power supply to a backup power supply. Therefore, the SSD can continue to operate normally without losing any data. Additionally, the SSD's SoC controller can receive an interrupt signal from the system to take appropriate action.

[0044] Figure 4 This is a diagram illustrating a power protection system 400 according to an embodiment of the present invention. By way of example and without any limitation, the power protection system 400 can be used in storage devices such as solid-state drives.

[0045] Reference Figure 4 The power protection system 400 may include multiple power converters PS1-PSn 410, a backup power converter 420, a power switch array 430, and a power control complex programmable logic device (CPLD) 440.

[0046] Multiple power converters PS1-PSn 410 can receive input power, generate various operating voltages with different voltage levels, and provide operating voltages through a power switch array 430. In some embodiments, each power converter can be Figure 2 The internal power regulator in the device receives power from the main unit 50 or Figure 2 The power supply 130 is the input power supply and generates operating voltages for setting internal components (e.g., memory controller 110, buffer memory 115, and memory device 120).

[0047] In this embodiment, the multiple power converters PS1-PSn 410 can be, for example, Figure 3A and Figure 5 The diagram shows multiple DC-DC converters implemented in a power management integrated circuit (PMIC). In another embodiment, the multiple power converters PS1-PSn 410 can be as follows: Figure 3B and Figure 6 The diagram shows multiple discrete DC-DC converters.

[0048] The backup power converter 420 can generate a backup operating voltage under the control of the power control CPLD 440 and provide the backup operating voltage to internal components via the power switch array 430. The backup operating voltage can be a voltage that replaces the operating voltage generated by a faulty power converter among the multiple power converters 410.

[0049] In some embodiments, the backup power converter 420 can be shared by all internal power supplies requiring power failure protection (i.e., power converters PS1-PSn). The output voltage level of the backup power converter 420 can be configured by the power control CPLD 440 through the internal registers of the backup power converter 420.

[0050] The power switch array 430 may include a plurality of power switch pairs PSW1-PSWn corresponding to a plurality of power converters PS1-PSn 410. Each power switch pair may include a first power switch (i.e., bottom switch) connected between the power converter and the internal components among the plurality of power converters PS1-PSn 410 and a second power switch (i.e., top switch) connected between the backup power converter 420 and the internal components.

[0051] In some embodiments, each power switch pair may include two power field-effect transistors (FETs), the two power field-effect transistors (FETs) including a first power switch (i.e., FET_bottom) and a second power switch (i.e., FET_top).

[0052] The power control CPLD 440 can monitor power failures of multiple power converters PS1-PSn 410. When a power failure is detected in one of the power converters PS1-PSn 410, the power control CPLD 440 can configure the power level of the backup power converter 420. The configured power level can correspond to the failed power converter. Furthermore, the power control CPLD 440 can control the target power switch pair corresponding to the failed power converter, such that the operating voltage generated by the backup power converter 420 is applied to the internal components through the second power switch of the target power switch pair.

[0053] In some embodiments, the power control CPLD 440 can monitor undervoltage and overvoltage events of all internal power supplies based on preset thresholds for each of the internal power supplies. Upon detecting a fault in an internal power converter, the power control CPLD 440 can immediately configure the output voltage level of the backup power converter 420 to be the same as the output voltage level of the faulty internal power supply. At this time, the power control CPLD 440 can control the power FET pair so that the power supply to the faulty internal power converter can be switched from the faulty power converter to the backup power converter 420.

[0054] As described above, multiple power converters PS1-PSn 410 can be used in, for example... Figure 5 Multiple DC-DC converters implemented in the power management integrated circuit (PMIC) shown, or such as Figure 6 The diagram shows multiple discrete DC-DC converters. Figure 5 In the PMIC, multiple power converters PS1-PSn 410 can be connected to the power switch array 430 and the power control CPLD 440 via multiple PMIC channels. Figure 6 In this configuration, multiple discrete DC-DC converters 410 may be hardwired and connected to a power switch array 430 and a power control CPLD 440.

[0055] Reference Figure 5 and Figure 6 The power switch array 430 can be implemented using an array of multiple power switches, i.e., power FETs. Two power FETs can form a pair of FET_top and FET_bottom. In each power FET pair, FET_bottom can be connected to a corresponding power converter among multiple power converters 410, and FET_top can be connected to a backup power converter 420. Each power FET pair can be controlled by a power control CPLD 440. The multiple power switches can provide various operating voltages for the internal components of the SSD. In some embodiments, as shown in Listing 1, the operating voltages of the SSD can include the voltages of the memory controller 110 (i.e., SoC_Core, SoC_IO_AON), the voltages of the buffer memory 115 (i.e., DDR_Core_IO, DDR_VPP), the voltages of the memory device 120 (i.e., NAND_Core, NAND_IO, NAND_VPP), and the voltages of miscellaneous devices (i.e., Power_n).

[0056] The power control CPLD 440 may include a controller 442, an input interface 444, and an output interface 446. The input interface 444 can receive analog and digital inputs and transmit digital outputs. Analog inputs may include the operating voltages of multiple power converters 410 and the input voltage Vin from the host device 50 or the power supply 130 (i.e., the PLP capacitor).

[0057] The controller 442 can use the analog input of the input interface 444 to monitor the operating voltages of multiple power converters 410 to detect power failures in faulty power converters. The controller 442 can use a set voltage level to determine whether any of the power converters has an undervoltage or overvoltage fault. Optionally, the detection of a power failure in a faulty power converter can be performed by the input interface 444. Further, the controller 442 can control the input interface 444 and the output interface 446 based on the detection of a power failure in a faulty power converter.

[0058] Input interface 444 can receive digital inputs from controller 442 corresponding to the voltage level of the faulty power converter based on the detection of a power failure in the faulty power converter. Further, the digital inputs may include signals from other devices. Input interface 444 can communicate with backup power converter 420 to adjust the voltage to an equal set voltage level for the faulty power converter. In some embodiments, input interface 444 can communicate with backup power converter 420 via an internal integrated circuit (I2C) bus.

[0059] Output interface 446 may include an interrupt generator and a power switch (i.e., FET) driver controlled by controller 442. The interrupt generator may generate an interrupt signal to notify the faulty power converter that a power failure has occurred. In some embodiments, output interface 446 may generate a power failure interrupt (PFI) and provide the PFI to memory controller (e.g., SoC controller) 110.

[0060] A power switch (i.e., FET) driver can drive a target power switch pair in the power switch array 430. The power switch driver can output an enable signal EN to the target power switch pair corresponding to the failed power converter. The enable signal EN can disable the first power switch of the target power switch pair and enable the second power switch of the target power switch pair, so that the backup power converter 420 is connected to the internal components.

[0061] In some embodiments, the power switch driver may include multiple power FET drivers corresponding to multiple power FET pairs. When no power failure is detected, for each FET pair, power FET_top is off and power FET_bottom is on. Therefore, the internal power supply draws power from its respective power converter. When an internal power failure is detected, power FET_top is on and power FET_bottom is off. Therefore, the internal power supply draws power from backup power converter 420.

[0062] Figure 7 This is a flowchart illustrating the operation method of a power protection system 400 according to an embodiment of the present invention. Figure 7 The operation method can be implemented by the power control CPLD 440 through hardware description language (HDL) code.

[0063] Reference Figure 7 After the SSD is powered on, in operation 710, the power control CPLD 440 can determine whether the input voltage VIN is good. When the input voltage VIN is determined to be good, in operation 720, the power control CPLD 440 can perform an initialization operation. For this operation, the power control CPLD 440 can turn on all first power switches (i.e., FET_bottom (FET_BOT)) and turn off all second power switches (i.e., FET_top (FET_TOP)). Furthermore, the power control CPLD 440 can enable the backup power converter (i.e., DC-DC converter) 420.

[0064] In operation 730, the power control CPLD 440 can monitor power failures of multiple power converters to detect a power failure in one of the multiple power converters 410 (i.e., any PMIC channel or discrete DC-DC converter). When a power failure of a power converter is detected, in operation 740, the power control CPLD 440 can perform a power failure action. First, the power control CPLD 440 can send a power failure interrupt (PFI) (e.g., logic level '0') to the memory controller (e.g., SoC controller) 110 via the interrupt generator of the control output interface 446. Second, the power control CPLD 440 can adjust the output of the backup power converter 420 to the voltage level of the failed power converter via the control input interface 444. Third, the power control CPLD 440 can control the target power switch pair corresponding to the failed power converter. In other words, the power control CPLD 440 can turn off the FET_bottom (FET_BOT) of the target power switch pair and turn on the FET_top (FET_TOP) of the target power switch pair.

[0065] Return to reference Figure 5 and Figure 6 The backup power converter 420 may include a voltage decoder 422 and a register 424. The voltage decoder 422 receives multiple signals corresponding to multiple voltage levels of the backup power converter 420 from the power control CPLD 440 via a hardwired path and decodes the corresponding voltage levels. For example, three signals can be used to indicate eight voltage levels. The register 424 receives voltage levels from the power control CPLD 440 via an I2C bus to adjust the output voltage of the backup power converter 420.

[0066] In some embodiments, the power control CPLD 440 can use a combination of hardwired paths and an I2C bus to adjust the output voltage of the backup power converter 420. Since hardwired paths are faster than the I2C bus, the hardwired path can be used as a first step, and the I2C bus as a second step. In the first step, the hardwired path can be used to quickly but coarsely set the output voltage of the backup DC-DC converter 420 to an approximate level. In the second step, the I2C bus can be used to accurately adjust the output voltage of the backup DC-DC converter 420 to the desired level.

[0067] In some embodiments, the backup power converter 420 may be a small, single-channel PMIC with an internal step-down buck converter, since all internal power supplies except the operating voltage NAND_VPP use a step-down converter. The operating voltage NAND_VPP uses a boost converter, but no protection is required because NAND flash memory has an internal boost switching mechanism.

[0068] Upon power-up, the backup power converter 420 can start at the default voltage set by the output buck converter manufacturer. Once powered on, the output of the backup power converter 420 can be adjusted via the power control CPLD 440 through the I2C bus by controlling the internal register 424 of the backup power converter 420.

[0069] In some embodiments, the output of the backup power converter 420 can be set to the intermediate voltage level of all internal power converters. This scheme can reduce the voltage ramp-up or ramp-down conversion time as needed. In some embodiments, the power capacity of the backup power converter 420 can be matched with the highest capacity among all power converters.

[0070] exist Figure 5 and Figure 6In the power protection system 400, the total conversion time from detecting an internal power supply fault to the stable output of the backup DC-DC converter 420 may be limited by the minimum permissible voltage drop level of the faulty internal power supply. The total conversion time of the power protection system 400 mainly consists of the following: fault detection of the power control CPLD 440, communication between the power control CPLD 440 and the backup DC-DC converter 420, output voltage adjustment of the backup DC-DC converter 420, and switching of the corresponding power FET switches in the power FET switch array 430. Among these, the communication between the power control CPLD 440 and the backup DC-DC converter 420 via the I2C bus to set the desired output voltage of the backup DC-DC converter 420 consumes most of the time.

[0071] Figure 8A An internal power supply voltage conversion process with undervoltage fault and the allowable total conversion time are illustrated according to an embodiment of the present invention.

[0072] Reference Figure 8A The requirement is that the backup DC-DC converter 420 completes its output voltage adjustment and startup before the internal power supply voltage level drops to the minimum operating voltage level. To meet this requirement, a set of output signals from the power control CPLD 440 is provided to the backup DC-DC converter 420 via a hardwired path. This set of output signals can be decoded by the voltage decoder 422 of the backup DC-DC converter 420 as the desired voltage level to be set. For example, three signals can be used to indicate eight voltage levels. The signal provision via the hardwired path is much faster than writing to the register 424 of the backup DC-DC converter 420 via I2C bus communication. As mentioned above, since I2C bus operation allows for setting voltage levels with finer resolution, the power control CPLD 440 can use two paths. That is, the hardwired path can be used as the first step, and then the I2C path can be used as the second step.

[0073] Similarly, Figure 8A The solution can be applied to Figure 8B , Figure 8B The internal power supply voltage conversion process with overvoltage faults and the allowable total conversion time are shown.

[0074] Reference Figure 8BThe requirement is that the backup DC-DC converter 420 completes its output voltage adjustment and startup before the internal power supply voltage level rises to the maximum operating voltage level. To meet this requirement, a set of output signals from the power control CPLD 440 is provided to the backup DC-DC converter 420 via a hardwired path. This set of output signals can be decoded by the voltage decoder 422 of the backup DC-DC converter 420 as the desired voltage level to be set. For example, three signals can be used to indicate eight voltage levels. The hardwired path provides the signals much faster than writing to the register 424 of the backup DC-DC converter 420 via I2C bus communication. As mentioned above, since I2C bus operation allows for setting voltage levels with finer resolution, the power control CPLD 440 can use two paths. That is, the hardwired path can be used first, followed by the I2C path.

[0075] exist Figure 8A and Figure 8B In power supply fault detection, due to the limited transition time allowed by the minimum or maximum operating voltage levels, implementing a time-consuming double-check function to filter out potential false power fault events may be impractical. However, power supply voltages naturally contain noise and glitch that can mask the fault trigger level. Therefore, measures such as... Figure 9 The post-inspection scheme is shown.

[0076] Figure 9 This is a flowchart illustrating the post-check operation of a power protection system 400 according to an embodiment of the present invention.

[0077] After the internal power supply is switched to the backup DC-DC converter 420 in the event of a fault, the power control CPLD 440 of the power protection system 400 continues to monitor the output of the faulty power converter (i.e., the faulty PMIC channel or the faulty discrete DC-DC converter) to perform... Figure 9 Post-inspection procedures.

[0078] Reference Figure 9The power control CPLD 440 can perform a post-check operation according to "N-striking filtering," where N can be 1, 2, 3, or greater. In operation 910, the power control CPLD 440 can check the output of the faulty power converter. When the output of the faulty power converter is found to be good, in operation 915, the power control CPLD 440 can wait for a set time period (e.g., x milliseconds). After the set time period has elapsed, in operation 920, the power control CPLD 440 can check the output of the faulty power converter again. In other words, a set time period x is inserted between consecutive checks to wait for the voltage to bounce back to a bad level, thus filtering out possible voltage noise and interference. In some embodiments, x can be set by the power control CPLD 440 to match the actual power supply noise profile. Any failure in the consecutive checks can start the entire process from the first check in operation 910. Therefore, the power control CPLD 440 can perform N consecutive checks on the output of the faulty power converter. Determining that all N consecutive checks are good means that the previous fault of the faulty power converter was actually false. Therefore, during operation 940, the power control CPLD 440 can take fault recovery actions. Fault recovery actions may include: 1) switching the internal power supply back to the faulty power converter (i.e., the PMIC channel or DC-DC converter) (i.e., restoring the faulty power converter); 2) changing the PFI from logic level '0' to logic level '1' to notify the memory controller (e.g., the SoC controller) 110 of a false fault event; and 3) adjusting the output of the standby DC-DC converter 420 back to its originally set voltage level (e.g., the intermediate voltage level of all internal power converters).

[0079] As described above, the embodiment provides a power failure protection system capable of continuously monitoring for any internal power failure events in a storage device such as an SSD. Upon detecting a power failure, the system immediately adjusts the output voltage level of a backup DC-DC converter to match the output voltage level of the failed power converter and replaces the failed power converter with the backup DC-DC converter (i.e., disconnects the failed power converter and connects the backup DC-DC converter). The system also sends a signal to notify the SoC controller of the internal power failure event. The embodiment reduces data loss due to internal power failures in the SSD and provides effective internal power loss protection in the SSD.

[0080] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are exemplary and not restrictive. The invention is intended to cover all modifications and alternatives falling within the scope of the claims. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A power failure protection system for a solid-state drive, the power failure protection system comprising: Multiple power converters, each power converter providing a set operating voltage to the internal components of the solid-state drive; A backup power converter provides backup operating voltage to the internal components; A power switch array includes multiple power switch pairs, each power switch pair including a first power switch connected between a power converter and the internal component in the multiple power converters and a second power switch connected between a backup power converter and the internal component. as well as A power control complex programmable logic device, the power control complex programmable logic device being configured to: Monitor power failures of the multiple power converters; When a power failure is detected in one of the plurality of power converters, the power level of the backup power converter is configured, and the configured power level corresponds to the faulty power converter. and Control the target power switch pair corresponding to the faulty power converter, such that the operating voltage generated by the backup power converter is applied to the internal component through the second power switch of the target power switch pair.

2. The power failure protection system according to claim 1, wherein the plurality of power converters includes a plurality of DC-DC converters included in a power management integrated circuit (PMIC), or discrete DC-DC converters.

3. The power failure protection system according to claim 1, wherein each power switch in each of the plurality of power switch pairs comprises a power field-effect transistor, i.e., a power FET.

4. The power failure protection system according to claim 1, wherein the power control complex programmable logic device comprises: The input interface receives the operating voltages of the plurality of power converters and communicates with the backup power converter to adjust the voltage to be equal to the set voltage level of the faulty power converter; The output interface generates an interrupt signal to notify that a power failure has occurred in the faulty power converter and drives the target power switch pair. as well as The controller monitors the operating voltage of the plurality of power converters to detect power failures in the faulty power converters, and controls the output interface to drive the target power switch pair based on the detection of power failures in the faulty power converters.

5. The power failure protection system according to claim 4, wherein the output interface includes a power switch driver, and The controller controls the power switch driver to disable the first power switch of the target power switch pair and enable the second power switch of the target power switch pair, thereby connecting the backup power converter to the internal component.

6. The power failure protection system according to claim 4, wherein the output interface includes an interrupt generator that generates the interrupt signal and transmits the interrupt signal to the memory controller of the solid-state drive.

7. The power failure protection system of claim 4, wherein the backup power converter has the power capacity of the highest power converter among the plurality of power converters and is configured to have an intermediate voltage level of all the plurality of power converters.

8. The power failure protection system according to claim 4, wherein the power control complex programmable logic device communicates with the backup power converter through a combination of hard-wired paths and an internal integrated circuit bus, i.e., an I2C bus.

9. The power failure protection system according to claim 4, wherein the power control complex programmable logic device checks whether the faulty power converter is operating normally after switching from the faulty power converter to the backup power converter.

10. The power failure protection system according to claim 9, wherein the power control complex programmable logic device checks multiple times within a set time period whether the faulty power converter is operating normally.

11. The power failure protection system of claim 9, wherein when the faulty power converter is detected to be operating normally, the power control complex programmable logic device restores the faulty power converter by controlling a target power switch pair corresponding to the faulty power converter, such that the voltage generated by the restored power converter is applied to the internal component through a first power switch of the target power switch pair.

12. The power failure protection system of claim 1, wherein the internal components include a memory controller, a memory device, and a buffer memory interconnected with each other.

13. A solid-state drive, comprising: Internal components, including interconnected memory devices, buffer memory, and memory controller; as well as The power failure protection system receives power from the host, generates one or more different operating voltages, and provides one of the operating voltages to the internal components. The power failure protection system mentioned above includes: Multiple power converters, each power converter providing a set operating voltage to the internal components; A backup power converter provides backup operating voltage to the internal components; A power switch array comprising multiple power switch pairs, each power switch pair comprising a first power switch connected between a power converter and the internal component, and a second power switch connected between a backup power converter and the internal component; and A power control complex programmable logic device, the power control complex programmable logic device being configured to: Monitor power failures of the multiple power converters; When a power failure is detected in one of the plurality of power converters, the power level of the backup power converter is configured, and the configured power level corresponds to the failed power converter; and Control the target power switch pair corresponding to the faulty power converter, such that the operating voltage generated by the backup power converter is applied to the internal component through the second power switch of the target power switch pair.

14. The solid-state driver of claim 13, wherein the plurality of power converters comprises a plurality of DC-DC converters included in a power management integrated circuit (PMIC), or discrete DC-DC converters, and Each power switch in each of the plurality of power switch pairs includes a power field-effect transistor, i.e., a power FET.

15. The solid-state driver of claim 13, wherein the power control complex programmable logic device comprises: The input interface receives the operating voltages of the plurality of power converters and communicates with the backup power converter to adjust the voltage to be equal to the set voltage level of the faulty power converter; The output interface generates an interrupt signal to notify the faulty power converter that a power failure has occurred, and drives the target power switch pair. as well as The controller monitors the operating voltage of the plurality of power converters to detect power failures in the faulty power converters, and controls the output interface to drive the target power switch pair based on the detection of power failures in the faulty power converters.

16. The solid-state driver of claim 15, wherein the output interface comprises a power switch driver, and The controller controls the power switch driver to disable the first power switch of the target power switch pair and enable the second power switch of the target power switch pair, thereby connecting the backup power converter to the internal component.

17. The solid-state drive of claim 15, wherein the output interface includes an interrupt generator that generates the interrupt signal and transmits the interrupt signal to the memory controller.

18. The solid-state driver of claim 15, wherein the backup power converter has the power capacity of the highest power converter among the plurality of power converters and is configured to have an intermediate voltage level for all the plurality of power converters.

19. The solid-state driver of claim 15, wherein the power control complex programmable logic device communicates with the backup power converter via a combination of a hard-wired path and an internal integrated circuit bus, i.e., an I2C bus.

20. The solid-state driver of claim 15, wherein the power control complex programmable logic device: After switching from the faulty power converter to the backup power converter, the faulty power converter is checked multiple times within a set time period to ensure it is operating normally; and When the faulty power converter is found to be operating normally, the faulty power converter is restored by controlling the target power switch pair corresponding to the faulty power converter, so that the voltage generated by the restored power converter is applied to the internal components through the first power switch of the target power switch pair.

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